Method of bipolar transistor fabrication and related devices

Abstract

The embodiment of the present application provides a bipolar transistor preparation method and a bipolar transistor. The bipolar transistor comprises an emitter and a base, the emitter and the base are arranged in a stack, the bipolar transistor preparation method comprises: performing a partial etching treatment on the emitter to form a target etching area in the emitter; wherein the etching depth of the target etching area is less than the thickness of the emitter before etching; depositing metal in the target etching area to obtain a metal layer; performing an annealing treatment on the metal layer, and the metal layer after the annealing treatment diffuses to the base. The bipolar transistor preparation method and the bipolar transistor can reduce the risk of base damage.

Description

Technical Field

[0001] The embodiments described in this application relate to the field of semiconductor technology, and in particular to a method for fabricating bipolar transistors and related apparatus. Background Technology

[0002] A bipolar junction transistor (BJT) is a type of transistor that utilizes both electrons and holes to conduct electricity. Due to its high-frequency and high-power characteristics, BJTs can be applied in applications such as radio frequency communication, millimeter-wave radar, high-speed optical communication, and high-speed switching circuits. A BJT consists of an emitter, a base, and a collector. In the manufacturing process of a BJT, the emitter and base are placed adjacent to each other. After etching the emitter, a metal layer can be deposited in the etched area to form an ohmic contact between the metal layer and the base, thereby enabling the BJT to connect to external circuits.

[0003] However, in the above scheme, the requirement for the etching process is that the emitter must be etched to expose the base beneath it without damaging the base. This scheme still carries a risk of damage to the base. Summary of the Invention

[0004] In view of this, multiple embodiments of this application aim to provide a method and related apparatus for fabricating bipolar transistors, which can reduce the risk of base damage.

[0005] One embodiment of this application provides a method for fabricating a bipolar transistor, the bipolar transistor including an emitter and a base, the emitter and the base being stacked together, the method comprising: partially etching the emitter to form a target etched region in the emitter; wherein the etching depth of the target etched region is less than the thickness of the emitter before etching; depositing metal in the target etched region to obtain a metal layer; annealing the metal layer, the annealed metal layer diffusing to the base.

[0006] Optionally, the step of depositing metal in the target etched region to obtain a metal layer includes: etching a portion of the target etched region to expose the base electrode in that portion; and depositing metal in the target etched region to obtain a metal layer that forms an ohmic contact with the base electrode.

[0007] Optionally, the bipolar transistor fabrication method conforms to a fabrication specification, which defines the correspondence between the material of the metal layer, the annealing temperature, the annealing time, and the metal diffusion depth, as well as the correspondence between the metal diffusion depth, the thickness of the emitter before etching, and the etching depth.

[0008] Optionally, the bipolar transistor fabrication method further includes: determining the expected metal diffusion depth based on the thickness of the emitter before etching and the etching depth, and in conjunction with the fabrication specifications; determining at least one set of fabrication parameters corresponding to the expected metal diffusion depth from the fabrication specifications, the fabrication parameters being used as the basis for fabricating the bipolar transistor; wherein any set of fabrication parameters includes the material of the metal layer, the annealing temperature, and the annealing time; at least one parameter differs among the sets of fabrication parameters.

[0009] Optionally, the etching depth of the target etching region is within a preset etching depth range, which is 10nm to 50nm, and the thickness of the emitter after etching is within 12nm to 15nm.

[0010] Optionally, the thickness of the metal layer is within a preset metal thickness range, which is 50nm to 500nm.

[0011] Optionally, the annealing temperature corresponding to the annealing treatment is within a preset annealing temperature range, wherein the preset annealing temperature range is 300℃~500℃.

[0012] Optionally, the annealing time corresponding to the annealing process is within a preset annealing time range, which is 1 min to 3 min.

[0013] Optionally, the metal layer may be made of titanium, platinum, or gold.

[0014] Optionally, the emitter is partially etched to form a target etched region in the emitter, including: partially etching the emitter based on a mask corresponding to a specified pattern to form a plurality of target etched regions in the emitter, the plurality of target etched regions forming the specified pattern on a surface perpendicular to the etching direction.

[0015] One embodiment of this application provides a bipolar transistor, including: an emitter, a base, and a metal layer; wherein the emitter and the base are stacked, the emitter includes a target etched region, and the metal layer is deposited in the target etched region; the target etched region is obtained by partially etching the emitter, and the etching depth of the target etched region is less than the thickness of the emitter before etching; the metal layer diffuses to the base after annealing.

[0016] In several embodiments provided in this application, the emitter is partially etched to form a target etched region, such that the etching depth of the target etched region is less than the thickness of the emitter before etching. Then, metal is deposited in the target etched region to obtain a metal layer. After annealing the metal layer, the annealed metal layer can diffuse to the base. This avoids base damage caused by etching and reduces the risk of base damage. Attached Figure Description

[0017] Figure 1 A flowchart of a bipolar transistor fabrication method provided in one embodiment of this application.

[0018] Figure 2 A schematic diagram a of a bipolar transistor cross-sectional structure provided for one embodiment of this application.

[0019] Figure 3 A schematic cross-sectional view of a bipolar transistor provided for one embodiment of this application is shown in diagram b.

[0020] Figure 4 A schematic cross-sectional view of a bipolar transistor provided for one embodiment of this application is shown in diagram c.

[0021] Figure 5 A schematic cross-sectional structure diagram d of a bipolar transistor provided for one embodiment of this application.

[0022] Figure 6 A schematic cross-sectional structure diagram e of a bipolar transistor provided for one embodiment of this application. Detailed Implementation

[0023] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0024] In the description of the embodiments of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0025] In related technologies, bipolar transistors include: ordinary bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), insulated gate bipolar transistors (IGBTs), Darlington transistors, etc. Bipolar transistors rely on two types of charge carriers (electrons and holes) to conduct electricity, thereby enabling connection with external circuits.

[0026] Taking HBTs as an example, the fabrication process typically employs molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) to deposit multiple layers of semiconductor material onto a substrate, controlling the thickness and doping concentration of each layer. Then, photolithography is used to define the emitter, base, and collector in the HBT. Next, dry or wet etching is used to remove some material from the emitter, exposing the adjacent base. Depositing metal in the etched region forms a metal layer in ohmic contact with the base, creating a pathway for the flow of both charge carriers. The HBT can then connect to external circuitry through this metal layer.

[0027] Since the base is located between the emitter and collector, etching techniques are typically used to remove material from the emitter to expose the base covered by the emitter. When the etching precision is low, it's easy for parts of both the emitter and base to be removed during the etching process, leading to base damage. Even with sufficiently high etching precision, once the emitter is etched to expose the base, the base material is still prone to oxidation due to exposure, which can also cause base damage.

[0028] Therefore, it is necessary to provide a method for fabricating a bipolar transistor, in which the emitter is partially etched to form a target etched region, such that the etching depth of the target etched region is less than the thickness of the emitter before etching. Then, metal is deposited in the target etched region to obtain a metal layer. After annealing the metal layer, the annealed metal layer can diffuse to the base. This avoids base damage caused by etching and reduces the risk of base damage.

[0029] Please see Figure 1 This application provides a method for fabricating a bipolar transistor. This method can be used to fabricate a bipolar crystal, wherein the bipolar transistor includes an emitter and a base, the emitter and the base being stacked together. In this embodiment, the bipolar transistor fabrication method may include the following steps.

[0030] Step S110: Perform partial etching on the emitter to form a target etched region in the emitter; wherein the etching depth of the target etched region is less than the thickness of the emitter before etching.

[0031] Step S120: Deposit metal in the target etched area to obtain a metal layer.

[0032] Step S130: Anneal the metal layer, and the annealed metal layer diffuses to the base.

[0033] In this embodiment, the bipolar transistor can be a bipolar transistor (HBT) or other types of transistors including an emitter and a base; this application does not limit the specific type. Taking an HBT as an example, an HBT includes an emitter and a base. The emitter is formed using a wide bandgap material (such as AlGaAs) to reduce hole injection into the base and thus improve electron injection efficiency. The base is formed using a narrow bandgap material (such as GaAs, GaAsSb, InGaAs, GaPSb) to increase electron throughput and reduce base resistance. Because the bandgap of the emitter is larger than that of the base, it ensures that electrons in the base do not easily flow to the emitter, achieving the desired current direction. A hole is a virtual particle in a semiconductor, representing the absence of an electron; when an electron leaves its original position, the position where the electron is located becomes a hole. The base has a higher doping concentration than the emitter. Doping concentration refers to the number of impurity atoms added per cubic centimeter of material. The higher the doping concentration, the better the conductivity, but it is easy to affect the structural stability of the material. The lower the doping concentration, the weaker the conductivity, but the stronger the structural stability of the material.

[0034] In addition, such as Figure 2 and Figure 5 As shown, in the process of fabricating a bipolar transistor, in addition to the base and emitter, the bipolar transistor may also include photoresist, passivation layer, emitter metal, emitter contact layer, emitter capping layer, and substrate.

[0035] The bipolar transistor consists of several components: a substrate, a supporting layer typically made of silicon or gallium arsenide (GaAs); a collector, a region between the substrate and base for collecting electrons with low doping concentration to handle large output current; a base, a control region between the collector and emitter for regulating electron flow from the emitter to the collector; an emitter, a semiconductor material covering the base surface, designed to reduce reverse hole flow due to its wide bandgap; an emitter capping layer, a wide bandgap doped semiconductor covering the emitter surface to protect it and improve electron injection efficiency; an emitter contact layer, a semiconductor layer between the emitter capping layer and the emitter metal, improving ohmic contact and reducing contact resistance; and an emitter metal layer on top of the emitter contact layer for communication with external circuitry. Finally, a passivation layer, a protective material layer typically made of silicon dioxide (SiO2) or silicon nitride (Si3N4), protects the semiconductor surface. Photoresist is a photosensitive material used to define specific patterns and protect the covered areas from being removed during subsequent etching processes.

[0036] To enable bipolar transistors (BPTs) to communicate with external circuits, during BPT fabrication, photoresist can be coated onto the wafer surface. A specific photoresist pattern is formed using photolithography, and etching is performed on the areas not covered by the photoresist using patterned masking techniques. This partially etches the emitter, forming a target etched region within the emitter. This partial etching process can be understood as removing a portion of the material from the emitter while ensuring the base is not exposed to air due to etching. The thickness of the target etched region is less than the thickness of the emitter, thus preventing the base from being exposed and reducing the risk of base damage. The number of partially etched regions is not limited in this embodiment. Furthermore, in... Figure 2 The etched area shown deposits metal to obtain a metal layer, and then removes... Figure 2 The photoresist shown in the figure is used to obtain, as shown in the figure. Figure 3 The bipolar transistor shown is an example. Deposition refers to physical vapor deposition (such as evaporation and sputtering), chemical vapor deposition, electroplating, or solution deposition. Based on this, [further details can be added]. Figure 3 The metal layer shown undergoes annealing, allowing it to diffuse to the base and make contact. This enables the bipolar transistor to connect to external circuitry via the metal layer. For details, please refer to [reference needed]. Figure 4 .

[0037] The bipolar transistor fabrication method provided in this application involves partially etching the emitter to form a target etched region, such that the etching depth of the target etched region is less than the thickness of the emitter before etching. Then, metal is deposited in the target etched region to obtain a metal layer. After annealing the metal layer, the annealed metal layer can diffuse to the base. This avoids base damage caused by etching and reduces the risk of base damage.

[0038] In some embodiments, the step of depositing metal in the target etched region to obtain a metal layer includes: etching a portion of the target etched region to expose the base in the portion of the target etched region; and depositing metal in the target etched region to obtain a metal layer that forms an ohmic contact with the base.

[0039] In this embodiment, the target etching area can be further etched to form an ohmic contact between the base and the metal layer. This avoids the problem of the base failing to contact the metal layer due to insufficient metal diffusion depth, and also reduces the contact resistance. Please refer to [link to relevant documentation]. Figure 5 In the fabrication of bipolar transistors, patterned mask technology can be used to further etch areas not covered by photoresist, exposing the base electrode in certain regions of the target etched area. Specifically, this can involve multiple etching operations on a portion of the target etched area, each using a photomask with a different linewidth. As the number of etching operations increases, the linewidth of the corresponding photomask gradually increases, resulting in a shape where the surface of a portion of the area is parallel to the etching direction, forming a shape such as... Figure 5 The inverted trapezoid shown is an example. The linewidth is the smallest feature size of the pattern on the mask, and can represent the width of elements such as wires or transistor gates.

[0040] The target etched region can be either non-uniform or uniform, and may include at least two etching depths: a maximum etching depth equal to the thickness of the emitter before etching, and a minimum etching depth less than the thickness of the emitter. This ensures that the base is exposed as little as possible, reducing the risk of base damage. The number of target etched regions is not limited in this embodiment. Furthermore, in... Figure 5 The etched area shown deposits metal to obtain a metal layer, and then removes... Figure 5 The photoresist shown in the figure is used to obtain, as shown in the figure. Figure 6 The bipolar transistor shown, in Figure 6 In the bipolar transistor shown, an ohmic contact is formed between the base and the metal layer. Figure 6Based on this, annealing can be performed to expand the contact area between the base and the metal layer. Specifically, the appropriate annealing temperature or annealing time can be selected according to actual needs to ensure that the diffusion depth of the metal layer meets expectations, thereby obtaining the required device performance.

[0041] In some embodiments, the bipolar transistor fabrication method conforms to fabrication specifications that define the correspondence between the material of the metal layer, annealing temperature, annealing time, and metal diffusion depth, as well as the correspondence between the metal diffusion depth, the thickness of the emitter before etching, and the etching depth.

[0042] In this embodiment, in order to control the metal diffusion depth so that the bipolar transistor fabricated based on the bipolar transistor fabrication method has the expected device performance, a fabrication specification can be given to clarify the correspondence between the metal layer material, annealing temperature, annealing time and diffusion depth. This correspondence can be given by multiple numerical variation curves, each of which is used to indicate the change of diffusion depth with annealing time under given parameters.

[0043] For example, Example 1: This correspondence can characterize the change in metal diffusion depth of a titanium material's metal layer with annealing time at an annealing temperature of 300℃, and this metal diffusion depth can at least characterize the depth of lateral diffusion and / or longitudinal diffusion. Example 2: This correspondence can characterize the change in metal diffusion depth of a titanium material's metal layer with annealing time at an annealing temperature of 410℃. Example 3: This correspondence can characterize the change in metal diffusion depth of a gold material's metal layer with annealing time at an annealing temperature of 500℃.

[0044] In some implementations, the relationship between metal diffusion depth and annealing time can be expressed as a linear increasing relationship, that is, the metal diffusion depth increases with increasing annealing time. However, the rate and magnitude of increase in different relationships can be different. Taking a given annealing temperature and material as an example, the relationship between metal diffusion depth and annealing time can be expressed as shown in the table below:

[0045] Metal diffusion depth (nm) Annealing time (min) 42 1 57 2 61 3 61.5 4 …… ……

[0046] In this embodiment, the preparation specification also defines the correspondence between the thickness of the emitter before etching and the etching depth. With the thickness of the emitter before etching and the etching depth clearly defined, the metal diffusion depth can be automatically determined and the material, annealing temperature, and annealing time corresponding to the metal diffusion depth can be determined from the preparation specification.

[0047] In some embodiments, the bipolar transistor fabrication method further includes: determining an expected metal diffusion depth based on the thickness of the emitter before etching and the etching depth, and in conjunction with the fabrication specifications; determining at least one set of fabrication parameters corresponding to the expected metal diffusion depth from the fabrication specifications, the fabrication parameters being used as the basis for fabricating the bipolar transistor; wherein any set of fabrication parameters includes the material of the metal layer, the annealing temperature, and the annealing time; at least one parameter differs among the sets of fabrication parameters.

[0048] In this embodiment, to improve the automation of the fabrication process, given the thickness and etching depth of the emitter before etching, the remaining thickness of the emitter in the etched region after etching can be determined. This remaining thickness can be used as a basis for determining the expected metal diffusion depth. Optionally, the expected device performance can also be used as a basis for determining the expected metal diffusion depth. Based on this, the material, annealing temperature, and annealing time of the metal layer corresponding to the preset diffusion depth can be selected from the correspondence as fabrication parameters. The expected metal diffusion depth can correspond to multiple sets of fabrication parameters. For example, the preset diffusion depth corresponds to set A, set B, and set C of fabrication parameters. The annealing temperature and metal layer material differ between set A and set B, and the material, annealing temperature, and annealing time differ between set B and set C. The expected metal diffusion depth can be obtained by applying any set of fabrication parameters.

[0049] In some embodiments, the etching depth of the target etching region is within a preset etching depth range, which is 10nm to 50nm, and the thickness of the emitter after etching is within 12nm to 15nm.

[0050] In this embodiment, to avoid abnormal metal deposition and diffusion, the thickness of the target etched region can be limited to 10nm to 50nm to reduce metal diffusion paths, avoid potential defects affecting device performance, and ensure a good bonding interface between the deposited metal and other semiconductor materials. For bipolar transistors using gallium arsenide as the base, if the thickness of the emitter after etching is less than 12nm, the barrier height of the aluminum gallium arsenide / gallium arsenide heterojunction decreases, and the reverse leakage current increases. If the thickness of the emitter after etching is greater than 15nm, the metal diffusion path is blocked, and the nonlinearity of the contact resistance deteriorates. Therefore, this application ensures that the thickness of the emitter after etching is within 12nm to 15nm, which can avoid the aforementioned problems, prevent plasma damage during the isolation etching process, control the surface roughness of the base region at a low level, thereby suppressing the interface state density and avoiding a decrease in current gain due to an increase in the surface recombination rate. In some implementations, this thickness allows the metal layer composed of eutectic alloy / nickel (AuGe / Ni) to form a gradient doped interface through thermal diffusion during annealing at 400°C, thereby reducing contact resistance, base resistance, and increasing the maximum oscillation frequency.

[0051] In some embodiments, the thickness of the metal layer is within a preset metal thickness range, which is 50 nm to 500 nm.

[0052] In this embodiment, in order to ensure both good electrical conductivity and thermal conductivity to cope with high-heat working environment, the thickness of the metal layer can be limited to 50nm to 500nm.

[0053] In some embodiments, the annealing temperature corresponding to the annealing process is within a preset annealing temperature range, which is 300℃~500℃.

[0054] In this embodiment, to avoid abnormal diffusion or oxidation of the metal layer, the annealing temperature can be limited to 300°C to 500°C. At the same time, the annealing time of the annealing process can be controlled to ensure that the metal layer has effective mechanical strength and electrical properties and does not undergo abnormal diffusion.

[0055] In some implementations, the annealing time corresponding to the annealing process is within a preset annealing time range, which is 1 min to 3 min.

[0056] In this embodiment, in order to ensure that the metal diffusion depth meets the expectations, the annealing time can be controlled within 1 min to 3 min.

[0057] In some embodiments, when the thickness of the emitter after etching is within 12nm to 15nm, the base material is gallium arsenide, the etching depth is within 10nm to 50nm, the thickness of the metal layer is within 50nm to 500nm, the annealing temperature is within 300℃ to 500℃, and the annealing time is within 1min to 3min, a bipolar transistor that meets the expected metal diffusion depth can be fabricated.

[0058] In some embodiments, the metal layer is made of titanium, platinum, or gold.

[0059] In this embodiment, in order to ensure that the metal layer has good electrical and thermal conductivity, titanium, platinum or gold can be used as the material of the metal layer to utilize the chemical properties of the material to provide good electrical and thermal conductivity.

[0060] In some embodiments, partially etching the emitter to form a target etched region in the emitter includes: partially etching the emitter based on a mask corresponding to a specified pattern to form a plurality of target etched regions in the emitter, the plurality of target etched regions forming the specified pattern on a surface perpendicular to the etching direction.

[0061] In this embodiment, in order to form the desired etched shape to achieve the specified electrical performance, dry etching (such as plasma etching) or wet etching can be used to partially etch the emitter so that multiple target etched areas form a specified pattern on a surface perpendicular to the etching direction, thereby achieving the expected device performance.

[0062] Please see Figure 4 One embodiment of this application also provides a bipolar transistor, which can be applied in a radio frequency chip. The bipolar transistor may include: an emitter, a base, and a metal layer; wherein the emitter and the base are stacked, the emitter includes a target etched region, and the metal layer is deposited in the target etched region; the target etched region is obtained by partially etching the emitter, and the etching depth of the target etched region is less than the thickness of the emitter before etching; the metal layer diffuses to the base after annealing.

[0063] In this embodiment, the specific structure and function of the bipolar transistor can be explained by referring to other embodiments of this application, and will not be repeated here.

[0064] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of the invention.

[0065] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0066] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0067] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0068] The above description is merely a specific embodiment of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a bipolar transistor, characterized in that, The bipolar transistor includes an emitter and a base, wherein the emitter and the base are stacked together; the method for fabricating the bipolar transistor includes: The emitter is partially etched to form a target etched region in the emitter; wherein the etching depth of the target etched region is less than the thickness of the emitter before etching; Deposit metal in the target etched area to obtain a metal layer; The metal layer is annealed, and the annealed metal layer diffuses to the base electrode.

2. The method according to claim 1, characterized in that, The step of depositing metal in the target etched area to obtain a metal layer includes: A portion of the target etched region is etched to expose the base electrode in that portion of the target etched region. Metal is deposited in the target etched region to obtain a metal layer that forms an ohmic contact with the base.

3. The method according to claim 1, characterized in that, The bipolar transistor fabrication method conforms to the fabrication specifications, which define the correspondence between the material of the metal layer, the annealing temperature, the annealing time, and the metal diffusion depth, as well as the correspondence between the metal diffusion depth, the thickness of the emitter before etching, and the etching depth.

4. The method according to claim 3, characterized in that, The bipolar transistor fabrication method further includes: Based on the thickness of the emitter before etching and the etching depth, and in conjunction with the fabrication specifications, the expected metal diffusion depth is determined; At least one set of fabrication parameters corresponding to the expected metal diffusion depth is determined from the fabrication specifications. These fabrication parameters are used as the basis for fabricating bipolar transistors. Each set of fabrication parameters includes the material of the metal layer, the annealing temperature, and the annealing time. At least one parameter differs among the sets of fabrication parameters.

5. The method according to claim 1, characterized in that, The etching depth of the target etching area is within a preset etching depth range, which is 10nm to 50nm, and the thickness of the emitter after etching is within 12nm to 15nm.

6. The method according to any one of claims 1 to 5, characterized in that, The thickness of the metal layer is within a preset metal thickness range, which is 50nm to 500nm.

7. The method according to any one of claims 1 to 5, characterized in that, The annealing temperature corresponding to the annealing treatment is within the preset annealing temperature range, which is 300℃~500℃.

8. The method according to any one of claims 1 to 5, characterized in that, The annealing time corresponding to the annealing process is within the preset annealing time range, which is 1 min to 3 min.

9. The method according to any one of claims 1 to 5, characterized in that, The metal layer is made of titanium, platinum, or gold.

10. The method according to any one of claims 1 to 5, characterized in that, Partial etching of the emitter to form a target etched region in the emitter includes: The emitter is partially etched based on a mask corresponding to a specified pattern to form multiple target etched regions in the emitter, the multiple target etched regions forming the specified pattern on a surface perpendicular to the etch direction.

11. A bipolar transistor, characterized in that, include: Emitter, base, and metal layer; The emitter and the base are stacked together. The emitter includes a target etching region, and the metal layer is deposited in the target etching region. The target etching region is obtained by partially etching the emitter, and the etching depth of the target etching region is less than the thickness of the emitter before etching. The metal layer diffuses to the base after annealing.

Images