Super junction IGBT device and method of manufacturing the same

Abstract

The application provides a super junction IGBT device and a preparation method thereof. The super junction IGBT device comprises a semiconductor structure, an emitter region, a trench gate structure, a dummy gate structure, a collector region and electrodes. The semiconductor structure comprises a laminated substrate, a column layer, a carrier storage layer and a base region, and the column layer comprises first and second columns. The emitter region is located on the upper layer of the base region above the first column. The trench gate structure penetrates the region and extends to the carrier storage layer from the bottom surface, and the emitter region is adjacent to the trench gate structure. The dummy gate structure penetrates the base region and the carrier storage layer above the second column and extends to the upper layer of the second column from the bottom surface, and at least one dummy gate structure is adjacent to the trench gate structure. The collector region is located on the lower layer of the substrate. The electrodes are electrically connected to the corresponding regions respectively. The application improves the compromise relationship between the turn-off oscillation, the conduction loss and the turn-off loss of the device by arranging the carrier storage layer and the dummy gate structure penetrating the base region and the carrier storage layer and being electrically connected to the emitter.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a superjunction IGBT device and its fabrication method. Background Technology

[0002] Trench-gate IGBTs (Insulated Gate Bipolar Transistors) combine the advantages of MOS devices (high input impedance, fast switching speed, and easy drive) with the advantages of bipolar junction transistors (BJTs) (low forward voltage). They are widely used in medium- and high-power power electronic systems. The electric field equation inside the drift region of a trench-gate IGBT is approximately equivalent to a one-dimensional Poisson equation. The doping concentration of the carrier storage layer above the drift region is limited by the breakdown voltage and cannot be further increased. Consequently, it is difficult to improve the conduction loss of the device by increasing the doping concentration of the carrier storage layer. Figure 1 The diagram shows a cross-sectional view of a trench gate IGBT device, including a collector 01, a collector region 011, a field-stop layer 012, a drift region 013, a carrier storage layer 014, a base region 015, an N-type emitter region 016, a P-type contact region 017, a gate trench 02, a gate oxide layer 021, a polysilicon gate 022, an interlayer dielectric layer 03, and an emitter 04. Currently, the trade-off between conduction loss and switching speed is typically optimized by increasing the density of the trench gate and reducing the size of the trench. However, due to limitations in process technology and the micro-trench effect, the size of the trench gate is difficult to further reduce. To further improve the trade-off between conduction loss and turn-off loss, superjunction IGBT devices, which introduce a superjunction structure in the drift region of the device, have emerged, such as... Figure 2 As shown, it is similar to Figure 1 The difference in the device is that the drift region 013 and the carrier storage layer 014 are replaced with alternating N-type pillars 018 and P-type pillars 019. Although this structure improves the trade-off relationship between the device's turn-off loss and conduction loss, the improvement is limited, and there is also a serious problem of excessive turn-off oscillation.

[0003] Therefore, there is an urgent need to find a superjunction IGBT device that can improve the trade-off relationship between the on-state loss and the off-state loss of the device while also improving the off-state oscillation of the device. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a superjunction IGBT device and its fabrication method, which solves the problems of difficulty in further improving the trade-off relationship between conduction loss and turn-off loss and severe turn-off oscillation in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a superjunction IGBT device, comprising:

[0006] A semiconductor structure includes a first conductivity type substrate, a pillar layer, a first conductivity type carrier storage layer, and a second conductivity type base region stacked sequentially. The pillar layer includes a first conductivity type first pillar and a second conductivity type second pillar arranged alternately and adjacently along the X direction, and the X direction is perpendicular to the stacking direction of the substrate and the pillar layer.

[0007] The first conductivity type emission region is located on the upper surface of the base region directly above the first pillar and is spaced at a predetermined distance from the second pillar;

[0008] A trench gate structure extends through the base region and its bottom surface extends into the carrier storage layer. The emitter region is adjacent to the trench gate structure near the sidewall of the trench gate structure.

[0009] A pseudo-gate structure penetrates the base region and the carrier storage layer directly above the second pillar and extends to the upper surface of the second pillar at its bottom. At least one of the pseudo-gate structures adjacent to the first pillar is adjacent to the trench gate structure.

[0010] The second conductivity type collector region is located on the lower surface layer of the substrate;

[0011] The emitter is electrically connected to the emitter region and the pseudo-gate structure;

[0012] The collector electrode is electrically connected to the current collecting region.

[0013] The gate is electrically connected to the trench gate structure.

[0014] Optionally, the doping concentration of the substrate is greater than the doping concentration of the first pillar.

[0015] Optionally, the doping concentration of the carrier storage layer is greater than the doping concentration of the first pillar.

[0016] Optionally, the trench gate structure includes a first trench, a gate dielectric layer, and a first conductive layer. The first trench penetrates the base region and extends to the carrier storage layer at its bottom. The gate dielectric layer covers the inner wall and bottom surface of the first trench. The first conductive layer fills the first trench and is electrically connected to the gate. The dummy gate structure includes a second trench, a dielectric layer, and a second conductive layer. The second trench penetrates the base region and the carrier storage layer and extends to the upper surface of the second pillar. The dielectric layer covers the inner wall and bottom surface of the second trench. The second conductive layer fills the second trench and is electrically connected to the emitter.

[0017] Optionally, the device further includes a first contact area of ​​a second conductivity type located on the upper surface of the base region directly above the first pillar. The first contact area is adjacent to the sidewall of the trench gate structure and electrically connected to the emitter, away from the emitter region.

[0018] Optionally, the device further includes a second contact area of ​​a second conductivity type located on the upper surface of the base region directly above the second pillar, the second contact area being electrically connected to the emitter.

[0019] Optionally, the second contact area is spaced at a preset distance from the pseudo-gate structure.

[0020] Optionally, at least two spaced-apart trench grid structures are provided directly above the same first column, and at least two spaced-apart pseudo grid structures are provided directly above the same second column, with adjacent trench grid structures and pseudo grid structures being adjacent to each other.

[0021] Optionally, the device further includes an interlayer dielectric layer, a first contact hole, and a second contact hole. The interlayer dielectric layer covers the exposed upper surface of the semiconductor structure, the trench gate structure, the dummy gate structure, and the emitter region. The first contact hole penetrates the interlayer dielectric layer directly above the emitter region and the dummy gate structure, and its bottom surface exposes the upper surface of the emitter region and the dummy gate structure. The emitter fills the first contact hole and is electrically connected to the emitter region and the dummy gate structure through the first contact hole. The second contact hole penetrates the interlayer dielectric layer directly above the trench gate structure and its bottom surface exposes the upper surface of the trench gate structure. The gate fills the second contact hole and is electrically connected to the trench gate structure through the second contact hole.

[0022] This invention also provides a method for fabricating a superjunction IGBT device, comprising the following steps:

[0023] A semiconductor structure is provided, the semiconductor structure comprising a first conductivity type substrate, a pillar layer, a first conductivity type carrier storage layer and a second conductivity type base region in a sub-stacked manner, the pillar layer comprising a first conductivity type first pillar and a second conductivity type second pillar arranged alternately adjacent to each other along an X direction, the X direction being perpendicular to the stacking direction of the substrate and the pillar layer;

[0024] A trench gate structure and a pseudo gate structure are formed embedded in the semiconductor structure. The trench gate structure penetrates the base region and extends to the carrier storage layer at its bottom surface. The pseudo gate structure penetrates the base region and the carrier storage layer directly above the second pillar and extends to the upper surface of the second pillar at its bottom surface. At least one pseudo gate structure adjacent to the first pillar is adjacent to the trench gate structure.

[0025] A first conductivity type emission region is formed on the upper surface of the base region located directly above the first pillar, the emission region being adjacent to the trench gate structure near the sidewall of the trench gate structure;

[0026] An emitter electrically connected to the emitter region and the pseudo-gate structure, and a gate electrically connected to the trench gate structure are formed;

[0027] A second conductivity type collector region and a collector electrode electrically connected to the collector region are formed on the lower surface layer of the substrate.

[0028] As described above, the superjunction IGBT device and its fabrication method of the present invention, by setting an isolation base region and a carrier storage layer between the second pillar on the upper surface of the pillar layer, and setting a pseudo-gate structure in the device that penetrates the base region and the carrier storage layer and extends to the upper surface of the second pillar, the pseudo-gate structure is electrically connected to the emitter. By assisting in the depletion of the carrier storage layer through the pseudo-gate structure, the doping concentration of the carrier storage layer can be further increased, enhancing the conductivity modulation effect during device turn-on and reducing the on-state voltage drop. At the same time, the pseudo-gate structure can form a self-biased MOS structure. During device turn-off, as the potential of the carrier storage layer increases, the self-biased MOS structure turns on and forms a hole path, increasing the carrier extraction speed, improving the device turn-off speed, and improving the device turn-off oscillation problem. By making the pseudo-gate structure adjacent to the trench gate structure, the Miller capacitance C of the device is reduced. gc The parasitic capacitance C between the gate and emitter is reduced and increased. ge This further optimizes the trade-off between conduction and turn-off losses, improving the dynamic performance of the device. At the same time, by attracting holes to accumulate below the pseudo-gate structure through the pseudo-gate structure electrically connected to the emitter, the voltage overshoot of the trench gate structure during the device turn-on stage can be avoided, improving the gate control capability and having high industrial application value. Attached Figure Description

[0029] Figure 1 The diagram shows a cross-sectional view of a trench gate IGBT device.

[0030] Figure 2 The diagram shows a cross-sectional view of a superjunction IGBT device.

[0031] Figure 3 The diagram shown is a cross-sectional view of the superjunction IGBT device of the present invention.

[0032] Figure 4 The diagram shown is a schematic cross-sectional view of another superjunction IGBT device according to the present invention.

[0033] Figure 5 The diagram shows the process flow of the fabrication method of the superjunction IGBT device of the present invention.

[0034] Figure 6 The diagram shows a cross-sectional view of the semiconductor structure used in the fabrication method of the superjunction IGBT device of the present invention.

[0035] Figure 7 The diagram shows a cross-sectional structure after the formation of the first trench in the fabrication method of the superjunction IGBT device of the present invention.

[0036] Figure 8 The diagram shown is a cross-sectional view of the superjunction IGBT device fabrication method of the present invention after forming a trench gate structure.

[0037] Figure 9 The diagram shows a cross-sectional structure after the formation of the second trench in the fabrication method of the superjunction IGBT device of the present invention.

[0038] Figure 10 The diagram shows a cross-sectional view of the superjunction IGBT device fabrication method of the present invention after the formation of the pseudo-gate structure.

[0039] Figure 11 The diagram shows a cross-sectional structure of the superjunction IGBT device after the emitter region is formed, according to the fabrication method of the present invention.

[0040] Figure 12 The diagram shown is a cross-sectional view of the superjunction IGBT device fabrication method of the present invention after the formation of the interlayer dielectric layer.

[0041] Figure 13 The diagram shows a cross-sectional structure of the superjunction IGBT device after the collector region is formed, according to the fabrication method of the present invention.

[0042] Explanation of icon numbers

[0043] 01 Collector

[0044] 011 Collection Area

[0045] 012 Field Cutoff Layer

[0046] 013 Drift Zone

[0047] 014 Carrier Storage Layer

[0048] 015 Base Area

[0049] 016 N-type launch area

[0050] 017 P-type contact area

[0051] 018 N-type column

[0052] 019 P-type column

[0053] 02 Gate Trench

[0054] 021 Gate oxide layer

[0055] 022 Polysilicon gate

[0056] 03 Interlayer Dielectric Layer

[0057] 04 Emitter

[0058] 1. Semiconductor Structure

[0059] 11 Substrate

[0060] 12 column layers

[0061] 121 First Pillar

[0062] 122 Second Column

[0063] 13 Carrier Storage Layer

[0064] 14 base regions

[0065] Launch Area 15

[0066] 16 First Contact Zone

[0067] 17 Second Contact Zone

[0068] 18 power collection areas

[0069] 2. Groove grid structure

[0070] 21 First trench

[0071] 22 Gate dielectric layer

[0072] 23 First conductive layer

[0073] 24 Pseudo-gate structure

[0074] 25 Second trench

[0075] 26 Dielectric layers

[0076] 27 Second conductive layer

[0077] 3 Interlayer dielectric layer

[0078] 31 First contact hole

[0079] 4 Emitter

[0080] 5 collectors Detailed Implementation

[0081] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0082] Please see Figures 3 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0083] Example 1

[0084] This embodiment provides a superjunction IGBT device, such as Figure 3 and Figure 4 The diagrams shown depict two cross-sectional structures of the superjunction IGBT device, including a semiconductor structure 1, a first conductivity type emitter region 15, a trench gate structure 2, a dummy gate structure 24, a second conductivity type collector region 18, an emitter 4, a collector 5, and a gate. The semiconductor structure 1 comprises a first conductivity type substrate 11, a pillar layer 12, a first conductivity type carrier storage layer 13, and a second conductivity type base region 14, stacked sequentially. The pillar layer 12 includes a first conductivity type first pillar 121 and a second conductivity type second pillar 122 arranged alternately along the X-direction, perpendicular to the stacking direction of the substrate 11 and the pillar layer 12. The emitter region 15 is located on the first pillar. The base region 14 is located on the upper surface of the base region 14 directly above the first pillar 121 and is spaced at a predetermined distance from the second pillar 122; the trench gate structure 2 extends through the region and its bottom surface extends into the carrier storage layer 13; the emitter region 15 is adjacent to the sidewall of the trench gate structure 2; the dummy gate structure 24 extends through the base region 14 directly above the second pillar 122 and the carrier storage layer 13 and its bottom surface extends to the upper surface of the second pillar 122; at least one dummy gate structure 24 adjacent to the first pillar 121 is adjacent to the trench gate structure 2; the collector region 18 is located on the lower surface of the substrate 11; the emitter 4 is electrically connected to the emitter region 15 and the dummy gate structure 24; the collector 5 is electrically connected to the collector region 18; and the gate is electrically connected to the trench gate structure 2.

[0085] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0086] As an example, the doping concentration of substrate 11 is greater than that of the first pillar 121.

[0087] It should be noted that the substrate 11 is usually a heavily doped region, so that after the collector region 18 is formed on its lower surface layer, it can serve as the field cutoff layer of the device, thereby reducing the on-resistance and saturation voltage drop of the device.

[0088] Specifically, while ensuring device performance, the doping concentration of the substrate 11 in semiconductor structure 1 can be selected according to actual conditions; the height of the pillar layer 12 in semiconductor structure 1 can be selected according to actual conditions; the size, shape, and doping concentration of the first pillar 121 in pillar layer 12 can be selected according to actual conditions; the size, shape, and doping concentration of the second pillar 122 in pillar layer 12 can be selected according to actual conditions; and the number of alternating first pillar 121 and second pillar 122 in pillar layer 12 along the X direction can be selected according to actual conditions.

[0089] As an example, the doping concentration of the carrier storage layer 13 is greater than the doping concentration of the first pillar 121.

[0090] Specifically, the carrier storage layer 13 is usually a heavily doped region used to reduce the on-state voltage drop of the device. While ensuring device performance, the thickness and doping concentration of the carrier storage layer 13 can be selected according to the actual situation.

[0091] Specifically, while ensuring device performance, the thickness and doping concentration of the base region 14 can be selected according to the actual situation.

[0092] It should be noted that in the device, the carrier storage layer 13 isolates the pillar layer 12 and the base region 14 so that the second pillar 122 is floating. The first pillar 121 and the second pillar 122 in the pillar layer 12 are arranged alternately along the X direction, which can optimize the electric field distribution in the pillar layer 12 region of the device. By utilizing the lateral depletion of the superjunction pillars, the extraction of carriers in the device is enhanced, thereby improving the device's withstand voltage and switching speed.

[0093] Specifically, the emitter region 15 usually forms an ohmic contact with the emitter 4. The doping concentration of the emitter region 15 can be selected according to the actual situation while ensuring device performance.

[0094] As an example, the trench gate structure 2 includes a first trench 21, a gate dielectric layer 22, and a first conductive layer 23. The first trench 21 penetrates the base region 14 and extends to the carrier storage layer 13 at its bottom. The gate dielectric layer 22 covers the inner wall and bottom surface of the first trench 21. The first conductive layer 23 fills the first trench 21 and is electrically connected to the gate. The pseudo-gate structure 24 includes a second trench 25, a dielectric layer 26, and a second conductive layer 27. The second trench 25 penetrates the base region 14 and the carrier storage layer 13 and extends to the upper surface of the second pillar 122 at its bottom. The dielectric layer 26 covers the inner wall and bottom surface of the second trench 25. The second conductive layer 27 fills the second trench 25 and is electrically connected to the emitter 4.

[0095] Specifically, the gate dielectric layer 22 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the dielectric layer 26 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the first conductive layer 23 is made of polysilicon or other suitable conductive materials; and the second conductive layer 27 is made of polysilicon or other suitable conductive materials. Preferably, silicon oxide layers are used as the gate dielectric layer 22 and the dielectric layer 26, respectively, and polysilicon layers are used to fill the first trench 21 and the second trench 25, respectively.

[0096] It should be noted that in the adjacent trench gate structure 2 and pseudo gate structure 24, the area of ​​the pseudo gate structure 24 adjacent to the first trench 21 serves as an inner wall of the first trench 21. When the exposed inner wall is the dielectric layer 26, the gate dielectric layer 22 may or may not cover the inner wall while ensuring device performance. When the exposed inner wall is the second conductive layer 27, the gate dielectric layer 22 covers the inner wall. The area of ​​the trench gate structure 2 adjacent to the second trench 25 serves as an inner wall of the second trench 25. When the exposed inner wall is the gate dielectric layer 22, the dielectric layer 26 may or may not cover the inner wall while ensuring device performance. When the exposed inner wall is the first conductive layer 23, the dielectric layer 26 covers the inner wall.

[0097] Specifically, while ensuring device performance, the opening size and shape of the first trench 21 can be selected according to actual conditions; the distance between the bottom surface of the first trench 21 and the bottom surface of the carrier storage layer 13 can be selected according to actual conditions; the thickness of the gate dielectric layer 22 can be selected according to actual conditions; the opening size and shape of the second trench 25 can be selected according to actual conditions; the distance between the bottom surface of the second trench 25 and the upper surface of the pillar layer 12 can be selected according to actual conditions; and the thickness of the dielectric layer 26 can be selected according to actual conditions.

[0098] As an example, the device also includes a second conductivity type first contact region 16 located on the upper surface of the base region 14 directly above the first pillar 121. The first contact region 16 is adjacent to the sidewall of the trench gate structure 2 and is electrically connected to the emitter 4, away from the emitter region 15. Figure 3 As shown.

[0099] Specifically, while ensuring device performance, the size, shape, and thickness of the first contact area 16 can be selected according to the actual situation.

[0100] As an example, the device also includes a second contact region 17 of a second conductivity type located on the upper surface of the base region 14 directly above the second pillar 122. The second contact region 17 is electrically connected to the emitter 4, such as... Figure 4 As shown.

[0101] Specifically, while ensuring device performance, the size, shape, and thickness of the second contact area 17 can be selected according to the actual situation.

[0102] As an example, the second contact area 17 is spaced at a predetermined distance from the pseudo-gate structure 24.

[0103] Specifically, while ensuring device performance, the distance between the second contact area 17 and the pseudo-gate structure 24 adjacent to the trench gate structure 2 can be selected according to the actual situation.

[0104] It should be noted that the second contact region 17 is electrically connected to the emitter 4, and the carrier storage layer 13 isolates the base region 14 from the second pillar 12, so that the pseudo-gate structure 24 independently forms a RET (Recessed-Emitter-Trench) structure. The RET structure constitutes a self-biased MOS structure. When the device is turned on, the self-biased MOS structure is turned off, which has no effect on the conduction performance of the device. When the device is turned off, as the potential of the second pillar 122 increases, the self-biased MOS structure turns on, forming a hole channel in the carrier storage layer 13 near the pseudo-gate structure 24, which promotes the extraction of carriers when the device is turned off and improves the turn-off speed of the device.

[0105] As an example, at least two grooved grid structures 2 are provided directly above the same first column 121, and at least two pseudo-grid structures 24 are provided directly above the same second column 122, with the adjacent grooved grid structures 2 and pseudo-grid structures 24 being adjacent to each other.

[0106] Specifically, by setting no fewer than two trench gate structures 2 directly above the same first pillar 121 and no fewer than two dummy gate structures 24 directly above the same second pillar 122, the number of conductive channels and the number of self-biased MOS structures in the device can be increased, thereby improving the power density and turn-off speed of the device.

[0107] As an example, the device also includes an interlayer dielectric layer 3, a first contact hole 31, and a second contact hole. The interlayer dielectric layer 3 covers the exposed upper surfaces of the semiconductor structure 1, the trench gate structure 2, the dummy gate structure 24, and the emitter region 15. The first contact hole 31 penetrates the interlayer dielectric layer 3 directly above the emitter region 15 and the dummy gate structure 24, and its bottom surface exposes the upper surfaces of the emitter region 15 and the dummy gate structure 24. The emitter 4 fills the first contact hole 31 and is electrically connected to the emitter region 15 and the dummy gate structure 24 through the first contact hole 31, respectively. The second contact hole penetrates the interlayer dielectric layer 3 directly above the first trench gate structure 2 and its bottom surface exposes the upper surface of the trench gate structure 2. The gate fills the second contact hole and is electrically connected to the trench gate structure 2 through the second contact hole. It should be noted that the upper surface of the pseudo-gate structure 24 exposed on the bottom surface of the first contact hole 31 is the upper surface of the second conductive layer 27 in the pseudo-gate structure 24, and the upper surface of the trench gate structure 2 exposed on the bottom surface of the second contact hole is the upper surface of the first conductive layer 23 in the trench gate structure 2. That is, the emitter 4 is electrically connected to the second conductive layer 27 of the pseudo-gate structure 24, and the gate is electrically connected to the first conductive layer 23 of the trench gate structure 2.

[0108] It should be noted that when the upper surface of the base region 14 is provided with the first contact area 16, the interlayer dielectric layer 3 also covers the exposed surface of the first contact area 16, the bottom surface of the first contact hole 31 exposes the first contact area 16, and the emitter 4 is electrically connected to the first contact area 16 through the first contact hole 31; when the upper surface of the base region 14 directly above the second pillar 122 is provided with the second contact area 17, the interlayer dielectric layer 3 also covers the exposed surface of the second contact area 17, the bottom surface of the first contact hole 31 exposes the second contact area 17, and the emitter 4 is electrically connected to the second contact area 17 through the first contact hole 31.

[0109] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. Preferably, a silicon oxide layer is used as the interlayer dielectric layer 3.

[0110] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 3 can be selected according to the actual situation; the opening size and opening shape of the first contact hole 31 can be selected according to the actual situation; the opening size and opening shape of the second contact hole can be selected according to the actual situation.

[0111] Specifically, the emitter 4 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the gate is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials.

[0112] Specifically, collector 5 covers the side of collector region 18 away from pillar layer 12, and the contact type between collector region 18 and collector 5 is ohmic contact. While ensuring device performance, the size, shape, thickness, and doping concentration of collector region 18 can be selected according to actual conditions. Here, thickness refers to the distance between the upper and lower surfaces of collector region 18.

[0113] Specifically, the material of collector 5 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials.

[0114] Specifically, by setting a pillar layer 12, a carrier storage layer 13, and a pseudo-gate structure 24 penetrating the base region 14 and the carrier storage layer 13 in the device, the bottom surface of the pseudo-gate structure 24 extends to the upper surface of the second pillar 122 and is electrically connected to the emitter 4. The superjunction structure is used to optimize the electric field inside the device, which makes the wafer for fabricating the device thinner. At the same time, the pseudo-gate structure 24 assists in depleting the carrier storage layer 13, which is conducive to further increasing the doping concentration of the carrier storage layer 13, enhancing the carrier storage effect of the device, thereby enhancing the conductivity modulation effect during the device conduction process, and further reducing the on-state voltage drop of the device.

[0115] Specifically, by making the dummy gate structure 24 adjacent to the trench gate structure 2, the Miller capacitance C can be reduced by utilizing the coupling between the trench gate structure 2 and the dummy gate structure 24. gc At the same time, it increases the parasitic capacitance C between the gate and emitter 4 of the device. ge This optimizes the trade-off between the conduction loss and turn-off loss of the device, improves the dynamic performance of the device, and at the same time utilizes the attraction of holes by the pseudo gate structure 24 to make the holes accumulate below the pseudo gate structure 24, and make most of the displacement current flow into the pseudo gate structure 24, reducing the hole displacement current of the trench gate structure 2, avoiding voltage overshoot of the trench gate structure 2 during the device turn-on stage, and improving the control capability of the gate.

[0116] Specifically, by setting a pseudo-gate structure 24 that penetrates the carrier storage layer 13 and is adjacent to the trench gate structure 2 directly above the second pillar 122, the pseudo-gate structure 24 independently constitutes a RET structure with a self-biased MOS structure. During the device turn-off process, as the potential of the carrier storage layer 13 increases, the self-biased MOS structure turns on, forming a hole path near the pseudo-gate structure 24. Together with the lateral depletion region formed by the superstructure, it accelerates the carrier extraction speed during the device turn-off process, improves the device turn-off speed, improves the device turn-off oscillation problem, and improves the device performance.

[0117] In this embodiment, the superjunction IGBT device incorporates a carrier storage layer 13 and a dummy gate structure 24 that penetrates the base region 14 directly above the second pillar 122 and extends to the top surface of the pillar layer 12. The dummy gate structure 24 assists in depleting the carrier storage layer 13, further increasing the doping concentration of the carrier storage layer 13 and enhancing the carrier storage effect while reducing the on-state voltage drop. Since the dummy gate structure 24 is electrically connected to the emitter 4, it can independently form a self-biased MOS structure. In the ET structure, during device turn-off, as the potential of the carrier storage layer 13 increases, the self-biased MOS structure turns on, forming a hole path. This accelerates the carrier extraction speed during turn-off, improving the device's turn-off speed and mitigating turn-off oscillation. Because the dummy gate structure 24 is adjacent to the trench gate structure 2, and the dummy gate structure 24 attracts holes to accumulate below it, voltage overshoot of the trench gate structure 2 during device turn-on is avoided, enhancing gate control. Simultaneously, the proximity of the dummy gate structure 24 to the trench gate structure 2 reduces the Miller capacitance C of the device. gc The parasitic capacitance C between the gate and emitter 4 is reduced and increased. ge This optimizes the trade-off between the device's on-state and off-state losses, thereby improving the device's dynamic performance.

[0118] Example 2

[0119] This embodiment also provides a method for fabricating a superjunction IGBT device, such as... Figure 5 The diagram shown is a process flow chart of the fabrication method of the superjunction IGBT device, including the following steps:

[0120] S1: A semiconductor structure is provided, the semiconductor structure including a first conductivity type substrate, a pillar layer, a first conductivity type carrier storage layer and a second conductivity type base region in a sub-stacked manner, the pillar layer including a first conductivity type first pillar and a second conductivity type second pillar arranged alternately adjacent to each other along the X direction, the X direction being perpendicular to the stacking direction of the substrate and the pillar layer;

[0121] S2: Form a trench gate structure and a pseudo gate structure embedded in the semiconductor structure. The trench gate structure penetrates the base region and extends to the carrier storage layer at its bottom surface. The pseudo gate structure penetrates the base region and the carrier storage layer directly above the second pillar and extends to the upper surface of the second pillar at its bottom surface. At least one pseudo gate structure adjacent to the first pillar is adjacent to the trench gate structure.

[0122] S3: Form a first conductivity type emission region on the upper surface of the base region located directly above the first pillar, the emission region being adjacent to the trench gate structure near the sidewall of the trench gate structure;

[0123] S4: Form an emitter electrically connected to the emitter region and the pseudo-gate structure, and a gate electrically connected to the trench gate structure;

[0124] S5: Form a second conductivity type collector region located on the lower surface of the substrate and a collector electrode electrically connected to the collector region.

[0125] Please see Figures 6 to 10 Steps S1 and S2 are performed as follows: A semiconductor structure 1 is provided. The semiconductor structure 1 includes a first conductivity type substrate 11, a pillar layer 12, a first conductivity type carrier storage layer 13, and a second conductivity type base region 14, which are stacked in a sub-layer. The pillar layer 12 includes a first conductivity type first pillar 121 and a second conductivity type second pillar 122 arranged alternately along the X direction. The X direction is perpendicular to the stacking direction of the substrate 11 and the pillar layer 12. A trench gate structure 2 and a pseudo gate structure 24 are formed embedded in the semiconductor structure 1. The trench gate structure 2 penetrates the base region 14 and extends to the carrier storage layer 13. The pseudo gate structure 24 penetrates the base region 14 and the carrier storage layer 13 directly above the second pillar 122 and extends to the upper surface of the second pillar 122. At least one pseudo gate structure 24 adjacent to the first pillar 121 is adjacent to the trench gate structure 2.

[0126] Specifically, such as Figure 6 The diagram shows a cross-sectional view of semiconductor structure 1. Semiconductor structure 1 is typically a composite film structure of the emitter region 15 of the device to be fabricated. The substrate 11 in semiconductor structure 1 serves as the fabrication platform and forms the film layer for the collector region 18. The thickness, size, and shape of the substrate 11 can be selected according to the actual situation while ensuring device performance.

[0127] Specifically, the substrate 11 may be made of silicon, silicon germanium, silicon carbide, gallium nitride, diamond, or other suitable materials. Preferably, a silicon wafer is used as the substrate 11.

[0128] Specifically, the pillar layer 12 is usually a homogeneous epitaxial layer of the substrate 11, the carrier storage layer 13 is a homogeneous epitaxial layer of the pillar layer 12, and the base region 14 is a homogeneous layer or a homogeneous epitaxial layer of the carrier storage layer 13.

[0129] It should be noted that the pillar layer 12 in the semiconductor structure 1 is usually formed by a combination of multiple epitaxial processes and multiple implantation processes. During the fabrication of the pillar layer 12 on the upper surface of the substrate 11, after each epitaxial process to form the first conductivity type epitaxial layer, ion implantation is required in the region corresponding to the second pillar 122 in the epitaxial layer before the next epitaxial process is performed. Usually, the region in the epitaxial layer that has not been ion implanted is the region corresponding to the first pillar 121, and the ion implanted region is the region corresponding to the second pillar 122.

[0130] Specifically, the pillar layer 12 is formed by combining multiple epitaxial processes with multiple ion implantations. Different numbers of epitaxial processes and ion implantations can be used depending on the voltage level, resulting in high process flexibility. Furthermore, the number of epitaxial processes, the ion implantation dose, and the thickness of the pillar layer 12 are related to the voltage level of the device to be fabricated, and are not limited here.

[0131] It should be noted that the carrier storage layer 13 in semiconductor structure 1 is usually fabricated using a high-concentration epitaxial process to improve the quality of the fabricated carrier storage layer 13. However, if the device performance is guaranteed, the carrier storage layer 13 can also be formed using an ion implantation process.

[0132] Specifically, the methods for forming the base region 14 include ion implantation or other suitable methods.

[0133] Specifically, the trench gate structure 2 includes a first trench 21, a gate dielectric layer 22, and a first conductive layer 23. The first trench 21 penetrates the base region 14 and extends to the carrier storage layer 13 at its bottom. The gate dielectric layer 22 covers the inner wall and bottom surface of the first trench 21. The first conductive layer 23 fills the first trench 21 and is electrically connected to the gate. The pseudo-gate structure 24 includes a second trench 25, a dielectric layer 26, and a second conductive layer 27. The second trench 25 penetrates the base region 14 and the carrier storage layer 13 and extends to the upper surface of the second pillar 122 at its bottom. The dielectric layer 26 covers the inner wall and bottom surface of the second trench 25. The second conductive layer 27 fills the second trench 25 and is electrically connected to the emitter 4.

[0134] It should be noted that when fabricating the trench grid structure 2 and the pseudo-grid structure 24, the trench grid structure 2 can be fabricated first, followed by the pseudo-grid structure 24, or vice versa. Furthermore, during the fabrication of the latter trench structure, the dielectric layer on the inner wall adjacent to the former trench structure and the latter trench structure can be removed, or the dielectric layer on the inner wall adjacent to the former trench structure and the latter trench structure can be retained. The following section briefly explains the fabrication process of the trench grid structure 2 and the pseudo-grid structure 24, taking the example of fabricating the trench grid structure 2 first and removing the grid dielectric layer 22 on the inner wall adjacent to the pseudo-grid structure 24.

[0135] Specifically, such as Figure 7 , Figure 8 , Figure 9 and Figure 10The figures shown are cross-sectional view diagrams after the formation of the first trench 21, the trench gate structure 2, the second trench 25, and the dummy gate structure 24. The formation of the trench gate structure 2 and the dummy gate structure 24 includes the following steps: forming a masking layer with a pattern of the first trench 21 on the upper surface of the semiconductor structure 1, and forming a first trench 21 that penetrates the base region 14 and extends to the carrier storage layer 13 based on the masking layer; sequentially forming a gate dielectric layer 22 covering the inner wall and bottom surface of the first trench 21 and a first conductive layer 23 filling the first trench 21, wherein the gate dielectric layer 22 encloses the first conductive layer filling the first trench 21. The sidewalls and bottom surface of layer 23, the first trench 21, the gate dielectric layer 22 and the first conductive layer 23 constitute a trench gate structure 2; a shielding layer with a second trench 25 pattern is formed on the upper surface of semiconductor structure 1, and a second trench 25 is formed based on the shielding layer, penetrating the base region 14 and the carrier storage layer 13 and extending to the upper surface of the second pillar 122, and at least one second trench 25 is adjacent to a nearby trench gate structure 2; a dielectric layer 26 covering the inner wall and bottom surface of the second trench 25 and a second conductive layer 27 filling the second trench 25 are formed in sequence, the dielectric layer 26 wraps the sidewalls and bottom surface of the second conductive layer 27, and the second trench 25, the dielectric layer 26 and the second conductive layer 27 constitute a pseudo gate structure 24.

[0136] Specifically, the method for forming the masking layer with the first groove 21 pattern and the masking layer with the second groove 25 pattern is a commonly used photolithography process, which will not be described in detail here.

[0137] Specifically, the method for forming the first trench 21 includes dry etching, wet etching, or other suitable methods; the method for forming the second trench 25 includes dry etching, wet etching, or other suitable methods.

[0138] Specifically, after forming the first trench 21 and before forming the gate dielectric layer 22, the process includes removing the masking layer with the pattern of the first trench 21. The method for removing the masking layer is a commonly used method for removing hard mask layers, which will not be described in detail here.

[0139] Specifically, after forming the second trench 25 and before forming the dielectric layer 26, the process includes removing the masking layer with the pattern of the second trench 25. The method for removing the masking layer is a commonly used method for removing hard mask layers, which will not be described in detail here.

[0140] Specifically, the methods for forming the gate dielectric layer 22 include thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0141] It should be noted that the gate dielectric layer 22 typically covers the inner wall of the first trench 21 while also covering the upper surface of the semiconductor structure 1.

[0142] Specifically, forming the first conductive layer 23 includes the following steps: forming a first conductive material layer that fills the first trench 21 and covers the upper surface of the gate dielectric layer 22 directly above the semiconductor structure 1; removing the first conductive material layer covering the upper surface of the gate dielectric layer 22 directly above the semiconductor structure 1; and the remaining first conductive material layer filling the first trench 21 serves as the first conductive layer 23.

[0143] Specifically, the method for forming the dielectric layer 26 includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods. Preferably, the dielectric layer 26 is formed using a thermal oxidation process.

[0144] It should be noted that, since the gate dielectric layer 22 that usually covers the upper surface of the semiconductor structure 1 is not removed during the formation of the first conductive layer 23, the dielectric layer 26 formed by the thermal oxidation process does not cover the upper surface of the gate dielectric layer 22 directly above the semiconductor structure 1 and the gate dielectric layer 22 exposed on the inner wall of the second trench 25.

[0145] Specifically, forming the second conductive layer 27 includes the following steps: forming a second conductive material layer that fills the second trench 25 and covers the upper surface of the gate dielectric layer 22 directly above the semiconductor structure 1; removing the second conductive material layer covering the upper surface of the gate dielectric layer 22 directly above the semiconductor structure 1; and the remaining second conductive material layer filling the second trench 25 serves as the second conductive layer 27.

[0146] Specifically, the methods for forming the first conductive material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods; the methods for forming the second conductive material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods; the methods for removing the first conductive material layer from the upper surface of the gate dielectric layer 22 covering the semiconductor structure 1 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods; and the methods for removing the second conductive material layer from the upper surface of the gate dielectric layer 22 covering the semiconductor structure 1 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods.

[0147] Specifically, at least two spaced-apart grooved grid structures 2 are provided directly above the same first column 121, and at least two spaced-apart pseudo-grid structures 24 are provided directly above the same second column 122. The grooved grid structures 2 and pseudo-grid structures 24 that are close to each other are adjacent. That is, when multiple grooved grid structures 2 and pseudo-grid structures 24 are formed directly above the same first column 121 and the same second column 122, the grooved grid structures 2 and pseudo-grid structures 24 that are close to each other are adjacent.

[0148] Please see Figures 11 to 13Steps S3, S4 and S5 are executed: a first conductivity type emitter region 15 is formed on the upper surface of the base region 14 directly above the first pillar 121, the emitter region 15 is adjacent to the trench gate structure 2 near the sidewall of the trench gate structure 2; an emitter 4 electrically connected to the emitter region 15 and the pseudo gate structure 24 and a gate electrically connected to the trench gate structure 2 are formed; a second conductivity type collector region 18 is formed on the lower surface of the substrate 11 and a collector electrode 5 electrically connected to the collector region 18.

[0149] Specifically, such as Figure 11 The diagram shown is a cross-sectional view of the structure after the emission region 15 is formed. The method for forming the emission region 15 includes ion implantation or other suitable methods.

[0150] Specifically, while ensuring device performance, the thickness, size, and shape of the emission region 15 can be selected according to the actual situation.

[0151] Specifically, after the emitter region 15 is formed and before the emitter 4 and the gate are formed, the step of forming a first contact region 16 of the second conductivity type on the upper surface of the base region 14 located directly above the first pillar 121 is also included. The first contact region 16 is adjacent to the sidewall of the trench gate structure 2 away from the emitter region 15 and is electrically connected to the emitter 4.

[0152] It should be noted that, while ensuring device performance, the emitter region 15 can also be formed after the first contact region 16 is formed.

[0153] Specifically, the first contact region 16 is usually a heavily doped region that forms an ohmic contact with the subsequently fabricated emitter 4. The doping concentration of the first contact region 16 can be selected according to the actual situation while ensuring device performance.

[0154] Specifically, after forming the trench gate structure 2 and the dummy gate structure 24, and before forming the emitter 4 and the gate, the process also includes forming a second contact region 17 of the second conductivity type on the upper surface of the base region 14 located directly above the second pillar 122. The second contact region 17 is electrically connected to the subsequently fabricated emitter 4 and is spaced at a predetermined distance from the dummy gate structure 24.

[0155] Specifically, the method for forming the first contact region 16 includes ion implantation or other suitable methods; the method for forming the second contact region 17 includes ion implantation or other suitable methods.

[0156] It should be noted that, while ensuring device performance, the second contact area 17 can be formed before or after the formation of the emitter area 15. Similarly, the second contact area 17 can be formed before, after, or simultaneously with the first contact area 16. Preferably, the first contact area 16 and the second contact area 17 are formed simultaneously.

[0157] Specifically, the second contact region 17 is usually a heavily doped region that forms an ohmic contact with the subsequently fabricated emitter 4. The doping concentration of the second contact region 17 can be selected according to the actual situation while ensuring device performance.

[0158] Specifically, such as Figure 12 As shown, this is a cross-sectional structural diagram after the formation of the interlayer dielectric layer 3. After the formation of the emitter region 15 and before the formation of the gate and emitter 4 of the device, the method further includes the step of forming the interlayer dielectric layer 3 that exposes the upper surface of the semiconductor structure 1, the emitter region 15, the trench gate structure 2 and the dummy gate structure 24.

[0159] It should be noted that when the upper surface layer of the base region 14 has the first contact region 16 and the second contact region 17, the interlayer dielectric layer 3 also covers the exposed upper surface of the first contact region 16 and the second contact region 17.

[0160] Specifically, the methods for forming the interlayer medium layer 3 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0161] Specifically, after forming the interlayer dielectric layer 3 and before forming the gate and emitter 4, the process includes forming a first contact hole 31 and a second contact hole. The first contact hole 31 penetrates the interlayer dielectric layer 3 directly above the emitter region 15 and the second conductive layer 27. The second contact hole penetrates the interlayer dielectric layer 3 directly above the first conductive layer 23. The bottom of the first contact hole 31 exposes the emitter region 15 and the second conductive layer 27, respectively, and the bottom surface of the second contact hole exposes the first conductive layer 23.

[0162] It should be noted that when the first contact area 16 and the second contact area 17 are formed on the upper surface of the base area 14, the bottom of the first contact hole 31 also exposes the first contact area 16 and the second contact area 17.

[0163] Specifically, the method for forming the first contact hole 31 includes dry etching, wet etching, or other suitable methods; the method for forming the second contact hole includes dry etching, wet etching, or other suitable methods.

[0164] Specifically, the emitter 4 fills the first contact hole 31 and is electrically connected to the emitter region 15 and the second conductive layer 27 through the first contact hole 31, and the gate fills the second contact hole and is electrically connected to the first conductive layer 23 through the second contact hole.

[0165] It should be noted that when the bottom of the first contact hole 31 exposes the first contact area 16 and the second contact area 17, the emitter 4 is also electrically connected to the first contact area 16 and the second contact area 17 through the first contact hole 31.

[0166] Specifically, forming the emitter 4 and the gate includes the following steps: forming a metal material layer that fills the first contact hole 31 and the second contact hole and covers the upper surface of the interlayer dielectric layer 3; forming a patterned masking layer on the upper surface of the metal material layer; and etching the metal material layer based on the patterned masking layer to simultaneously form the gate and the emitter 4.

[0167] Specifically, the method for forming a patterned masking layer is the same as the method for creating a patterned photoresist layer in the commonly used photolithography process, which will not be elaborated here; the methods for forming a metal material layer include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; the methods for etching the metal material layer based on the patterned masking layer include dry etching, wet etching, or other suitable methods.

[0168] Specifically, such as Figure 13 The diagram shown is a cross-sectional view of the current collector region 18 after its formation. The methods for forming the current collector region 18 include ion implantation or other suitable methods. The methods for forming the current collector 5 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0169] Specifically, a carrier storage layer 13 and a pseudo-gate structure 24 that penetrates the base region 14 and the carrier storage layer 13 and is electrically connected to the emitter 4 are formed in the semiconductor structure 1. The pseudo-gate structure 24 assists in depleting the carrier storage layer 13, thereby enhancing the conductivity modulation effect during the device's turn-on process, reducing the device's on-resistance, and improving the device's turn-off performance.

[0170] The fabrication method of the superjunction IGBT device in this embodiment forms a pseudo-gate structure 24 that penetrates the base region 14 and the carrier storage layer 13. The pseudo-gate structure 24 is used to assist in the depletion of the carrier storage layer 13, thereby enhancing the conductivity modulation effect during the device's turn-on process, reducing the device's on-resistance, and improving the device's turn-off performance.

[0171] In summary, the superjunction IGBT device and its fabrication method of the present invention improve the device structure by forming a carrier storage layer that isolates the base region and the second pillar on the upper surface of the pillar layer. A pseudo-gate structure is provided in the device, penetrating the base region and the carrier storage layer and extending to the upper surface of the second pillar. The pseudo-gate structure is electrically connected to the emitter. The pseudo-gate structure assists in depleting the carrier storage layer, allowing for a further increase in the doping concentration of the carrier storage layer. This enhances the conductivity modulation effect during device turn-on, reduces the on-state voltage drop, and simultaneously forms a RET structure with a self-biased MOS structure. During device turn-off, as the potential of the carrier storage layer increases, the self-biased MOS structure turns on, forming a hole path, increasing the carrier extraction speed during turn-off, improving the turn-off speed, mitigating the turn-off oscillation problem, and enhancing device performance. By making the pseudo-gate structure adjacent to the trench gate structure, the Miller capacitance C of the device is increased. gc The parasitic capacitance C between the gate and emitter is reduced and increased. ge This invention optimizes the trade-off between conduction and turn-off losses, improving the device's dynamic performance. Simultaneously, by utilizing a dummy gate structure electrically connected to the emitter, holes are attracted to accumulate below the dummy gate structure, preventing voltage overshoot of the trench gate structure during device turn-on and enhancing gate control. Therefore, this invention effectively overcomes various shortcomings of existing technologies and possesses high industrial applicability.

[0172] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A superjunction IGBT device, characterized in that, include: A semiconductor structure includes a first conductivity type substrate, a pillar layer, a first conductivity type carrier storage layer, and a second conductivity type base region stacked sequentially. The pillar layer includes a first conductivity type first pillar and a second conductivity type second pillar arranged alternately and adjacently along the X direction, and the X direction is perpendicular to the stacking direction of the substrate and the pillar layer. The first conductivity type emission region is located on the upper surface of the base region directly above the first pillar and is spaced at a predetermined distance from the second pillar; A trench gate structure extends through the base region and its bottom surface extends into the carrier storage layer. The emitter region is adjacent to the trench gate structure near the sidewall of the trench gate structure. A pseudo-gate structure penetrates the base region and the carrier storage layer directly above the second pillar and extends to the upper surface of the second pillar at its bottom. At least one of the pseudo-gate structures adjacent to the first pillar is adjacent to the trench gate structure. The second conductivity type collector region is located on the lower surface layer of the substrate; The emitter is electrically connected to the emitter region and the pseudo-gate structure; The collector electrode is electrically connected to the current collecting region. The gate is electrically connected to the trench gate structure.

2. The superjunction IGBT device according to claim 1, characterized in that: The doping concentration of the substrate is greater than that of the first pillar.

3. The superjunction IGBT device according to claim 1, characterized in that: The doping concentration of the carrier storage layer is greater than that of the first pillar.

4. The superjunction IGBT device according to claim 1, characterized in that: The trench gate structure includes a first trench, a gate dielectric layer, and a first conductive layer. The first trench penetrates the base region and extends to the carrier storage layer at its bottom. The gate dielectric layer covers the inner wall and bottom surface of the first trench. The first conductive layer fills the first trench and is electrically connected to the gate. The pseudo-gate structure includes a second trench, a dielectric layer, and a second conductive layer. The second trench penetrates the base region and the carrier storage layer and extends to the upper surface of the second pillar. The dielectric layer covers the inner wall and bottom surface of the second trench. The second conductive layer fills the second trench and is electrically connected to the emitter.

5. The superjunction IGBT device according to claim 1, characterized in that: The device also includes a first contact area of ​​a second conductivity type located on the upper surface of the base region directly above the first pillar. The first contact area is adjacent to the sidewall of the trench gate structure and electrically connected to the emitter, away from the emitter region.

6. The superjunction IGBT device according to claim 1, characterized in that: The device also includes a second contact area of ​​a second conductivity type located on the upper surface of the base region directly above the second pillar, and the second contact area is electrically connected to the emitter.

7. The superjunction IGBT device according to claim 6, characterized in that: The second contact area is spaced at a preset distance from the pseudo-gate structure.

8. The superjunction IGBT device according to claim 1, characterized in that: At least two grooved grid structures are provided at intervals directly above the same first column, and at least two pseudo-grid structures are provided at intervals directly above the same second column, with adjacent grooved grid structures and pseudo-grid structures being adjacent to each other.

9. The superjunction IGBT device according to claim 1, characterized in that: The device also includes an interlayer dielectric layer, a first contact hole, and a second contact hole. The interlayer dielectric layer covers the exposed upper surface of the semiconductor structure, the trench gate structure, the dummy gate structure, and the emitter region. The first contact hole penetrates the interlayer dielectric layer directly above the emitter region and the dummy gate structure, and its bottom surface exposes the upper surface of the emitter region and the dummy gate structure. The emitter fills the first contact hole and is electrically connected to the emitter region and the dummy gate structure through the first contact hole. The second contact hole penetrates the interlayer dielectric layer directly above the trench gate structure and its bottom surface exposes the upper surface of the trench gate structure. The gate fills the second contact hole and is electrically connected to the trench gate structure through the second contact hole.

10. A method for fabricating a superjunction IGBT device, characterized in that, Includes the following steps: A semiconductor structure is provided, the semiconductor structure comprising a first conductivity type substrate, a pillar layer, a first conductivity type carrier storage layer and a second conductivity type base region in a sub-stacked manner, the pillar layer comprising a first conductivity type first pillar and a second conductivity type second pillar arranged alternately adjacent to each other along an X direction, the X direction being perpendicular to the stacking direction of the substrate and the pillar layer; A trench gate structure and a pseudo gate structure are formed embedded in the semiconductor structure. The trench gate structure penetrates the base region and extends to the carrier storage layer at its bottom surface. The pseudo gate structure penetrates the base region and the carrier storage layer directly above the second pillar and extends to the upper surface of the second pillar at its bottom surface. At least one pseudo gate structure adjacent to the first pillar is adjacent to the trench gate structure. A first conductivity type emission region is formed on the upper surface of the base region located directly above the first pillar, the emission region being adjacent to the trench gate structure near the sidewall of the trench gate structure; An emitter electrically connected to the emitter region and the pseudo-gate structure, and a gate electrically connected to the trench gate structure are formed; A second conductivity type collector region and a collector electrode electrically connected to the collector region are formed on the lower surface layer of the substrate.

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