Super junction IGBT device and method of manufacturing the same

Abstract

The application provides a super-junction IGBT device and a preparation method thereof. The super-junction IGBT device comprises a semiconductor structure, an emitter region, a first and second trench structure and electrodes. The semiconductor structure comprises a substrate, a column layer, a carrier storage layer and a base region. The column layer comprises first and second columns arranged alternately along the X direction. The emitter region is located on the upper layer of the base region above the first column. The first trench structure penetrates the base region and extends to the carrier storage layer. The emitter region is adjacent to the first trench structure. The second trench structure is embedded in the upper layer of the semiconductor structure and extends to the upper layer of the column layer. At least one second trench structure penetrates the first trench structure, and at least part of the bottom of the second trench structure is located in the first column. The collector region is located on the lower layer of the substrate. The electrodes are electrically connected to the corresponding regions. The application improves the performance of the device by arranging the carrier storage layer and the second trench structure penetrating the carrier storage layer and electrically connected to the emitter.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a superjunction IGBT device and its fabrication method. Background Technology

[0002] IGBT (Insulated Gate Bipolar Transistor) devices are widely used in the power electronics field due to their high input impedance and high current capability. Currently, for trench gate IGBT devices with a carrier storage layer (NCS layer), the breakdown voltage limits the doping concentration of the carrier storage layer. Furthermore, limitations in manufacturing processes and the micro-trench effect make it difficult to further reduce the trench size. Consequently, the trade-off between forward conduction loss and switching loss is difficult to improve. Figure 1 The diagram shows a cross-sectional view of a trench gate IGBT device, including a collector region 01, a field-stop layer 011, a drift region 012, a carrier storage layer 013, a base region 014, an emitter region 015, a P-type contact region 016, a gate trench 02, a gate oxide layer 021, a polysilicon gate 022, an interlayer dielectric layer 03, an emitter 04, and a collector 05. To improve the performance of trench gate IGBT devices, superjunction IGBTs with superjunction structures containing N-type and P-type pillars are introduced into the drift region of the device, such as... Figure 2 The diagram shown is a cross-sectional view of a superjunction IGBT device, which utilizes... Figure 1 The drift region 012 and carrier storage layer 013 of the trench gate IGBT device are replaced with P-type pillars 017 and N-type pillars 018, which improves the trade-off relationship between turn-off loss and conduction loss. However, the concentration of carrier storage layer in the device is still difficult to increase, and the improvement in the trade-off relationship between turn-off loss and conduction loss is limited. At the same time, it also has the problem of excessive turn-off oscillation.

[0003] Therefore, there is an urgent need to find a superjunction IGBT device that can improve the turn-off oscillation and further improve the trade-off relationship between the turn-off loss and the turn-on loss. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a superjunction IGBT device and its fabrication method, which solves the problem that the trade-off relationship between turn-off loss and turn-on loss of IGBT devices in the prior art is difficult to improve and that turn-off oscillation is too large.

[0005] To achieve the above and other related objectives, the present invention provides a superjunction IGBT device, comprising:

[0006] A semiconductor structure includes a first conductivity type substrate, a pillar layer, a first conductivity type carrier storage layer, and a second conductivity type base region stacked sequentially. The pillar layer includes a first conductivity type first pillar and a second conductivity type second pillar arranged alternately adjacent to each other along the X direction, and the X direction is perpendicular to the stacking direction of the substrate and the pillar layer.

[0007] At least one emitter region of a first conductivity type is located on the upper surface of the base region directly above the first pillar;

[0008] The first trench structure penetrates the base region and extends its bottom surface into the carrier storage layer. The emitter region is adjacent to the sidewall of the first trench structure.

[0009] A second trench structure is embedded in the upper surface of the semiconductor structure and extends to the upper surface of the pillar layer. At least one second trench structure penetrates the first trench structure, and at least a portion of the bottom of the second trench structure penetrating the first trench structure is located on the upper surface of the first pillar.

[0010] The second conductivity type collector region is located on the lower surface layer of the substrate.

[0011] The emitter is electrically connected to the emission region and the second trench structure;

[0012] The collector electrode is electrically connected to the current collecting region.

[0013] The gate is electrically connected to the first trench structure.

[0014] Optionally, the doping concentration of the substrate is greater than the doping concentration of the first pillar.

[0015] Optionally, the first trench structure includes a first trench, a first dielectric layer, and a first conductive layer. The first trench penetrates the base region and its bottom surface extends into the carrier storage layer. The first dielectric layer covers the inner wall and bottom surface of the first trench. The first conductive layer fills the first trench and is electrically connected to the gate. The second trench structure includes a second trench, a second dielectric layer, and a second conductive layer. The bottom surface of the second trench extends to the upper surface of the pillar layer. The second dielectric layer covers the inner wall and bottom surface of the second trench. The second conductive layer fills the second trench and is electrically connected to the emitter.

[0016] Optionally, the first trench structure is located directly above the first pillar, the bottom of the second trench structure penetrating the first trench structure is located in the first pillar, and at least one of the second trench structures penetrates the base region and the carrier storage layer directly above the second pillar and extends to the second pillar at its bottom.

[0017] Optionally, the upper surface of the base region is further provided with a second conductive contact area, the contact area being adjacent to the sidewall of the emission area directly above the first post away from the first trench structure, and the sidewall of the contact area away from the emission area being adjacent to the sidewall of the second trench structure directly above the second post.

[0018] Optionally, in the X direction, the second groove structure located directly above the second post and the first groove structure located directly above the first post are arranged alternately.

[0019] Optionally, the first groove structure is located directly above the junction area of ​​the first column and the second column, the second groove structure penetrates the first groove structure, and the bottom of the second groove structure is located on the upper surface of the first column and the second column in the junction area.

[0020] Optionally, the upper surface of the base area directly above the second column is further provided with the emission area, which is adjacent to the sidewall of the first trench structure.

[0021] Optionally, the device further includes an interlayer dielectric layer, a first contact hole, and a second contact hole. The interlayer dielectric layer covers the exposed upper surface of the semiconductor structure, the first trench structure, the second trench structure, and the emitter region. The first contact hole penetrates the interlayer dielectric layer and its bottom surface exposes the emitter region and the upper surface of the second trench structure. The second contact hole penetrates the interlayer dielectric layer and its bottom surface exposes the upper surface of the first trench structure. The emitter fills the first contact hole and is electrically connected to the emitter region and the second trench structure through the first contact hole. The gate fills the second contact hole and is electrically connected to the first trench structure through the second contact hole.

[0022] This invention also provides a method for fabricating a superjunction IGBT device, comprising the following steps:

[0023] A semiconductor structure is provided, comprising a substrate of a first conductivity type, a pillar layer, a carrier storage layer of a first conductivity type, and a base region of a second conductivity type, which are stacked sequentially. The pillar layer includes a first pillar of a first conductivity type and a second pillar of a second conductivity type arranged alternately and adjacently along the X direction, wherein the X direction is perpendicular to the stacking direction of the substrate and the pillar layer.

[0024] A first trench structure and a second trench structure are formed embedded in the upper surface of the semiconductor structure. The first trench structure penetrates the base region and its bottom surface extends into the carrier storage layer. The bottom surface of the second trench structure extends into the upper surface of the pillar layer. At least one second trench structure penetrates the first trench structure, and at least a portion of the bottom of the second trench structure penetrating the first trench structure is located on the upper surface of the first pillar.

[0025] At least one first conductivity type emission region is formed on the upper surface of the base region located directly above the first pillar, the emission region being adjacent to the first trench structure near the sidewall of the first trench structure;

[0026] An emitter electrically connected to the emitter region and the second trench structure, and a gate electrically connected to the first trench structure are formed.

[0027] A second conductivity type collector region and a collector electrode electrically connected to the collector region are formed on the lower surface layer of the substrate.

[0028] As described above, the superjunction IGBT device and its fabrication method of the present invention, by setting a carrier storage layer and a second trench structure penetrating the first trench structure and the carrier storage layer in the device, utilizes the second trench structure to attract holes, causing the holes to accumulate below the first trench structure, thereby reducing the voltage overshoot of the first trench structure during the device turn-on phase and improving the gate control capability of the device. At the same time, by utilizing the second trench structure to penetrate the first trench structure, the Miller capacitance C of the device is reduced. gc Increase the parasitic capacitance C between the gate and emitter. ge This improves the trade-off relationship between turn-off and turn-on losses in the device. Furthermore, the second trench structure can assist in depleting the carrier storage layer, enhancing the carrier storage effect and subsequently strengthening the conductivity modulation effect during turn-on, further reducing the on-state voltage drop. By setting a second trench structure that penetrates the base region and the carrier storage layer in the device, a self-biased MOS structure is formed. During device turn-off, a hole extraction channel is created, accelerating the carrier extraction speed and increasing the turn-off speed. This improves the turn-off oscillation problem, enhances device performance, and has high industrial application value. Attached Figure Description

[0029] Figure 1 The diagram shows a cross-sectional view of a trench gate IGBT device.

[0030] Figure 2 The diagram shows a cross-sectional view of a superjunction IGBT device.

[0031] Figure 3 The diagram shown is a cross-sectional view of the superjunction IGBT device of the present invention.

[0032] Figure 4 The diagram shown is a schematic cross-sectional view of another superjunction IGBT device according to the present invention.

[0033] Figure 5 This diagram shows a third cross-sectional structure of the superjunction IGBT device of the present invention.

[0034] Figure 6 The diagram shows the process flow of the fabrication method of the superjunction IGBT device of the present invention.

[0035] Figure 7 The diagram shows a cross-sectional view of the semiconductor structure used in the fabrication method of the superjunction IGBT device of the present invention.

[0036] Figure 8 The diagram shows a cross-sectional structure after the formation of the first trench in the fabrication method of the superjunction IGBT device of the present invention.

[0037] Figure 9 The diagram shown is a cross-sectional view of the superjunction IGBT device fabrication method of the present invention after the formation of the first trench structure.

[0038] Figure 10 The diagram shows a cross-sectional structure after the formation of the second trench in the fabrication method of the superjunction IGBT device of the present invention.

[0039] Figure 11 The diagram shows a cross-sectional view of the superjunction IGBT device fabrication method of the present invention after the formation of the second trench structure.

[0040] Figure 12 The diagram shown is a cross-sectional view of the superjunction IGBT device fabrication method of the present invention after the formation of the interlayer dielectric layer.

[0041] Figure 13 The diagram shows a cross-sectional structure of the superjunction IGBT device after the emitter is formed, as shown in the fabrication method of the present invention.

[0042] Figure 14 The diagram shows a cross-sectional structure of the superjunction IGBT device after the collector region is formed, according to the fabrication method of the present invention.

[0043] Explanation of icon numbers

[0044] 01 Collection Area

[0045] 011 Field Cutoff Layer

[0046] 012 Drift Zone

[0047] 013 Carrier Storage Layer

[0048] 014 Base Area

[0049] Launch Area 015

[0050] 016 P-type contact area

[0051] 017 P-type column

[0052] 018 N-type column

[0053] 02 Gate Trench

[0054] 021 Gate oxide layer

[0055] 022 Polysilicon gate

[0056] 03 Interlayer Dielectric Layer

[0057] 04 Emitter

[0058] 05 Collector

[0059] 1. Semiconductor Structure

[0060] 11 Substrate

[0061] 12 column layers

[0062] 121 First Pillar

[0063] 122 Second Column

[0064] 13 Carrier Storage Layer

[0065] 14 base regions

[0066] Launch Area 15

[0067] 16 Contact Area

[0068] 17 Collection Area

[0069] 2 First trench structure

[0070] 21 First trench

[0071] 22 First dielectric layer

[0072] 23 First conductive layer

[0073] 24 Second trench structure

[0074] 25 Second trench

[0075] 26 Second dielectric layer

[0076] 27 Second conductive layer

[0077] 3 Interlayer dielectric layer

[0078] 31 First contact hole

[0079] 4 Emitter

[0080] 5 collectors Detailed Implementation

[0081] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0082] Please see Figures 3 to 14 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0083] Example 1

[0084] This embodiment provides a superjunction IGBT device, such as Figures 3 to 5 The diagrams shown are schematic cross-sectional views of several types of the superjunction IGBT device, including a semiconductor structure 1, a first conductivity type emitter region 15, a first trench structure 2, a second trench structure 24, a second conductivity type collector region 17, an emitter 4, a collector 5, and a gate. The semiconductor structure 1 includes a first conductivity type substrate 11, a pillar layer 12, a first conductivity type carrier storage layer 13, and a second conductivity type base region 14, stacked sequentially. The pillar layer 12 includes a first conductivity type first pillar 121 and a second conductivity type second pillar 122, arranged alternately and adjacently along the X-direction, perpendicular to the stacking direction of the substrate 11 and the pillar layer 12. At least one emitter region 15 is located on the first pillar 121. The base region 14 is located on the upper surface of the substrate 11. A first trench structure 2 penetrates the base region 14 and extends to the carrier storage layer 13 at its bottom. The emitter region 15 is adjacent to the sidewall of the first trench structure 2. A second trench structure 24 is embedded in the upper surface of the semiconductor structure 1 and extends to the upper surface of the pillar layer 12 at its bottom. At least one second trench structure 24 penetrates the first trench structure 2, and at least a portion of the bottom of the second trench structure 24 penetrating the first trench structure 2 is located on the upper surface of the first pillar 121. A collector region 17 is located on the lower surface of the substrate 11. An emitter 4 is electrically connected to the emitter region 15 and the second trench structure 24. A collector 5 is electrically connected to the collector region 17. A gate is electrically connected to the first trench structure 2.

[0085] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0086] Specifically, substrate 11 is typically used as a process platform for fabricating pillar layer 12 and semiconductor layer for forming collector region 17. The size, shape and thickness of substrate 11 can be selected according to actual conditions while ensuring device performance.

[0087] It should be noted that the doping concentration of substrate 11 is greater than that of the first pillar 121, and substrate 11 is usually a heavily doped region, so as to serve as the field cutoff layer of the device after the collector region 17 is formed, thereby reducing the on-resistance and saturation voltage drop of the device.

[0088] Specifically, while ensuring device performance, the doping concentration of substrate 11 can be selected according to the actual situation.

[0089] Specifically, the height of the first pillar 121 and the second pillar 122 (i.e. the thickness of the pillar layer 12) is usually related to the breakdown voltage of the device. By adjusting the height of the first pillar 121 and the second pillar 122 and the doping concentration, devices with different breakdown voltage levels can be formed.

[0090] Specifically, while ensuring device performance, the size, shape, height, and doping concentration of the first pillar 121 can be selected according to actual conditions; the size, shape, height, and doping concentration of the second pillar 122 can also be selected according to actual conditions. Here, the size refers to the cross-sectional dimension of the first pillar 121 (second pillar 122) perpendicular to the stacking direction of the substrate 11 and the pillar layer 12, and the height refers to the distance from the bottom surface of the first pillar 121 (second pillar 122) to the top surface.

[0091] Specifically, by alternating the arrangement of the first pillar 121 and the second pillar 122, the electric field distribution of the device in the stacking direction of the substrate 11 and the pillar layer 12 can be optimized. The lateral depletion of the superjunction pillars can be used to enhance the extraction of charge carriers in the device, thereby improving the device's voltage withstand capability and switching speed.

[0092] It should be noted that the carrier storage layer 13 is usually a heavily doped film layer used to reduce the on-state voltage drop of the device. While ensuring device performance, the thickness and doping concentration of the carrier storage layer 13 can be selected according to the actual situation.

[0093] Specifically, the base region 14 is used to form the conductive channel of the device. It is usually a lightly doped region. While ensuring device performance, the thickness and doping concentration of the base region 14 can be selected according to the actual situation.

[0094] Specifically, the contact type between emitter region 15 and emitter 4 is an ohmic contact. While ensuring device performance, the shape, size, thickness, and doping concentration of emitter region 15 can be selected according to actual conditions. Here, thickness refers to the distance between the upper and lower surfaces of emitter region 15.

[0095] As an example, the first trench structure 2 includes a first trench 21, a first dielectric layer 22, and a first conductive layer 23. The first trench 21 penetrates the base region 14 and its bottom surface extends into the carrier storage layer 13. The first dielectric layer 22 covers the inner wall and bottom surface of the first trench 21. The first conductive layer 23 fills the first trench 21 and is electrically connected to the gate. The second trench structure 24 includes a second trench 25, a second dielectric layer 26, and a second conductive layer 27. The bottom surface of the second trench 25 extends to the upper surface of the pillar layer 12. The second dielectric layer 26 covers the inner wall and bottom surface of the second trench 25. The second conductive layer 27 fills the second trench 25 and is electrically connected to the emitter 4.

[0096] Specifically, while ensuring device performance, the opening size and shape of the first trench 21 can be selected according to actual conditions; the distance between the bottom surface of the first trench 21 and the bottom surface of the carrier storage layer 13 can be selected according to actual conditions; the thickness of the first dielectric layer 22 can be selected according to actual conditions; the opening size and shape of the second trench 25 can be selected according to actual conditions; the distance between the bottom surface of the second trench 25 and the upper surface of the pillar layer 12 can be selected according to actual conditions; and the thickness of the second dielectric layer 26 can be selected according to actual conditions.

[0097] Specifically, the material of the first dielectric layer 22 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the material of the first conductive layer 23 includes polysilicon or other suitable conductive materials; the material of the second dielectric layer 26 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; and the material of the second conductive layer 27 includes polysilicon or other suitable conductive materials.

[0098] As an example, the first trench structure 2 is located directly above the first pillar 121, and the bottom of the second trench structure 24 penetrating the first trench structure 2 is located in the first pillar 121. At least one second trench structure 24 penetrates the base region 14 and the carrier storage layer 13 directly above the second pillar 122 and extends its bottom into the second pillar 122. That is, the first trench structure 2 is located directly above the first pillar 121, the second trench structure 24 located directly above the first pillar 121 penetrates the first trench structure 2, and at least one second trench structure 24 is provided directly above the second pillar 122 on both sides of the first pillar 121 in the X direction. Preferably, when the first trench structure 2 is located directly above the first pillar 121, the second trench structure 24 located directly above the first pillar 121 penetrates the first trench structure 2, and each of the two second pillars 122 on both sides of the first pillar 121 has a second trench structure 24 whose bottom surface extends into the second pillar 122.

[0099] It should be noted that when the first trench structure 2 is located directly above the first pillar 121, and the second trench structure 24 located directly above the first pillar 121 penetrates the first trench structure 2, the second trench 25 penetrates the first conductive layer 23, the first dielectric layer 22 at the bottom of the first trench 21, and the carrier storage layer 13 below the first trench 21, with its bottom surface extending to the upper surface of the first pillar 121. The second dielectric layer 26 covers the first conductive layer 23 exposed on the inner wall of the second trench 25 and the semiconductor structure 1 exposed on the inner wall and bottom surface. The second dielectric layer 26 also wraps around the sidewalls and bottom surface of the second conductive layer 27. The second trench 25 located directly above the second pillar 122 penetrates the base region 14 and the carrier storage layer 13, with its bottom surface extending to the upper surface of the second pillar 122. The second dielectric layer 26 in the second trench structure 24 located directly above the second pillar 122 covers the semiconductor structure 1 exposed on the inner wall and bottom surface of the second trench 25.

[0100] Specifically, when the first trench structure 2 is located directly above the first post 121, and the second trench structure 24 directly above the first post 121 penetrates the first trench structure 2, and when at least one second trench structure 24 is provided directly above the second post 122, the distance between the second trench structure 24 directly above the second post 122 and the first trench structure 2 directly above the first post 121 can be selected according to the actual situation, while ensuring the performance of the device.

[0101] As an example, the upper surface of the base region 14 is further provided with a second conductive contact region 16. The contact region 16 is adjacent to the sidewall of the emitter region 15 directly above the first pillar 121, away from the sidewall of the first trench structure 2. The sidewall of the contact region 16 away from the emitter region 15 is adjacent to the sidewall of the second trench structure 24 directly above the second pillar 122. That is, the first trench structure 2 is located directly above the first pillar 121, and the second trench structure 24 directly above the first pillar 121 penetrates the first trench structure 2. A second trench structure 24 is provided directly above each of the two second pillars 122 on both sides of the first pillar 121 along the X direction. The sidewall of the contact region 16 away from the emitter region 15 is adjacent to the sidewall of the second trench structure 24 directly above the second pillar 122. Figure 3 As shown.

[0102] It should be noted that the contact area 16 is usually electrically connected to the emitter 4, and the contact type between the contact area 16 and the emitter 4 is an ohmic contact.

[0103] Specifically, the first trench structure 2 is located directly above the first pillar 121, and the second trench structure 24 directly above the first pillar 121 penetrates the first trench structure 2. When a second trench structure 24 is provided directly above each of the two second pillars 122 on both sides of the first pillar 121 along the X direction, the distance between the first trench structure 2 and the second trench structure 24 directly above the second pillar 122 can be selected according to the actual situation while ensuring device performance. The size, shape, thickness and doping concentration of the contact area 16 can be selected according to the actual situation.

[0104] As an example, in the X direction, the second groove structure 24 located directly above the second post 122 and the first groove structure 2 located directly above the first post 121 are arranged alternately, that is, when the first groove structure 2 is directly above the first post 121, the first groove structure 2 directly above the first post 121 and the second groove structure 24 directly above the second post 122 are arranged alternately along the X direction. Preferably, in the X direction, the second groove structure 24 directly above the second post 122 and the first groove structure 2 directly above the first post 121 are arranged in a periodic alternation.

[0105] Specifically, the second trench structure 24 is located directly above the second pillar 122, and when the contact area 16 is adjacent to the sidewall of the first trench structure 2 directly above the first pillar 121, the second trench structure 24 independently forms a RET (Recessed-Emitter-Trench) structure. The RET structure constitutes a self-biased MOS structure. When the device is turned off, as the potential of the second pillar 122 increases, the self-biased MOS structure turns on, thereby forming a hole channel in the carrier storage layer 13 near the second trench structure 24, which promotes the extraction of carriers when the device is turned off and improves the turn-off speed of the device.

[0106] As an example, the first groove structure 2 is located directly above the junction area of ​​the first column 121 and the second column 122. The second groove structure 24 penetrates the first groove structure 2, and the bottom of the second groove structure 24 is located on the upper surface of the junction area of ​​the first column 121 and the second column 122. That is, the first groove structure 2 is located directly above the junction area of ​​the first column 121 and the second column 122, and the second groove structure 24 is also located directly above the junction area of ​​the first column 121 and the second column 122 and penetrates the first groove structure 2. Figure 4 As shown.

[0107] Specifically, the first trench structure 2 and the second trench structure 24 are both located directly above the junction area of ​​the first post 121 and the second post 122, and the second trench structure 24 penetrates the first trench structure 2. The upper surface of the base area 14 directly above the first post 121 is provided with a contact area 16 electrically connected to the emitter 4. The emitter area 15 is located on the upper surface of the base area 14 directly above the first post 121 between two adjacent first trench structures 2. The contact area 16 directly above the first post 121 is adjacent to the side wall of the emitter area 15 away from the first trench structure 2.

[0108] As an example, the upper surface of the base region 14 directly above the second pillar 122 is also provided with an emission region 15. This emission region 15 is adjacent to the sidewall of the first trench structure 2, meaning that both the first trench structure 2 and the second trench structure 24 are located directly above the junction area of ​​the first pillar 121 and the second pillar 122. When the second trench structure 24 penetrates the first trench structure 2, the upper surface of the base region 14 directly above the second pillar 122 between two adjacent first trench structures 2 is provided with an emission region 15. This emission region 15 is adjacent to the sidewall of the first trench structure 2 and is electrically connected to the emitter 4. Figure 5 As shown.

[0109] Specifically, both the first trench structure 2 and the second trench structure 24 are located directly above the junction area of ​​the first post 121 and the second post 122. When the second trench structure 24 penetrates the first trench structure 2, the number of conductive channels in the device can be increased and the power density of the device can be improved by setting an emitter region 15 electrically connected to the emitter 4 on the upper surface of the base region 14 directly above the second post 122 between two adjacent first trench structures 2.

[0110] Specifically, both the first trench structure 2 and the second trench structure 24 are located directly above the junction area of ​​the first post 121 and the second post 122. When the second trench structure 24 penetrates the first trench structure 2, the upper surface of the base area 14 directly above the second post 122 between two adjacent first trench structures 2 is also provided with a contact area 16 electrically connected to the emitter 4. The contact type between the contact area 16 and the emitter 4 is an ohmic contact. At the same time, the contact area 16 is adjacent to the side wall of the emitter area 15 directly above the second post 122, away from the first trench structure 2.

[0111] As an example, the device also includes an interlayer dielectric layer 3, a first contact hole 31, and a second contact hole. The interlayer dielectric layer 3 covers the exposed upper surfaces of the semiconductor structure 1, the first trench structure 2, the second trench structure 24, and the emitter region 15. The first contact hole 31 penetrates the interlayer dielectric layer 3 and exposes the upper surfaces of the emitter region 15 and the second trench structure 24 on its bottom surface. The second contact hole penetrates the interlayer dielectric layer 3 and exposes the upper surface of the first trench structure 2 on its bottom surface. The emitter 4 fills the first contact hole 31 and is electrically connected to the emitter region 15 and the second trench structure 24 through the first contact hole 31. The gate fills the second contact hole and is electrically connected to the first trench structure 2 through the second contact hole. Here, the upper surface of the second trench structure 24 exposed on the bottom surface of the first contact hole 31 is the upper surface of the second conductive layer 27 in the second trench structure 24, and the upper surface of the first trench structure 2 exposed on the bottom surface of the second contact hole is the upper surface of the first conductive layer 23 in the first trench structure 2. That is, the emitter 4 is electrically connected to the second conductive layer 27, and the gate is electrically connected to the first conductive layer 23.

[0112] It should be noted that when the upper surface of the base region 14 has a contact region 16, the interlayer dielectric layer 3 also covers the exposed upper surface of the contact region 16, and the bottom surface of the first contact hole 31 also exposes the contact region 16. The emitter 4 is electrically connected to the contact region 16 through the first contact hole 31.

[0113] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 3 can be selected according to the actual situation; the opening size and opening shape of the first contact hole 31 can be selected according to the actual situation; the opening size and opening shape of the second contact hole can be selected according to the actual situation.

[0114] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0115] Specifically, the emitter 4 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the gate is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials.

[0116] Specifically, collector 5 covers the side of collector region 17 facing away from pillar layer 12. The contact type between collector region 17 and collector 5 is ohmic contact. While ensuring device performance, the size, shape, thickness, and doping concentration of collector region 17 can be selected according to actual conditions. Here, thickness refers to the distance between the upper and lower surfaces of collector region 17.

[0117] Specifically, the material of collector 5 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials.

[0118] Specifically, by setting a carrier storage layer 13 and a second trench structure 24 extending from the bottom surface to the upper surface of the pillar layer 12 and electrically connected to the emitter 4 in the semiconductor structure 1, the electric field inside the device is optimized by utilizing the superjunction structure. The second trench structure 24 assists in depleting the carrier storage layer 13, making the wafer for fabricating the device thinner, and the doping concentration of the carrier storage layer 13 can be further increased, enhancing the carrier storage effect of the device, thereby enhancing the conductivity modulation effect during the device conduction process, and making the on-state voltage drop of the device lower.

[0119] Specifically, by making the second trench structure 24 penetrate the first trench structure 2, the Miller capacitance C can be reduced by utilizing the coupling between the first trench structure 2 and the second trench structure 24. gc Increase the parasitic capacitance C between the gate and emitter 4 of the device. ge This optimizes the trade-off relationship between turn-off loss and turn-on loss of the device, improves the dynamic performance of the device, and at the same time, the attraction of holes by the second trench structure 24 allows most of the displacement current to flow into the second trench structure 24, reducing the hole displacement current of the first trench structure 2, avoiding voltage overshoot of the first trench structure 2 during the device turn-on stage, and enhancing the gate control capability of the device.

[0120] Specifically, by setting a RET structure that penetrates the carrier storage layer 13 and forms a self-biased MOS structure directly above the second pillar 122, during the device turn-off process, as the potential of the carrier storage layer 13 increases, the MOS structure turns on, and a hole pathway is formed near the second trench structure 24 in the RET structure. This pathway, together with the lateral depletion region formed by the superstructure, further accelerates the carrier extraction speed during the device turn-off process, improves the device turn-off speed, alleviates the device turn-off oscillation problem, and enhances the device performance.

[0121] The superjunction IGBT device of this embodiment incorporates a carrier storage layer 13 and a second trench structure 24 that penetrates the carrier storage layer 13 and extends to the pillar layer 12 at its bottom surface within the semiconductor structure 1. At least one second trench structure 24 penetrates the first trench structure 2. The second trench structure 24, penetrating the carrier storage layer 13, assists in depleting the carrier storage layer 13, allowing for a higher doping concentration in the carrier storage layer 13. This enhances the carrier storage effect of the device, improves the conductivity modulation effect during device conduction, and further reduces the on-state voltage drop. Simultaneously, by setting a second trench structure 24 directly above the second pillar 122, penetrating the base region 14 and the carrier storage layer 13, this second trench structure 24 constitutes a RET structure with a self-biased MOS structure. During device turn-off, as the potential of the carrier storage layer 13 increases, the self-biased MOS structure turns on, forming a hole pathway near the second trench structure 24 in the RET structure. This accelerates the carrier extraction speed during turn-off, improves the device turn-off speed, alleviates the device turn-off oscillation problem, and enhances device performance. Furthermore, by making at least one second trench structure 24 penetrate the first trench structure 2, the Miller capacitance C of the device is reduced. gc This increases the parasitic capacitance C between the gate and emitter 4 of the device. ge This optimizes the trade-off relationship between turn-off loss and turn-on loss of the device, improves the dynamic performance of the device, and at the same time, by attracting holes through the bottom of the second trench structure 24 that penetrates the first trench structure 2, the hole displacement current of the first trench structure 2 is reduced, the voltage overshoot of the first trench structure 2 during the turn-on phase of the device is avoided, and the gate control capability of the device is enhanced.

[0122] Example 2

[0123] This embodiment also provides a method for fabricating a superjunction IGBT device, such as... Figure 6 The diagram shown is a process flow chart of the fabrication method of the superjunction IGBT device, including the following steps:

[0124] S1: A semiconductor structure is provided, comprising a first conductivity type substrate, a pillar layer, a first conductivity type carrier storage layer and a second conductivity type base region stacked sequentially, wherein the pillar layer comprises a first conductivity type first pillar and a second conductivity type second pillar arranged alternately adjacent to each other along the X direction, and the X direction is perpendicular to the stacking direction of the substrate and the pillar layer;

[0125] S2: Form a first trench structure and a second trench structure embedded in the upper surface of the semiconductor structure. The first trench structure penetrates the base region and its bottom surface extends into the carrier storage layer. The bottom surface of the second trench structure extends into the upper surface of the pillar layer. At least one second trench structure penetrates the first trench structure, and at least a portion of the bottom of the second trench structure penetrating the first trench structure is located on the upper surface of the first pillar.

[0126] S3: Form at least one first conductivity type emission region on the upper surface of the base region located directly above the first pillar, the emission region being adjacent to the first trench structure near the sidewall of the first trench structure;

[0127] S4: Form an emitter electrically connected to the emitter region and the second trench structure, and a gate electrically connected to the first trench structure;

[0128] S5: Form a second conductivity type collector region located on the lower surface of the substrate and a collector electrode electrically connected to the collector region.

[0129] Please see Figures 7 to 11 Steps S1 and S2 are performed as follows: A semiconductor structure 1 is provided, comprising a first conductivity type substrate 11, a pillar layer 12, a first conductivity type charge carrier storage layer 13, and a second conductivity type base region 14 stacked sequentially. The pillar layer 12 includes a first conductivity type first pillar 121 and a second conductivity type second pillar 122 arranged alternately and adjacently along the X direction, with the X direction perpendicular to the stacking direction of the substrate 11 and the pillar layer 12. A first trench structure 2 and a second trench structure 24 are formed embedded in the upper surface of the semiconductor structure 1. The first trench structure 2 penetrates the base region 14 and extends to the charge carrier storage layer 13 at its bottom surface. The second trench structure 24 penetrates the base region 14 and the charge carrier storage layer 13 and extends to the upper surface of the pillar layer 12 at its bottom surface. At least one second trench structure 24 penetrates the first trench structure 2, and at least a portion of the bottom of the second trench structure 24 penetrating the first trench structure 2 is located on the upper surface of the first pillar 121.

[0130] Specifically, such as Figure 7 The diagram shows a cross-sectional view of semiconductor structure 1. The substrate 11 is made of materials including silicon, silicon germanium, silicon carbide, gallium nitride, diamond, or other suitable materials.

[0131] Specifically, the pillar layer 12 is usually a homogeneous epitaxial layer of the substrate 11, the carrier storage layer 13 is a homogeneous epitaxial layer of the pillar layer 12, and the base region 14 is a homogeneous layer or a homogeneous epitaxial layer of the carrier storage layer 13.

[0132] It should be noted that the pillar layer 12 in the semiconductor structure 1 is usually formed by combining multiple epitaxial processes and multiple implantation processes. During the fabrication of the pillar layer 12, after each epitaxial layer of the first conductivity type is formed by the epitaxial process, ion implantation is performed on the region corresponding to the second pillar 122 in the epitaxial layer to form the doped layer constituting the first pillar 121 and the doped layer constituting the second pillar 122. The region that is not ion implanted is the region corresponding to the first pillar 121 in each epitaxial layer.

[0133] Specifically, the pillar layer 12 is formed by combining multiple epitaxial growths with multiple ion implantations. This process offers high flexibility, allowing for different numbers of epitaxial growths and ion implantations to be used depending on the voltage level. Furthermore, the number of epitaxial growths, the ion implantation dose, and the thickness of the pillar layer 12 during the fabrication process are related to the voltage level of the device to be fabricated, and are not limited here.

[0134] It should be noted that, in order to improve the quality of the fabricated carrier storage layer 13, the carrier storage layer 13 in the semiconductor structure 1 is fabricated using a concentration epitaxial process. While ensuring device performance, the carrier storage layer 13 can also be formed using an ion implantation process.

[0135] Specifically, the methods for forming the base region 14 include ion implantation or other suitable methods.

[0136] Specifically, the first trench structure 2 includes a first trench 21, a first dielectric layer 22, and a first conductive layer 23. The first trench 21 penetrates the base region 14 and extends to the carrier storage layer 13 at its bottom. The first dielectric layer 22 covers the inner wall and bottom surface of the first trench 21. The first conductive layer 23 fills the first trench 21 and is electrically connected to the gate. The second trench structure 24 includes a second trench 25, a second dielectric layer 26, and a second conductive layer 27. The bottom surface of the second trench 25 extends to the pillar layer 12. The second dielectric layer 26 covers the inner wall and bottom surface of the second trench 25. The second conductive layer 27 fills the second trench 25 and is electrically connected to the emitter 4.

[0137] Specifically, such as Figure 8 , Figure 9 , Figure 10 and Figure 11The figures shown are cross-sectional structural diagrams after the formation of the first trench 21, the first trench structure 2, the second trench 25, and the second trench structure 24, respectively. The formation of the first trench structure 2 and the second trench structure 24 includes the following steps: forming a shielding layer with a pattern of the first trench 21 on the upper surface of the semiconductor structure 1, and forming a first trench 21 based on the shielding layer, penetrating the base region 14 and extending to the carrier storage layer 13 at its bottom surface; sequentially forming a first dielectric layer 22 covering the inner wall and bottom surface of the first trench 21 and a first conductive layer 23 filling the first trench 21, wherein the first dielectric layer 22 encloses the sidewalls and bottom surface of the first conductive layer 23 filling the first trench 21; the first trench 21 and the first dielectric layer 22 are then formed. Layer 22 and the first conductive layer 23 constitute the first trench structure 2; a shielding layer with a second trench 25 pattern is formed on the upper surface of the semiconductor structure 1, and a second trench 25 extending to the pillar layer 12 is formed based on the shielding layer, and at least one second trench 25 penetrates the first conductive layer 23, the first dielectric layer 22 located on the bottom surface of the first trench 21, and the carrier storage layer 13 directly below the first trench 21, and at least a portion of the bottom surface of the second trench 25 is located in the first pillar 121; a second dielectric layer 26 covering the inner wall and bottom surface of the second trench 25 and a second conductive layer 27 filling the second trench 25 are formed in sequence, the second dielectric layer 26 wrapping the sidewall and bottom surface of the second conductive layer 27, and the second trench 25, the second dielectric layer 26 and the second conductive layer 27 constitute the second trench structure 24.

[0138] Specifically, the method for forming the masking layer with the first groove 21 pattern is a commonly used photolithography process, which will not be described in detail here; the method for forming the masking layer with the second groove 25 pattern is a commonly used photolithography process, which will not be described in detail here.

[0139] Specifically, the method for forming the first trench 21 includes dry etching, wet etching, or other suitable methods; the method for forming the second trench 25 includes dry etching, wet etching, or other suitable methods.

[0140] It should be noted that after forming the first trench 21 and before forming the first dielectric layer 22, the process includes a step of removing the masking layer with the pattern of the first trench 21. The method for removing the masking layer is a commonly used method for removing hard masking layers, which will not be described in detail here. Similarly, after forming the second trench 25 and before forming the second dielectric layer 26, the process includes a step of removing the masking layer with the pattern of the second trench 25. The method for removing the masking layer is a commonly used method for removing hard masking layers, which will not be described in detail here.

[0141] Specifically, the method for forming the first dielectric layer 22 includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the second dielectric layer 26 includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods. Preferably, both the first dielectric layer 22 and the second dielectric layer 26 are fabricated using a thermal oxidation process.

[0142] It should be noted that the first dielectric layer 22 also covers the exposed upper surface of the semiconductor structure 1. After the formation of the first dielectric layer 22 and before the formation of the first conductive layer 23, the process includes forming a first conductive material layer that fills the first trench 21 and covers the upper surface of the first dielectric layer 22 directly above the semiconductor structure 1, and removing the first conductive material layer covering the upper surface of the first dielectric layer 22 directly above the semiconductor structure 1. The remaining first conductive material layer filling the first trench 21 serves as the first conductive layer 23. Since the first dielectric layer 22 covering the upper surface of the semiconductor structure 1 is usually not removed during the formation of the first conductive layer 23, the second dielectric layer formed by the thermal oxidation process... The second dielectric layer 26 does not cover the upper surface of the first dielectric layer 22 directly above the semiconductor structure 1, and the second dielectric layer 26 formed by thermal oxidation covers the inner wall and bottom surface of the second trench 25 but does not cover the first dielectric layer 22 exposed on the inner wall of the second trench 25. After the formation of the second dielectric layer 26 and before the formation of the second conductive layer 27, the process includes the steps of forming a second conductive material layer that fills the second trench 25 and covers the upper surface of the first dielectric layer 22 directly above the semiconductor structure 1, and removing the second conductive material layer that covers the upper surface of the first dielectric layer 22 directly above the semiconductor structure 1. The remaining second conductive material layer that fills the second trench 25 is used as the second conductive layer 27.

[0143] Specifically, the methods for forming the first conductive material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods; the methods for forming the second conductive material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods; the methods for removing the first conductive material layer on the upper surface of the first dielectric layer 22 covering the semiconductor structure 1 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods; and the methods for removing the second conductive material layer on the upper surface of the first dielectric layer 22 covering the semiconductor structure 1 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods.

[0144] Specifically, when the first trench structure 2 is located directly above the first pillar 121, the bottom of the second trench structure 24 penetrating the first trench structure 2 is located on the upper surface of the first pillar 121, and at least one second pillar 122 adjacent to the first pillar 121 in the X direction is formed directly above a second trench structure 24. The second trench structure 24 located directly above the second pillar 122 penetrates the base region 14 and the carrier storage layer 13 directly above the second pillar 122, and the bottom surface of the second trench structure 24 extends to the upper surface of the second pillar 122.

[0145] Specifically, when the first trench structure 2 is located directly above the junction area of ​​the first pillar 121 and the second pillar 122 in the pillar layer 12, the second trench structure 24 penetrates the first trench structure 2 and the carrier storage layer 13 directly below the first trench structure 2. The bottom of the second trench structure 24 extends to the upper surface of the pillar layer 12, and part of the bottom area of ​​the second trench structure 24 is located in the first pillar 121, while another part is located in the second pillar 122.

[0146] Please see Figures 12 to 14 Steps S3, S4 and S5 are executed: at least one first conductivity type emitter region 15 is formed on the upper surface of the base region 14 located directly above the first pillar 121, the emitter region 15 is adjacent to the sidewall of the first trench structure 2; an emitter 4 electrically connected to the emitter region 15 and the second trench structure 24 and a gate electrically connected to the first trench structure 2 are formed; a second conductivity type collector region 17 is formed on the lower surface of the substrate 11 and a collector electrode 5 electrically connected to the collector region 17.

[0147] Specifically, the methods for forming the emission region 15 include ion implantation or other suitable methods.

[0148] Specifically, when the first trench structure 2 is located directly above the junction area of ​​the first column 121 and the second column 122 in the column layer 12, the emission area 15 can also be located on the upper surface of the base area 14 directly above the second column 122, and the sidewall of the emission area 15 located directly above the second column 122 is adjacent to the first trench structure 2.

[0149] Specifically, after forming the first trench structure 2 and the second trench structure 24, and before forming the gate and emitter 4 of the device, the step of forming a second conductivity type contact region 16 located on the upper surface of the base region 14 is included. The contact region 16 is adjacent to the sidewall of the emitter region 15 away from the first trench structure 2.

[0150] Specifically, the methods for forming the contact region 16 include ion implantation or other suitable methods.

[0151] It should be noted that when the first trench structure 2 is located directly above the first column 121 and the second trench structure 24 is formed directly above the second column 122, the sidewall of the contact area 16 away from the emission area 15 is adjacent to the second trench structure 24. When the first trench structure 2 is located directly above the junction area of ​​the first column 121 and the second column 122 in the column layer 12, and the emission area 15 is formed directly above the second column 122, the upper surface layer of the base area 14 directly above the second column 122 also forms a contact area 16, and the contact area 16 is adjacent to the sidewall of the emission area 15 away from the first trench structure 2.

[0152] Specifically, such as Figure 12 The diagram shown is a cross-sectional view of the structure after the interlayer dielectric layer 3 is formed. After the emitter region 15 and the contact region 16 are formed, and before the gate and emitter 4 of the device are formed, the method further includes forming an interlayer dielectric layer 3 that exposes the upper surface of the semiconductor structure 1, the emitter region 15, the contact region 16, the first trench structure 2 and the second trench structure 24.

[0153] Specifically, the methods for forming the interlayer medium layer 3 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0154] Specifically, after forming the interlayer dielectric layer 3 and before forming the gate and emitter 4, the process includes forming a first contact hole 31 and a second contact hole. The first contact hole 31 penetrates the interlayer dielectric layer 3 directly above the emitter region 15, the contact region 16 and the second conductive layer 27. The second contact hole penetrates the interlayer dielectric layer 3 directly above the first conductive layer 23. The bottom of the first contact hole 31 exposes the emitter region 15, the contact region 16 and the second conductive layer 27, respectively. The bottom surface of the second contact hole exposes the first conductive layer 23.

[0155] Specifically, the method for forming the first contact hole 31 includes dry etching, wet etching, or other suitable methods; the method for forming the second contact hole includes dry etching, wet etching, or other suitable methods.

[0156] Specifically, the emitter 4 fills the first contact hole 31 and is electrically connected to the emitter region 15, the contact region 16 and the second conductive layer 27 through the first contact hole 31, respectively. The gate fills the second contact hole and is electrically connected to the first conductive layer 23 through the second contact hole.

[0157] Specifically, such as Figure 13 The diagram shown is a cross-sectional view of the emitter 4 after its formation. The formation of the emitter 4 and the gate includes the following steps: forming a metal material layer that fills the first contact hole 31 and the second contact hole and covers the upper surface of the interlayer dielectric layer 3; forming a patterned masking layer on the upper surface of the metal material layer; and etching the metal material layer based on the patterned masking layer to simultaneously form the gate and the emitter 4.

[0158] Specifically, methods for forming metal material layers include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; methods for etching metal material layers based on patterned masking layers include dry etching, wet etching, or other suitable methods; and methods for forming patterned masking layers are commonly used photolithography processes for creating patterned photoresist layers, which will not be elaborated here.

[0159] Specifically, such as Figure 14 The diagram shown is a cross-sectional view of the current collector region 17 after its formation. The methods for forming the current collector region 17 include ion implantation or other suitable methods. The methods for forming the current collector 5 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0160] Specifically, by forming a second trench structure 24 that penetrates the first trench structure 2 in the semiconductor structure 1, the trade-off relationship between the turn-off loss and the turn-on loss of the device is improved, the voltage overshoot of the first trench structure 2 during the turn-on phase of the device is reduced, and the gate control capability of the device is enhanced.

[0161] The fabrication method of the superjunction IGBT device in this embodiment forms a carrier storage layer 13 and a second trench structure 24 that penetrates the first trench structure 2 and the carrier storage layer 13 and extends to the pillar layer 12. The second trench structure 24 is electrically connected to the emitter 4, which improves the trade-off relationship between the turn-off loss and the turn-on loss of the device, reduces the voltage overshoot of the first trench structure 2 during the turn-on stage of the device, and enhances the gate control capability of the device.

[0162] In summary, the superjunction IGBT device and its fabrication method of the present invention reduce the Miller capacitance C of the device by improving the device structure and setting a carrier storage layer and a second trench structure that penetrates the first trench structure and the carrier storage layer. gc This increases the parasitic capacitance C between the gate and emitter. geThis invention improves the trade-off relationship between turn-off and turn-on losses, reduces voltage overshoot of the first trench structure during turn-on, enhances gate control capability, and the second trench structure assists in depleting the carrier storage layer, enhancing carrier storage effect and improving conductance modulation during turn-on, thereby further reducing on-state voltage drop. By incorporating a second trench structure that penetrates the base region and carrier storage layer, a self-biased MOS structure is formed, creating a hole extraction channel during turn-off, accelerating carrier extraction, increasing turn-off speed, mitigating turn-off oscillation, and improving overall performance. Therefore, this invention effectively overcomes the shortcomings of existing technologies and has high industrial applicability.

[0163] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A superjunction IGBT device, characterized in that, include: A semiconductor structure includes a first conductivity type substrate, a pillar layer, a first conductivity type carrier storage layer, and a second conductivity type base region stacked sequentially. The pillar layer includes a first conductivity type first pillar and a second conductivity type second pillar arranged alternately adjacent to each other along the X direction, and the X direction is perpendicular to the stacking direction of the substrate and the pillar layer. At least one emitter region of a first conductivity type is located on the upper surface of the base region directly above the first pillar; The first trench structure penetrates the base region and extends its bottom surface into the carrier storage layer. The emitter region is adjacent to the sidewall of the first trench structure. A second trench structure is embedded in the upper surface of the semiconductor structure and extends to the upper surface of the pillar layer. At least one second trench structure penetrates the first trench structure, and at least a portion of the bottom of the second trench structure penetrating the first trench structure is located on the upper surface of the first pillar. The second conductivity type collector region is located on the lower surface layer of the substrate. The emitter is electrically connected to the emission region and the second trench structure; The collector electrode is electrically connected to the current collecting region. The gate is electrically connected to the first trench structure.

2. The superjunction IGBT device according to claim 1, characterized in that: The doping concentration of the substrate is greater than that of the first pillar.

3. The superjunction IGBT device according to claim 1, characterized in that: The first trench structure includes a first trench, a first dielectric layer, and a first conductive layer. The first trench penetrates the base region and its bottom surface extends into the carrier storage layer. The first dielectric layer covers the inner wall and bottom surface of the first trench. The first conductive layer fills the first trench and is electrically connected to the gate. The second trench structure includes a second trench, a second dielectric layer, and a second conductive layer. The bottom surface of the second trench extends to the upper surface of the pillar layer. The second dielectric layer covers the inner wall and bottom surface of the second trench. The second conductive layer fills the second trench and is electrically connected to the emitter.

4. The superjunction IGBT device according to claim 1, characterized in that: The first trench structure is located directly above the first pillar, and the bottom of the second trench structure that penetrates the first trench structure is located in the first pillar. At least one of the second trench structures penetrates the base region and the carrier storage layer directly above the second pillar and extends to the second pillar at its bottom.

5. The superjunction IGBT device according to claim 4, characterized in that: The upper surface of the base region is further provided with a second conductive contact area, which is adjacent to the sidewall of the emission area directly above the first pillar away from the first trench structure, and the sidewall of the contact area away from the emission area is adjacent to the sidewall of the second trench structure directly above the second pillar.

6. The superjunction IGBT device according to claim 4, characterized in that: In the X direction, the second groove structure located directly above the second column and the first groove structure located directly above the first column are arranged alternately.

7. The superjunction IGBT device according to claim 1, characterized in that: The first groove structure is located directly above the junction area between the first column and the second column, the second groove structure penetrates the first groove structure, and the bottom of the second groove structure is located on the upper surface of the first column and the second column in the junction area.

8. The superjunction IGBT device according to claim 7, characterized in that: The upper surface of the base area directly above the second column is also provided with the emission area, which is adjacent to the sidewall of the first trench structure.

9. The superjunction IGBT device according to claim 1, characterized in that: The device also includes an interlayer dielectric layer, a first contact hole, and a second contact hole. The interlayer dielectric layer covers the semiconductor structure, the first trench structure, the second trench structure, and the exposed upper surface of the emitter region. The first contact hole penetrates the interlayer dielectric layer and its bottom surface exposes the emitter region and the upper surface of the second trench structure. The second contact hole penetrates the interlayer dielectric layer and its bottom surface exposes the upper surface of the first trench structure. The emitter fills the first contact hole and is electrically connected to the emitter region and the second trench structure through the first contact hole. The gate fills the second contact hole and is electrically connected to the first trench structure through the second contact hole.

10. A method for fabricating a superjunction IGBT device, characterized in that, Includes the following steps: A semiconductor structure is provided, comprising a substrate of a first conductivity type, a pillar layer, a carrier storage layer of a first conductivity type, and a base region of a second conductivity type, which are stacked sequentially. The pillar layer includes a first pillar of a first conductivity type and a second pillar of a second conductivity type arranged alternately and adjacently along the X direction, wherein the X direction is perpendicular to the stacking direction of the substrate and the pillar layer. A first trench structure and a second trench structure are formed embedded in the upper surface of the semiconductor structure. The first trench structure penetrates the base region and its bottom surface extends into the carrier storage layer. The bottom surface of the second trench structure extends into the upper surface of the pillar layer. At least one second trench structure penetrates the first trench structure, and at least a portion of the bottom of the second trench structure penetrating the first trench structure is located on the upper surface of the first pillar. At least one first conductivity type emission region is formed on the upper surface of the base region located directly above the first pillar, the emission region being adjacent to the first trench structure near the sidewall of the first trench structure; An emitter electrically connected to the emitter region and the second trench structure, and a gate electrically connected to the first trench structure are formed. A second conductivity type collector region and a collector electrode electrically connected to the collector region are formed on the lower surface layer of the substrate.

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