Terminal structure, method for manufacturing the same, semiconductor device, and electric appliance

Abstract

The application provides a terminal structure of a semiconductor device, a preparation method of the terminal structure, a semiconductor device and an electrical equipment, and relates to the technical field of semiconductors. The terminal structure comprises: a drift layer; a gate electrode; the gate electrode is arranged on one side of the drift layer; a first doped part; along the extension direction of the gate electrode, at least part of the first doped part wraps the end part of the gate electrode; and the doping type of the first doped part is different from the doping type of the drift layer. In the terminal structure, the first doped part can form a heterojunction with the drift layer, so as to reduce the electric field intensity and the carrier density of the end part of the gate electrode, reduce the collision ionization rate, reduce the risk of avalanche breakdown failure, and improve the reliability of the terminal structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a terminal structure of a semiconductor device and its preparation method, a semiconductor device, and an electrical device. Background Technology

[0002] For semiconductor devices, breakdown voltage (BV) is an important indicator. When a semiconductor device is reverse blocked, the curvature effect at the edge of the main junction (the heterojunction inside the semiconductor device that performs core functions such as rectification, switching, and voltage withstand) will cause the electric field to concentrate, causing the semiconductor device to break down at a voltage lower than the ideal breakdown voltage.

[0003] In related technologies, shallow doping terminals are used to improve the actual breakdown voltage that semiconductor devices can withstand. Shallow doping terminals are placed on the periphery of the main junction. Compared with the doping structure with a lower doping concentration in the main junction, it can allow the depletion layer at the edge of the main junction to extend outward smoothly, so that the electric field changes slowly and the peak electric field is reduced, thereby enabling the semiconductor device to withstand a higher breakdown voltage.

[0004] However, due to the low doping concentration of shallow-doped terminals, charge carriers and lattice atoms are prone to collisions in the terminal junction formed by the shallow-doped terminal and the drift layer, resulting in a chain reaction, avalanche breakdown failure, and reduced reliability of shallow-doped terminals. Summary of the Invention

[0005] This application provides a terminal structure and its fabrication method, a semiconductor device, and an electrical device, aiming to reduce the risk of avalanche breakdown failure of the terminal structure and improve the reliability of the terminal structure.

[0006] In a first aspect, embodiments of this application provide a terminal structure for a semiconductor device, comprising: Drift layer; Gate; the gate is disposed on one side of the drift layer; A first doped portion; along the extension direction of the gate, at least a portion of the first doped portion covers the end of the gate; the doping type of the first doped portion is different from the doping type of the drift layer.

[0007] Optionally, the terminal structure further includes A second doped portion; at least a portion of the second doped portion is disposed on the side of the gate along the extending direction of the gate; The doping type of the first doped portion is the same as that of the second doped portion, and the doping concentration of the first doped portion is greater than that of the second doped portion.

[0008] Optionally, the first doped portion includes a first sub-portion and a second sub-portion; The first sub-section is disposed at the contact position between the second doped section and the gate near the drift layer, and wraps around the end of the gate; The second sub-section is disposed on the side of the second doped section opposite to the drift layer, and is located on the side of the second doped section close to the gate.

[0009] Optionally, the terminal structure further includes an insulating dielectric layer, a metal component, and a stop ring; The cutoff ring and the second doped portion are disposed on the same side of the drift layer. Along the extension direction of the gate, the cutoff ring is located on the side of the drift layer away from the gate. The insulating dielectric layer is disposed on the side of the second doped portion opposite to the drift layer, and covers the second doped portion and at least a portion of the drift layer; The metal components are spaced apart on the side of the insulating dielectric layer that faces away from the drift layer.

[0010] Secondly, embodiments of this application provide a method for fabricating a terminal structure of a semiconductor device, the method comprising: A drift layer is provided with a second doped portion; the second doped portion is disposed on one side of the drift layer; A trench is formed on one side of the drift layer where the second doped portion is located; the trench is used to accommodate the gate. A first doped portion is prepared at the end of the trench.

[0011] Optionally, an insulating dielectric layer is provided on the side of the second doped portion facing away from the drift layer; the process of forming a trench on the side of the drift layer where the second doped portion is located includes: A hard mask is prepared on the surface of the insulating dielectric layer; Etch the hard mask and the insulating dielectric layer until the drift layer is exposed; The drift layer is etched to form the trench.

[0012] Optionally, the step of preparing a first doped portion at the end of the trench includes: Photoresist is coated on the surface of the trench and the unetched hard mask; Deactivate the photoresist at least at the ends of the trench; Remove the deactivated photoresist to expose the ends of the trench; Target impurity particles are injected to form the first doped portion.

[0013] Optionally, after the step of injecting target impurity particles to form the first doped portion, the method further includes: Remove the remaining photoresist and hard mask, and etch the trench to form a chamfered structure at the ends of the trench.

[0014] Optionally, a gate oxide layer is disposed between the gate and the drift layer; after the step of implanting target impurity particles to form the first doped portion, the method further includes: During the fabrication of the gate oxide layer, the first doped portion is activated by annealing so that at least a portion of the first doped portion covers the end of the trench.

[0015] Optionally, an insulating dielectric layer is provided on the side of the second doped portion facing away from the drift layer; after the step of preparing the first doped portion at the end of the trench, the method further includes: Contact holes are formed in the insulating dielectric layer; A metal part is fabricated at the location of the contact hole so that the terminal structure forms a conductive circuit.

[0016] Thirdly, embodiments of this application provide a semiconductor device, the semiconductor device including the terminal structure of the semiconductor device described in the first aspect above, or the semiconductor device including the terminal structure of the semiconductor device prepared by the preparation method of the terminal structure of the semiconductor device described in the second aspect above.

[0017] Fourthly, embodiments of this application provide an electrical device including the semiconductor device described in the third aspect.

[0018] Beneficial effects In this embodiment, at least a portion of the first doped portion is configured to encapsulate the end of the gate; the first doped portion and the drift layer can form a heterojunction, which can adjust the electric field distribution of the terminal structure under withstand voltage and reduce the electric field strength near the end of the gate; under withstand voltage, the reverse high voltage will cause the depletion layer of the heterojunction to expand, so that the carriers near the end of the gate are forced to move out, and the movable carriers are almost cleared. Therefore, the carrier density near the end of the gate is reduced. The reduction of electric field strength and carrier density will reduce the impact ionization rate at this location, reduce the risk of avalanche breakdown failure at this location, and improve the reliability of the terminal structure. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic cross-sectional view of the terminal structure of the semiconductor device provided in an embodiment of this application; Figure 2 This is a flowchart of the steps in the fabrication method of the terminal structure of the semiconductor device provided in the embodiments of this application; Figure 3 It is a flowchart of the steps in the fabrication method of semiconductor devices provided by related technologies; Figure 4 This is a flowchart of the steps in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 5 This is a schematic diagram of the first cross-sectional structure corresponding to the method for fabricating the terminal structure of the semiconductor device provided in the embodiments of this application; Figure 6 This is a schematic diagram of the second cross-sectional structure corresponding to the method for fabricating the terminal structure of the semiconductor device provided in the embodiments of this application; Figure 7 This is a schematic diagram of the third cross-sectional structure corresponding to the method for fabricating the terminal structure of the semiconductor device provided in the embodiments of this application; Figure 8 This is a schematic diagram of the fourth cross-sectional structure corresponding to the method for fabricating the terminal structure of the semiconductor device provided in the embodiments of this application; Figure 9 This is a schematic diagram of the fifth cross-sectional structure corresponding to the method for fabricating the terminal structure of the semiconductor device provided in the embodiments of this application; Figure 10 This is a schematic diagram of the sixth cross-sectional structure corresponding to the method for fabricating the terminal structure of the semiconductor device provided in the embodiments of this application; Figure 11 This is a schematic diagram of the seventh cross-sectional structure corresponding to the method for fabricating the terminal structure of the semiconductor device provided in the embodiments of this application; Figure 12 This is a schematic diagram of the eighth cross-sectional structure corresponding to the method for fabricating the terminal structure of the semiconductor device provided in the embodiments of this application; Figure 13 This is a top view of a semiconductor device provided in an embodiment of this application.

[0020] Figure label: 1. Drift layer; 2. Gate; 3. First doped section; 4. Second doped section; 5. Insulating dielectric layer; 6. Metal component; 7. Cut-off ring; 21. Trench; 22. Chamfer structure; 31. First sub-section; 32. Second sub-section; 81. Hard mask; 82. Photoresist; 83. Contact hole; 84. Pad; X, drift layer thickness direction; Y, gate extension direction; preset direction, Z. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0023] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0024] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0025] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0026] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain tolerances. Taking into account the measurement and the tolerances associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0027] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0028] For semiconductor devices, breakdown voltage (BV) is an important indicator. BV refers to the voltage threshold at which the internal current of a semiconductor device suddenly increases and its insulation performance fails when the voltage applied to the device reaches a certain critical value. When a semiconductor device is in reverse blocking mode, the curvature effect at the edge of the main junction locally increases the electric field strength, causing the semiconductor device to break down even when the voltage at that location is lower than the ideal breakdown voltage.

[0029] Shallow doping termination is a technique to improve the actual breakdown voltage capability of semiconductor devices. Essentially, it involves placing a doped structure with a lower doping concentration around the main junction than the main junction itself. Specific techniques include field-limiting rings, junction terminal extension (JTE), and variable lateral doping (VLD). Shallow doping allows the depletion layer at the edge of the main junction to extend smoothly outwards, resulting in a gentler change in the electric field, preventing electric field concentration, and reducing the peak electric field, thus enabling the semiconductor device to withstand higher breakdown voltages.

[0030] However, due to the low doping concentration of shallow-doped terminals, when a high reverse voltage is applied, charge carriers and lattice atoms in the terminal junction formed by the shallow-doped terminal and the drift layer are prone to collision, generating new electron-hole pairs and forming a chain reaction. This leads to a rapid increase in reverse current, causing avalanche breakdown failure and reducing the reliability of shallow-doped terminals.

[0031] Based on this, embodiments of this application provide a terminal structure and its fabrication method, a semiconductor device, and an electrical device.

[0032] Firstly, embodiments of this application provide a terminal structure for a semiconductor device, such as... Figure 1 As shown, it includes: a drift layer 1; a gate 2; the gate 2 is disposed on one side of the drift layer 1; a first doped portion 3; along the extension direction of the gate 2, at least a portion of the first doped portion 3 covers the end of the gate 2; the doping type of the first doped portion 3 is different from the doping type of the drift layer 1.

[0033] This terminal structure can be used in various semiconductor devices with trench gate structures, such as insulated-gate bipolar transistors (IGBTs) and silicon carbide-metal oxide semiconductor field-effect transistors (SiC MOSFETs).

[0034] In one specific embodiment, the semiconductor device of this application can be an IGBT, which is suitable for medium and high voltage power conversion scenarios, such as motor drives, power inverters, and industrial control systems. The drift layer 1 can be an N-type doped structure, specifically phosphorus doping (P-doping), used to withstand reverse voltage in the device off state. Along the drift layer thickness direction X, a trench 21 gate structure is further formed above the drift layer 1.

[0035] It is important to note that in some IGBTs, such as cutoff field type IGBTs, the drift layer 1 serves as the mechanical support and electrical basis of the overall structure. In other IGBTs, such as punch-through type IGBTs, the P-type doped substrate on the side of the drift layer 1 facing away from the gate 2 can provide the mechanical support and electrical basis for the overall structure. In SiC MOSFETs, the N-type doped substrate on the side of the drift layer 1 facing away from the gate 2 can provide the mechanical support and electrical basis for the overall structure. All of these semiconductor devices have a drift layer 1.

[0036] Gate 2 is disposed on the side of drift layer 1 facing away from the substrate. Gate 2 extends along a preset direction and, when the semiconductor device is turned on, realizes the IGBT's turn-on and turn-off control function by controlling the formation of the channel. The end of gate 2 is the region where the semiconductor device's terminal structure is located. In this region, the electric field distribution is easily affected by geometric abrupt changes, resulting in local electric field concentration.

[0037] The first doped portion 3 corresponds to a Pwell (also known as a P-well, P-body, or bulk region) structure, which is a P-type doped region. Its doping type is different from the N-type doping type of the drift layer 1. Specifically, it can be boron doping (B-doping), aluminum doping (AL-doping), gallium doping (Ga-doping), etc., thereby forming a heterojunction (PN junction) between the drift layer 1 and the first doped portion 3. The first doped portion 3 is disposed at the end of the gate 2 along the gate extension direction Y, and at least partially surrounds the end of the gate 2, so that a P-type doped structure is formed around the end of the gate 2. In this structure, the first doped portion 3 can extend from the edge of the gate 2 to the outer peripheral region of the end of the gate 2, so that the end of the gate 2 is spatially semi-surrounded by the P-type doped region.

[0038] For the trench 21 gate structure, a local electric field concentration region is usually formed near the end of the gate 2. After the first doped portion 3 wraps around the end of the gate 2, since the doping type of the first doped portion 3 is different from that of the drift layer 1, the first doped portion 3 can form a heterojunction (PN junction) with the drift layer 1 around the end of the gate 2. This heterojunction can participate in the depletion layer expansion during reverse blocking, shield the local electric field, and provide local protection and electric field regulation for the end of the gate 2.

[0039] In this embodiment, at least a portion of the first doped portion is configured to encapsulate the end of the gate; the first doped portion and the drift layer can form a heterojunction, which can adjust the electric field distribution of the terminal structure under withstand voltage and reduce the electric field strength near the end of the gate; under withstand voltage, the reverse high voltage will cause the depletion layer of the heterojunction to expand, so that the carriers near the end of the gate are forced to move out, and the movable carriers are almost cleared. Therefore, the carrier density near the end of the gate is reduced. The reduction of electric field strength and carrier density will reduce the impact ionization rate at this location, reduce the risk of avalanche breakdown failure at this location, and improve the reliability of the terminal structure.

[0040] Optionally, refer to Figure 1 The terminal structure also includes a second doped portion 4; at least a portion of the second doped portion 4 is disposed on the side of the gate 2 along the extension direction of the gate 2; the doping type of the first doped portion 3 is the same as the doping type of the second doped portion 4, and the doping concentration of the first doped portion 3 is greater than the doping concentration of the second doped portion 4.

[0041] The termination structure may include a second doped portion 4, which corresponds to a shallowly doped termination breakdown region. Specifically, a junction-terminated extended structure (JTE) may be adopted, and the second doped portion 4 may be P-type doped. The second doped portion 4 may be arranged as a shallowly doped region surrounding the periphery of the main junction, wherein, along the extension direction of the gate 2, at least a portion of the second doped portion 3 is disposed on the side of the gate 2. The first doped portion 3 is disposed on the side of the second doped portion 4 closest to the gate 2.

[0042] The first doped portion 3 has the same doping type as the second doped portion 4, both being P-type windings, and both can form a PN junction with the N-type doped drift layer 1. The difference lies in the doping concentration: the first doped portion 3 has a higher doping concentration than the second doped portion 4. For example, the dopant implantation dose of the second doped portion 4 is less than 2e13 / cm3, while the dopant implantation dose of the first doped portion 3 is greater than 2e13 / cm3. Therefore, the first doped portion 3 can serve as a locally enhanced doped region near the end of the gate 2, while the second doped portion 4 can serve as a shallowly doped terminal breakdown region located in the peripheral region of the gate 2.

[0043] Taking the IGBT as an example of a semiconductor device, in the IGBT off state, a reverse blocking electric field is established inside the drift layer 1, and the edge of the main junction and the end region of the gate 2 will simultaneously experience changes in potential gradient. If only the second doping portion 4 is relied upon, the electric field can be well broadened in the direction of the main junction edge, but local electric field concentration may still occur at the end of the gate 2 due to structural abruptness. By setting the first doping portion 3 to wrap around the end of the gate 2, an additional heterojunction (PN junction) can be introduced near the end of the gate 2, so that the electric field no longer exhibits a sharp distribution when transitioning from the end of the gate 2 outward, but is gradually adjusted through the heterojunction (PN junction).

[0044] When the semiconductor device is reverse-biased, the second doped portion 4 is used to gently spread the depletion layer outward from the edge of the main junction, while the first doped portion 3 is disposed near the end of the gate 2 to adjust the local electric field at the end of the gate 2. Through the cooperation between the first doped portion 3 and the second doped portion 4, the termination structure retains the field-soothing effect of the shallowly doped termination breakdown region, while utilizing the first doped portion 3 to improve the local breakdown resistance near the end of the gate 2.

[0045] The presence of the first doped portion 3 and the second doped portion 4 enables the termination structure to regulate the electric field in zones. The second doped portion 4 is a shallowly doped termination voltage-bearing region located on the side of the gate 2. It can form a relatively gentle depletion expansion region around the main junction, preventing the electric field from abruptly terminating at the edge of the main junction. Simultaneously, the first doped portion 3 and the second doped portion 4 have the same doping type, both capable of forming a heterojunction with the drift layer 1. Therefore, they can jointly participate in depletion layer distribution regulation during reverse blocking. Furthermore, the doping concentration of the first doped portion 3 is greater than that of the second doped portion 4, giving the region near the end of the gate 2 a stronger local junction regulation capability, while the second doped portion 4 maintains the smooth stretching effect of the shallowly doped termination voltage-bearing region on the electric field. Thus, the second doped portion 4 does not need to bear the entire electric field at the edge of the main junction alone; the first doped portion 3 can first share and weaken the local electric field at the end of the gate 2 where electric field concentration is prone to occur. By weakening the electric field and expanding the depletion layer, the termination structure provided in this embodiment can reduce the possibility of ionization collisions of charge carriers in the termination junction formed by the second doped portion 4 and the drift layer 1, thereby reducing the risk of avalanche breakdown failure in the second doped portion 4 (shallow doped termination breakdown region). Thus, the termination structure improves the breakdown voltage while also enhancing the reliability of the second doped portion 4 (shallow doped termination breakdown region).

[0046] Optionally, refer to Figure 1The first doped portion 3 includes a first sub-portion 31 and a second sub-portion 32. The first sub-portion 31 is disposed on the side of the second doped portion 4 and the gate 2 near the drift layer 1 at the contact position, and wraps around the end of the gate 2. The second sub-portion 32 is disposed on the side of the second doped portion 4 away from the drift layer 1, and is located on the side of the second doped portion 4 near the gate 2.

[0047] The first doped portion 3 may include a first sub-portion 31 and a second sub-portion 32 depending on its location. The first sub-portion 31 and the second sub-portion 32 are two sub-regions of the first doped portion 3 that are generated under the same process step but are located in different positions.

[0048] The first sub-section 31 is disposed at the contact position between the second doped section 4 and the gate 2 on the side facing the drift layer 1. The first doped section 3 mainly relies on the first sub-section 31 to wrap the end of the gate 2. The heterojunction (PN junction) formed by the first doped section 3 and the drift layer 1 is also located around the first sub-section 31. The main structure of the first sub-section 31 is located on the lower side of the end of the gate 2, that is, on the side close to the drift layer 1, which can achieve the wrapping of the end of the gate 2 facing the drift layer 1. When the first doped section 3 is activated (annealed), the doped particles in the first sub-section 31 diffuse outward, causing the first sub-section 31 to expand and thus invade the second doped section 4, achieving the wrapping of the end of the gate 2 facing the second doped section 4.

[0049] The second sub-section 32 is disposed on the side of the second doped section 4 facing away from the drift layer 1, and is located on the side of the second doped section 4 near the gate 2. The second sub-section 32 is disposed at the end of the shallow doped terminal withstand voltage region near the gate 2, and is located in the surface region of the second doped section 4, so that the second sub-section 32 can form a conductive channel at the end of the second doped section 4 near the main junction and the gate 2.

[0050] The first sub-section 31 can be used to form an electric field intensity modulation and depletion guidance effect in the end region of the gate 2, and the second sub-section 32 can be used to form a conductive channel on the side of the second doped section 4 near the gate 2. In the embodiments of this application, both are prepared in the same process step.

[0051] In this embodiment, the first doped portion 3 is further divided into a first sub-portion 31 and a second sub-portion 32, enabling the termination structure to perform different functions at different locations. The first sub-portion 31 is located at the bottom of the contact position between the gate 2 and the second doped portion 4, and it can form a heterojunction (PN junction) with the drift layer 1 region corresponding to this position, thereby guiding the depletion layer expansion near the end of the gate 2. The second sub-portion 32 is located on the side of the second doped portion 4 away from the drift layer 1 and on the side of the second doped portion 4 closer to the gate 2. Therefore, the second sub-portion 32 can strengthen the starting position of the shallow doped termination breakdown region. Since the second sub-portion 32 has a higher doping concentration than the second doped portion 4, the second sub-portion 32 and the second doped portion 4 can form a high-low junction to achieve good ohmic contact for the metal connecting the electrodes.

[0052] Optionally, refer to Figure 1 The terminal structure also includes an insulating dielectric layer 5, a metal element 6, and a cutoff ring 7; the cutoff ring 7 and the second doped portion 4 are disposed on the same side of the drift layer 1, and along the extension direction of the gate 2, the cutoff ring 7 is located on the side of the drift layer 1 away from the gate 2; the insulating dielectric layer 5 is disposed on the side of the second doped portion 4 away from the drift layer 1, and covers the second doped portion 4 and at least part of the drift layer 1; the metal element 6 is disposed at intervals on the side of the insulating dielectric layer 5 away from the drift layer 1.

[0053] The termination structure also includes an insulating dielectric layer 5, a metal element 6, and a stop ring 7. The stop ring 7 and the second doped portion 4 are disposed on the same side of the drift layer 1, and along the extension direction of the gate 2, the stop ring 7 is located on the side of the drift layer 1 away from the gate 2. The stop ring 7 can be disposed in the peripheral region of the termination structure to define the boundary of the depletion layer extending outward during reverse blocking, preventing the depletion region from extending unrestricted to the edge of the semiconductor device.

[0054] An insulating dielectric layer 5 is disposed on the side of the second doped portion 4 facing away from the drift layer 1, and covers part of the surface of the drift layer 1 and the entire surface of the second doped portion 4. The insulating dielectric layer 5 can passivate and electrically isolate the drift layer 1 and the second doped portion 4, reducing unintended contact between the metal component 6 and the semiconductor layer. The insulating dielectric layer 5 may be composed of silicon dioxide, undoped silicate glass (USG) of several thousand angstroms, and borophosphosilicate glass (BPSG) of several thousand angstroms to provide insulation and isolation functions. The thickness of the insulating dielectric layer 5 near the gate 2 and near the cutoff ring 7 is thinner than the thickness at the center of these two locations to facilitate the fabrication of the second sub-portion 32 and the cutoff ring 7.

[0055] Metal parts 6 are spaced apart on the side of the insulating dielectric layer 5 facing away from the drift layer 1. Metal parts 6 can serve as electrical connection structures for the terminal structure, and are used to apply voltage to the terminal structure.

[0056] This embodiment introduces an insulating dielectric layer 5, a metal element 6, and a stop ring 7 on top of the doped structure. This allows the termination structure to not only regulate the electric field through internal doping distribution but also improve its breakdown voltage reliability through surface and peripheral boundary structures. The stop ring 7 is located on the side of the drift layer 1 away from the gate 2, and its function is to provide a termination boundary for the expansion of the depletion layer. When the device is reverse blocked, the depletion region extends outward along the gate extension direction Y. If the periphery of the termination structure lacks a stop structure, the electric field may continue to diffuse towards the edge of the semiconductor device and concentrate at the edge defect. The stop ring 7 can limit this expansion process, making the breakdown voltage range of the termination structure more controllable. The insulating dielectric layer 5 covers the second doped portion 4 and part of it, which can isolate the metal element 6 from the semiconductor surface. After the metal element 6 is spaced above the insulating dielectric layer 5, it can pass through the insulating dielectric layer 5 and contact the doped structure, so that the termination structure forms a conductive loop. The first doped portion 3 and the second doped portion 4 regulate the depletion layer from inside the semiconductor device, the insulating dielectric layer 5 prevents abnormal electrical connections between the inside of the semiconductor device and the outside, and the stop ring 7 defines the depletion boundary from the outside. The three work together to improve the reliability of the termination structure.

[0057] In summary, in the embodiments of this application, at least a portion of the first doped portion is configured to wrap around the end of the gate; the first doped portion and the drift layer can form a heterojunction, which can adjust the electric field distribution of the terminal structure under withstand voltage and reduce the electric field strength near the end of the gate; under withstand voltage, the reverse high voltage will cause the depletion layer of the heterojunction to expand, so that the carriers near the end of the gate are forced to move out, and the movable carriers are almost cleared. Therefore, the carrier density near the end of the gate is reduced. The reduction of electric field strength and carrier density will reduce the impact ionization rate at this location, reduce the risk of avalanche breakdown failure at this location, and improve the reliability of the terminal structure.

[0058] Secondly, embodiments of this application provide a method for fabricating a terminal structure of a semiconductor device, such as... Figure 2 As shown, Figure 2 This is a flowchart of the preparation method, which includes: Step 101: Provide a drift layer having a second doped portion; the second doped portion is disposed on one side of the drift layer; Step 102: A trench is formed on one side of the drift layer where the second doped portion is located; the trench is used to accommodate the gate. Step 103: Prepare a first doped portion at the end of the trench.

[0059] The fabrication method of the termination structure of a semiconductor device includes the following steps. First, a drift layer with a second doped portion is provided, the second doped portion being disposed on one side of the drift layer. The drift layer is N-type doped, and the second doped portion is P-type doped. The second doped portion can be formed on the surface region of the drift layer by ion implantation, serving as a shallow-doped termination voltage withstand region. Subsequently, a trench is fabricated on the side of the drift layer with the second doped portion, the trench serving to accommodate a gate. The trench can extend along a predetermined direction, its end being formed at the second doped portion, the end of the trench corresponding to the region where the end of the subsequent gate is located. Then, a first doped portion, P-type doped, is fabricated at the end of the trench. The first doped portion can be formed by selectively implanting target impurity particles, ensuring it is at least near the trench end, and in subsequent processes, it forms a local protection region for the gate with the drift layer surrounding the trench end.

[0060] This fabrication method arranges the process sequence according to the functional relationship of the terminal structure. First, a drift layer with a second doped portion is provided, allowing a shallowly doped terminal breakdown voltage region to be pre-formed on the surface of the drift layer, providing a foundation for the breakdown voltage of the subsequent terminal structure. Then, a trench is fabricated on the side of the drift layer with the second doped portion, ensuring the trench position corresponds to the subsequent gate position, thus clarifying the actual position of the gate end in the terminal structure. Furthermore, a first doped portion is fabricated at the end of the trench, allowing it to form directly around the trench end, rather than after the gate is formed, enabling the first doped portion to encapsulate the end of the gate.

[0061] The second doping portion is responsible for the smooth unfolding of the electric field around the main junction, while the first doping portion is responsible for the local enhancement near the trench end and the gate end. The two achieve synergy through this fabrication sequence.

[0062] It should be noted that this application advances the fabrication process of the first doped portion (PWell) to the process step of fabricating the trench, so that the first doped portion is formed before the gate, and the first doped portion can form a wrapping around the end of the gate.

[0063] Taking the fabrication of JTE lightly doped IGBTs as an example, Figure 3 The fabrication process of IGBTs in related technologies is illustrated. This process includes: A1, GR imp.

[0064] This step, officially called Guard Ring implant, mainly involves injecting impurity particles required to form the second doped portion into a semiconductor device.

[0065] A2, GR Drive in.

[0066] This step, officially called Guard Ring Drive in, is mainly used for annealing the terminal structure. The annealing temperature is between 1000℃ and 1200℃, and the annealing time is between 150 min and 350 min.

[0067] A3, LOCOS.

[0068] This step, called Local Oxidation of Silicon, is used to form the terminal structure. After this step, the drift layer with the second doped portion provided in step 101 above can be obtained. A4, TCH.

[0069] This step, called Trench, is used to etch a trench shape to accommodate the gate in subsequent process steps.

[0070] A5, SAC Ox.

[0071] This step, officially called Sacrifice Oxide, involves first preparing a sacrificial oxide layer, and then removing it using a specific solution, such as hydrofluoric acid (HF) (forming an oxide layer, which is then removed, hence the name sacrificial oxide layer). This step is used to repair interface damage caused by etching. In a furnace tube at 900℃~1100℃, oxygen is introduced to oxidize Si, generating a sacrificial oxide layer of approximately 1000 Å.

[0072] A6, Gate Ox.

[0073] This step, called Gate Oxide, is the preparation step of the gate oxide layer. In a furnace tube at 900℃~1100℃, oxygen is introduced to oxidize Si, which can generate a gate oxide layer of about 800Å~1200Å.

[0074] A7, Poly.

[0075] This step, short for PolySilicon, is the gate fabrication step. Polysilicon is filled into the trench etched in step A4 by chemical vapor deposition to form the gate.

[0076] A8, Pwell.

[0077] This step is the preparation step of the P-well, which includes the implantation and activation of P-type ions. When the gate voltage is higher than the threshold, a channel can be formed at the P-well.

[0078] A9, CSL.

[0079] This step is called the Carrier Stored Layer, which is a structure used to connect the Pwell and the drift layer.

[0080] A10, NPlus.

[0081] This step involves the preparation of a high-concentration N-well, which can be achieved by ion implantation to form a high-concentration N-type doped structure. This structure is used to form the emitter of the IGBT, where electrons are provided when the gate is turned on.

[0082] A11, CT.

[0083] This step, called Contact, refers to forming a contact hole by etching an insulating dielectric layer. This insulating dielectric layer is formed in step A3 above.

[0084] A12, MET.

[0085] This step, called Metal, refers to the process of connecting sputtered metal to contact holes to form multiple spaced metal parts on the surface of an insulating dielectric layer, thereby creating a conductive path on the current processing surface.

[0086] A13, Backside.

[0087] This step, known as the back-side process, refers to the fabrication of the back-side process by flipping the wafer.

[0088] The terminal structure preparation method provided in this application advances the Pwell preparation in step A8 to step A4, thereby forming the first doped portion (Pwell) included in the terminal structure. Figure 4 The fabrication process of the IGBT corresponding to the embodiment of this application is illustrated. The process includes: B1, GR imp.

[0089] This step is the same as step A1 above, and will not be repeated here.

[0090] B2, GR Drive in.

[0091] This step is the same as step A2 above, and will not be repeated here.

[0092] B3, LOCOS.

[0093] This step is the same as step A3 above, and will not be repeated here.

[0094] B4, TCH.

[0095] The step first involves etching trenches, and then preparing a first doped portion (Pwell) at the end of the trenches, including implanting impurity particles required to form the first doped portion.

[0096] B5, SAC Ox.

[0097] This step is the same as step A5 above, and will not be repeated here. It should be noted that the first doped portion prepared in B4 can be activated during the annealing process in this step, causing the first doped portion to wrap around the ends of the trench, forming a shape such as... Figure 1 The structure of the first doped portion is shown.

[0098] B6, Gate Ox.

[0099] This step is the same as step A6 above, and will not be repeated here. It should be noted that the first doped portion prepared in B4 can be activated during the annealing process in this step, causing the first doped portion to wrap around the ends of the trench, forming a shape such as... Figure 1 The structure of the first doped portion is shown.

[0100] B7, Poly.

[0101] This step is the same as step A7 above, and will not be repeated here.

[0102] B8, CSL.

[0103] This step is the same as step A9 above, and will not be repeated here.

[0104] B9, NPlus.

[0105] This step is the same as step A10 above, and will not be repeated here.

[0106] B10, CT.

[0107] This step is the same as step A11 above, and will not be repeated here.

[0108] B11, MET.

[0109] This step is the same as step A12 above, and will not be repeated here.

[0110] B12, Backside.

[0111] This step is the same as step A13 above, and will not be repeated here.

[0112] Depend on Figure 3 and Figure 4 As can be seen from the comparison, in the embodiment of this application, the implantation process of the first doped portion (Pwell) is moved forward to the trench etching step when preparing the terminal structure, so that the trench end is wrapped by the first doped portion (Pwell). In addition, in the embodiment of this application, the first doped portion (Pwell) can be activated by the preparation steps of the sacrificial oxide layer and the gate oxide layer.

[0113] Optionally, an insulating dielectric layer is disposed on the side of the second doped portion facing away from the drift layer, the insulating dielectric layer covering the second doped portion and at least a portion of the drift layer; step 102 may include: Sub-step 1021: Prepare a hard mask on the surface of the insulating dielectric layer; Sub-step 1022: Etch the hard mask and the insulating dielectric layer until the drift layer is exposed; Sub-step 1023: Etch the drift layer to form the trench.

[0114] like Figure 5 As shown, Figure 5 For the cross-sectional structure of the semiconductor terminal structure corresponding to sub-step 1021, when the drift layer 1 with the second doped portion 4 is obtained from step B3 above, an insulating dielectric layer 5 is provided on the side of the second doped portion 4 facing away from the drift layer 1. The insulating dielectric layer 5 covers the second doped portion 4 and the drift layer 1. When preparing the trench 21 on the side of the drift layer 1 with the second doped portion 4, a hard mask can be prepared on the surface of the insulating dielectric layer 5 by chemical vapor deposition. The hard mask can be an oxide, a nitride, or a combination of oxide and nitride, preferably silicon oxide, and its thickness can be 4000 Å to 8000 Å.

[0115] Subsequently, as Figure 6 As shown, Figure 6 This is the cross-sectional structure of the semiconductor terminal structure corresponding to sub-step 1022; in conjunction with the mask corresponding to trench 21, dry etching is used to etch the hard mask and insulating dielectric layer 5 until the drift layer 1 is exposed. This step can transfer the mask pattern to the insulating dielectric layer 5, so that the insulating dielectric layer 5 is exposed on the surface of the drift layer 1 in the area to be formed in trench 21, while other areas are still protected by the hard mask and insulating dielectric layer 5.

[0116] After that, as Figure 7 As shown, Figure 7 This is the cross-sectional structure of the semiconductor terminal structure corresponding to sub-step 1023; dry etching of the drift layer 1 can be performed using plasma etching to achieve anisotropic etching, forming a trench 21 for accommodating the gate 2. The trench 21 can extend from one side of the drift layer 1 with the second doped portion 4 to the other side, forming the sidewalls and bottom of the trench 21, and the extension depth of the trench 21 can be 3 μm to 6 μm. Since the insulating dielectric layer 5 has been patterned, the etched area of ​​the drift layer 1 can correspond to the pattern of the mask.

[0117] Sub-steps 1021-1023 belong to step B4 above.

[0118] This technical solution utilizes a hard mask and an insulating dielectric layer to fabricate trenches, which helps improve the stability of trench position and morphology. Since the trench is used to house the gate, the position of the trench end directly affects the region where the gate end is located, and the gate end is also a location prone to electric field concentration in the termination structure. Therefore, the higher the trench fabrication precision, the easier it is to achieve the subsequent encapsulation and protection of the gate end by the first doping layer. Firstly, a hard mask is fabricated on the surface of the insulating dielectric layer, which helps maintain the stability of the trench pattern during etching. Etching the hard mask and insulating dielectric layer until the drift layer is exposed accurately opens the area to be formed in the trench, while the non-etched areas remain protected by the hard mask and insulating dielectric layer. After further etching the drift layer to form the trench, the trench pattern position is consistent with the mask corresponding to the trench, which helps control the relative relationship between the trench end and the second and first doping layers. This process path ensures good repeatability at the critical trench end, thus laying the foundation for the subsequent fabrication of the first doping layer at the trench end.

[0119] Optionally, step 103 may include: Sub-step 1031: Coat the surface of the trench and the unetched hard mask with photoresist; Sub-step 1032: Deactivate the photoresist at least at the end of the trench; Sub-step 1033: Remove the deactivated photoresist to expose the end of the trench; Sub-step 1034: Inject target impurity particles to form the first doped portion.

[0120] When the first doped portion 3 is prepared at the end of the trench 21, as follows: Figure 8 As shown, Figure 8 For the cross-sectional structure of the semiconductor terminal structure corresponding to sub-step 1031, photoresist 82 can be coated on the entire wafer surface, including the trench 21 and the surface of the unetched hard mask 81, so that the photoresist 82 covers the inner wall of the trench 21, the bottom of the trench 21, and the surface of the hard mask 81. Before coating the photoresist 82, the wafer can be cleaned by a cleaning device to remove contaminants from the wafer surface.

[0121] Subsequently, as Figure 9 As shown, Figure 9For the cross-sectional structure of the semiconductor terminal structure corresponding to sub-steps 1032 and 1033, the photoresist 82 located at the end of trench 21 and the hard mask position is deactivated. Deactivation of the photoresist 82 can be achieved by exposing and developing the photoresist 82 using the mask corresponding to the first doping portion 3, or by other methods that can alter the removal characteristics of the photoresist 82, so that the photoresist 82 at the end of trench 21 behaves differently from the photoresist 82 at other locations in subsequent development or stripping processes. Afterwards, the deactivated photoresist is removed using a chemical cleaning solution corresponding to the photoresist, exposing the end of the trench, while the other areas of the trench remain covered by photoresist.

[0122] Next, as Figure 10 As shown, Figure 10 For the cross-sectional structure of the semiconductor terminal structure corresponding to sub-step 1034, target impurity particles are implanted into the wafer. The target impurity particles are used to form the first doping portion 3 of P-type doping, which can be boron, and the doping concentration can be 1e13 / cm³. 3 ~1e15 / cm 3 Since the end of trench 21 is exposed, target impurity particles can enter the drift layer 1 region near the end of trench 21, but are less likely to enter other regions of trench 21. A P-type doping can be formed in the layer facing the drift layer 1 at the end of trench 21, which forms the prototype of the first sub-section 31. Since the hard mask 81 is no longer blocked by the photoresist 82, the thinner hard mask 81 and insulating dielectric layer 5 allow some target particles to pass through, thereby forming another P-type doping at the position of the second doping section 4 near the end of trench 21. This P-type doping forms the prototype of the second sub-section 32. Through this method, the first doping section 3 can be selectively formed at the end of trench 21, so that the first doping section 3 has a strong positional correspondence with the end of trench 21, and provides a basis for the subsequent formation of the P-type doped structure surrounding the end of the gate 2.

[0123] Sub-steps 1031-1034 belong to step B4 above.

[0124] This technical solution utilizes photoresist deactivation to selectively expose the trench ends, allowing the first doped portion to be accurately fabricated near the trench ends. Since the primary function of the first doped portion is to encapsulate the gate end and regulate the end electric field, its formation location must correspond as closely as possible to the trench ends. If the first doped portion deviates from the trench ends, it may not effectively reduce the electric field concentration at the gate ends; if the first doped portion extends to unnecessary areas, it may affect the electric field distribution of other doped regions in the termination structure. By coating the wafer surface with photoresist, non-target areas can be protected first. Further deactivating and removing the photoresist at the trench ends exposes only the locations where the first doped portion needs to be formed. Subsequently, when target impurity particles are implanted, these particles mainly enter the trench ends and the side of the second doped portion near the trench ends, thus forming a localized first doped portion. This method does not require extensive additional doping of the entire termination region, reducing the interference of the first doped portion on the original shallow-doped termination breakdown voltage of the second doped portion. Therefore, the first doped portion can more accurately perform the function of adjusting the end electric field of the gate, so that the termination structure can improve the end breakdown resistance while maintaining the smooth expansion of the electric field.

[0125] Optionally, after sub-step 1034, the following steps are also included: Sub-step 1035: Remove the remaining photoresist and the remaining hard mask, and etch the trench to form a chamfered structure at the ends of the trench.

[0126] like Figure 11 and Figure 12 As shown, Figure 11 and Figure 12 The cross-sectional structure of the semiconductor terminal structure corresponding to sub-step 1034, after the step of implanting target impurity particles and forming the first doped portion 3, is as follows: Figure 11 As shown, the remaining photoresist 82 and mask can be removed, re-exposing the inner wall of trench 21, the end of trench 21, and the surface of the unetched insulating dielectric layer 5. Subsequently, as... Figure 12 As shown, the trench 21 is isotropically etched to form a chamfer structure 22 (rounded chamfer) at the end of the trench 21. The chamfer structure 22 is formed at the corner position at the end of the trench 21, so that the end of the trench 21 transitions from a sharp corner to a more gentle corner shape.

[0127] After completing the chamfered structure 22, the oxide layer of the gate 2 and the gate 2 can be fabricated, so that the end of the gate 2 corresponds to the end of the trench 21 with the chamfered structure 22. Thus, the end of the trench 21 is not only protected by the first doping portion 3 in terms of doping type, but also has its curvature reduced by the chamfered structure 22 in terms of geometry. For the termination structure, the first doping portion 3 and the chamfered structure 22 can work together near the end of the gate 2, making the electric field line distribution at the end of the gate 2 more gentle and reducing the local electric field concentration caused by the sharp morphology of the trench 21 end.

[0128] Sub-step 1035 belongs to step B4 above.

[0129] After the first doped portion is formed, the trench ends are further etched to form a chamfered structure, thereby improving the electric field distribution of the termination structure from both doping and geometry adjustment perspectives. The first doped portion can adjust the depletion layer at the gate end by forming a heterojunction with the drift layer. If the trench end shape is too sharp, additional electric field concentration may still occur. By forming a chamfered structure after implanting target impurity particles, the geometric transition at the trench end can be made smoother. Combined, the chamfered structure reduces the electric field concentration caused by geometric curvature, the first doped portion reduces the electric field concentration caused by the junction edge, and the second doped portion further bears the gradual expansion of the peripheral electric field. Thus, the termination structure can more effectively reduce the peak electric field at the gate end and improve the reliability of the semiconductor device in reverse blocking mode. In addition, the chamfered trench end facilitates the expansion of the first sub-part of the first doped portion to the trench side during formation, making it easier for the first sub-part to wrap around the trench end.

[0130] Optionally, a gate oxide layer is disposed between the gate and the drift layer, and after sub-step 1034, the method further includes... Sub-step 1036: During the preparation of the gate oxide layer, the first doped portion is activated by annealing so that at least a portion of the first doped portion covers the end of the trench.

[0131] After the step of injecting target impurity particles and forming the first doped portion, when preparing the gate oxide layer corresponding to the gate, the first doped portion can be activated by annealing so that at least part of the first doped portion covers the end of the trench.

[0132] Specifically, after the target impurity particles are injected near the trench end, they are in a state of incomplete electroactivation. Subsequently, during the heat treatment process for preparing the gate oxide layer, this heat treatment process can be used to anneal and activate the first doped portion, allowing the target impurity particles to enter a state where they can perform P-type doping. During the annealing process, the first sub-part of the first doped portion will expand outward due to thermal effects, thereby... Figure 1The trench ends are shown to be enclosed. After the gate is subsequently formed in the trench, the trench ends correspond to the gate ends, allowing the first doped portion to effectively enclose the gate ends. This method combines the activation process of the first doped portion with the gate oxide layer fabrication process, reducing additional process steps and matching the formation state of the first doped portion with the trench gate structure fabrication process. Sub-step 1036 belongs to step B6 above, and the gate oxide layer corresponds to the gate oxide layer in step B6 above.

[0133] It should be noted that when preparing the sacrificial oxide layer in step B5, the first doped portion can also be activated through its annealing process, thereby achieving the first sub-part wrapping the trench end.

[0134] This technical solution combines the annealing activation of the first doped portion with the gate oxide layer fabrication process, which helps improve process integration and enhances the effectiveness of the first doped portion. After the target impurity particles are implanted, although the first doped portion is spatially located near the trench end, it does not completely cover the trench end. Annealing activation causes the first sub-part of the first doped portion to expand and thus cover the trench end. The trench end corresponds to the end of the gate after the gate is formed. Therefore, this step ensures that the first sub-part of the first doped portion can cover the end of the gate, thereby regulating the electric field at the gate end. This technical solution also has process synergy. The gate oxide layer fabrication itself requires a heat treatment process. Incorporating the activation step of the first doped portion into this process avoids increasing the process complexity caused by independent activation steps, saving at least one heat treatment process (the activation step in step A8 above). As a result, the termination structure can obtain an effective Pwell structure with less process burden, making the depletion layer distribution near the gate end more stable and reducing the possibility of avalanche breakdown in the shallow doped termination breakdown region due to local high field.

[0135] Optionally, an insulating dielectric layer is provided on the side of the second doped portion facing away from the drift layer; after step 103, the method may further include: Step 104: Prepare contact holes in the insulating dielectric layer; Step 105: Prepare a metal part at the location of the contact hole so that the terminal structure forms a conductive circuit.

[0136] An insulating dielectric layer is disposed on the side of the second doped portion facing away from the drift layer, and this insulating layer covers the second doping and at least a portion of the drift layer (the drift layer between the second doped portion and the stop ring); as shown Figure 1As shown, after the first doped portion 3 is prepared at the end of the trench 21, a contact hole 83 can be prepared in the insulating dielectric layer 5. The contact hole 83 can be formed by patterning and etching processes, opening predetermined positions in the insulating dielectric layer 5 and exposing the area to be connected to the metal element 6. Subsequently, the metal element 6 is prepared at the position of the contact hole 83 to form a conductive loop in the terminal structure. The metal element 6 can be sputtered and deposited on the side of the insulating dielectric layer 5 opposite to the drift layer 1, and electrically connected to the corresponding area below through the contact hole 83. Depending on the actual layout of the terminal structure, the metal element 6 can be connected to the cutoff ring 7, the source region ( Figure 1 (Not shown in the figure), the second sub-section 32 in the first doped section 3 or other regions that need to be electrically connected form a conductive relationship.

[0137] By defining the contact position of the metal component through contact holes, unintended contact between the metal component and the drift layer surface can be avoided, while ensuring reliable connection of the areas that need to be brought out in the terminal structure. Fabricating the contact holes and metal component after the first doping sub-section is formed allows the metal component to fit with the completed doped terminal structure, thereby forming a terminal structure that possesses both electric field modulation and electrical connection capabilities.

[0138] Thirdly, embodiments of this application provide a semiconductor device, the semiconductor device including the terminal structure of the semiconductor device described in the first aspect above, or the semiconductor device including the terminal structure of the semiconductor device prepared by the preparation method of the terminal structure of the semiconductor device described in the second aspect above.

[0139] The semiconductor device may include the termination structure of the semiconductor device described in the first aspect above. In this case, a drift layer, a gate, a first doped portion, a second doped portion, an insulating dielectric layer, a metal element, and a cutoff ring are disposed in the termination region of the semiconductor device. The first doped portion at least partially covers the end of the gate, and the second doped portion is at least disposed on the side of the gate, so that the electric field is jointly adjusted by the first and second doped portions when the semiconductor device is reverse-biased. Alternatively, in another embodiment, the semiconductor device may include the termination structure of the semiconductor device prepared by the method for preparing the termination structure of the semiconductor device described in the second aspect above. In this case, the termination structure is formed by providing a drift layer with a second doped portion, preparing a trench, and preparing a first doped portion at the end of the trench, so that the first doped portion and the end of the trench have a good correspondence.

[0140] The aforementioned semiconductor devices can be power switching devices, rectifier devices, or other semiconductor devices requiring reverse blocking capability. Regardless of whether they are formed using a structurally defined method or obtained through a fabrication method, semiconductor devices can improve the electric field concentration problem near the end of the gate through the termination structure.

[0141] A top view of the aforementioned semiconductor device is shown below. Figure 13 As shown, Figure 13 The semiconductor device, which does not show metal components and an insulating oxide layer, includes a plurality of gates 2 spaced apart along a predetermined direction Z, which intersects with the gate extension direction Y. A second doped portion 4 is provided on the outer periphery of each gate 2, and a first doped portion is provided at the end of each gate 2 along its extension direction. Figure 13 (not shown in the image), the above Figure 1 Can be regarded as Figure 13 A cross-sectional schematic diagram of the middle SS. In addition, the semiconductor device includes a pad 84 covering a portion of the gate 2 surface for electrical connection to external circuitry.

[0142] This semiconductor device achieves the same technical effect as the terminal structure of the semiconductor device in the foregoing embodiments, and will not be described again here to avoid repetition.

[0143] Fourthly, embodiments of this application provide an electrical device including the semiconductor device described in the third aspect.

[0144] The electrical equipment can be any device requiring power conversion, power control, or power protection, such as power conversion equipment, motor drive equipment, energy storage conversion equipment, vehicle-mounted electronic control equipment, or industrial control equipment. Semiconductor devices can serve as power switching or rectifier devices in the electrical equipment, used to perform functions such as conduction, shutdown, freewheeling, rectification, or protection in the circuit. Since the semiconductor device includes the termination structure described in the foregoing embodiments, or includes a termination structure prepared using the foregoing preparation method, the semiconductor device can improve the electric field distribution during reverse blocking through the first doped portion, the second doped portion, and other termination structures. After the first doped portion wraps around the end of the gate, it can reduce the local electric field concentration near the end of the gate; the second doped portion, as a shallowly doped terminal withstand voltage region, can allow the depletion layer to extend smoothly outward; the cutoff ring, insulating dielectric layer, and metal components can further assist in the boundary definition, surface passivation, and conductive loop formation of the termination structure. When the electrical equipment uses this semiconductor device, it can achieve more stable device withstand voltage performance when subjected to reverse voltage or performing switching operations, thereby improving the reliability of the equipment during operation.

[0145] This technical solution applies the aforementioned semiconductor devices to electrical equipment, further translating the improved voltage withstand reliability of the terminal structure into operational stability at the equipment level. By employing the semiconductor devices described in the third aspect, the semiconductor devices in the electrical equipment can utilize the first doping portion to locally protect the gate end, and utilize the second doping portion to gently extend the electric field around the main junction. Thus, the second doping portion (the shallowly doped terminal voltage withstand region) no longer bears the concentrated electric field at the gate end alone, resulting in a more balanced electric field distribution and a reduced risk of avalanche breakdown failure. Furthermore, the semiconductor device also includes an insulating dielectric layer, metal components, and a cutoff ring, making the peripheral depletion boundary of the terminal structure more controllable. The improved breakdown voltage and reliability at the semiconductor device level can reduce the likelihood of equipment failure under high-voltage interruption, switching, or abnormal voltage surges. Therefore, this electrical equipment achieves higher electrical safety, operational stability, and long-term reliability, making it particularly suitable for applications requiring high voltage withstand capability from semiconductor devices.

[0146] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A termination structure for a semiconductor device, characterized in that, include: Drift layer; Gate; The gate is disposed on one side of the drift layer; First doping fraction; Along the extension direction of the gate, at least a portion of the first doped portion covers the end of the gate; the doping type of the first doped portion is different from the doping type of the drift layer.

2. The terminal structure according to claim 1, characterized in that, The terminal structure also includes A second doped portion; at least a portion of the second doped portion is disposed on the side of the gate along the extending direction of the gate; The doping type of the first doped portion is the same as that of the second doped portion, and the doping concentration of the first doped portion is greater than that of the second doped portion.

3. The terminal structure according to claim 2, characterized in that, The first doped portion includes a first sub-portion and a second sub-portion; The first sub-section is disposed at the contact position between the second doped section and the gate near the drift layer, and wraps around the end of the gate; The second sub-section is disposed on the side of the second doped section opposite to the drift layer, and is located on the side of the second doped section close to the gate.

4. The terminal structure according to claim 2, characterized in that, The terminal structure also includes an insulating dielectric layer, a metal component, and a stop ring; The cutoff ring and the second doped portion are disposed on the same side of the drift layer. Along the extension direction of the gate, the cutoff ring is located on the side of the drift layer away from the gate. The insulating dielectric layer is disposed on the side of the second doped portion opposite to the drift layer, and covers the second doped portion and at least a portion of the drift layer; The metal components are spaced apart on the side of the insulating dielectric layer that faces away from the drift layer.

5. A method for fabricating a terminal structure of a semiconductor device, characterized in that, The method includes: A drift layer is provided with a second doped portion; the second doped portion is disposed on one side of the drift layer; A trench is formed on one side of the drift layer where the second doped portion is located; the trench is used to accommodate the gate. A first doped portion is prepared at the end of the trench.

6. The preparation method according to claim 5, characterized in that, An insulating dielectric layer is disposed on the side of the second doped portion facing away from the drift layer; the process of forming a trench on the side of the drift layer where the second doped portion is disposed includes: A hard mask is prepared on the surface of the insulating dielectric layer; Etch the hard mask and the insulating dielectric layer until the drift layer is exposed; The drift layer is etched to form the trench.

7. The preparation method according to claim 6, characterized in that, The process of preparing a first doped portion at the end of the trench includes: Photoresist is coated on the surface of the trench and the unetched hard mask; Deactivate the photoresist at least at the ends of the trench; Remove the deactivated photoresist to expose the ends of the trench; Target impurity particles are injected to form the first doped portion.

8. The preparation method according to claim 7, characterized in that, After the step of injecting target impurity particles to form the first doped portion, the method further includes: Remove the remaining photoresist and hard mask, and etch the trench to form a chamfered structure at the ends of the trench.

9. The preparation method according to claim 7, characterized in that, A gate oxide layer is disposed between the gate and the drift layer; after the step of implanting target impurity particles to form the first doped portion, the method further includes: During the fabrication of the gate oxide layer, the first doped portion is activated by annealing so that at least a portion of the first doped portion covers the end of the trench.

10. The preparation method according to claim 5, characterized in that, An insulating dielectric layer is provided on the side of the second doped portion facing away from the drift layer; after the step of preparing the first doped portion at the end of the trench, the method further includes: A contact hole is prepared in the insulating dielectric layer; A metal part is fabricated at the location of the contact hole so that the terminal structure forms a conductive circuit.

11. A semiconductor device, characterized in that, The semiconductor device includes the terminal structure of the semiconductor device according to any one of claims 1 to 4, or the semiconductor device includes the terminal structure of the semiconductor device prepared by the method for preparing the terminal structure of the semiconductor device according to any one of claims 5 to 10.

12. An electrical appliance, characterized in that, Including the semiconductor device as described in claim 11.

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