An integrated adaptive cavity channel reverse conducting super junction HK dielectric IGBT device

Abstract

The application discloses an inverse conducting super-junction HK dielectric IGBT device integrated with adaptive hole channels, which comprises a P-type collector, an N+ short-circuit region, an N-type cutoff layer, an N-type drift region, a P column, an HK dielectric, an NCSL region, a P-body region, a P+ region, an N+ region, a SiO2 gate dielectric, a polysilicon separate gate, a polysilicon emitter gate, an emitter and a collector. The IGBT device has a structure in which the P column and the N-type drift region are alternately arranged with the HK column, so that a more optimal electric field distribution is achieved. The device is internally integrated with adaptive hole channels, is closed in a conduction state, enhances the conductance modulation by inhibiting hole extraction, reduces the conduction voltage, is opened during a turn-off transient period, shortens the turn-off time and reduces the turn-off loss by rapidly extracting holes from the drift region, and realizes the bidirectional conduction of the IGBT in the forward direction and the reverse direction by introducing the N+ short-circuit region at the bottom and forming a reverse parallel PIN freewheeling diode with the P-body region / N drift region.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically relating to a reverse-conductive superjunction HK dielectric IGBT device with integrated adaptive hole channels. Background Technology

[0002] Silicon carbide-based IGBTs, as third-generation semiconductor high-voltage power switching devices, are widely used in high-frequency, high-voltage scenarios such as new energy, rail transportation, and power grid inverters. Currently, commercially available and traditional SiC-IGBTs generally suffer from core technical problems such as the inability to synergistically optimize turn-off losses and on-state voltage drop, the breakdown voltage being limited by the degree of depletion of the drift region, and the need for a reverse-parallel external freewheeling diode, leading to lower device power density. Due to the inherent minority carrier storage effect of bipolar devices, carrier dissipation in the drift region is slow during turn-off, directly resulting in high turn-off losses and limited switching speed. Increasing the drift region thickness and optimizing doping to improve withstand voltage leads to a significant increase in forward voltage drop, creating an inherent contradiction between withstand voltage and losses. Furthermore, IGBTs need to withstand reverse freewheeling current in practical operation; traditional solutions require an external independent freewheeling diode, which not only increases package size and parasitic parameters but also reduces system power density and integration. Existing superjunction structures, gate dielectric optimization, or reverse-conducting structures cannot simultaneously solve the three major problems of loss, withstand voltage, and power density, making it difficult to meet the continuous upgrading requirements of high-voltage, high-frequency, high-efficiency, and high-density power electronic equipment for the comprehensive performance of devices. Summary of the Invention

[0003] The purpose of this invention is to solve the above-mentioned technical problems and provide a reverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel. By optimizing the electric field distribution through the superjunction structure and HK dielectric, the integrated adaptive hole channel realizes carrier control in the on and off states. Combined with the N+ short-circuit region, it realizes the reverse conduction function, and simultaneously reduces the on-state voltage drop and turn-off loss, and improves the breakdown voltage and power density.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] An inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channels includes a collector, a P-type collector disposed above the collector forming an ohmic contact; an N+ short-circuit region disposed to the left of the P-type collector; an N-type cutoff layer disposed above the P-type collector and the N+ short-circuit region; alternating arrangement of P-pillars, N-type drift regions, and HK dielectric above the N-type cutoff layer; an NCSL region disposed above the N-type drift region; a P-body region disposed above the NCSL region; and an N+ region and a P+ region disposed above the P-body region.

[0006] A first SiO2 gate dielectric is disposed on the right side of the P-body region, and a second SiO2 gate dielectric is disposed above the P-pillar; the first SiO2 gate dielectric covers a polysilicon discrete gate, and a polysilicon emitter gate is disposed above the second SiO2 gate dielectric; an emitter is disposed above the N+ region and the P+ region, forming an ohmic contact;

[0007] The P-pillar, the N-type drift region, and the HK dielectric are alternately arranged to optimize the electric field distribution and improve the breakdown voltage. The NCSL region and the polysilicon split gate cooperate to form an adaptive hole channel, which suppresses hole extraction when conducting to enhance conductivity modulation and reduce on-state voltage drop, and opens the channel to quickly extract holes when turning off to reduce turn-off loss. The P+ region, the P-body region, the NCSL region, the N-type drift region, the N-type cutoff layer, and the N+ short-circuit region constitute a reverse parallel PIN freewheeling diode to achieve bidirectional conduction.

[0008] In a preferred embodiment of the present invention, the N-type cutoff layer is continuously laid along the transverse direction of the device, and the bottom of the P-pillar, the N-type drift region and the HK dielectric are all in direct contact with the upper surface of the N-type cutoff layer, and the three are arranged adjacent to each other in the horizontal direction.

[0009] In a preferred embodiment of the present invention, the HK dielectric is a high dielectric constant dielectric pillar, the HK dielectric is located on the side of the P pillar away from the N-type drift region, and the HK dielectric, the P pillar, and the N-type drift region together constitute a superjunction composite drift region structure.

[0010] In a preferred embodiment of the present invention, the NCSL region completely covers the upper surface of the N-type drift region and part of the P-pillar, the lateral width of the NCSL region is the same as the lateral width of the N-type drift region, and the lower interface of the NCSL region is closely attached to the upper interface of the N-type drift region.

[0011] In a preferred embodiment of the present invention, the P-body region completely covers the upper surface of the NCSL region, the lateral width of the P-body region is equal to the lateral width of the NCSL region, and the P-body region extends to the side of the second SiO2 gate dielectric.

[0012] In a preferred embodiment of the present invention, the N+ region and the P+ region are arranged adjacent to each other on the upper surface of the P-body region, and the bottoms of the N+ region and the P+ region extend into the interior of the P-body region to form a heavily doped region.

[0013] In a preferred embodiment of the present invention, the first SiO2 gate dielectric is closely attached to the right sidewall and part of the upper surface of the P-body region, and the polysilicon separation gate completely encloses the upper surface and outer sidewall of the first SiO2 gate dielectric to form a gate-controlled insulating isolation structure.

[0014] In a preferred embodiment of the present invention, the second SiO2 gate dielectric partially covers the upper surface of the P-pillar, the lateral width of the second SiO2 gate dielectric is smaller than the top width of the P-pillar, and the polysilicon emitter gate and the P-pillar are electrically isolated through the second SiO2 gate dielectric.

[0015] In a preferred embodiment of the present invention, the N+ short-circuit region is a heavily doped N-type region, the bottom of the N+ short-circuit region is in direct contact with the collector, and the top of the N+ short-circuit region is in direct contact with the N-type cutoff layer.

[0016] In a preferred embodiment of the present invention, the substrate and functional layer of the device are both fabricated using 4H-SiC material. The P-type collector, the N-type cutoff layer, the N-type drift region, the NCSL region, and the P-body region are all epitaxial doped regions based on SiC material. The N+ short-circuit region, the N+ region, and the P+ region are all ion implantation regions based on SiC material.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. This invention achieves comprehensive performance improvements in three aspects—electric field control, carrier transport, and device integration—by integrating an adaptive hole channel, a superjunction HK dielectric structure, and an integrated reverse conduction structure, thereby achieving synergistic optimization of conduction and turn-off losses. The device forms an adaptive hole channel through the NCSL region and the polysilicon emitter gate. In the conduction state, the channel is closed, suppressing hole extraction and significantly enhancing the conduction modulation effect in the drift region, thus greatly reducing the forward conduction voltage drop. In the turn-off transient state, the channel automatically opens, rapidly extracting holes from the drift region, effectively weakening the minority carrier storage effect, significantly shortening the turn-off time, and reducing turn-off losses, thus resolving the technical contradiction of traditional bipolar devices where conduction and turn-off performance are difficult to balance.

[0019] 2. Significantly improves device breakdown voltage and electric field uniformity. A superjunction composite structure with alternating P-pillars, N-type drift regions, and HK dielectric pillars is adopted. The high dielectric constant of HK dielectric enhances the lateral electric field modulation capability, allowing the drift region to be depleted more fully and uniformly under the withstand voltage condition. This optimizes the longitudinal and lateral electric field distribution, suppresses electric field concentration, and achieves a higher breakdown voltage with the same drift region thickness. Alternatively, the drift region can be thinned to further reduce conduction losses under the same withstand voltage.

[0020] 3. Integrated reverse conduction function significantly improves power density. The N+ short-circuit region is integrated in the collector region, which, together with the P+ region, P-body region, NCSL region, N-type drift region, and N-type cutoff layer, naturally forms a reverse parallel PIN freewheeling diode. This achieves integrated forward conduction and reverse freewheeling of the IGBT, eliminating the need for an external freewheeling diode, reducing package size, lowering parasitic parameters, significantly improving device power density and system integration, and enhancing the device's applicability and reliability in high-frequency inverters and bridge arm circuits.

[0021] 4. Enhanced gate control capability and higher device stability. The use of a composite gate dielectric structure of HK dielectric and SiO2 improves gate control accuracy and interface quality, reduces gate leakage current, and enhances gate dielectric reliability under high temperature and high pressure conditions. The polysilicon discrete gate and polysilicon emitter gate are independently isolated, enabling independent control of the main channel and hole channel, thus improving device switching consistency and anti-interference capability.

[0022] 5. Adapting to SiC material characteristics to expand high-voltage and high-frequency application scenarios. The device is fabricated using SiC wide bandgap material, giving full play to the advantages of SiC's high critical electric field, high thermal conductivity, and high saturation drift velocity. It can operate stably under higher voltage, higher temperature, and higher frequency conditions, making it suitable for fields with stringent requirements for efficiency and reliability, such as new energy power generation, rail transportation, smart grids, and aerospace. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of the structure of a traditional IGBT device.

[0025] Figure 2 This application provides a schematic diagram of the structure of a reverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channels, as an embodiment of the present application.

[0026] Figure 3 This is a schematic flowchart illustrating a method for fabricating a reverse-conductive superjunction HK dielectric IGBT device with integrated adaptive hole channels, as provided in this application embodiment. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0028] Figure 2 Combination Figure 1 This invention provides a reverse-conductive superjunction HK dielectric IGBT device with integrated adaptive hole channels, including a collector 34, a P-type collector 24 disposed above the collector 34 and forming an ohmic contact; an N+ short-circuit region 15 disposed to the left of the P-type collector 24, an N-type cutoff layer 14 disposed above the P-type collector 24 and the N+ short-circuit region 15, and an alternating arrangement of P-pillars 23, N-type drift regions 13, and HK dielectric 42 above the N-type cutoff layer 14; an NCSL region 12 disposed above the N-type drift region 13, a P-body region 22 disposed above the NCSL region 12; and an N+ region 11 and a P+ region 21 disposed above the P-body region 22.

[0029] A first SiO2 gate dielectric 41 is disposed on the right side of the P-body region 22, and a second SiO2 gate dielectric 43 is disposed above the P-pillar 23; the first SiO2 gate dielectric 41 is covered with a polysilicon split gate 32, and a polysilicon emitter gate 33 is disposed above the second SiO2 gate dielectric 43; an emitter 31 is disposed above the N+ region 11 and the P+ region 21 to form an ohmic contact.

[0030] Among them, P-pillar 23, N-type drift region 13 and HK dielectric 42 are arranged alternately to optimize electric field distribution and improve breakdown voltage; NCSL region 12 and polysilicon split gate 32 cooperate to form an adaptive hole channel, which suppresses hole extraction when conducting to enhance conductivity modulation and reduce conduction voltage drop, and opens the channel to quickly extract holes when turning off to reduce turn-off loss; P+ region 21, P-body region 22, NCSL region 12, N-type drift region 13, N-type cutoff layer 14 and N+ short-circuit region 15 constitute a reverse parallel PIN freewheeling diode to achieve bidirectional conduction.

[0031] The N-type cutoff layer 14 is continuously laid along the transverse direction of the device. The bottom of the P-pillar 23, the N-type drift region 13 and the HK dielectric 42 are all in direct contact with the upper surface of the N-type cutoff layer 14, and the three are arranged adjacent to each other in the horizontal direction.

[0032] HK dielectric 42 is a high dielectric constant dielectric pillar. HK dielectric 42 is located on the side of P pillar 23 away from N-type drift region 13. HK dielectric 42, P pillar 23, and N-type drift region 13 together constitute a superjunction composite drift region structure.

[0033] The NCSL area 12 completely covers the upper surface of the N-type drift area 13 and part of the P-pillar 23. The lateral width of the NCSL area 12 is the same as the lateral width of the N-type drift area 13, and the lower interface of the NCSL area 12 is closely attached to the upper interface of the N-type drift area 13.

[0034] The P-body region 22 completely covers the upper surface of the NCSL region 12. The lateral width of the P-body region 22 is equal to the lateral width of the NCSL region 12. The P-body region 22 extends to the side of the second SiO2 gate dielectric 43.

[0035] N+ region 11 and P+ region 21 are arranged adjacently on the upper surface of P-body region 22. The bottoms of N+ region 11 and P+ region 21 extend into the interior of P-body region 22, forming a heavily doped region.

[0036] The first SiO2 gate dielectric 41 is in close contact with the right sidewall and part of the upper surface of the P-body region 22. The polysilicon separation gate 32 completely wraps the upper surface and outer sidewall of the first SiO2 gate dielectric 41 to form a gate-controlled insulating isolation structure.

[0037] The second SiO2 gate dielectric 43 partially covers the upper surface of the P pillar 23. The lateral width of the second SiO2 gate dielectric 43 is smaller than the top width of the P pillar 23. The polysilicon emitter gate 33 and the P pillar 23 are electrically isolated through the second SiO2 gate dielectric 43.

[0038] The N+ short-circuit region 15 is a heavily doped N-type region. The bottom of the N+ short-circuit region 15 is in direct contact with the collector 34, and the top of the N+ short-circuit region 15 is in direct contact with the N-type cutoff layer 14.

[0039] The substrate and functional layers of the device are both fabricated using 4H-SiC material. The P-type collector 24, N-type cutoff layer 14, N-type drift region 13, NCSL region 12, and P-body region 22 are all epitaxial doped regions based on SiC material; the N+ short-circuit region 15, N+ region 11, and P+ region 21 are all ion implantation regions based on SiC material.

[0040] This invention Figure 2 The device structure shown is relative to Figure 1 Several key improvements have been made to the traditional IGBT structure. The improvements and their corresponding effects are as follows:

[0041] Improved drift region structure: Traditional IGBT structures only use a single N-type drift region; this invention... Figure 2A superjunction composite structure is adopted above the N-type cutoff layer 14, in which P-pillars 23, N-type drift regions 13, and HK dielectric 42 are arranged alternately in the transverse direction. Its function is to enhance the transverse electric field modulation of the drift region, completely deplete the drift region, optimize the electric field distribution, suppress electric field concentration, and significantly improve the breakdown voltage; the high dielectric constant of the HK dielectric further enhances the gate control capability and withstand voltage performance.

[0042] The invention introduces a novel adaptive hole channel structure: a carrier-free adaptive control structure in traditional IGBT structures; Figure 2 An NCSL region 12, a second SiO2 gate dielectric 43, and a polysilicon emitter gate 33 are added, which, together with the P-pillar 23, form an adaptive hole channel. Function: In the on-state, the channel is closed, suppressing hole extraction, enhancing conductivity modulation, and reducing on-state voltage drop; in the off-state, the channel is open, rapidly extracting holes from the drift region, shortening turn-off time, and reducing turn-off losses, achieving synergistic optimization of on- and off-state performance.

[0043] Gate structure improvement: Traditional IGBTs have a single-gate structure; this invention... Figure 2 A dual-gate separation structure is adopted, namely, a first SiO2 gate dielectric 41 and a polysilicon separate gate 32 are located on the right side of the P-body region 22, and a second SiO2 gate dielectric 43 and a polysilicon emitter gate 33 are located above the P-pillar 23. Function: To achieve independent control of the main channel and hole channel, improve switching accuracy and stability, and enhance the dynamic performance and anti-interference capability of the device.

[0044] Improved collector structure: Traditional IGBTs have a single P-type collector; this invention... Figure 2 An N+ short-circuit region 15 is integrated next to the P-type collector 24. Its function is to form a reverse-parallel PIN freewheeling diode with the P+ region, P-body region, NCSL region, N-type drift region, and N-type cutoff layer, enabling bidirectional conduction of the device. This eliminates the need for an external freewheeling diode, improving power density, reducing package size, and lowering parasitic parameters.

[0045] Overall material and performance upgrades: Traditional IGBT structures are mostly made of silicon-based materials; this invention... Figure 2 It employs SiC wide-bandgap semiconductor material. Its function is to fully utilize the high critical electric field, high thermal conductivity, and high saturation drift velocity characteristics of SiC, enabling the device to operate stably under high voltage, high temperature, and high frequency conditions, thus expanding its application scenarios.

[0046] In conclusion, Figure 2 Compared to Figure 1 The core improvements are: superjunction HK dielectric composite drift region, adaptive hole channel, dual-gate separation structure, integrated N+ short-circuit reverse conduction structure, and SiC material system; the above improvements together achieve lower on-state voltage drop, lower turn-off loss, higher breakdown voltage, higher power density, and better high-temperature and high-voltage stability, comprehensively solving the performance bottlenecks of traditional IGBTs.

[0047] The working principle of this embodiment is as follows:

[0048] During normal operation, this device employs an alternating arrangement of P-pillars, N-type drift regions, and High-K dielectric material. By enhancing the lateral electric field strength of the drift regions, the drift regions are more completely depleted, thus improving the device's breakdown voltage. The device integrates an adaptive P-type hole channel using the emitter gate and NCSL region. During device turn-on, the NCSL region forms a barrier, suppressing hole extraction from the P-pillars, enhancing the device's conductance modulation and reducing the on-state voltage drop (Von). During the turn-off transient, as the P-pillar potential increases, the P-type hole channel opens, rapidly extracting holes from the drift region, thereby shortening the turn-off time and reducing the turn-off loss (Eoff). The P-type collector is embedded in the N+ short-circuit region, forming a reverse-parallel PIN freewheeling diode with the P-body region / N drift region, enabling bidirectional conduction. Therefore, the described characteristics contribute to achieving low turn-off loss, low on-state voltage drop, and high breakdown voltage, while also enabling bidirectional conduction and improving the overall electrical characteristics of the device.

[0049] like Figure 3 As shown, the fabrication method of the inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel in this embodiment includes the following steps:

[0050] Step 1: Substrate Preparation. An N-type 4H-SiC single crystal is selected as the substrate. Step 2: Epitaxial Layer Growth. An N-type drift region 13 is grown on the upper surface of the substrate using chemical vapor deposition (CVD). Step 3: Etching. Trenches are formed within the N-type drift region 13 using inductively coupled plasma (ICP) dry etching. Step 4: Filling to Form P-Pillars 23 and HK Dielectric 42. Step 5: Epitaxial Layer Growth. An NCSL region 13 is grown on the upper surface of the N-type drift region 13. Step 6: Epitaxial Layer Growth. A P-body region 22 is grown on the upper surface of the NCSL region 13. Step 7: Etching. Trenches are formed within the NCSL region 13 and the P-body region 22. Step 8: Gate Formation. A first SiO2 gate dielectric 41 and a second SiO2 gate dielectric 43 are formed using a dry oxygen oxidation process at 1200°C in high-temperature oxygen. A polysilicon discrete gate 32 and a polysilicon emitter gate 33 are formed on the gate oxide layer using photolithography and dry etching processes. Step 9: Emitter ion implantation. N+ regions 11 and 21 are implanted onto the upper surface of the P-body region 22 using an ion implantation process. Step 10: Collector ion implantation. A P-type collector 24 is implanted onto the lower surface of the N-type cutoff layer 14. Step 11: N+ short-circuit region formation. An N+ short-circuit region 15 is implanted to the left of the P-type collector 24. Step 12: Device electrode formation.

[0051] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A reverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel, characterized in that, The device includes a collector (34), a P-type collector (24) is disposed above the collector (34) and forms an ohmic contact; an N+ short-circuit region (15) is disposed on the left side of the P-type collector (24), an N-type cut-off layer (14) is disposed above the P-type collector (24) and the N+ short-circuit region (15), and a P-pillar (23), an N-type drift region (13), and an HK dielectric (42) are alternately arranged above the N-type cut-off layer (14); an NCSL region (12) is disposed above the N-type drift region (13), a P-body region (22) is disposed above the NCSL region (12); and an N+ region (11) and a P+ region (21) are disposed above the P-body region (22). A first SiO2 gate dielectric (41) is disposed on the right side of the P-body region (22), and a second SiO2 gate dielectric (43) is disposed above the P pillar (23); the first SiO2 gate dielectric (41) is covered with a polysilicon split gate (32), and a polysilicon emitter gate (33) is disposed above the second SiO2 gate dielectric (43); an emitter (31) is disposed above the N+ region (11) and the P+ region (21), forming an ohmic contact; The P-pillar (23), the N-type drift region (13), and the HK dielectric (42) are arranged alternately to optimize the electric field distribution and improve the breakdown voltage. The NCSL region (12) and the polysilicon split gate (32) cooperate to form an adaptive hole channel. When the circuit is turned on, the hole extraction is suppressed to enhance the conductivity modulation and reduce the on-state voltage drop. When the circuit is turned off, the channel is opened to quickly extract holes to reduce the turn-off loss. The P+ region (21), the P-body region (22), the NCSL region (12), the N-type drift region (13), the N-type cut-off layer (14), and the N+ short-circuit region (15) constitute a reverse parallel PIN freewheeling diode to achieve bidirectional conduction.

2. The inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel according to claim 1, characterized in that, The N-type cutoff layer (14) is laid continuously in the transverse direction of the device. The bottom of the P-pillar (23), the N-type drift region (13) and the HK dielectric (42) are all in direct contact with the upper surface of the N-type cutoff layer (14), and the three are arranged adjacent to each other in the horizontal direction.

3. The inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel according to claim 1, characterized in that, The HK dielectric (42) is a high dielectric constant dielectric pillar. The HK dielectric (42) is located on the side of the P pillar (23) away from the N-type drift region (13). The HK dielectric (42), the P pillar (23), and the N-type drift region (13) together constitute a superjunction composite drift region structure.

4. The inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel according to claim 1, characterized in that, The NCSL region (12) completely covers the upper surface of the N-type drift region (13) and part of the P-pillar (23). The lateral width of the NCSL region (12) is consistent with the lateral width of the N-type drift region (13). The lower interface of the NCSL region (12) is closely attached to the upper interface of the N-type drift region (13).

5. The inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel according to claim 1, characterized in that, The P-body region (22) completely covers the upper surface of the NCSL region (12), the lateral width of the P-body region (22) is equal to the lateral width of the NCSL region (12), and the P-body region (22) extends to the side of the second SiO2 gate dielectric (43).

6. The inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel according to claim 1, characterized in that, The N+ region (11) and the P+ region (21) are arranged adjacent to each other on the upper surface of the P-body region (22). The bottoms of the N+ region (11) and the P+ region (21) extend into the interior of the P-body region (22) to form a heavily doped region.

7. The inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel according to claim 1, characterized in that, The first SiO2 gate dielectric (41) is in close contact with the sidewall and part of the upper surface of the right side of the P-body region (22), and the polysilicon separation gate (32) completely wraps the upper surface and outer sidewall of the first SiO2 gate dielectric (41) to form a gate-controlled insulating isolation structure.

8. The inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel according to claim 1, characterized in that, The second SiO2 gate dielectric (43) partially covers the upper surface of the P pillar (23). The lateral width of the second SiO2 gate dielectric (43) is smaller than the top width of the P pillar (23). The polysilicon emitter gate (33) and the P pillar (23) are electrically isolated through the second SiO2 gate dielectric (43).

9. The inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel according to claim 1, characterized in that, The N+ short-circuit region (15) is a heavily doped N-type region. The bottom of the N+ short-circuit region (15) is in direct contact with the collector (34), and the top of the N+ short-circuit region (15) is in direct contact with the N-type cutoff layer (14).

10. The inverse-conducting superjunction HK dielectric IGBT device with integrated adaptive hole channel according to any one of claims 1-9, characterized in that, The substrate and functional layer of the device are both made of 4H-SiC material. The P-type collector (24), the N-type cutoff layer (14), the N-type drift region (13), the NCSL region (12), and the P-body region (22) are all epitaxial doped regions based on SiC material. The N+ short-circuit region (15), the N+ region (11), and the P+ region (21) are all ion implantation regions based on SiC material.

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