A power device, manufacturing method and chip

Abstract

The application discloses a kind of power device, manufacturing method and chip, applied to semiconductor technical field, can include drift region, carrier storage layer, P-type buried layer, P-type body region, N+ area, at least one first groove and second groove, gate oxide layer, P+ area, multiple P-type base region, interlayer dielectric and emitter metal;First groove extends to P-type buried layer, second groove passes through N+ area and extends to carrier storage layer and part is located in P-type body region;Hole path can be formed in P-type base region and P-type buried layer, so that hole is preferentially extracted from the path, reduce the number of hole extracted from the hole path near the gate polysilicon, in turn limit the rapid rise of displacement current near the gate polysilicon, weaken electromagnetic interference influence, P-type body region and N+ area can form hole barrier, inhibit the hole stored in P-type base region is extracted from the path, in turn weaken electromagnetic interference influence.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a power device, a manufacturing method, and a chip. Background Technology

[0002] With the rapid development of semiconductor technology, the demand for reducing electromagnetic interference in power semiconductor devices is increasing. In existing technologies, the number of holes in the hole accumulation region near the trench is reduced by split gate structure, thereby weakening the large accumulation of holes near the gate and limiting the rapid rise of displacement current near the gate, thus reducing electromagnetic interference. However, this solution is difficult to manufacture and has high manufacturing costs. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a power device, manufacturing method and chip that overcomes or at least partially solves the above problems.

[0004] In a first aspect, embodiments of the present invention provide a power device, comprising: a first cross-sectional region; The first cross-sectional region includes: Drift zone; A carrier storage layer is located on the upper surface of the drift region; A P-type buried layer is located within the carrier storage layer; The P-type body region is located within the carrier storage layer and is not in contact with the P-type buried layer; The N+ region is located within the carrier storage layer, and a portion of the N+ region is in contact with a portion of the surface of the P-type body region; At least one first trench and a second trench, the first trench extending to the P-type buried layer, the second trench passing through the N+ region and extending to the carrier storage layer and partially located within the P-type body region; the second trench is filled with gate polysilicon, and the first trench is filled with emitter polysilicon. A gate oxide layer is located on the sidewalls and bottom of the first trench and the sidewalls and bottom of the second trench; The P+ region is located within the P-shaped body region, and the upper surface of the P+ region is flush with the upper surface of the P-shaped body region. Multiple P-type base regions are located above the carrier storage layer and distributed on both sides of the first trench and extend into the second trench; Interlayer medium, located on a portion of the surface of the P-type base region, the surface of the first trench, the surface of the second trench, and a portion of the surface of the N+ region; The emitter metal is located on the surface of the interlayer dielectric, a portion of the surface of the P-type base region between the first trench, a portion of the surface of the N+ region, and the surface of the P+ region.

[0005] Optionally, the power device further includes: The cutoff layer is located below the drift region; The collector area is located below the cutoff layer; The collector metal is located below the P-type collector region.

[0006] Optionally, the P-type buried layer also extends into the drift region.

[0007] Optionally, the first trench includes a plurality of trenches, and the distance between the centers of a plurality of adjacent first trenches is less than or equal to 1.6 μm.

[0008] Optionally, it also includes a second cross-sectional area that alternates with the first cross-sectional area along a first direction; The second cross-sectional region includes the drift region, the carrier storage reservoir, the P-type body region, the N+ region, the at least one first trench, the second trench, the gate oxide layer, the P+ region, the plurality of P-type base regions, the interlayer dielectric, and the emitter metal.

[0009] Optionally, the N+ region is divided into a first N+ region and a second N+ region by the second trench.

[0010] Optionally, the doping concentration of the P-type base region is less than the doping concentration of the first N+ region and the second N+ region.

[0011] Optionally, the doping concentration of the P-type buried layer is greater than the doping concentration of the P-type base region.

[0012] Secondly, the present invention also discloses a method for manufacturing a power device, the method comprising: Provide substrate for the drift region; A carrier storage layer is formed on the substrate in the drift region; A P-type buried layer is formed within the carrier storage layer; A P-type body region and an N+ region are formed within the carrier storage layer, wherein the P-type body region is not in contact with the P-type buried layer, and a portion of the N+ region is in contact with a portion of the surface of the P-type body region. Etching is performed on a portion of the P-type buried layer, a portion of the carrier storage layer, and a portion of the N+ region, and silicon is deposited in the etched areas. A first trench is formed in a portion of the deposited silicon region, and a second trench is formed in the portion of the deposited silicon region and a portion of the N+ region. The first trench extends to the P-type buried layer, and the second trench passes through the N+ region and extends to the carrier storage layer and is partially located within the P-type body region. Polycrystalline silicon is filled in the first trench and the second trench; A gate oxide layer is formed on the sidewalls and bottom of the first trench and the second trench; Multiple P-type base regions are formed on both sides of the first trench, and the P-type base regions are located above the carrier storage layer and extend into the second trench; A P+ region is formed within the P-type body region; and the upper surface of the P+ region is flush with the upper surface of the P-type body region. An interlayer medium is formed on a portion of the surface of the P-type base region, the surface of the first trench, the surface of the second trench, and a portion of the surface of the N+ region. An emitter metal is formed on the surface of the interlayer medium, a portion of the surface of the P-type base region between the first trenches, a portion of the surface of the N+ region, and the surface of the P+ region.

[0013] Thirdly, the present invention also discloses a chip comprising the aforementioned power device.

[0014] The present invention has the following advantages: This invention discloses a power device, a fabrication method, and a chip. The invention may include a drift region, a carrier storage layer, a P-type buried layer, a P-type body region, an N+ region, at least one first trench and a second trench, a gate oxide layer, a P+ region, multiple P-type base regions, an interlayer dielectric, and an emitter metal. The first trench extends to the P-type buried layer, and the second trench passes through the N+ region and extends to the carrier storage layer, partially located within the P-type body region. The N+ region is divided into a first N+ region and a second N+ region by the second trench. A hole path can be formed in the P-type base region and the P-type buried layer, allowing holes to be preferentially extracted from this path, reducing the number of holes extracted from the hole path near the gate polysilicon, thereby limiting the rapid rise of displacement current near the gate polysilicon and weakening the impact of electromagnetic interference. The P-type body region and the N+ region can form a hole barrier, suppressing the extraction of holes stored in the P-type base region from this path, thereby weakening the impact of electromagnetic interference.

[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of a power device according to an embodiment of the present invention; Figure 2 This is a structural block diagram of a power device according to an embodiment of the present invention from a certain perspective; Figure 3 This is a schematic diagram of the structure of a power device provided by related technologies; Figure 4 This is a structural block diagram of another power device provided in an embodiment of the present invention; Figure 5 This is a structural block diagram of another power device provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the hole path when a power device is turned on, provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the hole path when a power device is turned off, provided by an embodiment of the present invention; Figure 8 This is a structural block diagram of another junction field-effect transistor provided in an embodiment of the present invention; Figure 9 This is a structural block diagram of another power device provided in an embodiment of the present invention; Figure 10 This is a structural block diagram of a second cross-sectional region provided in an embodiment of the present invention; Figure 11 This is a flowchart illustrating the steps of a method for manufacturing a power device according to an embodiment of the present invention; Figure 12 This is a schematic flowchart of a method for manufacturing a power device according to an embodiment of the present invention; Figure 13 This is a schematic flowchart of another method for manufacturing a power device provided in an embodiment of the present invention; Figure 14 This is a schematic flowchart of another method for manufacturing a power device provided in an embodiment of the present invention; Figure 15 This is a schematic flowchart of another method for manufacturing a power device provided in an embodiment of the present invention; Figure 16 This is a schematic flowchart of another method for manufacturing a power device provided in an embodiment of the present invention; Figure 17 This is a schematic flowchart of another method for manufacturing a power device provided in an embodiment of the present invention; Figure 18 This is a schematic flowchart of another method for manufacturing a power device provided in an embodiment of the present invention. Detailed Implementation

[0017] Embodiments of the present invention will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0018] This invention discloses a power device, which may include a drift region, a carrier storage layer, a P-type buried layer, a P-type body region, an N+ region, at least one first trench and a second trench, a gate oxide layer, a P+ region, multiple P-type base regions, an interlayer dielectric, and an emitter metal. The first trench extends to the P-type buried layer, and the second trench passes through the N+ region and extends to the carrier storage layer, with a portion located within the P-type body region. A hole path can be formed in the P-type base region and the P-type buried layer, allowing holes to be preferentially extracted from this path, reducing the number of holes extracted from the hole path near the gate polysilicon, thereby limiting the rapid rise of the displacement current near the gate polysilicon and weakening the impact of electromagnetic interference. The P-type body region and the N+ region can form a hole barrier, suppressing the extraction of holes stored in the P-type base region from this path, thereby weakening the impact of electromagnetic interference.

[0019] Reference Figure 1 The diagram illustrates a structural block diagram of a power device according to an embodiment of the present invention, which may include: a first cross-sectional region AA', wherein the first cross-sectional region AA' may include: Drift Zone 101; The carrier storage layer 102 is located on the upper surface of the drift region; P-type buried layer 103 is located within the carrier storage layer; The P-type body region 104 is located within the carrier storage layer and is not in contact with the P-type buried layer 103; N+ region 105 is located within the carrier storage layer, and part of the N+ region is in contact with part of the surface of the P-type body region; At least one first trench 1061 and a second trench 1062, the first trench extending to the P-type buried layer, the second trench passing through the N+ region and extending to the carrier storage layer and partially located within the P-type body region; the second trench is filled with gate polysilicon, and the first trench is filled with emitter polysilicon. Gate oxide layer 107 is located on the sidewall and bottom of the first trench, and on the sidewall and bottom of the second trench; P+ region 108 is located within the P-type body region, and the upper surface of P+ region is flush with the upper surface of P-type body region; Multiple P-type base regions 109 are located above the carrier storage layer and distributed on both sides of the first trench and extend to the second trench; Interlayer medium 110, located on a portion of the surface of the P-type base region, the surface of the first trench, the surface of the second trench, and a portion of the surface of the N+ region; Emitter metal 111 is located on the surface of the interlayer dielectric, a portion of the surface of the P-type base region between the first trenches, a portion of the surface of the N+ region, and the surface of the P+ region.

[0020] In embodiments of the present invention, such as Figure 2 The diagram illustrates a structural block diagram of a power device provided by an embodiment of the present invention from a single viewpoint, wherein the above-mentioned Figure 1 The structural block diagram is as follows Figure 2 Cross-sectional view along the middle AA'.

[0021] Figure 1 In the middle, the drift region 101 can be an N-type doped drift region. As the voltage withstand and current conduction substrate structure of the power device, the drift region is the basic functional layer of the power device. It is located in the lower layer of the device and provides a support substrate for all functional layer structures above. The material can be an N-type semiconductor. It is the key area for the power device to withstand reverse high voltage and realize carrier drift conduction.

[0022] The carrier storage layer 102 can be an N-type carrier storage layer. The carrier storage layer is located on the upper surface of the drift region and sandwiched between the drift region and the P-type base region above. It is a key structure for optimizing the switching characteristics and reducing the switching loss of the power device. The function of this structure is to store a large number of minority carriers during the device conduction period, which greatly increases the carrier concentration during conduction, effectively reduces the forward conduction voltage drop of the device, and reduces conduction loss.

[0023] The P-type buried layer 103 is an embedded P-type doped region that can be located inside the carrier storage layer. It serves as an auxiliary breakdown voltage and electric field modulation structure within the device. This structure can effectively modulate the electric field distribution inside the device, optimize the electric field strength at the interface between the drift region and the carrier storage layer, alleviate the electric field concentration effect inside the device under high voltage operation, avoid device breakdown caused by excessively high local electric fields, and improve the reverse breakdown voltage stability and avalanche resistance of the device. At the same time, the P-type buried layer can form a PN junction with the surrounding N-type carrier storage layer. When reverse cutoff occurs, it can help block the high voltage at the drain end, shunt part of the reverse electric field stress, effectively improve the high voltage reliability of the device, and also suppress parasitic leakage current during device operation, thus optimizing the device's turn-off characteristics.

[0024] P-type body region 104 is a P-type main functional region embedded inside the carrier storage layer. It is different from the embedded structure of the P-type buried layer and does not contact the P-type buried layer 103. As the P-type doped host, the P-type body region can form a complete PN junction structure with the surrounding N-type carrier storage layer and N+ region to build the electrical junction barrier of the power device.

[0025] The N+ region 105 is a highly concentrated N-type doped region located inside the carrier storage layer. Part of the N+ region 105 is in close contact with a portion of the P-type bulk region. It is a key heavily doped region for achieving ohmic contacts and constructing carrier conduction channels. The high doping characteristic gives this region extremely low resistivity, significantly reducing contact resistance and conduction losses during forward conduction and improving current transfer efficiency. The first trench 1061 and the second trench 1062 are two functionally differentiated etched trench structures within the power device. They form a three-dimensional structure that achieves trench gate control, polysilicon filling, and zoned electrical isolation. The filling materials and functions of the two trenches are completely different. The first trench is etched deep into the P-type buried layer and filled with emitter polysilicon. Its main function is to work with the bottom P-type buried layer to construct an emitter conduction and isolation structure, achieving vertical conduction in the emitter region of the device. At the same time, the three-dimensional trench structure optimizes the internal electric field distribution and improves the withstand voltage performance. The second trench is a through-type trench structure that can be filled with gate polysilicon, serving as the trench gate carrier of the device. The two trenches work together to form a discrete gate and emitter polysilicon structure, achieving physical isolation between gate control and emitter conduction, avoiding electrode crosstalk. At the same time, the trench-type three-dimensional structure significantly reduces the lateral size of the device, improves the device integration, and optimizes the channel density and switching response speed.

[0026] The gate oxide layer 107 is an insulating dielectric layer uniformly grown on the inner walls of all trenches, completely covering the sidewalls and bottom of the first trench and the sidewalls and bottom of the second trench. It is the dielectric structure for power devices to achieve gate insulation and gate-controlled coupling. This structure has extremely high insulation performance and dielectric stability, which can completely isolate the polysilicon in the trench from the surrounding semiconductor silicon substrate, effectively preventing leakage and short circuits between the gate polysilicon, emitter polysilicon and the underlying semiconductor region, and ensuring the electrical independence of the device electrode structure. At the same time, the gate oxide layer is a key dielectric for gate electric field coupling. When a control voltage is applied to the gate, the electric field can act on the surface of the P-type body region through the gate oxide layer, regulate the surface carrier concentration, and realize the opening and closing of the channel.

[0027] The P+ region 108 is a highly concentrated P-type doped region located inside the P-type body region, with its upper surface completely flush with the upper surface of the P-type body region. It is a heavily doped contact optimization structure for the device. The high concentration of P-type doping significantly reduces the contact resistance between the P-type body region and the upper emitter metal, achieving good ohmic contact in the P-type body region, effectively eliminating contact voltage drop during device operation, and reducing conduction losses.

[0028] Multiple P-type base regions 109 are surface P-type doped regions distributed above the carrier storage layer. They are arranged in an array on both sides of the first trench, and the region boundary extends to the position of the second trench. They are the isolation and electrical control regions on the surface of the power device.

[0029] Interlayer dielectric 110 is an insulating and isolating dielectric layer on the surface of the device, covering part of the surface of the P-type base region, the entire surface of the first trench, the entire surface of the second trench, and part of the surface of the N+ region. It is a key structure for the isolation of the surface electrodes and the insulation of the circuit of the power device. This dielectric layer has excellent insulation, withstand voltage and passivation properties. Its function is to isolate the non-target contact area between the surface emitter metal and the underlying trench polysilicon and semiconductor substrate, limit the conduction contact range of the electrodes, avoid short circuits and leakage between the metal layer and the underlying structure, and eliminate electrical crosstalk between electrodes. At the same time, the interlayer dielectric can passivate semiconductor defects on the surface of the device, reduce the surface state density, suppress surface leakage and device aging failure, improve the long-term operating reliability of the device, and also flatten the surface structure of the device, providing a good process basis for the uniform deposition of the emitter metal.

[0030] Emitter metal 111 is the outermost conductive metal layer of the device, covering the surface of the interlayer dielectric, the surface of the P-type base region between the first trenches, the surface of the N+ region, and the surface of the P+ region. It is the core electrode lead-out structure of the device, responsible for collecting and outputting the device's conduction current. This emitter metal layer has extremely low resistivity, excellent conductivity, and adhesion stability, enabling it to collect the conduction current of each power unit of the device over a large area. After convergence, it achieves stable current output, significantly reducing the electrode loss of the device. At the same time, its multi-region bonding structure design can simultaneously achieve stable contact with the N-type conduction region and the P-type potential fixed region, taking into account the requirements of current transmission and potential stability. It also effectively improves the current uniformity of the device, avoids overheating and breakdown problems caused by local current concentration, and ensures the high-power and high-stability operating characteristics of the device.

[0031] like Figure 3 The diagram shows a structural block diagram of a power device provided by the related technology. It can be seen that the power device in the related technology does not include a P-type buried layer. The hole path is the path between the P-type body region and the P-type base region. This path can charge the gate, causing a rapid increase in the displacement current near the gate, which worsens the EMI (Electromagnetic Interference) effect.

[0032] like Figure 4The diagram illustrates a structural block diagram of another power device provided by an embodiment of the present invention. The power device of the present invention may include a P-type buried layer. When the concentration of the P-type buried layer is at least one order of magnitude greater than that of the P-type base region, the concentration difference between the P-type buried layer and the P-type base region can form a hole path, so that holes can be drawn away from the path more effectively, thereby reducing the number of holes drawn away from the hole path near the gate, and thus limiting the rapid rise of the displacement current near the gate and optimizing the EMI effect.

[0033] like Figure 5 This diagram illustrates a structural block diagram of another power device provided by an embodiment of the present invention. Since the N+ and P-type body regions form a PN junction, a built-in barrier, i.e., a built-in electric field, is formed from the N+ region to the P-type body region. This barrier hinders the movement of holes. Due to the concentration difference, the N+ region and the carrier storage layer form a high-low junction, causing electrons in the deep N+ region to drift towards the carrier storage layer. Therefore, the potential of the deep N+ region is higher than that of the carrier storage layer. It can be understood that N+ and N- form a PN junction with the electric field direction from N+ to N-. The potential of the deep N+ region will prevent holes from accumulating near the gate oxide. The deep N+ region can significantly reduce the number of holes that are drawn away from the hole path near the gate, limit the rapid rise of the displacement current near the gate, and optimize the EMI effect.

[0034] like Figure 6 This diagram illustrates a hole path during the turn-on of a power device according to an embodiment of the present invention. Since both the P+ buried layer and the P-type body region form a built-in electric field with the carrier storage layer, they attract holes. Meanwhile, the high-low junction formed by the N+ and the carrier storage layer hinders the accumulation of holes below the gate.

[0035] like Figure 7 The diagram illustrates a hole path when a power device is turned off, as provided in an embodiment of the present invention. It can be seen that the hole path is from the P-type base region to the P-type buried layer, which allows holes to be drawn away from this path more effectively, thus reducing the number of holes drawn away from the hole path near the gate.

[0036] like Figure 8 This diagram illustrates a structural block diagram of another junction field-effect transistor provided by an embodiment of the present invention. This junction field-effect transistor can be composed of two transistors of the present invention. Figure 1The provided power device composition shows that the junction field-effect transistor (JFET) is formed by two power devices, each with its own N+ region 105 and P-type body region 104. As the voltage applied to the gate gradually increases, the P-type body region in the JFET gradually depletes until it is pinched off. When the JFET region is pinched off, holes cannot be extracted from it. The floating P-region can modulate the distribution of charge carriers, enhance the conductivity modulation effect of the drift region, reduce the on-state voltage drop, reduce the current path, and improve short-circuit performance. During the turn-on phase, as the gate voltage gradually increases, the depletion region of the JFET gradually expands until it is pinched off, effectively weakening the hole path and thus limiting the rapid rise of the displacement current near the gate, optimizing the EMI effect.

[0037] This invention discloses a power device, which may include a drift region, a carrier storage layer, a P-type buried layer, a P-type body region, an N+ region, at least one first trench and a second trench, a gate oxide layer, a P+ region, multiple P-type base regions, an interlayer dielectric, and an emitter metal. The first trench extends to the P-type buried layer, and the second trench passes through the N+ region and extends to the carrier storage layer, and is partially located within the P-type body region. A hole path can be formed by the P-type base region and the P-type buried layer, so that holes are preferentially extracted from this path, reducing the number of holes extracted from the hole path near the gate polysilicon, thereby limiting the rapid rise of the displacement current near the gate polysilicon and weakening the influence of electromagnetic interference. The P-type body region and the N+ region can form a hole barrier to suppress the extraction of holes stored in the P-type base region from this path, thereby weakening the influence of electromagnetic interference.

[0038] In one embodiment of the present invention, the power device further includes: Cutoff layer 112 is located below the drift zone; Collector region 113 is located below the cutoff layer; Collector metal 114 is located below the P-type collector region.

[0039] In this embodiment of the invention, the cutoff layer is disposed below the drift region, serving as a transition buffer semiconductor functional layer between the drift region and the lower collector region. It is generally made of low-doped N-type or similar material, and it bears the carriers and high-voltage electric field stress conducted longitudinally from the upper drift region. When the device is turned off and subjected to reverse high voltage conditions, it can distribute the electric field intensity borne by the drift region, preventing the electric field from concentrating and breaking down the silicon substrate. During the high current transmission stage of the power device in the forward conduction phase, the cutoff layer does not form a significant barrier to the electron carriers, ensuring that the longitudinal current is smoothly transported from the drift region to the collector region. At the same time, this layer can block the rapid upward diffusion of highly doped impurities from the collector region into the drift region, preventing the doping concentration in the drift region from being increased and impairing the withstand voltage capability. It can also alleviate the process stress caused by the difference in lattice doping between the upper and lower layers, improve the overall wafer structure stability, and suppress adverse phenomena such as leakage dark current and reverse leakage current, playing multiple roles of voltage stabilization buffer, impurity blocking, and leakage current suppression.

[0040] The collector region is located directly below the cutoff layer and is the collector semiconductor substrate of the power device. It is usually a P-type region adapted to conduction requirements. When the device is turned on, a large number of electron carriers that have been conducted through the drift region, carrier storage layer and trench channel will eventually all flow into the collector region to complete the current collection.

[0041] The collector metal is located on the lower surface of the collector area and is the conductive electrode layer that connects the power device's collector terminal to the external circuit. It is usually made of a metal material with low resistivity, strong adhesion, and high temperature resistance. During the operation of the power device, all the current collected in the collector area is output to the external power circuit through the collector metal.

[0042] In one embodiment of the invention, the P-type buried layer further extends into the drift region.

[0043] In embodiments of the present invention, such as Figure 9 This diagram illustrates a structural block diagram of another power device provided by an embodiment of the present invention. The P-type buried layer 103 can further extend into the drift region 101, and the first P+ buried layer can be as follows: Figure 9 By fabricating a P-Pillar structure, it can function similarly to a semi-superjunction. P-Pillar fabrication involves first etching wide trenches, then filling these trenches with P-Pillars. The P-Pillars are typically doped with phosphorus (P), with a concentration generally around 5e14cm⁻¹. -3 ~1e16cm -3 between.

[0044] Because a P-pillar structure is added in the vertical direction of the device, a transverse electric field modulation effect is generated in the drift region under the blocking voltage operating state. This effect completely depletes the excess charge carriers in the transverse direction, and the originally tilted electric field distribution is approximately flattened, thereby increasing the breakdown voltage of the power device. Furthermore, because more charge carriers can be depleted laterally, the doping concentration of the power device can be greatly increased, which can also reduce the on-resistance of the device. In other words, the breakdown voltage of the device is not reduced while the on-resistance is reduced, and it can even be increased accordingly.

[0045] In one embodiment of the present invention, the first trench includes a plurality of trenches, and the distance between the centers of the plurality of adjacent first trenches is less than or equal to 1.6 μm.

[0046] In this embodiment of the invention, the number of first trenches is multiple, meaning at least two. The spacing between the centers of multiple adjacent first trenches can be controlled within 1.6 μm, which can increase the power unit arrangement density per unit area of ​​the chip, increase the effective conductive area to improve current carrying capacity and reduce on-state voltage drop. At the same time, the densely arranged trenches, combined with the internal emitter polysilicon, can uniformly modulate the internal electric field, alleviate local electric field spikes, and reduce switching losses while ensuring voltage withstand stability, thereby improving the overall power density and operating efficiency of the device.

[0047] In one embodiment of the present invention, a second cross-sectional region is further included, which is alternately arranged with the first cross-sectional region along a first direction; the second cross-sectional region includes the drift region, carrier storage reservoir, P-type body region, N+ region, at least one first trench, second trench, gate oxide layer, P+ region, multiple P-type base regions, interlayer dielectric and emitter metal.

[0048] In embodiments of the present invention, such as Figure 2 BB' represents the second section region. The first section region and the second section region are arranged alternately in the first direction. A corresponding cross-sectional view can be taken from the second section region, such as... Figure 10 This illustrates a structural block diagram of a second cross-sectional region provided in an embodiment of the present invention; the second cross-sectional region and... Figure 1 The first cross-sectional region includes the same drift region, carrier storage reservoir, P-type body region, N+ region, at least one first trench, second trench, gate oxide layer, P+ region, multiple P-type base regions, interlayer dielectric and emitter metal. The second cross-sectional region differs from the first cross-sectional region in that it does not include the P-type buried layer 103. When the section is cut from AA', only the P-type buried layer 103 can be seen. When the section is cut from BB', the P-type buried layer 103 cannot be seen.

[0049] In one embodiment of the present invention, the N+ region is divided into a first N+ region and a second N+ region by a second trench.

[0050] In embodiments of the present invention, such as Figure 1 Due to the penetrating and separating effect of the second trench 1062, the N+ region can be divided into two independent sub-regions: the first N+ region 1051 and the second N+ region 1052. The partitioned N+ regions can adapt to different electrical connection requirements and form good ohmic contact with the upper emitter metal to ensure stable output of conduction current. At the same time, the trench structure optimizes the local carrier distribution and suppresses the parasitic effects of power devices.

[0051] In one embodiment of the present invention, the doping concentration of the P-type base region is less than the doping concentration of the first N+ region and the second N+ region.

[0052] In this embodiment of the invention, the low-doped P-type base region can ensure the channel control accuracy of the power device, reduce the junction capacitance, and optimize the breakdown voltage and switching characteristics. At the same time, the high-doped N+ region can significantly reduce the contact resistance between the semiconductor and the emitter metal, forming a good ohmic contact and effectively reducing the forward conduction loss of the device. The difference in concentration between the two regions balances the switching performance and conduction capability of the device.

[0053] In one embodiment of the present invention, the doping concentration of the P-type buried layer is greater than the doping concentration of the P-type base region.

[0054] In this embodiment of the invention, since the concentration of the P-type buried layer is at least one order of magnitude greater than that of the P-type base region, the concentration difference between the P-type buried layer and the P-type base region can form a hole path, so that holes are preferentially drawn away from this path, reducing the number of holes drawn away from the hole path near the gate, thereby limiting the rapid rise of the displacement current near the gate and optimizing the EMI effect.

[0055] This invention discloses a power device, which may include a drift region, a carrier storage layer, a P-type buried layer, a P-type body region, an N+ region, at least one first trench and a second trench, a gate oxide layer, a P+ region, multiple P-type base regions, an interlayer dielectric, and an emitter metal. The first trench extends to the P-type buried layer, and the second trench passes through the N+ region and extends to the carrier storage layer, with a portion located within the P-type body region. A hole path can be formed in the P-type body region and the P-type buried layer, allowing holes to be preferentially extracted from this path, reducing the number of holes extracted from the hole path near the gate polysilicon, thereby limiting the rapid rise of the displacement current near the gate polysilicon and weakening the impact of electromagnetic interference. The P-type body region and the N+ region can form a hole barrier, suppressing the extraction of holes stored in the P-type base region from this path, thereby weakening the impact of electromagnetic interference.

[0056] like Figure 11 The diagram illustrates a flowchart of a method for fabricating a power device according to an embodiment of the present invention. The method includes: Step 201: Provide a drift region substrate.

[0057] In this embodiment of the invention, the drift region can be N-type doped, and a semiconductor silicon wafer with standard thickness and uniform N-type doping concentration can be used as the drift region substrate.

[0058] Step 202: Form a carrier storage layer on the drift region substrate.

[0059] In this embodiment of the invention, a 200-400 Å oxide layer can be grown on top of the N-type drift region using thermal oxygenation. Then, an N-CSL region is prepared on the surface of the N-type drift region using ion implantation with a mask. The N-CSL is implanted with phosphorus (P) as the donor dopant, typically at a concentration of 1e12cm⁻¹. -3 ~1e14cm -3 Between, such as Figure 12 The diagram illustrates a process flow of a power device fabrication method provided by an embodiment of the present invention, in which a carrier storage layer can be obtained by implanting phosphorus P donor doping onto a substrate in the drift region.

[0060] Step 203: Form a P-type buried layer within the carrier storage layer.

[0061] In embodiments of the present invention, such as Figure 13 This diagram illustrates a flow chart of another method for fabricating a power device according to an embodiment of the present invention. A P-type buried layer 103 can be formed within the carrier storage layer 102 using ion implantation with a mask. The concentration of the acceptor dopant (typically boron B) implanted into the P+ buried layer is typically 1e13cm⁻¹. -3 ~1e15cm -3 between.

[0062] Step 204: A P-type body region and an N+ region are formed in the carrier storage layer, wherein the P-type body region does not contact the P-type buried layer, and part of the N+ region contacts part of the surface of the P-type body region.

[0063] In embodiments of the present invention, such as Figure 13 A P-type bulk region 104 can be first fabricated on the wafer surface using ion implantation within the carrier storage layer 102 in conjunction with a mask, followed by the N+ region 105. The concentration of acceptor doping (typically boron B) implanted into the P-type bulk region 104 is typically 8e12cm. -3 ~5e14cm -3 Between these points, the concentration of donor-doped (typically arsenic, As) implanted in the N+ region at 105 cm⁻¹ is generally 1e¹⁵ cm⁻¹. -3 ~5e15cm -3 between.

[0064] Step 205: Etch in a portion of the P-type buried layer, a portion of the carrier storage layer, and a portion of the N+ region, and deposit silicon in the etched areas.

[0065] In embodiments of the present invention, such as Figure 14 The diagram illustrates a process flow diagram of another power device fabrication method provided by an embodiment of the present invention. Etching can be performed on a portion of the P-type buried layer, a portion of the carrier storage layer, and a portion of the N+ region, and dry etching can be used.

[0066] like Figure 15 The diagram illustrates a process flow diagram of another power device fabrication method provided by an embodiment of the present invention, in which silicon can be deposited in the etched area with a doping concentration consistent with N-Drift.

[0067] Step 206: A first trench is formed in a portion of the deposited silicon region, and a second trench is formed in a portion of the deposited silicon region and a portion of the N+ region. The first trench extends to the P-type buried layer, and the second trench passes through the N+ region and extends to the carrier storage layer and is partially located within the P-type bulk region.

[0068] In embodiments of the present invention, such as Figure 16 This diagram illustrates a flow chart of another power device fabrication method provided by an embodiment of the present invention. It describes a method for removing the oxide layer generated by thermal oxidation on the silicon surface, followed by the deposition of a layer of LPTEOS several thousand angstroms thick. Using a mask, trenches are etched in specific windows using dry etching to remove the LPTEOS. Isotropic etching is then performed to smooth the bottom of the trenches, resulting in a first trench and a second trench. Finally, a dry oxidation method is used again to prepare an oxide layer of approximately 1000-1200 angstroms. The trench filling doping concentration is 1e20cm. -3 ~3e20cm -3 The polysilicon is then etched, and the excess polysilicon above the silicon surface is then etched.

[0069] Step 207: Fill the first trench with emitter polysilicon and fill the second trench with gate polysilicon.

[0070] In embodiments of the present invention, such as Figure 16 Emitter polysilicon can be filled in the first trench, and gate polysilicon can be filled in the second trench.

[0071] Step 208: A gate oxide layer is formed on the sidewalls and bottom of the first and second trenches.

[0072] In this embodiment of the invention, a gate oxide layer 107 may be formed on the sidewalls and bottom of the first trench and the second trench.

[0073] Step 209: A plurality of P-type base regions are formed on both sides of the first trench. The P-type base regions are located above the carrier storage layer and extend into the second trench.

[0074] like Figure 17 This diagram illustrates a process flow of another power device fabrication method provided by an embodiment of the present invention. Multiple P-type base regions 109 can be formed on both sides of the first trench 1061 using ion implantation. The concentration of the P-Base implantation acceptor dopant (typically boron B) is typically 8e12cm⁻¹. -3 ~5e14cm -3 between.

[0075] Step 210: Form a P+ region within the P-type body region; and the upper surface of the P+ region is flush with the upper surface of the P-type body region; In embodiments of the present invention, such as Figure 17The P+ region 108 can be formed within the P-type body region 107 by ion implantation. The concentration of the P+ implantation acceptor dopant (typically boron difluoride BF2) is generally 5e14cm. -3 ~2e15cm -3 between.

[0076] Step 211: An interlayer medium is formed on a portion of the surface of the P-type base region, the surface of the first trench, the surface of the second trench, and a portion of the surface of the second N+ region.

[0077] In this embodiment of the invention, an interlayer dielectric 110 can be formed on a portion of the surface of the P-type base region, the surface of the first trench, the surface of the second trench, and a portion of the surface of the second N+ region, and then as follows: Figure 18 The diagram illustrates a process flow of another power device fabrication method provided by an embodiment of the present invention, in which the interlayer dielectric 110 is etched to form contact holes, followed by sputtering a layer of TI / TIN of several hundred angstroms, and then rapid annealing is performed.

[0078] Step 212: An emitter metal is formed on the surface of the interlayer dielectric, a portion of the surface of the P-type base region between the first trenches, a portion of the surface of the second N+ region, and the surface of the P+ region.

[0079] In this embodiment of the invention, a layer of AlCu several micrometers can be sputtered onto the surface of the interlayer medium, a portion of the surface of the P-type base region between the first trenches, a portion of the surface of the second N+ region, and the surface of the P+ region to form an emitter metal. Ti / TIN and AlCu will form a good mechanical connection.

[0080] This invention discloses a method for fabricating a power device, which may include a drift region, a carrier storage layer, a P-type buried layer, a P-type body region, an N+ region, at least one first trench and a second trench, a gate oxide layer, a P+ region, multiple P-type base regions, an interlayer dielectric, and an emitter metal; the first trench extends to the P-type buried layer, and the second trench passes through the N+ region and extends to the carrier storage layer, and is partially located within the P-type body region; the N+ region is divided into a first N+ region and a second N+ region by the second trench; a hole path can be formed in the P-type body region and the P-type buried layer, so that holes are preferentially extracted from this path, reducing the number of holes extracted from the hole path near the gate polysilicon, thereby limiting the rapid rise of the displacement current near the gate polysilicon and weakening the influence of electromagnetic interference; the P-type body region and the N+ region can form a hole barrier to suppress the extraction of holes stored in the P-type base region from this path, thereby weakening the influence of electromagnetic interference.

[0081] In one embodiment of the present invention, it includes: A cutoff layer is formed beneath the substrate in the drift region; A current-collecting region is formed below the cutoff layer; Collector metal is formed below the collector region.

[0082] In this embodiment of the invention, the cutoff layer 112 and the current collector region 113 are prepared by ion implantation, and the implantation concentration of the N-cutoff layer is 1e12cm. -3 ~1e14cm -3 The injection concentration in the collector region is 5e12cm. -3 ~2e14cm -3 Finally, a layer of alloy with multiple thicknesses and compositions is sputtered on the back side to form the current collector metal 114, resulting in... Figure 1 The power transistor shown.

[0083] In one embodiment of the present invention, the doping concentration of the P-type buried layer is greater than the doping concentration of the P-type base region.

[0084] In one embodiment of the present invention, the first trench includes a plurality of trenches, and the distance between the centers of the plurality of adjacent first trenches is less than or equal to 1.6 μm.

[0085] In one embodiment of the present invention, the N+ region is divided into a first N+ region and a second N+ region by a second trench.

[0086] In one embodiment of the present invention, the doping concentration of the P-type base region is less than the doping concentration of the first N+ region and the second N+ region.

[0087] In one embodiment of the present invention, the doping concentration of the P-type buried layer is greater than the doping concentration of the P-type base region.

[0088] This invention discloses a method for fabricating a power device, which may include a drift region, a carrier storage layer, a P-type buried layer, a P-type body region, an N+ region, at least one first trench and a second trench, a gate oxide layer, a P+ region, multiple P-type base regions, an interlayer dielectric, and an emitter metal; the first trench extends to the P-type buried layer, and the second trench passes through the N+ region and extends to the carrier storage layer, and is partially located within the P-type body region; a hole path can be formed in the P-type base region and the P-type buried layer, so that holes are preferentially extracted from this path, reducing the number of holes extracted from the hole path near the gate polysilicon, thereby limiting the rapid rise of the displacement current near the gate polysilicon and weakening the influence of electromagnetic interference; the P-type body region and the N+ region can form a hole barrier to suppress the extraction of holes stored in the P-type base region from this path, thereby weakening the influence of electromagnetic interference.

[0089] This invention also provides a chip, including the power device described above.

[0090] The terms "first" and "second" in the specification and claims of this invention may explicitly or implicitly include one or more of those features. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0091] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0092] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0093] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0094] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A power device, characterized in that, include: First section region; The first cross-sectional region includes: Drift zone; A carrier storage layer is located on the upper surface of the drift region; A P-type buried layer is located within the carrier storage layer; The P-type body region is located within the carrier storage layer and is not in contact with the P-type buried layer; The N+ region is located within the carrier storage layer, and a portion of the N+ region is in contact with a portion of the surface of the P-type body region; At least one first trench and a second trench, the first trench extending to the P-type buried layer, the second trench passing through the N+ region and extending to the carrier storage layer and partially located within the P-type body region; the second trench is filled with gate polysilicon, and the first trench is filled with emitter polysilicon. A gate oxide layer is located on the sidewalls and bottom of the first trench and the sidewalls and bottom of the second trench; The P+ region is located within the P-shaped body region, and the upper surface of the P+ region is flush with the upper surface of the P-shaped body region. Multiple P-type base regions are located above the carrier storage layer and distributed on both sides of the first trench and extend into the second trench; Interlayer medium, located on a portion of the surface of the P-type base region, the surface of the first trench, the surface of the second trench, and a portion of the surface of the N+ region; The emitter metal is located on the surface of the interlayer dielectric, a portion of the surface of the P-type base region between the first trench, a portion of the surface of the N+ region, and the surface of the P+ region.

2. The power device according to claim 1, characterized in that, The power device further includes: The cutoff layer is located below the drift region; The collector area is located below the cutoff layer; The collector metal is located below the P-type collector region.

3. The power device according to claim 1, characterized in that, The P-type buried layer also extends into the drift region.

4. The power device according to claim 1, characterized in that, The first trench includes a plurality of trenches, and the distance between the centers of a plurality of adjacent first trenches is less than or equal to 1.6 μm.

5. The power device according to claim 1, characterized in that, It also includes a second cross-sectional area that alternates with the first cross-sectional area along a first direction; The second cross-sectional region includes the drift region, the carrier storage reservoir, the P-type body region, the N+ region, the at least one first trench, the second trench, the gate oxide layer, the P+ region, the plurality of P-type base regions, the interlayer dielectric, and the emitter metal.

6. The power device according to claim 1, characterized in that, The N+ region is divided into a first N+ region and a second N+ region by the second trench.

7. The power device according to claim 6, characterized in that, The doping concentration of the P-type base region is less than that of the first N+ region and the second N+ region.

8. The power device according to claim 1, characterized in that, The doping concentration of the P-type buried layer is greater than the doping concentration of the P-type base region.

9. A method for manufacturing a power device, characterized in that, The method includes: Provide substrate for the drift region; A carrier storage layer is formed on the substrate in the drift region; A P-type buried layer is formed within the carrier storage layer; A P-type body region and an N+ region are formed within the carrier storage layer, wherein the P-type body region is not in contact with the P-type buried layer, and a portion of the N+ region is in contact with a portion of the surface of the P-type body region. Etching is performed on a portion of the P-type buried layer, a portion of the carrier storage layer, and a portion of the N+ region, and silicon is deposited in the etched areas. A first trench is formed in a portion of the deposited silicon region, and a second trench is formed in the portion of the deposited silicon region and a portion of the N+ region. The first trench extends to the P-type buried layer, and the second trench passes through the N+ region and extends to the carrier storage layer and is partially located within the P-type body region. Polycrystalline silicon is filled into the first trench and the second trench; A gate oxide layer is formed on the sidewalls and bottom of the first trench and the second trench; Multiple P-type base regions are formed on both sides of the first trench, and the P-type base regions are located above the carrier storage layer and extend into the second trench; A P+ region is formed within the P-type body region; and the upper surface of the P+ region is flush with the upper surface of the P-type body region. An interlayer medium is formed on a portion of the surface of the P-type base region, the surface of the first trench, the surface of the second trench, and a portion of the surface of the N+ region. An emitter metal is formed on the surface of the interlayer medium, a portion of the surface of the P-type base region between the first trenches, a portion of the surface of the N+ region, and the surface of the P+ region.

10. The method for manufacturing a power device according to claim 9, characterized in that, Also includes: A cutoff layer is formed beneath the substrate in the drift region; A current-collecting region is formed below the cutoff layer; A collector metal is formed below the collector region.

11. The method for manufacturing a power device according to claim 9, characterized in that, The doping concentration of the P-type buried layer is greater than the doping concentration of the P-type base region.

12. A chip, characterized in that, The chip includes the power device according to any one of claims 1-9.

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