An IGBT device and method of manufacture

Abstract

The application relates to the technical field of semiconductors, and discloses an IGBT device and a preparation method, the preparation method comprising the following steps: providing a substrate, the substrate comprising a first surface and a second surface arranged oppositely; etching a plurality of grooves on the first surface, the grooves comprising gate trenches and dummy trenches; sequentially forming a first oxide layer, an oxidation-resistant barrier layer and a second oxide layer on the inner walls of the grooves; coating photoresist on the first surface and performing photoetching and developing, forming photoresist masks covering the two side edges of the gate trenches and being open in the middle region, and completely removing the photoresist above the dummy trenches; removing the exposed second oxide layer; removing the residual photoresist; removing the exposed oxidation-resistant barrier layer; removing the exposed first oxide layer; performing first thermal oxidation treatment on the first surface to form a third oxide layer, the thickness of the third oxide layer being greater than that of the first oxide layer; removing the residual oxidation-resistant barrier layer; removing the residual first oxide layer; and performing second thermal oxidation treatment on the first surface to form a fourth oxide layer on the inner walls of the grooves. The technical scheme of the application aims to improve the static voltage resistance performance of the device while reducing the dynamic switching loss.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an IGBT device and its fabrication method. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) possess excellent characteristics such as high input impedance, high voltage and high current withstand capability, and fast switching speed, and have been widely used in power electronics conversion fields such as new energy vehicles, smart grid energy storage systems, and rail transportation. As application scenarios increasingly demand high power density and high reliability, the structure of IGBT devices continues to evolve.

[0003] In existing technologies, compared to traditional planar gate IGBTs, trench gate IGBTs eliminate the parasitic effects inherent in planar structures, such as those found in junction field-effect transistors (JFETs), by embedding the gate structure inside the substrate. This structural change significantly reduces the on-state voltage drop, thereby substantially reducing static conduction losses. Therefore, trench gate IGBTs have become the mainstream high-performance power device structure.

[0004] However, in the actual fabrication and application of trench gate IGBTs, due to the physical damage caused by the trench etching process and the poor step coverage of the gate oxide layer at the bottom and corners of the deep trench, the trench gate structure is more prone to electrical defects than the planar structure, which significantly increases the risk of gate oxide breakdown.

[0005] In actual R&D and production, a common practice to improve device reliability is to increase the overall thickness of the gate oxide layer. However, increasing the overall gate oxide thickness leads to a significant increase in the device's threshold voltage and also substantially increases the device's dynamic switching losses, making it impossible to achieve both high conduction and switching performance. Existing conventional mass production processes generally employ one-time gate oxide growth technology, resulting in a completely uniform gate oxide thickness across the trench surface, sidewalls, and trench bottom. This makes it impossible to individually control the oxide layer thickness in specific areas such as dummy trenches or the bottom of gate trenches where high-voltage electric fields are easily concentrated, thus limiting further optimization of the static withstand voltage and dynamic performance of trench gate IGBTs. Summary of the Invention

[0006] The main objective of this invention is to provide an IGBT device and its fabrication method, which aims to improve the static withstand voltage performance of the device while reducing dynamic switching losses.

[0007] To achieve the above objectives, the present invention proposes an IGBT device, the fabrication method of which includes:

[0008] A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other;

[0009] A plurality of grooves are etched on the first surface, the grooves including gate trenches and dummy trenches;

[0010] A first oxide layer, an antioxidant barrier layer covering the first oxide layer, and a second oxide layer covering the antioxidant barrier layer are sequentially formed on the inner wall of the groove.

[0011] Photoresist is coated on the first surface and photolithographic development is performed. A photoresist mask covering both sides of the gate trench and having an opening in the middle region is formed above the gate trench. The photoresist is completely removed above the dummy trench.

[0012] Using the remaining photoresist as a mask, a first etching process is used to remove the exposed second oxide layer to expose the underlying antioxidant barrier layer;

[0013] Remove any remaining photoresist;

[0014] The exposed antioxidant barrier layer is removed using a second etching process to expose the underlying first oxide layer;

[0015] The first oxide layer is removed using a first etching process to expose the silicon surface of the substrate;

[0016] A first thermal oxidation treatment is performed on the first surface to form a third oxide layer on the exposed silicon surface, the thickness of the third oxide layer being greater than the thickness of the first oxide layer;

[0017] The remaining antioxidant barrier layer is removed using a second etching process;

[0018] The remaining first oxide layer is removed using a first etching process;

[0019] A second thermal oxidation treatment is performed on the first surface to form a fourth oxide layer covering the inner wall of the groove.

[0020] In some embodiments of the present invention, the material of the antioxidant barrier layer is silicon nitride or silicon oxynitride.

[0021] In some embodiments of the present invention, the second etching process includes: etching the antioxidant barrier layer by immersion in hot phosphoric acid.

[0022] In some embodiments of the present invention, the first etching process includes: immersion etching using a diluted hydrofluoric acid solution.

[0023] In some embodiments of the present invention, the size of the photolithographic opening in the middle of the gate trench is ≥0.2μm;

[0024] The overlap dimension of the photoresist covering the two sides of the gate trench is ≥0.1μm.

[0025] In some embodiments of the present invention, the second oxide layer is formed using a low-pressure chemical vapor deposition process with tetraethyl orthosilicate as a precursor.

[0026] In some embodiments of the present invention, the first thermal oxidation treatment is a wet thermal oxidation process.

[0027] In some embodiments of the present invention, the second thermal oxidation treatment is a dry thermal oxidation process.

[0028] In some embodiments of the present invention, the gate trench and the dummy trench are alternately spaced.

[0029] In some embodiments of the present invention, the thickness of the fourth oxide layer is less than the thickness of the third oxide layer.

[0030] The present invention also discloses an IGBT device, including a substrate, wherein the substrate has a gate trench and a dummy trench;

[0031] The inner walls of both the gate trench and the dummy trench are covered with a gate oxide layer.

[0032] The thickness of the gate oxide layer at the bottom of the gate trench is greater than the thickness of the gate oxide layer in the channel region of the gate trench sidewall;

[0033] The thickness of the gate oxide layer within the dummy trench is greater than the thickness of the gate oxide layer within the channel region of the gate trench sidewall.

[0034] In some embodiments of the present invention, the gate trench and the dummy trench are alternately spaced.

[0035] The technical solution of this invention achieves localized differentiation in the thickness of the gate oxide layer by constructing a temporary mask stack of a first oxide layer / antioxidant barrier layer / second oxide layer, combined with photolithography. On one hand, at the bottom of the gate trench and in the dummy trench region, the oxide layer is composed of a third oxide layer and a fourth oxide layer, resulting in a larger thickness. This effectively enhances the vertical field plate effect, improves the static withstand voltage, and mitigates gate-emitter short-circuit defects caused by trench etching, thereby increasing the mass production yield of the device. On the other hand, because the channel region on the sidewall of the gate trench is protected from the growth of the third oxide layer and is only covered by the second-grown fourth oxide layer, the threshold voltage of the device is stabilized within a safe window, and dynamic switching losses are significantly reduced. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0037] Figure 1 This is a schematic cross-sectional view of an existing IGBT device.

[0038] Figure 2 This invention relates to a method for fabricating the IGBT device.

[0039] Figure 3-13 This is a cross-sectional structural schematic diagram of each step in the fabrication method of the IGBT device of the present invention;

[0040] Figure 14 This is a waveform diagram comparing the dynamic performance improvement of the embodiments of the present invention with that of the prior art;

[0041] Figure 15 The waveform diagrams show a comparison of the shutdown tail current (Ice) and voltage (Vce) of the embodiments of the present invention with those of the prior art.

[0042] Figure label:

[0043] 100, Substrate; 200, Trench; 210, Gate Trench; 220, Dummy Trench; 300, First Oxide Layer; 400, Antioxidant Barrier Layer; 500, Second Oxide Layer; 600, Photoresist; 700, Third Oxide Layer; 800, Fourth Oxide Layer; 900, Gate Oxide Layer;

[0044] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0046] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0047] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, the user should consider such a combination of technical solutions to be non-existent and not within the scope of protection claimed by this invention.

[0048] Please see the appendix Figure 1 Currently, existing trench gate IGBTs typically employ a "one-time gate oxide growth" process, resulting in a uniform gate oxide thickness across the trench surface, sidewalls, and bottom. While this uniform oxide thickness simplifies the fabrication process, high-voltage electric field concentration is highly likely to occur at the bottom of the trench and in the dummy trench 220 when the device is off, significantly increasing the risk of gate oxide breakdown. Since existing oxide growth processes cannot individually control the oxide thickness in specific areas such as the bottom of the dummy trench 220 or the gate trench 210, the industry often adopts a solution of overall gate oxide thickening to improve reliability.

[0049] However, due to the overall thickening of the gate oxide layer 900 on the trench surface, the threshold voltage of the device increases significantly, and the dynamic switching loss increases substantially, making the static withstand voltage characteristics and dynamic switching speed of the device a prominent contradiction that is difficult to balance.

[0050] Based on this, this application aims to provide a solution that can solve the above-mentioned technical problems, so as to achieve a balance between optimizing the static withstand voltage electric field distribution and dynamic energy loss without affecting the electrical characteristics.

[0051] See appendix Figure 2 This invention proposes an IGBT device and its fabrication method, the fabrication method comprising:

[0052] S101, a substrate 100 is provided, the substrate 100 including a first surface and a second surface disposed opposite to each other;

[0053] S102, a plurality of grooves 200 are etched on the first surface, the grooves 200 including gate trenches 210 and dummy trenches 220;

[0054] S103, a first oxide layer 300, an antioxidant barrier layer 400 covering the first oxide layer 300, and a second oxide layer 500 covering the antioxidant barrier layer 400 are sequentially formed on the inner wall of the groove 200.

[0055] S104, photoresist 600 is coated on the first surface and photolithography is performed to form a photoresist 600 mask covering both sides of the gate trench 210 and having an opening in the middle region, and the photoresist 600 is completely removed above the dummy trench 220.

[0056] S105, using the remaining photoresist 600 as a mask, the first etching process is used to remove the exposed second oxide layer 500 to expose the underlying antioxidant barrier layer 400;

[0057] S106, remove residual photoresist 600;

[0058] S107, the exposed antioxidant barrier layer 400 is removed using a second etching process to expose the underlying first oxide layer 300;

[0059] S108, the first etching process is used to remove the exposed first oxide layer 300 to expose the silicon surface of the substrate 100;

[0060] S109, a first thermal oxidation treatment is performed on the first surface to form a third oxide layer 700 on the exposed silicon surface. The thickness of the third oxide layer 700 is greater than the thickness of the first oxide layer 300.

[0061] S110, the second etching process is used to remove all remaining antioxidant barrier layers 400;

[0062] S111, the first etching process is used to remove all remaining first oxide layers 300;

[0063] S112, a second thermal oxidation treatment is performed on the first surface to form a fourth oxide layer 800 covering the inner wall of the groove 200.

[0064] Understandably, this invention achieves localized differentiation in the thickness of the gate oxide layer 900 by constructing a temporary mask stack of a first oxide layer 300, an antioxidant barrier layer 400, and a second oxide layer 500, in conjunction with photolithography. On one hand, at the bottom of the gate trench 210 and in the dummy trench 220 region, the oxide layer is formed by the superposition of a third oxide layer 700 and a fourth oxide layer 800, resulting in a larger thickness. This effectively enhances the vertical field plate effect, improves the static withstand voltage, and simultaneously mitigates gate-emitter short-circuit defects caused by trench etching, thereby increasing the mass production yield of the device. On the other hand, since the channel region on the sidewall of the gate trench 210 is protected from the growth of the third oxide layer 700 and is only covered by the second-grown fourth oxide layer 800, the device threshold voltage is stabilized within a safe window, and dynamic switching losses are significantly reduced.

[0065] Below, in conjunction with Figures 3 to 13The cross-sectional structural diagram shown provides a further detailed description of the IGBT device and its fabrication method provided in this application. Those skilled in the art should understand that the specific values ​​and process conditions described below are merely preferred embodiments of the present invention and do not constitute a limitation thereof.

[0066] In step S101, a substrate 100 is provided, the substrate 100 including a first surface and a second surface disposed opposite to each other;

[0067] Optionally, the semiconductor substrate 100 can be a single-crystal silicon substrate 100, a silicon carbide substrate 100, or a gallium nitride substrate 100; this application preferably uses a single-crystal silicon substrate 100. The first surface serves as the front side for subsequent fabrication of the IGBT front-end core device structure, while the second surface is used for subsequent formation of the back-side collector structure. By providing an initial substrate 100 with high flatness, a good physical basis can be provided for subsequent deep trench etching and high-precision photolithography processes, thereby effectively ensuring the device's process yield.

[0068] See appendix Figure 3 In step S102, a plurality of grooves 200 are etched on the first surface, the grooves 200 including gate trenches 210 and dummy trenches 220.

[0069] First, a hard mask layer (e.g., silicon oxide or silicon nitride hard mask) is coated and patterned on the first surface, and etching windows are opened on the hard mask using photolithography. Subsequently, the semiconductor substrate 100 is etched downwards using an anisotropic dry etching process (e.g., inductively coupled plasma (ICP) etching or reactive ion etching (RIE)) to form several deep grooves 200.

[0070] Through this step, a deep trench structure including a gate trench 210 and a dummy trench 220 can be formed on the first surface side of the substrate 100. Optionally, the trench structure of the present invention is suitable for designs with a trench width of 0.4 μm or more, and the trench depth is preferably between 3 μm and 8 μm.

[0071] Preferably, the gate trench 210 and the dummy trench 220 are arranged alternately in space. Utilizing the characteristic that the dummy trench 220 is always at the emitter potential, the alternating arrangement of the dummy trenches 220 between the gate trench 210 forms a stable longitudinal electric field buffer band. When the device is turned off, this effectively isolates and weakens the high-voltage electric field, preventing excessive impact of localized strong electric fields on the gate oxide at the bottom of the gate trench 210, thus improving the device's surge resistance and withstand voltage reliability.

[0072] For further details, please refer to the appendix. Figure 4In step S103, a first oxide layer 300, an antioxidant barrier layer 400 covering the first oxide layer 300, and a second oxide layer 500 covering the antioxidant barrier layer 400 are sequentially formed on the inner wall of the groove 200.

[0073] Specifically, see the appendix. Figure 5 This step first involves using a thermal oxidation process to grow a first oxide layer 300 in situ on the inner wall of the groove 200 and the first surface of the substrate 100. This first oxide layer 300 primarily serves as a padding layer, and its thickness is preferably 200 Å to 1000 Å. Next, a low-pressure chemical vapor deposition (LPCVD) process is used to deposit an antioxidant barrier layer 400 on the first oxide layer 300. This antioxidant barrier layer 400 is preferably made of silicon nitride or silicon oxynitride, and its thickness is preferably 500 Å to 2000 Å. Finally, using LPCVD and tetraethyl orthosilicate (TEOS) as a precursor, a second oxide layer 500 is deposited on the surface of the antioxidant barrier layer 400. The thickness of this second oxide layer 500 is preferably 1000 Å to 15000 Å. Understandably, the TEOS oxide layer, due to its step coverage capability, can cover the sidewalls and bottom of the groove 200, while also facilitating the adhesion of the subsequent photoresist 600 and improving photolithography accuracy.

[0074] In this design, the first oxide layer 300 buffers the thermal mismatch stress between the antioxidant barrier layer 400 and the silicon substrate 100; while the second oxide layer 500 serves as a sacrificial layer and photolithography aid layer for subsequent wet etching. By incorporating the antioxidant barrier layer 400, it exhibits distinctly different chemical etching selectivity compared to the first oxide layer 300 and the second oxide layer 500. This etching selectivity, based on material differences, enables precise windowing and removal of each film structure. Simultaneously, the antioxidant barrier layer 400 also possesses resistance to high-temperature oxygen diffusion, preventing unintended oxidation of the underlying silicon surface. The synergistic effect of the etching selectivity and antioxidant isolation of the antioxidant barrier layer 400 allows for differentiated local control of the gate oxide layer 900 thickness in different regions of the same device.

[0075] In step S104, photoresist 600 is coated on the first surface and photolithography is performed to form a photoresist 600 mask covering both sides of the gate trench 210 and having an opening in the middle region. The photoresist 600 is then completely removed over the dummy trench 220.

[0076] See appendix Figure 6In this step, a photoresist layer 600 is coated on the first surface and the second oxide layer 500, and alignment, exposure, and development are performed using a photomask. During this process, differentiated pattern definitions are used: for the gate trench 210, a window is opened at its center, and the photoresist 600 on both sides of the window overlaps and covers the edges of the trench; for the dummy trench 220, the photoresist 600 above it is completely removed, leaving it in a fully open state.

[0077] Preferably, to ensure the reliability of the mask state during mass production, this step preferably sets a certain engineering margin, namely, the photolithographic aperture size of the gate trench 210 is ≥0.2μm, and the overlap size of the photoresist 600 covering the edge of the gate trench 210 is ≥0.1μm. This overlap size can ensure the stability of the photoresist 600 covering the sidewall of the gate trench 210 and prevent the photoresist 600 from falling off.

[0078] In step S105, using the remaining photoresist 600 as a mask, the exposed second oxide layer 500 is removed by the first etching process to expose the underlying antioxidant barrier layer 400.

[0079] See appendix Figure 7 Using the retained photoresist 600 as a protective mask, the exposed second oxide layer 500 is wet-etched using a first etching process. Specifically, this first etching process can involve immersion etching with a diluted hydrofluoric acid solution, for example, rinsing with a 10:1 hydrofluoric acid solution. During the actual etching process, due to over-etching and capillary action, not only is the second oxide layer 500 in the opening area vertically removed, but a certain height of TEOS is also removed along the sidewall gaps. Because the diluted hydrofluoric acid has etching selectivity for the underlying silicon nitride layer (i.e., it only etches silicon oxide and not silicon nitride), this step can accurately expose the underlying antioxidant barrier layer 400 without etching it.

[0080] See appendix Figure 8 Perform step S106 to remove residual photoresist 600;

[0081] After the partial removal of the second oxide layer 500 is completed, all remaining photoresist 600 from steps S104 and S105 is completely stripped using conventional dry stripping methods (such as oxygen plasma ashing process) or wet stripping solutions.

[0082] In step S107, the exposed antioxidant barrier layer 400 is removed using a second etching process to expose the underlying first oxide layer 300.

[0083] After the photoresist 600 is completely removed, this step employs a second etching process to etch the exposed antioxidant barrier layer 400. This second etching process preferably uses hot phosphoric acid immersion etching; in practice, the temperature can be set between 150°C and 180°C. Utilizing the strong corrosiveness of hot phosphoric acid to silicon nitride and its almost non-corrosive selectivity to silicon oxide, the antioxidant barrier layer 400 in the middle of the gate and at the dummy trench 220 can be precisely hollowed out, thereby exposing the underlying first oxide layer 300. This highly selective etching ensures the integrity of the bottom first oxide layer 300, allowing it to continue serving as a protective layer for the underlying silicon.

[0084] See appendix Figure 9 Step S108 is executed, in which the exposed first oxide layer 300 is removed by a first etching process to expose the silicon surface of the substrate 100.

[0085] Next, the first etching process (i.e., immersion etching with diluted hydrofluoric acid solution) is used again to remove the exposed first oxide layer 300. Since the first oxide layer 300 is relatively thin, ranging from 200 Å to 1000 Å, over-etching damage to the underlying silicon surface can be prevented by controlling the etching time or using a lower concentration of hydrofluoric acid. This step exposes a clean silicon surface of the substrate 100 without any thick gate oxide growth in the central opening region of the gate trench 210 and the dummy trench 220 region.

[0086] See appendix Figure 10 Step S109 is executed to perform a first thermal oxidation treatment on the first surface to form a third oxide layer 700 on the exposed silicon surface. The thickness of the third oxide layer 700 is greater than the thickness of the first oxide layer 300.

[0087] In this step, the substrate 100 undergoes a first thermal oxidation treatment. Specifically, this thermal oxidation treatment preferably employs a wet thermal oxidation process, in which hydrogen gas is introduced into the furnace tube during the heating process. ) and oxygen ( A mixed gas is used, and the reaction temperature is preferably between 950°C and 1250°C. A third oxide layer 700 is formed by growing an oxide layer on the exposed silicon surface. The thickness of this third oxide layer 700 is preferably set to 500 Å to 10000 Å, which is much greater than that of the first oxide layer 300. Due to the faster growth rate and better step coverage of wet thermal oxidation, thick films can be grown more effectively at the bottom of the deep trench and within the dummy trench 220. Simultaneously, due to the presence of the anti-oxidation barrier layer 400 above the sidewall of the gate trench 210, this thick oxide layer is selectively grown only at the bottom of the gate trench 210 and in the dummy trench 220 region. This thick oxide layer, acting as an insulating layer for the longitudinal field plate, can significantly alleviate electric field concentration under high voltage and prevent gate oxide breakdown.

[0088] Perform step S110, using the second etching process to remove all remaining antioxidant barrier layers 400;

[0089] This step employs a second etching process to completely remove all remaining antioxidant barrier layer 400 above the sidewalls of the gate trench 210, thus exposing the underlying first oxide layer 300 again.

[0090] Perform step S111, using the first etching process to remove all remaining first oxide layers 300;

[0091] Next, see the appendix. Figure 11 The first etching process (i.e., diluted hydrofluoric acid solution) is then used again for global immersion etching to remove the first oxide layer 300 exposed on the top of the sidewall of the gate trench 210 in step S110, as well as the first oxide layer 300 remaining on the inner wall of the previously dummy trench 220. Since the thickness of the first oxide layer 300 is less than that of the third oxide layer 700, although the thickness of the bottom third oxide layer 700 will also be consumed simultaneously during this etching process, its initial thickness is large enough that sufficient insulating thickness remains after etching to ensure the field board effect.

[0092] At this point, the entire inner walls of the gate trench 210 and the dummy trench 220, including the sidewalls, bottom, and corners, are fully exposed to the unprotected semiconductor silicon surface.

[0093] See appendix Figure 12 Step S112 is executed to perform a second thermal oxidation treatment on the first surface, forming a fourth oxide layer 800 covering the inner wall of the groove 200.

[0094] In this step, the cleaned substrate 100 undergoes a second thermal oxidation treatment. This thermal oxidation treatment preferably employs a dry thermal oxidation process, in which high-purity oxygen (…) is introduced into the furnace tube. The oxidation temperature is also preferably between 950°C and 1250°C. This thermal oxidation will cover the entire inner wall of the trench 200 with a fourth oxide layer 800. The thickness of the fourth oxide layer 800 is 500 Å to 2000 Å, which is less than that of the third oxide layer 700. By covering the fourth oxide layer 800, the entire device exhibits an ideal oxide layer distribution: the bottom of the dummy trench 220 and the gate trench 210 is formed by a thicker insulating layer consisting of the third oxide layer 700 and the fourth oxide layer 800; while the channel region on the sidewall of the gate trench 210 is covered by a single layer, dense, and relatively thin fourth oxide layer 800.

[0095] Preferably, the fourth oxide layer 800 on the sidewall of the gate trench 210 is thinner than the third oxide layer 700. Under the same driving voltage, using a thinner gate oxide can generate a stronger vertical electric field, ensuring that the channel region can be quickly and fully inverted and turned on, thereby reducing the channel resistance and improving the dynamic response speed of the device.

[0096] The oxide layer generated by dry oxidation has extremely high density and extremely low interface state density, making it a better gate dielectric for controlling channel turn-on. By generating a thinner fourth oxide layer 800, the vertical electric field in the channel region is effectively improved, accelerating the channel turn-on and turn-off response speed, ensuring that the IGBT can be turned on and off extremely quickly under the gate drive voltage, thereby significantly reducing dynamic switching losses.

[0097] It should be noted that after this step, refer to Figure 13 Those skilled in the art can obtain a complete IGBT device structure by continuing to fill polysilicon, implanting to form PBODY and N+ source regions, and fabricating top metal and back collector through conventional processes.

[0098] To further verify the superior performance brought about by the preparation method and device structure of this invention, please refer to... Figure 14 and Figure 15 The performance comparison waveforms shown are used for illustration.

[0099] like Figure 14 The waveform comparison diagrams show that curve A1 represents the prior art, while curve B1 represents the embodiment of the present invention. After adopting the structure of the present invention, both the falling edge of the bus voltage and the rising edge of the turn-on current are steeper than before optimization, and the waveform reaches the turn-on steady state earlier. This indicates that the turn-on response time of the device of the present invention is shortened compared to before optimization, effectively reducing turn-on losses.

[0100] Figure 15 The waveforms of collector current (Ice) and collector-emitter voltage (Vce) during device turn-off were further compared over time. It can be clearly seen that during the turn-off phase, the existing conventional structure (Original) exhibits a gradual decrease in Ice with a long tail current, which leads to higher turn-off losses and limits the operating frequency. In contrast, the device using the structure of this invention (Improved) shows an extremely steep decrease in Ice, significantly suppressing the tail current, and a much faster rise in Vce.

[0101] Because this invention retains a thinner and denser fourth oxide layer 800 in the sidewall channel region of the gate trench 210, the gate capacitance in this region is significantly reduced. Under the same driving voltage, the channel can turn on and off more quickly, greatly improving the dynamic switching speed of the device and effectively suppressing [further issues]. Figure 15The long tail current phenomenon in the middle.

[0102] By forming a thick composite gate oxide layer consisting of a third oxide layer 700 and a fourth oxide layer 800 at the bottom of the dummy trench 220 and the gate trench 210, this extra-thick insulating layer acts as an excellent "longitudinal field plate" when the device is turned off and subjected to high voltage, greatly reducing the peak electric field at the bottom of the gate trench 210 and in the dummy trench 220.

[0103] The thick oxide layer filling the bottom of the gate trench 210 and the dummy trench 220 effectively compensates for the bottom tip defects caused by the dry etching of deep trenches, and significantly improves the gate-emitter short circuit problem caused by defects.

[0104] In summary, Figure 14 and Figure 15 The waveform verification results fully demonstrate that this invention successfully overcomes the technical contradiction between the "static withstand voltage" and "dynamic loss" of traditional trench gate IGBTs by constructing gate oxide layers 900 with differentiated thicknesses in different regions of the trench. While effectively improving the device's withstand voltage and gate oxide reliability, it significantly reduces dynamic switching losses, achieving comprehensive optimization of the overall performance of the power device.

[0105] See appendix Figure 12 This application also provides an IGBT device, specifically, the semiconductor device includes a substrate 100, on which a gate trench 210 and a dummy trench 220 are formed. The inner walls of both the gate trench 210 and the dummy trench 220 are covered with a gate oxide layer 900;

[0106] The thickness of the gate oxide layer 900 at the bottom of the gate trench 210 is greater than the thickness of the gate oxide layer 900 in the channel region of the sidewall of the gate trench 210.

[0107] The thickness of the gate oxide layer 900 in the dummy trench 220 is greater than the thickness of the gate oxide layer 900 in the channel region of the sidewall of the gate trench 210.

[0108] Understandably, both the dummy trench 220 and the gate trench 210 in this application have a larger gate oxide thickness at their bottoms. When the IGBT is in the off state and subjected to reverse high voltage, the depletion layer extends downwards into the drift region, and the strong electric field concentrates at the bottom sharp corners and bends of the trench. Since the thicker insulating layer inside the dummy trench 220 acts as a "vertical field plate," it can effectively absorb and disperse the concentrated electric field lines, thus better weakening the peak electric field at the bottom of the trench and the bottom of the sidewalls. This significantly reduces the risk of gate oxide breakdown caused by high-voltage tip discharge and effectively improves the gate-emitter short-circuit problem caused by etching process defects, thereby greatly improving the device's static withstand voltage and wafer manufacturing yield.

[0109] In this application, the gate oxide layer 900 located in the channel region on the sidewall of the gate trench 210 has a relatively thin thickness. Due to the thinner core insulating layer controlling channel opening, a stronger vertical electric field can be induced in the channel region when the same driving voltage is applied to the gate, thereby rapidly forming a conductive channel. Simultaneously, the thin gate oxide structure effectively reduces the gate input capacitance. In practical high-frequency switching applications, the smaller gate capacitance shortens the time required for gate charging and discharging, improving the device's turn-on and turn-off speeds, thus effectively reducing the dynamic switching losses of the IGBT.

[0110] Preferably, the gate trench 210 and the dummy trench 220 are arranged alternately. Through this alternating arrangement, adjacent dummy trenches 220 can form a uniform longitudinal field plate array inside the device. When the IGBT is turned off and subjected to high voltage, the dummy trenches 220 at the emitter potential can effectively shield and absorb the high electric field, reduce the peak electric field intensity at the bottom of the adjacent gate trench 210, thereby better suppressing the breakdown risk of the gate oxide layer 900 and synergistically improving the high voltage reliability and overall manufacturing yield of the device.

[0111] In summary, by using the specific differential distribution of the gate oxide layer 900 thickness, this invention provides robust thick oxide layer insulation protection for IGBT devices in locations subjected to high voltage, while retaining a thinner gate dielectric layer in locations requiring fast-response switching. Ultimately, this achieves an excellent synergy and balance between the device's static withstand voltage performance and dynamic energy loss.

[0112] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

Claims

1. A method of manufacturing an IGBT device, characterized by, The preparation method includes: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other; A plurality of grooves are etched on the first surface, the grooves including gate trenches and dummy trenches; A first oxide layer, an antioxidant barrier layer covering the first oxide layer, and a second oxide layer covering the antioxidant barrier layer are sequentially formed on the inner wall of the groove. Photoresist is coated on the first surface and photolithographic development is performed. A photoresist mask covering both sides of the gate trench and having an opening in the middle region is formed above the gate trench. The photoresist is completely removed above the dummy trench. Using the remaining photoresist as a mask, a first etching process is used to remove the exposed second oxide layer to expose the underlying antioxidant barrier layer; Remove any remaining photoresist; The exposed antioxidant barrier layer is removed using a second etching process to expose the underlying first oxide layer; The first oxide layer is removed using a first etching process to expose the silicon surface of the substrate; A first thermal oxidation treatment is performed on the first surface to form a third oxide layer on the exposed silicon surface, the thickness of the third oxide layer being greater than the thickness of the first oxide layer; The remaining antioxidant barrier layer is removed using a second etching process; The remaining first oxide layer is removed using a first etching process; A second thermal oxidation treatment is performed on the first surface to form a fourth oxide layer covering the inner wall of the groove.

2. The method for fabricating an IGBT device as described in claim 1, characterized in that, The antioxidant barrier layer is made of silicon nitride or silicon oxynitride.

3. The method for fabricating an IGBT device as described in claim 2, characterized in that, The second etching process includes: etching the antioxidant barrier layer by immersion in hot phosphoric acid.

4. The method for fabricating an IGBT device as described in claim 1, characterized in that, The first etching process includes: immersion etching using a diluted hydrofluoric acid solution.

5. The method for fabricating an IGBT device as described in claim 1, characterized in that, The photolithographic aperture size in the middle of the gate trench is ≥0.2μm, and the overlap size of the photoresist covering the two sides of the gate trench is ≥0.1μm; And / or the gate trench and the dummy trench are alternately spaced.

6. The method for fabricating an IGBT device as described in claim 1, characterized in that, The second oxide layer is formed using a low-pressure chemical vapor deposition process with tetraethyl orthosilicate as a precursor.

7. The method for fabricating an IGBT device as described in claim 1, characterized in that, The first thermal oxidation treatment is a wet thermal oxidation process; The second thermal oxidation treatment is a dry thermal oxidation process.

8. The method for fabricating an IGBT device as described in claim 1, characterized in that, The thickness of the fourth oxide layer is less than the thickness of the third oxide layer.

9. An IGBT device, characterized in that, Includes a substrate, wherein the substrate has gate trenches and dummy trenches; The inner walls of both the gate trench and the dummy trench are covered with a gate oxide layer. The thickness of the gate oxide layer at the bottom of the gate trench is greater than the thickness of the gate oxide layer in the channel region of the gate trench sidewall; The thickness of the gate oxide layer within the dummy trench is greater than the thickness of the gate oxide layer within the channel region of the gate trench sidewall.

10. The IGBT device as described in claim 9, characterized in that, The gate trench and the dummy trench are arranged alternately.

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