A method of fabricating a gallium nitride HEMT device

Abstract

The application provides a manufacturing method of a gallium nitride HEMT device, comprising the following steps: forming a first channel layer on a provided substrate layer; forming a first barrier layer on the first channel layer; etching the first barrier layer and part of the first channel layer to form a groove, the sidewall of the groove being inclined at a certain angle; forming a second channel layer on the first barrier layer, the second channel layer covering the inner surface of the groove; forming a second barrier layer on the second channel layer; forming a gate structure on the second barrier layer above the groove; defining and etching the contact areas of a source and a drain at both ends of the gate structure through a photoetching process; and forming the source and the drain in the corresponding areas respectively.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for manufacturing a gallium nitride (HEMT) device. Background Technology

[0002] Gallium nitride (GaN) HEMTs (High Electron Mobility Transistors) are semiconductor devices that utilize two-dimensional electron gases (2DEGs) to achieve high current density and high frequency operation. Conventional GaN HEMTs are single-channel devices, and due to limitations in 2DEG density and mobility, their on-resistance is relatively high. To reduce the on-resistance of GaN HEMTs, multi-channel GaN HEMTs have been reported, but these all lead to a decrease in the device's threshold voltage or even a negative value (i.e., depletion-mode devices). Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a gallium nitride HEMT device to solve the problem of reduced threshold voltage in multi-channel gallium nitride HEMT devices.

[0004] This invention provides a method for manufacturing a gallium nitride HEMT device, comprising:

[0005] S10: Form a first channel layer on the provided substrate layer;

[0006] S20: Form a first barrier layer on the first channel layer;

[0007] S30: Etch the first barrier layer and part of the first channel layer to form a groove, wherein the sidewall of the groove is inclined at a certain angle;

[0008] S40: A second channel layer is formed on the first barrier layer, the second channel layer covering the inner surface of the groove;

[0009] S50: A second barrier layer is formed on the second channel layer;

[0010] S60: A gate structure is formed on the second barrier layer above the groove;

[0011] S70: The contact areas of the source and drain are defined and etched at both ends of the gate structure by photolithography, and the source and drain are formed in the corresponding areas respectively.

[0012] Furthermore, after step S60, step S61 is also included: forming a cap layer on the second barrier layer and on both sides of the gate structure.

[0013] Furthermore, both the first channel layer and the second channel layer are made of GaN.

[0014] Furthermore, after step S40, step S41 is also included: performing n-type ion implantation to form an n-type doped region in the first channel layer and the second channel layer, wherein the n-type doped region is located in the region between the bottom surface of the first barrier layer and the bottom surface of the second barrier layer at the bottom of the groove.

[0015] Furthermore, the doping material of the n-type doped region is silicon.

[0016] Furthermore, both the first barrier layer and the second barrier layer are made of AlGaN or InAlN.

[0017] Furthermore, the inclination angle of the sidewall of the groove is 10 degrees to 80 degrees.

[0018] Furthermore, step S60 includes:

[0019] A P-GaN layer is formed on the second barrier layer, and the P-GaN layer fills the groove;

[0020] A gate metal is formed on the P-GaN layer;

[0021] The P-GaN layer and the gate metal are etched to form a gate structure.

[0022] Furthermore, step S60 includes:

[0023] A first insulating layer is formed on the second barrier layer;

[0024] A gate metal is formed on the first insulating layer;

[0025] The first insulating layer and the gate metal are etched to form the gate structure.

[0026] Furthermore, step S60 includes:

[0027] Fluorine ion implantation is performed on the second barrier layer located at the bottom of the groove;

[0028] A gate metal is formed on the second barrier layer, and the gate metal fills the groove;

[0029] The gate metal is etched to form the gate structure.

[0030] The gallium nitride HEMT device prepared by the method of the present invention has a single channel (2DEG at the interface between the second channel layer and the second barrier layer) below the gate structure, thereby exhibiting the high threshold voltage characteristics of a single-channel gallium nitride HEMT device; and has dual channels (a first 2DEG at the interface between the first channel layer and the first barrier layer, and a second 2DEG at the interface between the second channel layer and the second barrier layer) on both sides of the gate structure, which can reduce the on-resistance of the drift region of the gallium nitride HEMT device. Attached Figure Description

[0031] Figures 1-10 This is a cross-sectional structural diagram of the main process nodes of an embodiment of the gallium nitride HEMT device manufacturing method provided by the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0033] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "connected" or "linked" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0034] Figures 1-10 This is a cross-sectional structural diagram of the main process nodes of an embodiment of the gallium nitride device manufacturing method of the present invention. Figures 1 to 10 As shown, the method for manufacturing the gallium nitride device of the present invention includes:

[0035] First, such as Figure 1As shown, a first channel layer 102 is formed on the provided substrate layer 101. The substrate layer 101 typically includes a substrate made of materials such as silicon (Si), aluminum oxide (Al2O3), silicon carbide (SiC), gallium nitride (GaN), or sapphire, and a nitride epitaxial layer formed on the substrate. The nitride epitaxial layer typically includes an aluminum nitride (AlN) nucleation layer and an aluminum gallium nitride (AlGaN) buffer layer. The material of the first channel layer 102 is GaN. A first barrier layer 103 is formed on the first channel layer 102. The material of the first barrier layer 103 is AlGaN or InAlN.

[0036] Next, as Figure 2 As shown, the first barrier layer 103 and part of the first channel layer 102 are etched to form a groove 104. The bottom of the groove 104 extends into the first channel layer 102. The sidewall of the groove 104 is inclined at a certain angle. The angle of inclination can be any angle between 10 degrees and 80 degrees. That is, the angle α between the sidewall of the groove 104 and the horizontal surface of the first channel layer 102 is any angle between 10 degrees and 80 degrees.

[0037] Next, as Figure 3 As shown, a second channel layer 105 is formed on the first barrier layer 103. The second channel layer 105 covers the first barrier layer 103 and the inner surface of the groove 104. The material of the second channel layer 105 is typically GaN. In this embodiment, the thickness of the second channel layer 105 is equal to the thickness of the first channel layer 102 that has been etched away, so that the second channel layer 105 located at the bottom of the groove 104 "fills" the portion of the first channel layer 102 that has been etched away. The thickness of the second channel layer 105 can be selected to be greater than or less than the thickness of the first channel layer 102 that has been etched away, depending on actual needs.

[0038] Next, n-type ion implantation is performed to form an n-type doped region 111 within the first channel layer 102 and the second channel layer 105. The n-type doped region 111 is located in the region between the bottom surface of the first barrier layer 103 and the bottom surface of the second barrier layer 106 (which will be formed in a subsequent step) located at the bottom of the groove 104. The doping material of the n-type doped region 111 is typically silicon (Si). It should be noted that the formation step of the second barrier layer 106 is performed after the fabrication process of the n-type ion doped region 111. The n-type doped region 11 is located in the area between the bottom surface of the first barrier layer 103 and the bottom surface of the second barrier layer 106 located at the bottom of the groove 104. It can be understood that the n-type doped region 11 is located in the area between the bottom surface of the first barrier layer 103 and the bottom surface of the second barrier layer 106 that will be grown later and eventually located at the bottom of the groove 104. In other words, from the perspective of the final product structure, the n-type doped region 11 is located in the area between the bottom surface of the first barrier layer 103 and the bottom surface of the second barrier layer 106 located at the bottom of the groove 104.

[0039] Next, as Figure 4 As shown, a second barrier layer 106 is formed on the second channel layer 105, and the material of the second barrier layer 106 is AlGaN or InAlN.

[0040] Since the 2DEGs are generated only at the interface between the first channel layer 102 and the first barrier layer 103 and at the interface between the second channel layer 105 and the second barrier layer 106, there are no 2DEGs between the first 2DEG and the second 2DEG located at the bottom of the groove 104. Therefore, when the gallium nitride HEMT device is turned on, a large on-resistance is generated between the first 2DEG and the second 2DEG located at the bottom of the groove 104 due to the absence of 2DEGs. By performing n-type doping on the first channel layer 102 and the second channel layer 105 in the region between the first 2DEG and the second 2DEG located at the bottom of the groove 104 to form an n-type doped region 111, an n-type current channel can be formed, which can reduce the on-resistance of the gallium nitride HEMT device.

[0041] Next, as Figures 5-6 As shown, a P-GaN layer 107 is formed on the second barrier layer 106, the P-GaN layer 107 fills the trench 104, and a gate metal 110 is formed on the P-GaN layer 107. Excess P-GaN layer 107 and gate metal 110 are etched away to form a gate structure. Thus, this embodiment is a gallium nitride HEMT device employing a P-GaN gate structure.

[0042] In other embodiments, the gate structure may also be formed by the following steps, such as Figure 7 As shown, a first insulating layer 207 is formed on the second barrier layer 106; a gate metal 210 is formed on the first insulating layer 207; excess first insulating layer 207 and gate metal 210 are etched away to form a gate structure. Therefore, this embodiment is a gallium nitride HEMT device employing an insulated gate structure. In another embodiment, the gate structure can also be formed by the following steps, such as... Figure 8 As shown, fluorine ions are implanted into the bottom of the groove 104 to form a fluorine ion implantation region 311, and a gate metal 310 is formed on the second barrier layer 106, and the gate metal 310 fills the groove 104; the excess gate metal 310 is etched away to form a gate structure. Thus, this example is a gallium nitride HEMT device with an implanted gate structure.

[0043] Next, as Figure 9 As shown, a cap layer 112 is formed on the second barrier layer 106; the material of the cap layer 112 is preferably GaN, but it can also be a passivation layer material such as silicon nitride; using GaN as the cap layer can reduce the surface state density introduced by the direct contact between the dangling bonds of Al elements in the second barrier layer 106 and the air compared with the traditional passivation layer, thereby improving the stability of the device.

[0044] Finally, as Figure 10 As shown, contact regions for the source and drain are defined and etched on both sides of the gate structure using photolithography, and source 108 and drain 109 are formed in the corresponding regions. The materials of source 108 and drain 109 can be composed of materials such as titanium (Ti), titanium nitride (TiN), aluminum (Al), or tantalum (Ta). In this embodiment, source 108 and drain 109 are simultaneously in contact with the first channel layer 102, the first barrier layer 103, the second channel layer 105, and the second barrier layer 106 through contact holes. Optionally, the contact holes may not penetrate the first barrier layer 103, so that source 108 and drain 109 are only in contact with the first barrier layer 103, the second channel layer 105, and the second barrier layer 106. This embodiment of the application does not limit this.

[0045] The gallium nitride HEMT device of the present invention has a single channel (2DEG at the interface between the second channel layer and the second barrier layer) below the gate structure, thereby having the high threshold voltage characteristics of a gallium nitride HEMT device; and has dual channels on both sides of the gate structure (a first 2DEG at the interface between the first channel layer 102 and the first barrier layer 103, and a second 2DEG at the interface between the second channel layer 105 and the second barrier layer 106), which can reduce the drift region on-resistance of the gallium nitride HEMT device.

[0046] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A method for manufacturing a gallium nitride HEMT device, characterized in that, include: S10: Form a first channel layer on the provided substrate layer; S20: Form a first barrier layer on the first channel layer; S30: Etch the first barrier layer and part of the first channel layer to form a groove, wherein the sidewall of the groove is inclined at a certain angle; S40: A second channel layer is formed on the first barrier layer, the second channel layer covering the inner surface of the groove; S50: A second barrier layer is formed on the second channel layer; S60: A gate structure is formed on the second barrier layer above the groove; S70: The contact areas of the source and drain are defined and etched at both ends of the gate structure by photolithography, and the source and drain are formed in the corresponding areas respectively.

2. The method for manufacturing a gallium nitride HEMT device as described in claim 1, characterized in that, After step S60, step S61 is also included: forming a cap layer on the second barrier layer and on both sides of the gate structure.

3. The method for manufacturing a gallium nitride HEMT device as described in claim 1, characterized in that, Both the first and second trench layers are made of GaN.

4. The method for manufacturing a gallium nitride HEMT device as described in claim 1, characterized in that, After step S40, step S41 is also included: performing n-type ion implantation to form an n-type doped region in the first channel layer and the second channel layer, wherein the n-type doped region is located in the region between the bottom surface of the first barrier layer and the bottom surface of the second barrier layer at the bottom of the groove.

5. The method for manufacturing a gallium nitride HEMT device as described in claim 4, characterized in that, The doping material of the n-type doped region is silicon.

6. The method for manufacturing a gallium nitride HEMT device as described in claim 1, characterized in that, Both the first barrier layer and the second barrier layer are made of AlGaN or InAlN.

7. The method for manufacturing a gallium nitride HEMT device as described in claim 1, characterized in that, The inclination angle of the sidewall of the groove is 10 degrees to 80 degrees.

8. A method for manufacturing a gallium nitride HEMT device as described in claim 1, characterized in that, Step S60 includes: A P-GaN layer is formed on the second barrier layer, and the P-GaN layer fills the groove; A gate metal is formed on the P-GaN layer; The P-GaN layer and the gate metal are etched to form a gate structure.

9. A method for manufacturing a gallium nitride HEMT device as described in claim 1, characterized in that, Step S60 includes: A first insulating layer is formed on the second barrier layer; A gate metal is formed on the first insulating layer; The first insulating layer and the gate metal are etched to form the gate structure.

10. A method for manufacturing a gallium nitride HEMT device as described in claim 1, characterized in that, Step S60 includes: Fluorine ion implantation is performed on the second barrier layer located at the bottom of the groove; A gate metal is formed on the second barrier layer, and the gate metal fills the groove; The gate metal is etched to form the gate structure.

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