A method of forming a semiconductor structure and a semiconductor structure

Abstract

The application provides a method for forming a semiconductor structure and the semiconductor structure. The method for forming a semiconductor structure provides a substrate, a gate structure is formed on the substrate, a top surface and a sidewall of the gate structure are covered with a hard mask layer, a first epitaxial structure and a second epitaxial structure are respectively formed in the substrate on both sides of the gate structure; a first cap layer is respectively formed on surfaces of the first epitaxial structure and the second epitaxial structure, and the first cap layer has a first thickness; the hard mask layer is removed to form a gap between the first cap layer and the gate structure; and a sidewall covering the sidewall of the gate structure is formed, and the sidewall fills the gap.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Integrated circuit (IC) technology is constantly being improved. These improvements often involve shrinking device geometry to achieve lower manufacturing costs, higher device integration density, higher speed, and better performance. As IC technology continues to evolve, semiconductors with different structures have been proposed to address the ever-increasing demand for transistor density in integrated circuits.

[0003] Embedded SiGe process is a widely used method for improving transistor structure. By utilizing the difference in lattice constants between germanium and silicon to generate compressive stress, it can be embedded in the source and drain regions to improve the hole mobility and saturation current of PMOS (n-type substrate, p-channel metal-oxide-semiconductor) and enhance the electrical performance of pEFT (PMOS-based field-effect transistor) devices. Summary of the Invention

[0004] In a first aspect, this application provides a method for forming a semiconductor structure, comprising:

[0005] A substrate is provided on which a gate structure is formed. The top surface and sidewalls of the gate structure are covered with a hard mask layer. A first epitaxial structure and a second epitaxial structure are formed in the substrates on both sides of the gate structure, respectively.

[0006] A first capping layer is formed on the surface of the first epitaxial structure and the second epitaxial structure, and the first capping layer has a first thickness;

[0007] Remove the hard mask layer to form a gap between the first cap layer and the gate structure;

[0008] A sidewall is formed that covers the sidewall of the gate structure, and the sidewall fills the gap.

[0009] Secondly, this application provides a semiconductor structure prepared by the method for forming a semiconductor structure described above. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0011] Figures 1A to 1F A schematic diagram of a semiconductor structure at an intermediate stage in the manufacturing process is shown.

[0012] Figure 2 A flowchart of a method for forming a semiconductor structure according to an embodiment of this application is shown.

[0013] Figures 3A to 3H This diagram illustrates a semiconductor structure at an intermediate stage in the manufacturing process according to an embodiment of this application, wherein:

[0014] Figure 3A A schematic diagram of the formation of a hard mask layer in a semiconductor structure according to an embodiment of this application is shown;

[0015] Figure 3B A schematic diagram showing the formation of a first epitaxial groove and a second epitaxial groove in a semiconductor structure according to an embodiment of this application is shown;

[0016] Figure 3C A schematic diagram showing the formation of a first epitaxial structure, a second epitaxial structure, and a first capping layer in a semiconductor structure according to an embodiment of this application is shown;

[0017] Figure 3D A schematic diagram of the formation of gaps in a semiconductor structure according to an embodiment of this application is shown;

[0018] Figure 3E A schematic diagram of the formation of a sidewall material layer in a semiconductor structure according to an embodiment of this application is shown;

[0019] Figure 3F A schematic diagram of the formation of sidewalls in a semiconductor structure according to an embodiment of this application is shown;

[0020] Figure 3G A schematic diagram showing the formation of a second capping layer and a photoresist layer in a semiconductor structure according to an embodiment of this application is shown;

[0021] Figure 3H A schematic diagram of the formation of the source and drain regions of a semiconductor structure according to an embodiment of this application is shown.

[0022] Explanation of reference numerals in the attached figures:

[0023] Figures 1A to 1F In the middle: 10-substrate; 12-shallow trench isolation structure; 14-groove; 16-silicon-germanium epitaxial structure; 18-capping layer; 20-silicon-germanium source region; 22-silicon-germanium drain region; 30-gate structure; 32-sidewall; 36-hard mask layer; 36a-hard mask layer residue; 40-photoresist layer;

[0024] Figure 2 In Chinese: S02, S04, S06, S08 - process steps;

[0025] Figures 3A-3HIn the diagram: 301-Substrate; 302-Shallow trench isolation structure; 303-First epitaxial trench; 304-Second epitaxial trench; 311-First epitaxial structure; 312-Second epitaxial structure; 315-First capping layer; 316-Second capping layer; 321-Protective layer; 322-Hard mask layer; 323-Photoresist layer; 351-Source region; 352-Drain region; 390-Gate structure; 391-Initial sidewall; 392a-Sidewall material layer; 392b-Sidewall; G-Gap. Detailed Implementation

[0026] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the present application. Repeated reference numerals may be used in the various embodiments; these repeated reference numerals are for simplicity and clarity only and do not indicate a relationship between the various embodiments.

[0027] Furthermore, in this application, spatial relationship terms such as "below," "under," "above," and "below" can be used to describe the relationship between one element and another in the accompanying drawings. In addition to the orientations shown in the drawings, these spatial relationship terms may also include different orientations of the device / structure during use (e.g., rotation of 90 degrees). The interpretation of the aforementioned spatial relationship terms should be adjusted accordingly for these different orientations.

[0028] In the description of this application, the term "connection" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. For example, in this application, the formation of a first feature over a second feature can include direct or indirect contact between the first and second features.

[0029] In the embodiments described in this application, the term "about" or a term with an equivalent meaning can refer to a given number of values ​​that vary within, for example, 10% of the value. It is understood that for numerical values ​​not defined by terms such as "about" in this application, the numerical value may also have a certain range of fluctuation, provided that the desired technical effect of the embodiments of this application can be achieved, and the numerical values ​​described in the embodiments are merely exemplary.

[0030] Figures 1A to 1F A schematic diagram of a semiconductor structure 100 at an intermediate stage in the manufacturing process is shown. The semiconductor structure 100 is typically a PMOS transistor. The following will refer to... Figures 1A to 1F The formation process of a semiconductor structure 100 is described in detail.

[0031] Figure 1A A schematic diagram of the formation of a hard mask layer 36 in the semiconductor structure 100 is shown. Figure 1AIn the semiconductor structure 100, a substrate 10 is provided on the substrate 10 for forming a gate structure 30 of a PMOS transistor. The semiconductor structure 100 also includes a hard mask layer 36, which covers the surface and sidewalls of the gate structure 30 while exposing the surfaces of the substrate 10 located on both sides of the gate structure 30. These locations are used for subsequent formation of silicon-germanium epitaxial structures. Shallow trench isolation structures 12 are also typically provided in the substrate 10, located on both sides of the gate structure 30.

[0032] Figure 1B A schematic diagram of the formation of the recess 14 in the semiconductor structure 100 is shown. Figure 1B In this process, the substrate 10 is etched using a hard mask layer 36 as a mask to form a recess 14 in the substrate 10 located on both sides of the gate structure 30. The recess 14 is used for subsequent formation of germanium-silicon epitaxial structures, and the shape of the recess 14 is typically Σ-shaped.

[0033] Figure 1C A schematic diagram showing the formation of a germanium-silicon epitaxial structure 16 and a capping layer 18 in the semiconductor structure 100 is shown. Figure 1C In this process, a germanium-silicon epitaxial structure 16 is grown in a groove using an epitaxial process, and a capping layer 18 is formed on the upper surface of the germanium-silicon epitaxial structure 16. The thickness of the capping layer 18 is typically 18nm to 25nm. One function of the capping layer 18 is to protect the underlying silicon-germanium epitaxial structure 16, and the other function is to provide a silicon source for the subsequent growth of metal silicides.

[0034] Figure 1D A schematic diagram of the formation of semiconductor structure 100 by removing hard mask layer 36 is shown. Figure 1D In the process, the hard mask layer 36 is removed by etching. Since the capping layer 18 is relatively thick, after this step, hard mask layer residue 36a is usually left in the gap between the capping layer 18 and the gate structure 30.

[0035] Figure 1E A schematic diagram of the formation of sidewalls 32 in the semiconductor structure 100 is shown. Figure 1E In this process, sidewalls 32 are formed on the sidewalls of the gate structure 30 through deposition and etching. During the etching process, due to the presence of hard mask layer residue 36a in the gap between the capping layer 18 and the gate structure 30, the original rectangular cross-section of the sidewalls 32 of the gate structure 30 and sidewalls 32 changes, resulting in the following changes: Figure 1E The diagram shows a trapezoidal morphology. Simultaneously, the sidewalls 32 also partially cover the silicon-germanium epitaxial structure 16.

[0036] Figure 1F This diagram illustrates the formation of a patterned photoresist layer 40 in the semiconductor structure 100 and the ion implantation of the silicon-germanium epitaxial structure 16. Figure 1FIn this process, an ion implantation process is performed on the silicon-germanium epitaxial structure 16 to form a germanium-silicon source region 20 and a germanium-silicon drain region 22. At this time, because the sidewall 32 covers part of the silicon-germanium epitaxial structure 16, the ion implantation process is abnormally hindered, affecting the ion implantation position in the silicon-germanium epitaxial structure. This affects the current path of the finally formed germanium-silicon source region 20 and germanium-silicon drain region 22, introducing high-resistivity regions and parasitic capacitances, changing the effective channel length of the semiconductor structure, and ultimately affecting the performance of the semiconductor structure.

[0037] Furthermore, since the capping layer is typically formed before the removal of the hard mask layer, the formation of sidewalls, and the ion implantation process, its thickness is easily affected by these processes. Moreover, multiple PMOS transistors are usually present on the same wafer, with varying positions, structures, and relative distances, further contributing to the loading effect of these processes (i.e., uneven process effects in different regions). This results in different PMOS transistors forming Σ-shaped grooves of varying widths during fabrication, leading to silicon-germanium epitaxial structures of varying heights and capping layers of varying depths and thicknesses. Consequently, insufficient silicon source is difficult to provide when forming metal silicides in some PMOS transistors, resulting in a lack of stress relief in the silicon-germanium source and drain regions, ultimately affecting device performance.

[0038] In view of this, embodiments of this application provide a method for forming a semiconductor structure and a semiconductor structure.

[0039] Figures 3A to 3H A schematic diagram of a semiconductor structure 300 according to an embodiment of this application is shown at an intermediate stage in the manufacturing process. The following is in conjunction with... Figures 3A to 3H The semiconductor structure 300 provided in the embodiments of this application will be described in detail.

[0040] Figure 3A A schematic diagram of the formation of a hard mask layer 322 in a semiconductor structure 300 according to an embodiment of this application is shown. Figure 3A As shown, a substrate 301 is provided, on which a gate structure 390 is formed, and the top surface and sidewalls of the gate structure 390 are covered with a hard mask layer 322.

[0041] Substrate 301 includes, but is not limited to, a silicon substrate. In some embodiments, substrate 301 may be formed with integrated circuit devices and various doped components such as n-type doped wells, p-type doped wells, source and drain electrodes, other doped components, or combinations thereof, for forming various devices or components of devices. Integrated circuit devices include various IC devices formed on substrate 301, including diodes, bipolar transistors, imaging sensors, resistors, capacitors, inductors, memory cells, or combinations thereof.

[0042] In some embodiments, such as Figure 3A As shown, the substrate 301 includes a gate region and epitaxial structure regions located on both sides of the gate region, and a gate structure 390 is disposed on the substrate 301 of the gate region.

[0043] A hard mask layer 322 is disposed on the substrate 301, covering the top surface and sidewalls of the gate structure 390 and exposing the epitaxial structure region. The material of the hard mask layer 322 may include at least one of silicon nitride or silicon oxynitride.

[0044] In some embodiments, such as Figure 3A As shown, an initial sidewall 391 is disposed on the sidewall of the gate structure 390, and a shallow trench isolation structure 302 is disposed in the substrate 301 outside the epitaxial structure region to isolate the internal and external environments of the shallow trench isolation structure 302. A protective layer 321 may be disposed on the substrate 301 to protect the substrate 301, and the protective layer 321 may cover the substrate 301 outside the epitaxial structure region and the shallow trench isolation structure 302, while exposing the substrate 301 at the epitaxial structure region. A hard mask layer 322 may cover the surface of the initial sidewall 391, the top surface of the gate structure 390, and the surface of the protective layer 321. The material of the protective layer 321 may be silicon dioxide.

[0045] Figure 3B A schematic diagram showing the formation of a first epitaxial groove 303 and a second epitaxial groove 304 in a semiconductor structure 300 according to an embodiment of this application is shown. Figure 3B As shown, using the hard mask layer 322 as a mask, the substrate 301 of the epitaxial structure region can be etched sequentially using dry etching and wet etching processes to form the first epitaxial groove 303 and the second epitaxial groove 304. Both the first epitaxial groove 303 and the second epitaxial groove 304 can be Σ-shaped grooves.

[0046] Figure 3C A schematic diagram showing the formation of a first epitaxial structure 311, a second epitaxial structure 312, and a first capping layer 315 in a semiconductor structure 300 according to an embodiment of this application is shown. Figure 3C As shown, a first epitaxial structure 311 is formed by epitaxially growing silicon-germanium material in the first epitaxial groove 303, and a second epitaxial structure 312 is formed by epitaxially growing silicon-germanium material in the second epitaxial groove 304; and a first capping layer 315 is formed on the first epitaxial structure 311 and the second epitaxial structure 312.

[0047] In some embodiments, such as Figure 3C As shown, the first epitaxial structure 311, the second epitaxial structure 312, and the first capping layer 315 are all fabricated using an epitaxial process. The material of the first capping layer 315 includes at least one of silicon, silicon nitride, silicon oxide, or silicon oxynitride.

[0048] Figure 3D A schematic diagram of the formation of gap G in a semiconductor structure 300 according to an embodiment of this application is shown. Figure 3D As shown, the hard mask layer 322 is removed by etching. At this time, there is a gap G between the first capping layer 315 and the initial sidewall 391 outside the gate structure 390, and no hard mask material remains in the gap G. Since there is no hard mask material residue in the gap G between the first capping layer 315 and the initial sidewall 391, the cause affecting the sidewall morphology can be fundamentally solved, thereby avoiding the deformation of the sidewall morphology and subsequent effects.

[0049] Figure 3E A schematic diagram of the formation of a sidewall material layer 392a in a semiconductor structure 300 according to an embodiment of this application is shown. Figure 3E As shown, a sidewall material layer 392a can be formed using a deposition process. The sidewall material layer 392a fills the gap G and covers the top surface of the protective layer 321, the first capping layer 315, the gate structure 390, and the surface of the initial sidewall 391. The material of the sidewall material layer 392a can be silicon nitride.

[0050] Figure 3F A schematic diagram of the formation of sidewall 392b in a semiconductor structure 300 according to an embodiment of this application is shown. Figure 3F As shown, a portion of the sidewall material layer 392a is etched away to form sidewall 392b. Sidewall 392b only covers the sidewall of the initial sidewall 391 and fills the gap G between the first capping layer 315 and the initial sidewall 391.

[0051] Since no hard mask material remains in the gap G between the first capping layer 315 and the initial sidewall 391 in the aforementioned steps, the risk of the sidewall 392b formed in this step covering the first capping layer 315 is greatly reduced. In other words, the sidewall 392b is only located in the gap G between the first capping layer 315 and the initial sidewall 391, and the longitudinal section of the gate structure 390 and the sidewall 392b has a rectangular morphology. Therefore, the ion implantation regions of the source and drain regions can be improved, avoiding the introduction of high-resistivity regions and parasitic capacitances, thereby improving the performance of the semiconductor structure.

[0052] Figure 3G A schematic diagram showing the formation of a second capping layer 316 and a photoresist layer 323 in a semiconductor structure 300 according to an embodiment of this application is shown. Figure 3G As shown, a patterned photoresist layer 323 is formed, and a second capping layer 316 is formed on the first capping layer 315 using the sidewall 392b and the patterned photoresist layer 323 as a mask. The patterned photoresist layer 323 covers the top surface of the protective layer 321 and the gate structure 390.

[0053] In some embodiments, such as Figure 3G As shown, a second capping layer 316 is formed on a first capping layer 315 using an epitaxial process. The total thickness A of the first capping layer 315 and the second capping layer 316 is between 18 nm and 25 nm. The first capping layer 315 has a first thickness, and the second capping layer 316 has a second thickness. In some embodiments, the second thickness can be greater than the first thickness, where the first thickness is A (25%–35%) and the second thickness is A (65%–75%).

[0054] At this time, the first capping layer 315 and the second capping layer 316 together constitute the capping layer located on the source region 351 and the drain region 352. The total thickness of the first capping layer 315 and the second capping layer 316 is the third thickness. In some embodiments, the ratio of the first thickness to the third thickness can be 0.25 to 0.35.

[0055] The material of the second capping layer 316 includes at least one of silicon, silicon nitride, silicon oxide, or silicon oxynitride, and the material of the second capping layer 316 may be the same as the material of the first capping layer 315.

[0056] This step, by depositing a second capping layer 316 after the aforementioned process steps and controlling the total thickness of the first capping layer 315 and the second capping layer 316, can balance the final thickness of the germanium-silicon capping layer of PMOS transistors of different sizes on the same wafer, improve the lack of silicon source during the formation of metal silicides due to the loading effect, thereby improving the uniformity of the quality of the semiconductor structure formed on the same wafer and thus improving the process yield.

[0057] Figure 3H A schematic diagram showing the formation of a source region 351 and a drain region 352 in a semiconductor structure 300 according to an embodiment of this application is shown. Figure 3H As shown, using the patterned photoresist layer 323 as a mask, ion implantation processes are performed on the first epitaxial structure 311 and the second epitaxial structure 312 respectively to form a source region 351 in the first epitaxial structure 311 and a drain region 352 in the second epitaxial structure 312.

[0058] In some embodiments, such as Figure 3H As shown, the implanted ion type in this step can be P-type ions to form a PMOS transistor. The mask used to form the source region 351 and drain region 352 in this step is the same as the mask used to fabricate the second capping layer 316, so that no other special process steps are introduced to fabricate the mask of the second capping layer 316, and therefore no additional process cost is increased.

[0059] The semiconductor structure 300 provided in this application reduces the residue of front-end process materials on both sides of the gate structure by dividing the capping layer into a first capping layer and a second capping layer and fabricating them separately at different nodes of the process flow. This improves the sidewall morphology, thereby improving the ion implantation regions of the source and drain regions, effectively reducing the high-resistivity regions and parasitic capacitance introduced by the current path, and ultimately improving the performance of the semiconductor structure. Simultaneously, forming the capping layer in two stages can balance the silicon source deficiency in some PMOS transistors during the metal silicide formation process caused by the loading effect on different PMOS transistors on the same wafer, effectively improving the uniformity of different PMOS structures on the same wafer, thereby improving process yield.

[0060] This application also provides a method 200 for forming a semiconductor structure.

[0061] Figure 2 A flowchart of a method 200 for forming a semiconductor structure 300 according to an embodiment of this application is shown. The method 200 for forming a semiconductor structure may include steps S02 to S08.

[0062] In step S02, a substrate (such as...) is provided. Figure 3A Substrate 301), on which a gate structure (such as...) is formed. Figure 3A The gate structure 390 in the middle), the top surface and sidewalls of the gate structure are covered with a hard mask layer (such as Figure 3A The hard mask layer 322 in the middle), and the first epitaxial structure (such as the hard mask layer 322 in the middle) are formed in the substrates on both sides of the gate structure respectively. Figure 3D The first extensional structure 311) and the second extensional structure (such as Figure 3D The second extensional structure 312 in the middle.

[0063] In step S04, a first capping layer (such as...) is formed on the surfaces of the first epitaxial structure and the second epitaxial structure, respectively. Figure 3D The first capping layer 315 in the middle has a first thickness.

[0064] In step S06, the hard mask layer is removed to form a gap (such as) between the first cap layer and the gate structure. Figure 3D The gap G in the middle.

[0065] In step S08, sidewalls (such as those covering the sidewalls of the gate structure) are formed. Figure 3F Side wall 392b), side wall filling gap.

[0066] In some embodiments, the first thickness is 4.5 nm to 9 nm.

[0067] In some embodiments, the material of the first capping layer includes at least one of silicon, silicon nitride, silicon oxide, or silicon oxynitride.

[0068] In some embodiments, after forming the sidewalls covering the sidewalls of the gate structure, a second capping layer (such as...) is further formed to cover the first capping layer. Figure 3G The second capping layer 316 in the middle has a second thickness.

[0069] In some embodiments, the sum of the first thickness and the second thickness is the third thickness, and the ratio of the first thickness to the third thickness is 0.25 to 0.35.

[0070] In some embodiments, the third thickness is 18 nm to 25 nm.

[0071] In some embodiments, the material of the second capping layer includes at least one of silicon, silicon nitride, silicon oxide, or silicon oxynitride, and the material of the second capping layer is the same as that of the first capping layer.

[0072] In some embodiments, after forming the second capping layer, the method further includes: performing an ion implantation process on the first epitaxial structure to form a source region (such as...) in the first epitaxial structure. Figure 3H Source region 351); and performing an ion implantation process on the second epitaxial structure to form a drain region (such as...) in the second epitaxial structure. Figure 3H (Leakage area 352 in the middle).

[0073] In some embodiments, the material of the hard mask layer includes at least one of silicon nitride or silicon oxynitride.

[0074] In some embodiments, forming a sidewall further includes: forming a sidewall material layer (such as...) Figure 3E The sidewall material layer 392a) covers the top surface and sidewalls of the gate structure, the surface of the first capping layer, and fills the gaps; and etches to remove a portion of the sidewall material layer, the portion of which covers the surface of the gate structure and the first capping layer, to form a sidewall.

[0075] The method 200 for forming a semiconductor structure provided in this application divides the capping layer into a first capping layer and a second capping layer, and fabricates them separately at different nodes in the process flow. This reduces the residue of front-end process materials on both sides of the gate structure, improves the sidewall morphology, and thus improves the ion implantation regions of the source and drain regions. It effectively reduces the introduction of high-resistivity regions and parasitic capacitances through the current path, and ultimately improves the performance of the semiconductor structure. Simultaneously, forming the capping layer in two stages can balance the silicon source deficiency in some PMOS transistors during the metal silicide formation process caused by the loading effect on different PMOS transistors on the same wafer, effectively improving the uniformity of different PMOS structures on the same wafer, thereby improving process yield.

[0076] This application also provides a semiconductor structure fabricated using the method provided in this application. The semiconductor structure provided in this application, by dividing the capping layer into a first capping layer and a second capping layer and fabricating them separately at different nodes in the process flow, can reduce the residue of front-end process materials on both sides of the gate structure, improve the sidewall morphology, and thus improve the ion implantation regions of the source and drain regions. This effectively reduces the introduction of high-resistivity regions and parasitic capacitances through the current path, ultimately improving the performance of the semiconductor structure. Simultaneously, forming the capping layer in two stages can balance the silicon source deficiency in some PMOS transistors during the metal silicide formation process caused by the loading effect on different PMOS transistors on the same wafer, effectively improving the uniformity of different PMOS structures on the same wafer, thereby improving process yield.

[0077] It is understood that the actions and steps described in the above embodiments and accompanying drawings can be performed in different orders to achieve the technical effects expected in this application, and are not limited to the order described in the above embodiments and accompanying drawings.

[0078] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. The scope of this application is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this application, and all such substitutions and modifications should fall within the scope of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a gate structure is formed. The top surface and sidewalls of the gate structure are covered with a hard mask layer. A first epitaxial structure and a second epitaxial structure are formed in the substrates on both sides of the gate structure, respectively. A first capping layer is formed on the surface of the first epitaxial structure and the second epitaxial structure, and the first capping layer has a first thickness; Remove the hard mask layer to form a gap between the first cap layer and the gate structure; A sidewall is formed that covers the sidewall of the gate structure, and the sidewall fills the gap.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The first thickness is 4.5nm to 9nm.

3. The method for forming a semiconductor according to claim 1, characterized in that, The material of the first capping layer includes at least one of silicon, silicon nitride, silicon oxide, or silicon oxynitride.

4. The method for forming a semiconductor according to claim 1, characterized in that, After forming the sidewalls covering the sidewalls of the gate structure, the method further includes: A second cap layer is formed to cover the first cap layer, the second cap layer having a second thickness.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, The sum of the first thickness and the second thickness is the third thickness, and the ratio of the first thickness to the third thickness is 0.25 to 0.

35.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The third thickness is 18nm to 25nm.

7. The method for forming a semiconductor structure according to claim 4, characterized in that, The material of the second capping layer includes at least one of silicon, silicon nitride, silicon oxide, or silicon oxynitride, and the material of the second capping layer is the same as that of the first capping layer.

8. The method for forming a semiconductor structure according to claim 4, characterized in that, After forming the second cap layer, the method further includes: An ion implantation process is performed on the first epitaxial structure to form a source region in the first epitaxial structure; An ion implantation process is performed on the second epitaxial structure to form a drain region in the second epitaxial structure.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the hard mask layer includes at least one of silicon nitride or silicon oxynitride.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The formation of the sidewall further includes: A sidewall material layer is formed, which covers the top surface and sidewalls of the gate structure, covers the surface of the first capping layer, and fills the gap. Etching is used to remove a portion of the sidewall material layer that covers the surface of the gate structure and the first capping layer to form the sidewall.

11. A semiconductor structure, characterized in that, It is prepared by the method of forming a semiconductor structure as described in any one of claims 1 to 10.

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