Method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device, mainly comprising sequentially forming a conductor material and a dielectric material on a semiconductor unit along a growth direction, then forming a photoresist material on the dielectric material along the growth direction, patterning the photoresist material to form a photoresist layer, patterning the dielectric material and the conductor material with the photoresist layer as a mask to form a dielectric layer and a conductor layer respectively, and finally removing the photoresist layer to pattern the semiconductor unit with the dielectric layer as a mask. The present application only needs one photoresist lithography process, thus simplifying the process and avoiding the alignment deviation problem when patterning the conductor layer and the semiconductor unit respectively, and greatly improving the process yield.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high electron mobility transistor. Background Technology

[0002] High electron mobility transistors (HEMTs), as a type of field-effect transistor, are widely used in integrated circuits. HEMTs use two materials with different bandgap widths to form a heterojunction, and naturally form a two-dimensional electron gas (2DEG) conductive channel at the heterojunction interface, thus exhibiting high electron mobility.

[0003] A method for manufacturing a high electron mobility transistor. For example... Figure 1 As shown, a barrier layer 92, a p-type doped material 93', and a conductor material 94' are sequentially formed on a semiconductor layer 91 along a growth direction G. A patterned first photoresist layer 95 is formed on the conductor material 94'. Using the first photoresist layer 95 as a mask, the conductor material 94' is patterned to form... Figure 2 A conductor layer 94 is shown. (See also...) Figure 3 A patterned second photoresist layer 96 is formed on the conductor layer 94 along the growth direction G. Using the second photoresist layer 96 as a mask, the P-type doped material 93' is patterned to form a shape as shown in the image. Figure 4 The p-type doped layer 93 is shown.

[0004] However, the above method requires two photoresist lithography processes to pattern the conductor material 94' and the P-type doped material 93' separately, making the process steps relatively cumbersome. Furthermore, in the two photoresist lithography processes, the patterns of the first photoresist layer 95 and the second photoresist layer 96 should theoretically completely overlap, and the patterns of the conductor layer 94 and the P-type doped layer 93 should also completely overlap. However, due to alignment deviations in the lithography machine, issues such as… Figure 4 The misalignment between the conductor layer 94 and the p-type doped layer 93, as shown, leads to a decrease in process yield. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing a semiconductor device that can at least overcome the shortcomings of the prior art.

[0006] The method for manufacturing a semiconductor device according to the present invention includes steps A to E.

[0007] Step A: Conductor material and dielectric material are sequentially formed on the semiconductor cell along the growth direction.

[0008] Step B: Form a photoresist material on the dielectric material along the growth direction.

[0009] Step C: Pattern the photoresist material to form a photoresist layer.

[0010] Step D: Using the photoresist layer as a mask, pattern the dielectric material and the conductor material to form a dielectric layer and a conductor layer respectively.

[0011] Step E: Remove the photoresist layer and pattern the semiconductor unit using the dielectric layer as a mask.

[0012] The method for manufacturing a semiconductor device according to the present invention further includes step F, defining a width direction perpendicular to the growth direction, wherein in step F, the conductor layer is etched such that the outer edge of the conductor layer is recessed relative to the outer edge of the semiconductor cell along the width direction.

[0013] In the method for manufacturing a semiconductor device according to the present invention, in step F, the dielectric layer is removed before etching the conductor layer.

[0014] The semiconductor device manufacturing method of the present invention has a first spacing and a second spacing on the outer edges of both sides of the conductor layer and the outer edges of both sides of the semiconductor unit along the width direction, wherein the first spacing and the second spacing are the same.

[0015] In the method for manufacturing a semiconductor device according to the present invention, in step A, the semiconductor unit has a semiconductor layer and a III-V compound layer sequentially along the growth direction, and the conductor material is formed on the III-V compound layer.

[0016] The semiconductor device manufacturing method of the present invention includes a III-V compound layer having a barrier layer and a doped layer along the growth direction, wherein in step E, the doped layer is patterned.

[0017] The semiconductor device manufacturing method of the present invention, wherein the doped layer is formed of magnesium-doped gallium nitride.

[0018] In the method for manufacturing a semiconductor device according to the present invention, in step A, the conductor material is titanium nitride.

[0019] In the method for manufacturing a semiconductor device according to the present invention, in step A, the dielectric material is silicon nitride or silicon oxide.

[0020] The beneficial effects of this invention are as follows: This invention simultaneously patterns the dielectric layer and the conductor layer using the photoresist layer, and then uses the dielectric layer as a mask to pattern the semiconductor unit. Therefore, only one photoresist lithography process is required, simplifying the process steps. Furthermore, since two photoresist lithography processes are not required, there are no alignment deviation problems with the lithography machine, and no alignment misalignment between the conductor layer and the semiconductor unit, significantly improving process yield. Attached Figure Description

[0021] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, wherein:

[0022] Figures 1-4 This is a schematic diagram of a conventional high electron mobility transistor manufacturing method;

[0023] Figure 5 This is a flowchart of the manufacturing method of the semiconductor device of the present invention;

[0024] Figure 6 yes Figure 5 A schematic diagram of steps A and B in the middle section;

[0025] Figure 7 yes Figure 5 A schematic diagram of steps C and D in the middle section;

[0026] Figure 8 yes Figure 5 A schematic diagram of step E in the middle section;

[0027] Figure 9 yes Figure 5 A schematic diagram of step E in the middle section;

[0028] Figure 10 yes Figure 5 A schematic diagram of step F in the middle section;

[0029] Figure 11 yes Figure 5 A schematic diagram of step F. Detailed Implementation

[0030] The relevant technical content, features, and effects of this invention will be clearly presented in the following detailed description of the embodiments with reference to the accompanying drawings. Furthermore, it should be noted that the accompanying drawings are only for illustrating the structural and / or positional relationships between components and are not related to the actual dimensions of each component.

[0031] See Figure 5 An embodiment of the method for manufacturing a semiconductor device according to the present invention includes steps A to F, which will be described step by step below with reference to the accompanying drawings.

[0032] Define a growth direction X and a width direction Y perpendicular to the growth direction X.

[0033] See Figure 6 In step A, a conductor material 2' and a dielectric material 3' are sequentially formed on a semiconductor unit 1 along the growth direction X.

[0034] Specifically, the semiconductor unit 1 sequentially comprises a semiconductor layer 11 and a group III-V compound layer 12 along the growth direction X. The group III-V compound layer 12 comprises a barrier layer 121 and a doped layer 122 along the growth direction X. The barrier layer 121 is formed, for example, but not limited to, aluminum gallium nitride. The doped layer 122 is formed, for example, but not limited to, a p-type doped group III-V compound. For example, the doped layer 122 is formed of magnesium-doped gallium nitride.

[0035] Specifically, the conductor material 2' is formed on the doped layer 122 of the III-V compound layer 12. The conductor material 2' can be a metal or a ceramic material. For example, the conductor material 2' can be titanium nitride. The dielectric material 3' can be silicon nitride or silicon oxide.

[0036] In step B, a photoresist material 4' is formed on the dielectric material 3' along the growth direction X.

[0037] See Figure 7 In step C, the photoresist material 4' is patterned to form a photoresist layer 4.

[0038] Specifically, after patterning the photoresist material 4', the formed photoresist layer 4 has a specific pattern, such as, but not limited to, a gate pattern.

[0039] In step D, the dielectric material 3' and the conductor material 2' are patterned using the photoresist layer 4 as a mask to form a dielectric layer 3 and a conductor layer 2, respectively.

[0040] Specifically, step D uses anisotropic etching methods, such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etching, to synchronously transfer the specific pattern on the photoresist layer 4 to the dielectric layer 3 and the conductor layer 2.

[0041] See Figure 8 and Figure 9 In step E, the photoresist layer 4 is removed, and the doped layer 122 of the semiconductor unit 1 is patterned using the dielectric layer 3 as a mask.

[0042] Specifically, step E involves transferring the specific pattern on the dielectric layer 3 to the doped layer 122 using an anisotropic etching method.

[0043] Since the specific patterns of the conductor layer 2 and the doped layer 122 of the semiconductor unit 1 are defined by the photoresist layer 4 and the dielectric layer 3, respectively, and the specific pattern of the dielectric layer 3 is defined by the photoresist layer 4, there will be no alignment misalignment between the conductor layer 2 and the semiconductor unit 1. In other words, along the width direction Y, the outer edge of the conductor layer 2 is flush with the outer edge of the doped layer 122 of the semiconductor unit 1.

[0044] See Figure 10 and Figure 11 In step F, the dielectric layer 3 is removed, and the conductor layer 2 is etched so that the outer edge of the conductor layer 2 is recessed relative to the outer edge of the semiconductor unit 1 along the width direction Y.

[0045] Specifically, in step F, isotropic etching, such as wet etching, is used to etch the conductor layer 2, reducing its thickness along the growth direction X and its width along the width direction Y. After etching, the outer edge of the conductor layer 2 is recessed relative to the outer edge of the semiconductor unit 1 along the width direction Y, forming a gap between the outer edge of the conductor layer 2 and the outer edge of the semiconductor unit 1. Since the outer edge of the conductor layer 2 is flush with the outer edge of the semiconductor unit 1 before step F, after isotropic etching, as... Figure 11 As shown, the outer edges of both sides of the conductor layer 2 and the outer edges of both sides of the semiconductor unit 1 along the width direction Y have a first spacing W1 and a second spacing W2, respectively. When the process error is negligible, the first spacing W1 will be the same as the second spacing W2, thus forming a left-right symmetrical gate structure.

[0046] Along the width direction Y, the width of the conductor layer 2 is designed to be smaller than the width of the doped layer 122 below, forming a stepped gate structure. This symmetrical gate structure ensures stable transistor performance. In this embodiment, before the wet etching in step F, the outer edge of the conductor layer 2 is flush with the outer edge of the doped layer 122 of the semiconductor unit 1, resulting in a relatively smooth sidewall surface. Therefore, compared to the uneven sidewall surface of the prior art... Figure 4This invention reduces the likelihood of foot defects during wet etching, allowing for more precise formation of symmetrical gate structures. This results in stable static and dynamic electrical properties and improved reliability for the transistor. Therefore, compared to existing technologies, this invention is not limited by the alignment limits of lithography machines and can form symmetrical gate structures more precisely with simpler process steps.

[0047] It should be noted that in step F of this embodiment, the dielectric layer 3 is removed before etching the conductor layer 2. However, the conductor layer 2 can also be etched directly without removing the dielectric layer 3. In this case, the thickness of the conductor layer 2 will not be reduced, only the width will be reduced.

[0048] In summary, the semiconductor device manufacturing method of the present invention simultaneously patterns the dielectric layer 3 and the conductor layer 2 using the photoresist layer 4, and then patterns the semiconductor unit 1 using the dielectric layer 3 as a mask. Therefore, only one photoresist lithography process is required, simplifying the manufacturing process. Furthermore, since two photoresist lithography processes are not required, there are no alignment deviation problems associated with the photoresist machine, and there is no alignment misalignment between the conductor layer 2 and the semiconductor unit 1, which significantly improves the process yield. Therefore, the objective of the present invention is indeed achieved.

[0049] The above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the claims and description of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method for manufacturing the semiconductor device includes: Step A: Sequentially form conductor material and dielectric material on the semiconductor cell along the growth direction; Step B: Form a photoresist material on the dielectric material along the growth direction; Step C: Pattern the photoresist material to form a photoresist layer; Step D: Using the photoresist layer as a mask, pattern the dielectric material and the conductor material to form a dielectric layer and a conductor layer respectively; and Step E: Remove the photoresist layer and pattern the semiconductor unit using the dielectric layer as a mask.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The method for manufacturing the semiconductor device further includes step F, defining a width direction perpendicular to the growth direction, wherein in step F, the conductor layer is etched such that the outer edge of the conductor layer is recessed relative to the outer edge of the semiconductor cell along the width direction.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that: In step F, the dielectric layer is removed before etching the conductor layer.

4. The method for manufacturing a semiconductor device according to claim 2 or 3, characterized in that: The outer edges of the conductor layer on both sides along the width direction and the outer edges of the semiconductor unit on both sides have a first spacing and a second spacing, respectively, wherein the first spacing and the second spacing are the same.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step A, the semiconductor unit has a semiconductor layer and a III-V compound layer sequentially along the growth direction, and the conductor material is formed on the III-V compound layer.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The III-V compound layer has a barrier layer and a doped layer along the growth direction, and in step E, the doped layer is patterned.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that: The doped layer is formed of magnesium-doped gallium nitride.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step A, the conductor material is titanium nitride.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step A, the dielectric material is silicon nitride or silicon oxide.

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