Method for manufacturing a two-dimensional semiconductor device and two-dimensional semiconductor device

Abstract

The application provides a preparation method of a two-dimensional semiconductor device and the two-dimensional semiconductor device, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps: providing a substrate and sequentially forming a two-dimensional semiconductor channel layer, an etching stop layer and a channel insulating layer on the surface of the substrate; performing a patterning treatment on the channel insulating layer to form an opening exposing part of the etching stop layer; removing the etching stop layer exposed by the opening by using a selective etching process until the surface of the two-dimensional semiconductor channel layer at the bottom is exposed to form a contact hole; and depositing a metal buffer layer in the contact hole to cover at least the bottom of the contact hole; wherein the atomic layer deposition process in a thermal growth mode is used to form the etching stop layer and / or the metal buffer layer; and a source-drain electrode is formed on the metal buffer layer in the contact hole. The application realizes a preparation process which can meet the large-scale preparation of two-dimensional semiconductor chips, is compatible with the existing silicon process, and has a small influence on the performance of the two-dimensional material itself.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for fabricating a two-dimensional semiconductor device and the two-dimensional semiconductor device itself. Background Technology

[0002] With the advancement of Moore's Law, the short-channel effect in silicon-based devices has approached its physical limit as the size of these devices shrinks. Two-dimensional semiconductor materials with excellent electrical properties, such as molybdenum sulfide from transition metal chalcogenides, are considered among the most likely semiconductor materials to replace silicon. However, the large-scale fabrication technology of two-dimensional semiconductor devices still faces many challenges, especially in source-drain contact engineering.

[0003] Taking molybdenum sulfide as an example, its ultra-thin structure makes it difficult for traditional ion implantation doping processes to form good source-drain contacts without damaging the material. In common source-drain metal fabrication processes, sputtering, due to its excessively high power, causes severe physical damage to the molybdenum sulfide lattice caused by high-energy particle bombardment. While commonly used laboratory evaporation processes, such as electron beam evaporation, cause less damage, they are difficult to apply in large-scale industrial production and have poor compatibility with existing silicon-based process lines, such as CMOS production lines, resulting in high equipment and maintenance costs. Summary of the Invention

[0004] This invention provides a method for fabricating a two-dimensional semiconductor device and the two-dimensional semiconductor device itself. It realizes a fabrication process that can meet the requirements of large-scale fabrication of two-dimensional semiconductor chips, is compatible with existing silicon processes, and has little impact on the performance of the two-dimensional materials themselves. It solves the technical problem that traditional processes are difficult to achieve low damage, high compatibility and scalable production.

[0005] In a first aspect, the present invention provides a method for fabricating a two-dimensional semiconductor device, comprising: A substrate is provided, and a two-dimensional semiconductor channel layer, an etch barrier layer, and a channel insulating layer are sequentially formed on the surface of the substrate; The channel insulating layer is patterned to form an opening that exposes a portion of the etch barrier layer; A selective etching process is used to remove the etch barrier layer exposed by the opening until the surface of the bottom two-dimensional semiconductor channel layer is exposed to form a contact hole; A metal buffer layer is deposited within the contact hole to at least cover the bottom of the contact hole; wherein the etching barrier layer and / or the metal buffer layer are formed using an atomic layer deposition process with thermal growth mode; Source and drain electrodes are formed on the metal buffer layer within the contact hole.

[0006] In some embodiments, the atomic layer deposition process employing a thermal growth mode includes: In a purely thermally driven environment without plasma participation, the structure to be deposited is heated to a preset reaction temperature; Precursor gas and reactant gas are alternately introduced, and thin films are deposited layer by layer by utilizing the self-limiting chemical reaction between the precursor gas and the reactant gas on the substrate surface to form the corresponding film layer.

[0007] In some embodiments, the etching barrier layer is formed using a thermal growth mode atomic layer deposition process, including: A metal-organic compound is used as the first precursor gas, and water vapor or ozone is used as the first reactant gas. The first precursor gas and the first reactant gas are alternately introduced to conformally grow a metal oxide film on the surface of the two-dimensional semiconductor channel layer as the etching barrier layer.

[0008] In some embodiments, the metal buffer layer is formed using an atomic layer deposition process with a thermal growth mode, including: A metal thin film is grown by reduction on the surface of the two-dimensional semiconductor channel layer at the bottom of the contact hole, using a metal-organic compound or metal halide as the second precursor gas and a nitrogen- or carbon-containing reducing gas as the second reactant gas.

[0009] In some embodiments, a selective etching process is used to remove the etching barrier layer exposed by the opening, including: The etching barrier layer exposed by the opening is removed by one of the following processes: inductively coupled plasma etching, wet etching, or atomic layer etching; wherein the atomic layer etching process includes peeling off the etching barrier layer atomically by alternating the introduction of chemically modified gas and inert bombardment gas until the surface of the bottom two-dimensional semiconductor channel layer is exposed to form a contact hole.

[0010] In some embodiments, a metal buffer layer is deposited within the contact hole to at least cover the bottom of the contact hole, including: A metal buffer layer is deposited within the contact hole to simultaneously cover the bottom and sidewalls of the contact hole.

[0011] In some embodiments, after removing the etch barrier layer and before depositing the metal buffer layer, the method further includes: The exposed surface of the two-dimensional semiconductor channel layer is subjected to in-situ defect repair treatment; wherein, the in-situ defect repair treatment includes in-situ thermal annealing by introducing a sulfur-based gas or a mixture of hydrogen and argon into the atomic layer deposition reaction chamber.

[0012] In some embodiments, the metal buffer layer is deposited within the contact hole, including: By dynamically changing the process parameters during the layer-by-layer growth process, thin films with different component ratios are deposited layer by layer, so that the metal buffer layer formed exhibits a component distribution in the thickness direction where the content of non-metallic elements gradually increases from the interface near the two-dimensional semiconductor channel layer to the surface.

[0013] In some embodiments, the metal buffer layer is formed using a thermal growth atomic layer deposition process, and after the metal buffer layer is deposited and before the source / drain electrodes are formed, the process further includes: By controlling and reducing the pressure in the atomic layer deposition reaction chamber and extending the residence time of the precursor, an additional dense homogeneous metal protective film is deposited at the sidewall steps of the contact hole using a thermal growth mode atomic layer deposition process.

[0014] In some embodiments, forming the source / drain electrodes includes: The source and drain electrodes are deposited using a plasma-enhanced atomic layer deposition process. In the plasma excitation stage of the plasma-enhanced atomic layer deposition process, a radio frequency bias voltage is applied to enhance the directionality of plasma active species and improve the uniformity of metal coverage at the bottom and sidewall steps of the contact hole.

[0015] In some embodiments, after forming the source and drain electrodes, the method further includes: A rapid thermal annealing process is performed on the two-dimensional semiconductor device under a non-oxidizing protective atmosphere; wherein the temperature of the rapid thermal annealing process is lower than the critical temperature at which the two-dimensional semiconductor channel layer undergoes a phase transition or decomposition, so as to drive the metal atoms at the bottom of the metal buffer layer to form bonds with the surface atoms of the two-dimensional semiconductor channel layer.

[0016] In some embodiments, the material constituting the two-dimensional semiconductor channel layer includes a transition metal chalcogenide semiconductor material, the material constituting the metal buffer layer includes at least one of titanium nitride, tantalum nitride, titanium, nickel, and platinum, and the material constituting the etch barrier layer includes a metal oxide material. The thickness of the etching barrier layer ranges from 1 nm to 10 nm, the thickness of the metal buffer layer ranges from 1 nm to 5 nm, and the thickness of the source / drain electrodes ranges from 5 nm to 15 nm.

[0017] In a second aspect, the present invention also provides a two-dimensional semiconductor device, which is prepared by the method for preparing a two-dimensional semiconductor device as described in the first aspect.

[0018] This invention protects the channel by introducing an etch barrier layer and employs selective etching to precisely open the contact holes, avoiding excessive damage to the channel during the etching of the insulating layer. Simultaneously, a plasma-free thermal growth atomic layer deposition process is used when depositing the critical interface layer, namely the metal buffer layer, eliminating plasma damage at its source and significantly reducing process-induced damage to the two-dimensional semiconductor channel layer. The thermal growth atomic layer deposition process is fully compatible with existing 8-inch and 12-inch silicon-based production lines and can be integrated into existing integrated circuit manufacturing processes, possessing extremely high mass production feasibility. A clean channel surface is obtained through selective etching, and a conformal and dense metal buffer layer is formed through thermal growth atomic layer deposition, ensuring maximum effective contact area and a good interfacial chemical state between the metal and semiconductor, providing a foundation for achieving low contact resistance. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of a method for fabricating a two-dimensional semiconductor device according to an embodiment of the present invention; Figures 2 to 9 This is a schematic diagram of the cross-sectional structure formed sequentially by each step of the fabrication method of a two-dimensional semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0022] This invention provides a method for fabricating a two-dimensional semiconductor device. Figure 1 This is a schematic flowchart illustrating a method for fabricating a two-dimensional semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the fabrication method of a two-dimensional semiconductor device includes the following steps: S101, Provide a substrate and sequentially form a two-dimensional semiconductor channel layer, an etch barrier layer and a channel insulating layer on the substrate surface.

[0023] S102. Pattern the channel insulation layer to form an opening that exposes part of the etch barrier layer.

[0024] S103. Selective etching process is used to remove the etch barrier layer exposed by the opening until the surface of the bottom two-dimensional semiconductor channel layer is exposed to form a contact hole.

[0025] S104. A metal buffer layer is deposited in the contact hole to at least cover the bottom of the contact hole; wherein the formation of the etch barrier layer and / or the formation of the metal buffer layer is carried out using an atomic layer deposition process with thermal growth mode.

[0026] S105. Source and drain electrodes are formed on the metal buffer layer inside the contact hole.

[0027] Figures 2 to 9 This is a schematic cross-sectional view of the structure formed by each step of the fabrication method of a two-dimensional semiconductor device provided in an embodiment of the present invention. Combined with... Figures 2 to 9 Two-dimensional semiconductor devices refer to semiconductor devices that use two-dimensional materials, such as transition metal chalcogenides with a thickness of one or several atomic layers, as the channel material. The substrate 100 refers to the substrate material used to support the entire device structure, such as silicon, silicon carbide, quartz, sapphire, or silicon wafers with an oxide layer. The two-dimensional semiconductor channel layer 200 refers to a thin layer composed of two-dimensional semiconductor material, which is the main region for carrier transport in the device. The etch barrier layer 300 refers to a thin film layer used to protect the underlying two-dimensional semiconductor channel layer 200 from over-etching during the etching of the channel insulating layer 400. The channel insulating layer 400 refers to a dielectric layer used to electrically isolate the active region of the device from other conductive layers or other regions. Patterning refers to a series of process steps, including photolithography and etching, used to form predetermined geometric patterns on the thin film.

[0028] Selective etching can remove one material at significantly different rates while leaving another exposed material almost untouched. Contact holes 500 refer to openings formed in the dielectric layer, used to fill conductive material to achieve electrical connection between the source / drain electrodes 700 and the underlying semiconductor channel layer. A metal buffer layer 600 refers to a thin metal film located between the source / drain electrodes 700 and the two-dimensional semiconductor channel layer 200, used to improve contact interface characteristics, such as blocking subsequent metal diffusion, reducing contact resistance, and buffering stress. Thermal growth mode atomic layer deposition refers to thin film deposition technology where the chemical reaction is entirely driven by thermal excitation, without plasma assistance. It achieves atomic-level precision thin film growth by alternately and sequentially introducing gaseous precursors, which undergo self-limiting chemical adsorption and reaction on the heated substrate 100 surface.

[0029] First, combined Figure 2 and Figure 3Before forming the source / drain contact, an etch barrier layer 300 is pre-deposited on the two-dimensional semiconductor channel layer 200, such as... Figure 4 As shown, the active region, i.e., the area where the two-dimensional semiconductor channel layer 200 is located, is defined using photolithography and etching processes. In the subsequent process of defining the contact hole 500, when the thicker channel insulating layer 400 is patterned and etched, this etch barrier layer 300 acts as an endpoint detection and physical barrier. Even if the etching process is slightly over-etched, it will stop at this etch barrier layer 300 without damaging the fragile, ultra-thin two-dimensional semiconductor channel layer 200 underneath. Then, combined with Figure 5 and Figure 6 For example, silicon nitride and silicon oxide films are grown as communication insulating layers, and the upper surface is treated with a chemical mechanical polishing process. Subsequently, as... Figure 7 As shown, an etching process with high selectivity for the two-dimensional semiconductor channel layer 200 material is used to precisely remove the etching barrier layer 300 at the bottom of the contact hole 500, thereby obtaining a clean and undamaged surface of the two-dimensional semiconductor channel layer 200. Then, as... Figure 8 As shown, a metal buffer layer 600 is deposited on this clean surface, laying the foundation for the subsequent formation of high-quality source / drain electrodes 700. Specifically, when forming the etch barrier layer 300 and / or the metal buffer layer 600, an atomic layer deposition process using thermal growth mode is employed. Since the entire process does not involve high-energy plasma, it avoids damage to the two-dimensional material lattice caused by high-energy particle bombardment. Simultaneously, its excellent conformality, namely step coverage capability and atomic-level thickness control precision, ensures the formation of a uniform and dense thin film on the bottom and sidewalls of the contact hole 500. Finally, as... Figure 9 As shown, source and drain electrodes 700 are formed on the metal buffer layer inside the contact hole 500.

[0030] Therefore, this embodiment of the invention protects the channel by introducing an etch barrier layer 300 and precisely opening the contact holes 500 using a selective etching process, avoiding excessive damage to the channel during the etching of the insulating layer. Simultaneously, a plasma-free thermal growth atomic layer deposition process is used when depositing the critical interface layer, namely the metal buffer layer 600, eliminating plasma damage at its source and significantly reducing process-induced damage to the two-dimensional semiconductor channel layer 200. The thermal growth atomic layer deposition process is fully compatible with existing 8-inch and 12-inch silicon-based production lines and can be integrated into existing integrated circuit manufacturing processes, possessing extremely high mass production feasibility. A clean channel surface is obtained through selective etching, and then a conformal and dense metal buffer layer 600 is formed through thermal growth atomic layer deposition, ensuring maximum effective contact area and good interfacial chemistry between the metal and semiconductor, providing a foundation for achieving low contact resistance.

[0031] In some embodiments, the atomic layer deposition process using a thermal growth mode includes: heating the structure to be deposited to a preset reaction temperature in a pure thermal-driven environment without plasma participation; alternately introducing precursor gas and reactive gas, and using the self-limiting chemical reaction of precursor gas and reactive gas on the surface of substrate 100 to deposit thin films layer by layer to form the corresponding film layer.

[0032] Specifically, a purely thermally driven environment means that no radio frequency power supply, microwave, or any other form of plasma generator is introduced into the deposition chamber; the activation energy required for the chemical reaction is entirely provided by the heat energy supplied by the heating stage of the substrate 100. The preset reaction temperature refers to a temperature range pre-set according to the type of thin film material being deposited. At this temperature, the precursor gas and the reactant gas can undergo the expected self-limiting chemical reaction. For example, for some metal oxides, the preset reaction temperature may be between 150°C and 350°C. The precursor gas refers to a volatile chemical substance containing the metal element or main component element of the thin film to be deposited, introduced into the reaction chamber in gaseous form. The reactant gas refers to another gaseous substance that chemically reacts with the precursor gas, used to decompose or convert the precursor into the target thin film material, such as oxides, nitrides, or metals. Self-limiting chemical reaction is a core characteristic of atomic layer deposition. When the precursor gas is pulsed into the chamber, it undergoes chemical adsorption with the active sites exposed on the surface of the substrate 100, forming only a monolayer. Once all active sites are occupied, the adsorption process automatically stops. The subsequently introduced reactive gas reacts only with the adsorbed precursor molecules to generate the target film and regenerates new active sites on the surface, preparing for the next cycle. This reaction itself is saturated and self-limiting.

[0033] First, the device structure to be deposited is heated to a preset temperature, such as 250°C. At this temperature, the precursor molecules gain sufficient thermal energy, and then a cycle of precursor pulse, purge, reactant pulse, and purge is performed sequentially. During the precursor pulse phase, precursor gas molecules diffuse across the entire surface of the substrate 100 and form chemisorption with the chemical dangling bonds on the substrate 100 surface. Due to the self-limiting reaction, once all active sites on the surface are covered, excess molecules will not be adsorbed, ensuring uniform monolayer coverage. Next, an inert gas, such as nitrogen or argon, is used for purging to remove unadsorbed or weakly adsorbed precursor molecules. Then, a reactive gas is introduced, which reacts with the adsorbed monolayer precursor to generate the desired solid film, such as a metal or metal compound, and produces volatile byproducts. A final purge removes the byproducts and excess reactants. With each complete precursor-purge-reactant-purge cycle, the film thickness increases precisely by one atomic layer. By controlling the number of cycles, the total film thickness can be precisely controlled.

[0034] Therefore, the entire process in this embodiment of the invention is plasma-free, which is crucial for the ultrathin two-dimensional semiconductor channel layer 200. Ions and free radicals in high-energy plasma can easily cause lattice defects, introduce interface states, and even cause amorphization in two-dimensional materials. This embodiment of the invention eliminates the above-mentioned damage through pure thermal drive. Atomic-level precision thickness control can be achieved by simply setting the number of cycles, which is crucial for optimizing the interface effect of the metal buffer layer 600. In the thermal growth mode atomic layer deposition process, the precursor is transported by the thermal motion of gas molecules. As long as the precursor gas can diffuse into the area, such as the bottom and sidewalls of the contact hole 500 with a large depth-to-width ratio, a uniform thin film can be formed. This is very advantageous for forming high-quality metal buffer layer 600 and electrodes on complex three-dimensional structures.

[0035] In some embodiments, the etching barrier layer 300 is formed using an atomic layer deposition process in a thermal growth mode, including: using a metal-organic compound as a first precursor gas, using water vapor or ozone as a first reactant gas, alternately introducing the first precursor gas and the first reactant gas, and conformally growing a metal oxide thin film on the surface of the two-dimensional semiconductor channel layer 200 to serve as the etching barrier layer 300.

[0036] Specifically, organometallic compounds refer to compounds containing at least one metal-carbon bond in their molecules, used as metal precursors in atomic layer deposition processes. Water vapor or ozone serves as the reactive gas with an oxygen source; water vapor is a mild oxidant, while ozone has stronger oxidizing power and higher reactivity. Metal oxide thin films refer to compound films composed of metal elements and oxygen elements, such as aluminum oxide, hafnium oxide, and titanium oxide. These films are typically dense, chemically stable, and possess good insulating properties.

[0037] In the process of forming an etch barrier layer 300, such as aluminum oxide, using an atomic layer deposition process with thermal growth mode, the substrate 100 with the two-dimensional semiconductor channel layer 200 is heated to approximately 200°C to 300°C. In the first half-cycle, trimethylaluminum is introduced as the first precursor gas. The trimethylaluminum molecules react with the hydroxyl or sulfur atoms exposed on the surface of the two-dimensional semiconductor channel layer 200, such as molybdenum disulfide, forming chemisorption. The process automatically stops after the surface is saturated, and excess trimethylaluminum is purged with an inert gas. Then, water vapor is introduced as the first reaction gas. The water vapor reacts with the chemisorbed trimethylaluminum to generate aluminum oxide and release methane. This reaction is also self-limiting. After the reaction is complete, hydroxyl groups are regenerated on the surface, preparing for the next cycle. This cycle is repeated to conformally grow the desired metal oxide film on the surface of the two-dimensional semiconductor channel layer 200.

[0038] Therefore, the metal oxide film differs from the common channel insulating layer 400 material in physical and chemical properties. In subsequent etching processes, an etchant with an extremely slow etching rate for metal oxides but a very fast etching rate for the channel insulating layer 400 can be selected. Thus, this metal oxide film can act as a perfect etch stop layer. Its presence greatly increases the process window for forming openings in the insulating layer, allowing for safe stopping above the etch stop layer 300 without precise control of the etching time, avoiding over-etching damage to the underlying two-dimensional semiconductor channel layer 200. Atomic layer deposition can directly conformally grow the etch stop layer 300 on the surface of the two-dimensional semiconductor channel layer 200, resulting in a etch stop layer 300 with a low interface state density, which is beneficial for maintaining the intrinsic properties of the channel.

[0039] In some embodiments, the metal buffer layer 600 is formed using an atomic layer deposition process in a thermal growth mode, including: using a metal-organic compound or metal halide as a second precursor gas, using a nitrogen- or carbon-containing reducing gas as a second reactant gas, alternately introducing the second precursor gas and the second reactant gas, and reducing and growing a metal thin film on the surface of the two-dimensional semiconductor channel layer 200 at the bottom of the contact hole 500 to serve as the metal buffer layer 600.

[0040] Specifically, metal halides refer to compounds formed by metals and halogen elements, such as titanium tetrachloride and tungsten hexachloride, which are used as precursors in certain metal atomic layer deposition processes. Reducing gases are substances that can donate electrons in chemical reactions, reducing other substances, such as metal ions in the precursor. For example, hydrogen can reduce metal chlorides to pure metals. Nitrogen- or carbon-containing reducing gases, such as ammonia, can act as reducing agents and provide a nitrogen source for depositing metal nitrides. Similarly, certain hydrocarbons can act as reducing agents and provide a carbon source for depositing metal carbides.

[0041] Taking the deposition of a titanium nitride metal buffer layer 600 as an example, the device structure with the contact hole 500 already formed is heated to a preset temperature, such as 300°C to 400°C. In the first half-cycle, titanium tetrachloride, as a second precursor gas, is introduced. Titanium tetrachloride molecules diffuse to the bottom of the contact hole 500 and chemically adsorb onto sulfur atoms or defect sites on the exposed two-dimensional semiconductor channel layer 200 surface. After purging, ammonia, as a second reactant gas, is introduced. On the heated substrate 100 surface, the ammonia reacts with the adsorbed titanium tetrachloride, or under specific conditions, titanium nitride is generated. The generated hydrogen chloride is a volatile byproduct and is carried away by purging. By controlling the number of cycles, the metal buffer layer 600 of the required thickness is grown layer by layer on the surface of the two-dimensional semiconductor channel layer 200.

[0042] Therefore, the metal thin film grown via thermal reduction reaction can form strong chemical bonds between its metal atoms and the chalcogen atoms on the surface of the two-dimensional semiconductor channel layer 200, replacing or bridging the dangling bonds on the surface, thereby effectively reducing the Schottky barrier at the metal-semiconductor interface and achieving lower contact resistance. Compared to the high-energy particle bombardment and impurity embedding caused by physical vapor deposition, the atomic layer deposition reduction growth process is more gentle. The precursor and reactant gases react under thermal drive, and the byproducts are all gaseous and are swept away, resulting in an atomically clean contact interface.

[0043] In some embodiments, such as Figure 7 As shown, the selective etching process for removing the etch barrier layer 300 exposed by the opening includes: removing the etch barrier layer exposed by the opening using one of inductively coupled plasma etching, wet etching, or atomic layer etching; wherein, the atomic layer etching process includes peeling off the etch barrier layer 300 atomically by alternating the introduction of chemically modified gas and inert bombardment gas until the surface of the bottom two-dimensional semiconductor channel layer 200 is exposed to form a contact hole 500.

[0044] Specifically, inductively coupled plasma etching (ICP-E) refers to anisotropic etching using high-density plasma generated by an inductive coil. It allows for highly selective etching of specific materials by adjusting process parameters. Wet etching, on the other hand, is isotropic, using liquid chemical reagents to react with the material to be etched, dissolving and removing it. Atomic layer etching (ALT) works on the opposite principle to atomic layer deposition (ALD), alternating between surface modification and removal steps. Each cycle removes only one atomic layer of material, achieving atomic-level precision control over the etching thickness. Chemically modified gas is introduced in the first half-cycle of ALT, reacting with the surface of the material to be etched to transform it into a new surface layer with lower volatility or different properties. Inert bombardment gas, introduced in the second half-cycle of ALT with RF bias, utilizes the physical bombardment of high-energy inert gas ions to sputter away the chemically modified surface layer from the first step.

[0045] When removing the etch barrier layer 300, atomic layer etching (ALT) can be used. The device is placed in an ALT reaction chamber. The first step involves introducing a chemically modified gas; for example, chlorine-containing gas can be used for the alumina etch barrier layer 300. The two react to generate volatile substances, but this reaction typically occurs only on the outermost layer, forming a thin aluminum chloride modified layer, without continuing the reaction inwards. The second step involves purging with an inert gas, followed by the introduction of an inert bombardment gas and the application of a directional radio frequency bias. High-energy argon ions are then directed to bombard the surface of the substrate 100, with their energy precisely controlled to break and sputter away the chemically modified aluminum chloride molecular layer, while having almost no etching effect on the underlying unmodified alumina layer. After each modification cycle, one atomic layer of alumina is precisely removed from the surface. This cycle continues until the etch barrier layer 300 is completely removed, exposing the underlying two-dimensional semiconductor channel layer 200.

[0046] In some embodiments, combined with Figure 8 and Figure 9 The metal buffer layer 600, which is deposited within the contact hole 500 and covers at least the bottom of the contact hole 500, is formed by depositing a metal buffer layer 600 within the contact hole 500 that simultaneously covers the bottom and sidewalls of the contact hole 500.

[0047] Specifically, the sidewall of the contact hole 500 refers to the vertical or inclined inner wall of the contact hole 500 formed in the channel insulating layer 400. Simultaneous coverage refers to the fact that the metal buffer layer 600, during the deposition process, is deposited not only on the exposed surface of the two-dimensional semiconductor channel layer 200 but also uniformly deposited on the insulating dielectric sidewall of the contact hole 500. When forming the metal buffer layer 600 using an atomic layer deposition process with thermal growth mode, the precursor gas transport depends on diffusion rather than directionality, allowing the precursor gas to reach and adsorb onto the sidewall surface of the contact hole 500. In subsequent reactive gas pulses, the precursor molecules on the sidewall also participate in the reaction, growing a metal thin film. Therefore, by controlling the number of atomic layer deposition cycles, a uniformly thick metal buffer layer 600 can be conformally and simultaneously grown on the bottom and sidewall of the contact hole 500.

[0048] Therefore, the subsequently formed source / drain electrodes 700 fill the contact holes 500, with the main contact surface being the metal buffer layer 600. If the metal buffer layer 600 only covers the bottom, the sides of the source / drain electrodes 700 will directly contact the channel insulating layer 400, resulting in limited adhesion. In this embodiment of the invention, the metal buffer layer 600 covers both the bottom and sidewalls, effectively providing a liner for the subsequently deposited source / drain metal, significantly increasing the contact area and adhesion between the electrode and the underlying structure, preventing electrode peeling during subsequent processes or use. The metal buffer layer 600 covering the sidewalls can serve as a seed layer for the subsequent main metal layer on the sidewalls, ensuring uniform and continuous growth of the main metal layer on the sidewalls, avoiding current congestion or open-circuit risks caused by discontinuous sidewall metal. Simultaneously, this metal buffer layer 600 also acts as a diffusion barrier layer, preventing metal atoms in the subsequent source / drain electrodes 700 from laterally diffusing into the channel insulating layer 400 during subsequent thermal annealing, thus improving the stability and reliability of the device.

[0049] In some embodiments, after removing the etch barrier layer 300 and before depositing the metal buffer layer 600, the method further includes: performing in-situ defect repair treatment on the exposed surface of the two-dimensional semiconductor channel layer 200; wherein the in-situ defect repair treatment includes in-situ thermal annealing by introducing a sulfur-based gas or a mixture of hydrogen and argon into the atomic layer deposition reaction chamber.

[0050] Specifically, in-situ defect repair refers to a thermal treatment process performed on the exposed two-dimensional semiconductor surface, without breaking the vacuum, within the same reaction chamber as the subsequent 600 metal buffer layer deposition process, aimed at eliminating or reducing internal or surface defects. Sulfur-based gases refer to gaseous compounds containing sulfur, such as hydrogen sulfide or organic sulfur compounds, used to provide sulfur atoms for sulfur vacancy defects. A mixture of hydrogen and argon refers to a reducing annealing atmosphere; hydrogen can reduce surface oxides or adsorb impurities, while argon serves as a dilution gas and heat transfer medium.

[0051] Even after selectively removing the etch barrier layer 300, some atomic-scale defects may still inevitably form on the surface of the two-dimensional semiconductor channel layer 200, even with a very mild process. The most common of these are sulfur vacancies, which can become recombination or scattering centers for charge carriers, pinning the Fermi level and significantly increasing contact resistance. In this embodiment of the invention, in-situ repair is performed in a high-vacuum atomic layer deposition chamber before depositing the metal buffer layer 600. If a sulfur-based gas is introduced at a temperature of 200°C to 300°C, the generated active sulfur atoms can diffuse and fill the sulfur vacancies on the two-dimensional semiconductor surface, thereby repairing lattice defects. If a mixture of hydrogen and argon is introduced, at high temperatures, hydrogen can reduce adsorbed oxygen or oxygen-containing groups on the surface, and argon bombardment can physically remove weakly adsorbed impurities. Simultaneously, the thermal annealing process itself can promote the migration and rearrangement of surface atoms, optimizing the lattice.

[0052] Therefore, by repairing these defects in situ before metal deposition, this invention can maximize the recovery of the intrinsic electronic structure of the two-dimensional semiconductor and reduce the contact resistance of the metal-semiconductor interface. In-situ treatment avoids sample exposure to air, preventing recontamination and oxidation of the fresh surface by moisture and oxygen, and seamlessly integrates with subsequent metal buffer layer 600 deposition, ensuring an atomically clean, low-defect contact interface. This process can be completed within an atomic layer deposition chamber without the need for additional specialized equipment, improving production efficiency and reducing the risk of contamination.

[0053] In some embodiments, combined with Figure 8 and Figure 9 A metal buffer layer 600 is deposited within the contact hole 500, including: by dynamically changing the process parameters during the layer-by-layer growth process, thin films with different component ratios are deposited layer by layer, so that the metal buffer layer 600 formed exhibits a component distribution in the thickness direction that gradually increases the content of non-metallic elements from the interface near the two-dimensional semiconductor channel layer 200 to the surface.

[0054] Specifically, dynamically changing process parameters means that during the atomic layer deposition of the metal buffer layer 600, the same deposition formulation, such as precursor pulse time, reactive gas type, and deposition temperature, is not always used. Instead, these parameters are adjusted purposefully and systematically at different deposition stages. Component ratio refers to the atomic proportions between constituent elements in non-stoichiometric compound films. For example, for titanium nitride, the component ratio could be titanium-rich TiN0.8, standard stoichiometric TiN, or nitrogen-rich TiN1.2. Component distribution refers to the variation of elemental composition in the film along its thickness. As the non-metallic element content gradually increases, assuming the metal buffer layer 600 is composed of titanium and nitrogen, near the interface of the two-dimensional semiconductor channel layer 200, the composition of the metal buffer layer 600 is titanium-rich. As the film grows, the relative amount of nitrogen precursor gradually increases, causing the nitrogen content in the film to gradually increase. When it reaches the surface of the metal buffer layer 600, its composition becomes nitrogen-rich.

[0055] Therefore, the titanium-rich titanium nitride region near the two-dimensional semiconductor channel layer 200 has a lower work function, which is beneficial for forming a smaller Schottky barrier with the two-dimensional semiconductor, thereby significantly reducing contact resistance. Furthermore, the nitrogen-rich titanium nitride region near the surface is chemically more stable, has stronger oxidation resistance, and provides better lattice matching and adhesion for subsequent source / drain host metal layers. The compositional gradient change can form a buffer region, reducing the stress generated at the metal-semiconductor interface due to lattice constant differences, improving interface stability, and preventing film delamination.

[0056] In some embodiments, combined with Figure 8 and Figure 9 The metal buffer layer 600 is formed using a thermal growth atomic layer deposition process. After the metal buffer layer 600 is deposited and before the source / drain electrodes 700 are formed, the process also includes: controlling and reducing the pressure in the atomic layer deposition reaction chamber and extending the residence time of the precursor, and using a thermal growth atomic layer deposition process to additionally deposit a dense homogeneous metal protective film at the sidewall steps of the contact hole 500.

[0057] Specifically, residence time refers to the time the precursor gas remains in the reaction chamber after being introduced and before the purging step begins. A longer residence time allows gas molecules to penetrate more fully into high aspect ratio structures, such as every corner of a step. Sidewall steps refer to the corner areas between the bottom and sidewalls of the contact hole 500, and between the sidewalls and the top surface. These areas are prone to incomplete coverage or low film density during film deposition due to geometric shielding effects. The dense homogeneous metal protective film refers to an additional film made of the same material as the metal buffer layer 600, but with optimized physical properties specifically designed to enhance the coverage and protection of weak areas such as steps, resulting in higher density and a more compact structure.

[0058] After the main deposition of the metal buffer layer 600 is completed, the process does not end immediately. Instead, the chamber pressure is controlled at a low level. At lower pressure, the mean free path of gas molecules increases, reducing intermolecular collisions and allowing precursor molecules to move more easily in straight or near-straight lines. However, when traversing complex three-dimensional structures, simple straight-line movement is not conducive to reaching shaded areas, such as the sidewalls of steps. Therefore, this embodiment of the invention also extends the residence time of the precursor gas. Under the combined effect of low pressure and long residence time, gas molecules have more time to diffuse rather than flow, using thermal motion to reach the sidewalls and corners of the steps, followed by several additional atomic layer deposition cycles. Since there may be more exposed active sites at the steps, and the surface reaction mode under low pressure and long residence time tends to fill micropores, the additional films deposited in these areas will be denser, effectively passivating these geometrically weak points.

[0059] Therefore, by optimizing deposition conditions, this embodiment of the invention reinforces the weakest areas with a dense homogeneous protective film, ensuring the integrity and continuity of the metal buffer layer 600 within the entire contact hole 500. This eliminates the risk of device failure due to metal fracture at the step, significantly improving process yield. The step is a potential fast path for subsequent metal atoms or external impurity atoms to diffuse into the channel region. Depositing an additional, denser homogeneous metal film at the step effectively thickens and densifies the weakest link in the diffusion barrier, further improving the long-term reliability of the device.

[0060] In some embodiments, forming the source / drain electrode 700 includes: depositing the source / drain electrode 700 using a plasma-enhanced atomic layer deposition process; wherein, during the plasma excitation stage of the plasma-enhanced atomic layer deposition process, a radio frequency bias voltage is controlled to enhance the directionality of plasma active species and improve the uniformity of metal coverage at the bottom and sidewall steps of the contact hole 500.

[0061] Specifically, plasma-enhanced atomic layer deposition (PALD) refers to the process of exciting reactive gases into plasma using a radio frequency (RF) or microwave power source during the reactant pulse phase. This generates highly reactive free radicals and ions, which can react with precursors, thereby lowering the deposition temperature or expanding the range of depositable materials. RF bias refers to an alternating voltage applied to the stage or electrode supporting the substrate. This voltage creates an electric field near the substrate surface, guiding ions in the plasma to bombard the substrate surface with specific energy and direction. Directionality refers to the tendency of ions in the plasma, under the influence of the electric field, to no longer diffuse isotropically but rather to impact the substrate surface perpendicularly along the electric field lines.

[0062] When forming a thick source / drain electrode 700 using plasma-enhanced atomic layer deposition (PEALD), more intense reaction conditions are required to increase the deposition rate. Simultaneously with the plasma excitation phase, an radio frequency bias is applied to the lower electrode supporting the substrate. This bias creates a DC bias electric field within the plasma sheath on the substrate surface. Positively charged ions are accelerated by this electric field and bombard the growing film surface with high energy and a near-vertical direction. This directional ion bombardment serves two purposes: first, it physically compacts the porous film, increasing its density; second, it sputters away unreacted precursors from overhanging structures formed at the top of the sidewalls or from dead zones at the bottom, or directly bombards active species to the bottom and deep sides of the contact hole 500, thereby achieving uniform coverage on the complex three-dimensional structure.

[0063] In some embodiments, such as Figure 9 As shown, after forming the source / drain electrodes 700, the process further includes: performing a rapid thermal annealing process on the two-dimensional semiconductor device under a non-oxidizing protective atmosphere; wherein the temperature of the rapid thermal annealing process is lower than the critical temperature at which the two-dimensional semiconductor channel layer 200 undergoes a phase transition or decomposition, so as to drive the metal atoms at the bottom of the metal buffer layer 600 to form bonds with the surface atoms of the two-dimensional semiconductor channel layer 200.

[0064] Specifically, a non-oxidizing protective atmosphere refers to a gaseous environment free of oxygen or oxidizing substances, introduced during the annealing process to protect the device from oxidation. Examples include high-purity nitrogen, argon, or a hydrogen-argon mixture. Rapid thermal annealing uses high-power lamps or resistance heating to heat the wafer to a set temperature at an extremely rapid rate, hold it for a very short time, and then rapidly cool it. For certain two-dimensional semiconductor materials, there is a temperature threshold; exceeding the critical temperature for phase transition or decomposition causes irreversible changes in the crystal structure. Bond formation refers to the formation of stronger chemical bonds between atoms in the metal buffer layer 600 and the surface atoms of the two-dimensional semiconductor channel layer 200, through the energy provided by thermal annealing, replacing or strengthening the original physical contacts or weak chemical bonds.

[0065] After the deposition of all source and drain electrodes 700 is completed, the device is placed in a rapid thermal annealing apparatus and purged with a non-oxidizing protective atmosphere. The temperature is then rapidly increased to a pre-selected temperature, such as 350°C, at a rate of, for example, 50°C / s. This temperature, determined experimentally, is below the temperature at which molybdenum disulfide undergoes significant decomposition. This brief high-temperature process provides sufficient diffusion and reaction activation energy to the atoms at the bottom of the metal buffer layer 600 and the surface of the two-dimensional semiconductor channel layer 200. Normally, in the room-temperature deposition state, metal atoms might form weak van der Waals forces or unbonded contacts with the channel surface atoms. After thermal annealing, the metal atoms gain kinetic energy and can enter or replace shallow lattice sites, forming stronger covalent or ionic bonds with chalcogenides. The device is then rapidly cooled, freezing these bonds.

[0066] Therefore, in this embodiment of the invention, through a rapid thermal annealing process, stronger chemical bonds are formed between metal atoms and semiconductor surface atoms. This not only significantly reduces the barrier height at the interface but also provides a more ordered transition layer with fewer defects, thereby significantly reducing contact resistance. By selecting a rapid thermal annealing process and controlling the temperature below the critical temperature, interface bonding optimization can be achieved while avoiding damage to the overall structure of the ultrathin two-dimensional semiconductor channel layer 200. Rapid heating and cooling reduce the total exposure time of the material at high temperatures.

[0067] In some embodiments, the material constituting the two-dimensional semiconductor channel layer 200 includes a transition metal chalcogenide semiconductor material, the material constituting the metal buffer layer 600 includes at least one of titanium nitride, tantalum nitride, titanium, nickel, and platinum, and the material constituting the etch barrier layer 300 includes a metal oxide material; the thickness of the etch barrier layer 300 ranges from 1 nm to 10 nm, the thickness of the metal buffer layer 600 ranges from 1 nm to 5 nm, and the thickness of the source / drain electrodes 700 ranges from 5 nm to 15 nm.

[0068] Specifically, transition metal chalcogenide semiconductor materials refer to compounds composed of transition metals, such as molybdenum and tungsten, and chalcogen elements, such as sulfur, selenium, and tellurium, for example, molybdenum disulfide and tungsten diselenide. The two-dimensional semiconductor channel layer 200 is selected from transition metal chalcogenide semiconductor materials because they possess excellent properties such as atomically flat surfaces, no dangling bonds, tunable band gaps, and high carrier mobility. The metal buffer layer 600 is selected from the listed materials because they have suitable work functions, good conductivity, strong adhesion, and the potential to act as diffusion barrier layers. The etch barrier layer 300 is selected from metal oxides, such as alumina, because they are dense, can be selectively etched, and are highly compatible with atomic layer deposition processes. If the etch barrier layer 300 is too thin, it may not effectively block etching; if it is too thick, it will increase the difficulty of subsequent selective etching. The thickness of the metal buffer layer 600 is between 1 nm and 5 nm to ensure that while fulfilling its interface modification and barrier functions, an excessively thick interface layer does not become an additional obstacle to carrier transport. The source and drain electrodes 700 have a thickness between 5nm and 15nm, ensuring sufficiently low resistance and good current carrying capacity.

[0069] This invention also provides a two-dimensional semiconductor device, which is fabricated using the fabrication method for two-dimensional semiconductor devices described in the foregoing embodiments. Therefore, it possesses the beneficial effects described in the foregoing embodiments, which will not be repeated here. Exemplarily, a two-dimensional semiconductor device refers to an electronic device manufactured using a two-dimensional semiconductor material as the core channel region, such as a field-effect transistor (FET) or logic circuit. Regarding FETs, in addition to the structure described in the foregoing embodiments, the gate of the FET can be located below or above the two-dimensional semiconductor channel layer 200; this invention does not specifically limit this.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a two-dimensional semiconductor device, characterized in that, include: A substrate is provided, and a two-dimensional semiconductor channel layer, an etch barrier layer, and a channel insulating layer are sequentially formed on the surface of the substrate; The channel insulating layer is patterned to form an opening that exposes a portion of the etch barrier layer; A selective etching process is used to remove the etch barrier layer exposed by the opening until the surface of the bottom two-dimensional semiconductor channel layer is exposed to form a contact hole; A metal buffer layer is deposited within the contact hole to at least cover the bottom of the contact hole; wherein the etching barrier layer and / or the metal buffer layer are formed using an atomic layer deposition process with thermal growth mode; Source and drain electrodes are formed on the metal buffer layer within the contact hole.

2. The method for fabricating a two-dimensional semiconductor device according to claim 1, characterized in that, Atomic layer deposition processes employing thermal growth include: In a purely thermally driven environment without plasma participation, the structure to be deposited is heated to a preset reaction temperature; Precursor gas and reactant gas are alternately introduced, and thin films are deposited layer by layer by utilizing the self-limiting chemical reaction between the precursor gas and the reactant gas on the substrate surface to form the corresponding film layer.

3. The method for fabricating a two-dimensional semiconductor device according to claim 2, characterized in that, The etching barrier layer is formed using a thermal growth mode atomic layer deposition process, including: A metal-organic compound is used as the first precursor gas, and water vapor or ozone is used as the first reactant gas. The first precursor gas and the first reactant gas are alternately introduced to conformally grow a metal oxide film on the surface of the two-dimensional semiconductor channel layer as the etching barrier layer.

4. The method for fabricating a two-dimensional semiconductor device according to claim 2, characterized in that, The metal buffer layer is formed using an atomic layer deposition process with thermal growth mode, including: A metal thin film is grown by reduction on the surface of the two-dimensional semiconductor channel layer at the bottom of the contact hole, using a metal-organic compound or metal halide as the second precursor gas and a nitrogen- or carbon-containing reducing gas as the second reactant gas.

5. The method for fabricating a two-dimensional semiconductor device according to any one of claims 1-4, characterized in that, The selective etching process is used to remove the etch barrier layer exposed by the opening, including: The etching barrier layer exposed by the opening is removed by one of the following processes: inductively coupled plasma etching, wet etching, or atomic layer etching; wherein the atomic layer etching process includes peeling off the etching barrier layer atomically by alternating the introduction of chemically modified gas and inert bombardment gas until the surface of the bottom two-dimensional semiconductor channel layer is exposed to form a contact hole.

6. The method for fabricating a two-dimensional semiconductor device according to any one of claims 1-4, characterized in that, A metal buffer layer is deposited within the contact hole to at least cover the bottom of the contact hole, comprising: A metal buffer layer is deposited within the contact hole to simultaneously cover the bottom and sidewalls of the contact hole.

7. The method for fabricating a two-dimensional semiconductor device according to any one of claims 1-4, characterized in that, Forming the source and drain electrodes includes: The source and drain electrodes are deposited using a plasma-enhanced atomic layer deposition process. In the plasma excitation stage of the plasma-enhanced atomic layer deposition process, a radio frequency bias voltage is applied to enhance the directionality of plasma active species and improve the uniformity of metal coverage at the bottom and sidewall steps of the contact hole.

8. The method for fabricating a two-dimensional semiconductor device according to any one of claims 1-4, characterized in that, After forming the source and drain electrodes, the method further includes: A rapid thermal annealing process is performed on the two-dimensional semiconductor device under a non-oxidizing protective atmosphere; wherein the temperature of the rapid thermal annealing process is lower than the critical temperature at which the two-dimensional semiconductor channel layer undergoes a phase transition or decomposition, so as to drive the metal atoms at the bottom of the metal buffer layer to form bonds with the surface atoms of the two-dimensional semiconductor channel layer.

9. The method for fabricating a two-dimensional semiconductor device according to any one of claims 1-4, characterized in that, The material constituting the two-dimensional semiconductor channel layer includes a transition metal chalcogenide semiconductor material; the material constituting the metal buffer layer includes at least one of titanium nitride, tantalum nitride, titanium, nickel, and platinum; and the material constituting the etch barrier layer includes a metal oxide material. The thickness of the etching barrier layer ranges from 1 nm to 10 nm, the thickness of the metal buffer layer ranges from 1 nm to 5 nm, and the thickness of the source / drain electrodes ranges from 5 nm to 15 nm.

10. A two-dimensional semiconductor device, characterized in that, It is prepared by the fabrication method of the two-dimensional semiconductor device as described in any one of claims 1-9.

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