Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The method comprises the following steps: forming a bottom structure; forming a gate structure on a part of the upper surface of the bottom structure; forming a dielectric layer structure on the bottom structure, the dielectric layer structure covering the gate structure; forming a field plate on the dielectric layer structure; forming a first etching stop layer on the field plate; forming a source structure and a drain structure on both sides of the gate structure respectively; forming an interlayer dielectric layer on the dielectric layer structure, the interlayer dielectric layer covering the field plate and the first etching stop layer; etching the interlayer dielectric layer to form a source contact hole, a gate contact hole, a drain contact hole and at least one field plate contact hole in the interlayer dielectric layer by using one mask, and the field plate contact hole stops on the upper surface of the first etching stop layer to avoid over-etching of the field plate caused by etching when the field plate contact hole is formed.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its manufacturing method. Background Technology

[0002] In semiconductor devices, field plates are used to adjust the electric field in the channel region, making the electric field more uniform, avoiding excessive electric field strength, and improving the breakdown voltage of the semiconductor device. Typically, when designing a field plate (FP), one or more field plates are designed between the gate and drain as needed. The height distance of these field plates from the 2DGE (Diode Edge Gear) varies depending on the electric field distribution. Field plate contact holes are formed on these field plates at different heights to connect to the source or gate for potential control. When forming these field plate contact holes, since the selectivity of the interlayer dielectric layer etching the field plate metal is no greater than 5, multiple etching processes using multiple photomasks are usually used to create field plate contact holes of different depths. This is to avoid over-etching of the field plate if etching is not stopped in time when forming multiple field plate contact holes of different depths, which could lead to open circuits. Using multiple photomasks for multiple etching processes to form multiple contact holes of different depths significantly increases manufacturing costs. Summary of the Invention

[0003] This application provides a semiconductor device and a method for manufacturing the same, to avoid the risk of open circuits caused by over-etching of the field plate during the formation of field plate contact holes.

[0004] In a first aspect, this application provides a method for manufacturing a semiconductor device, the method comprising: forming an underlying structure; forming a gate structure on a portion of the upper surface of the underlying structure; forming a dielectric layer structure on the underlying structure, the dielectric layer structure covering the gate structure; forming a field plate on the dielectric layer structure; forming a first etch stop layer on the field plate; forming a source structure and a drain structure on opposite sides of the gate structure, wherein the field plate is located between the gate structure and the drain structure; forming an interlayer dielectric layer on the dielectric layer structure, the interlayer dielectric layer covering the field plate, the first etch stop layer, and the source and drain structures; using a photomask, etching the interlayer dielectric layer to form a source contact hole, a gate contact hole, a drain contact hole, and at least one field plate contact hole therein, the field plate contact hole stopping at the upper surface of the first etch stop layer, wherein the etch selectivity ratio between the first etch stop layer and the interlayer dielectric layer is not less than 40.

[0005] Preferably, the method for forming the underlying structure includes: forming a substrate; forming a channel layer above the substrate; and forming a barrier layer on the channel layer, wherein the channel layer and the barrier layer comprise group III nitrides.

[0006] Preferably, the method for forming a gate structure on a portion of the upper surface of the underlying structure includes: forming a pGaN layer on the barrier layer, forming a gate metal layer on the pGaN layer, forming a hard mask in a predetermined region of the gate metal layer, and etching the pGaN layer and the gate metal layer using the hard mask as a mask to form the gate structure.

[0007] Preferably, the method of forming a dielectric layer structure on the underlying structure includes: forming a first dielectric layer to cover the exposed upper surface of the underlying structure, and encapsulating the gate structure.

[0008] Preferably, the method for forming a dielectric layer structure on the underlying structure includes: forming a first dielectric layer to cover the exposed upper surface of the underlying structure and to encapsulate the gate structure; forming a second etch stop layer on the first dielectric layer; forming a second dielectric layer on the second etch stop layer; defining a first etch window; and patterning the second dielectric layer to form a first opening in the exposed portion of the second etch stop layer; wherein the first opening is located between the gate structure and the drain structure, and the etch selectivity ratio between the second etch stop layer and the second dielectric layer is not less than 5.

[0009] Preferably, the method for forming the first opening further includes: defining a first etching window, and patterning the second dielectric layer and the second etching barrier layer to form a first opening in the exposed portion of the first dielectric layer.

[0010] Preferably, the method for forming a dielectric layer structure on the underlying structure includes: forming a first dielectric layer to cover the exposed upper surface of the underlying structure and to encapsulate the gate structure; forming a second etch stop layer on the first dielectric layer; forming a second dielectric layer on the second etch stop layer; forming a third dielectric layer on the second dielectric layer; defining a second etch window; patterning the third dielectric layer to form a second opening of the exposed portion of the second dielectric layer; defining a third etch window; patterning the second dielectric layer to form a third opening of the exposed portion of the second etch stop layer; wherein the second opening and the third opening are both located between the gate structure and the drain structure; the width of the second opening is greater than the width of the third opening, and the projection of the second opening on the underlying structure completely covers the projection of the third opening on the underlying structure; the etch selectivity ratio between the third dielectric layer and the second dielectric layer is not less than 5.

[0011] Preferably, the exposed second etch barrier layer or the exposed first dielectric layer, together with the exposed second dielectric layer and the third dielectric layer remaining after etching, form a stepped structure between the gate structure and the drain structure.

[0012] Preferably, the method of forming a field plate on the dielectric layer structure and forming a first etch barrier layer on the field plate includes: forming a field plate metal layer on the dielectric layer structure, forming a first etch barrier layer on the field plate metal layer, and using the same mask to pattern-etch the first etch barrier layer and the field plate metal layer to retain the field plate metal layer and the first etch barrier layer located between the gate structure and the drain structure, wherein the retained field plate metal layer and the first etch barrier layer are located on the stepped structure.

[0013] Preferably, when the number of field plate contact holes is greater than or equal to 2, the plurality of field plate contact holes extend downward from the upper surface of the interlayer dielectric layer to the upper surface of the first etching barrier layer at at least two different heights.

[0014] Preferably, the source contact hole extends downward from the upper surface of the interlayer dielectric layer to the source structure, the drain contact hole extends downward from the upper surface of the interlayer dielectric layer to the drain structure, and the gate contact hole extends downward from the upper surface of the interlayer dielectric layer to the gate structure.

[0015] Preferably, the method further includes: depositing a conductive material in the contact hole to form a conductive plug.

[0016] Preferably, before depositing conductive material in the field plate contact hole to form a field plate conductive plug, the method further includes: removing a first etch barrier layer in the field plate contact hole, so that the field plate conductive plug contacts the field plate.

[0017] Preferably, the method further includes: forming a plurality of metal connection layers on the interlayer dielectric layer, wherein a first metal connection layer is electrically connected to the upper surface of the source conductive plug, a second metal connection layer is electrically connected to the upper surface of the gate conductive plug, a third metal connection layer is electrically connected to the upper surface of the at least two field plate conductive plugs, and a fourth metal connection layer is electrically connected to the drain conductive plug.

[0018] Secondly, this application provides a semiconductor device, comprising: an underlying structure; a gate structure located on the upper surface of a portion of the underlying structure, and a source structure and a drain structure located on both sides of the gate structure; a dielectric layer structure located on the upper surface of the underlying structure, the dielectric layer structure covering the gate structure; a field plate located on the dielectric layer structure; a first etch stop layer located on the field plate, wherein the field plate is located between the gate structure and the drain structure; an interlayer dielectric layer located on the dielectric layer structure, the interlayer dielectric layer covering the field plate, the first etch stop layer, and the source structure and drain structure, and further comprising a source contact hole, a gate contact hole, a drain contact hole, and at least one field plate contact hole located within the interlayer dielectric layer, the field plate contact hole extending downward from the upper surface of the interlayer dielectric layer to the upper surface of the first etch stop layer, wherein the etch selectivity ratio between the first etch stop layer and the interlayer dielectric layer is not less than 40.

[0019] Preferably, the material of the first etching barrier layer is Al2O3.

[0020] Preferably, the material of the interlayer medium includes at least one of SiN or SiO2.

[0021] Preferably, the dielectric layer structure includes:

[0022] A first dielectric layer is located on the upper surface of the underlying structure, and the first dielectric layer covers the gate structure.

[0023] Preferably, the dielectric layer structure includes: a first dielectric layer located on the upper surface of the underlying structure, the first dielectric layer covering the gate structure; a second etch stop layer located on the first dielectric layer; and a second dielectric layer located on the second etch stop layer; wherein the second dielectric layer includes a first opening in the second etch stop layer for exposing a portion, the first opening being located between the gate structure and the drain structure, and wherein the etch selectivity ratio between the second etch stop layer and the second dielectric layer is not less than 5.

[0024] Preferably, the second dielectric layer includes a first opening in the first dielectric layer for exposing a portion of the first dielectric layer, the first opening being located between the gate structure and the drain structure.

[0025] Preferably, the dielectric layer structure includes: a first dielectric layer located on the upper surface of the underlying structure, the first dielectric layer covering the gate structure; a second etch stop layer located on the first dielectric layer; a second dielectric layer located on the second etch stop layer; and a third dielectric layer located on the second dielectric layer, wherein the third dielectric layer includes a second opening for exposing a portion of the second dielectric layer, the second dielectric layer includes a third opening for exposing a portion of the second etch stop layer, both the second opening and the third opening are located between the gate structure and the drain structure, the width of the second opening is greater than the width of the third opening, and the projection of the second opening on the underlying structure completely covers the projection of the third opening on the underlying structure, and the etch selectivity ratio between the third dielectric layer and the second dielectric layer is not less than 5.

[0026] Preferably, the exposed second etch barrier layer or the exposed first dielectric layer, together with the exposed second dielectric layer and the remaining third dielectric layer, form a stepped structure between the gate structure and the drain structure.

[0027] Preferably, the field plate metal layer located on the upper surface of the stepped structure is configured as the field plate.

[0028] Preferably, when the number of field plate contact holes is greater than or equal to 2, the plurality of field plate contact holes extend downward from the upper surface of the interlayer dielectric layer to the upper surface of the first etching barrier layer at at least two different heights.

[0029] Preferably, the source contact hole extends downward from the upper surface of the interlayer dielectric layer to the source structure, the drain contact hole extends downward from the upper surface of the interlayer dielectric layer to the drain structure, and the gate contact hole extends vertically downward from the upper surface of the interlayer dielectric layer to the gate structure.

[0030] Preferably, the device further includes a conductive plug located within the contact hole.

[0031] Preferably, the conductive plug of the field plate is in contact with the field plate.

[0032] Preferably, the semiconductor device further includes: a plurality of metal interconnect layers located on the interlayer dielectric layer, wherein the first metal interconnect layer is electrically connected to the upper surface of the source conductive plug, the second metal interconnect layer is electrically connected to the upper surface of the gate conductive plug, the third metal interconnect layer is electrically connected to the upper surface of the at least two field plate conductive plugs, and the fourth metal interconnect layer is electrically connected to the upper surface of the drain conductive plug.

[0033] This invention provides a semiconductor device and its fabrication method. The semiconductor device includes a field plate located between the gate structure and the drain structure, and a first etch barrier layer located on the field plate. The field plate effectively regulates and homogenizes the lateral electric field distribution, thereby significantly improving the device's withstand voltage capability. Since the etch selectivity ratio between the first etch barrier layer and the interlayer dielectric layer is not less than 40, when forming field plate contact holes, the field plate contact holes can accurately stop on the first etch barrier layer, thereby avoiding over-etching of the field plate. In addition, when multiple field plate contact holes of different depths are etched in the same illumination step, costs can be greatly reduced. Furthermore, when the field plate structure is a continuous field plate that rises in a stepped manner from the gate structure to the drain structure, if multiple field plate contact holes are formed on the stepped field plate, and the depths of the multiple field plate contact holes are inconsistent, due to the presence of the first etch barrier layer, the field plate contact holes of different depths can be precisely controlled to stop on the first etch barrier layer on the upper surface of the field plate, so that the field plate will not be over-etched, let alone etched through the field plate, so that the field plate remains intact, thereby ensuring that the field plate accurately controls the carriers of the channel layer below it. Attached Figure Description

[0034] The above and other objects, features, and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0035] Figures 1 to 8 This is a cross-sectional view of each stage of a method for manufacturing a semiconductor device according to one embodiment of this application.

[0036] Figures 9 to 15 This is a cross-sectional view of a portion of a method for manufacturing a semiconductor device according to one embodiment of this application. Detailed Implementation

[0037] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0038] Those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

[0039] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0040] Those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

[0041] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0042] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0043] First aspect:

[0044] This embodiment provides a semiconductor device, such as Figure 8 As shown. The semiconductor device includes: an underlying structure 10;

[0045] The gate structure 13 is located on the upper surface of the bottom structure 10, and the source structure 14 and drain structure 15 are located on both sides of the gate structure.

[0046] A dielectric layer structure located on the upper surface of the bottom structure 10, the dielectric layer structure covering the gate structure 13;

[0047] A field plate 21 located on the dielectric layer structure,

[0048] A first etch barrier layer 22 is located on the field plate 21, wherein the field plate 21 is located between the gate structure 13 and the drain structure 15;

[0049] An interlayer dielectric layer 25 is located on the dielectric layer structure, and the interlayer dielectric layer 25 covers the field plate 21, the first etch barrier layer 22, the source structure 14, and the drain structure 15.

[0050] It also includes source contact holes, gate contact holes, drain holes, and at least one field plate contact hole located within the interlayer dielectric layer 25, wherein the field plate contact hole extends downward from the upper surface of the interlayer dielectric layer 25 to the upper surface of the first etch barrier layer 22.

[0051] The etching selectivity ratio between the first etching barrier layer 22 and the interlayer dielectric layer 25 is not less than 40.

[0052] As an example, the semiconductor device is configured as a HEMT device, and the underlying structure 10 includes at least a semiconductor substrate 100, a channel layer 102 above the semiconductor substrate 100, and a barrier layer 103 on the upper surface of the channel layer 102. The channel layer 102 and the barrier layer 103 are preferably made of group III nitride materials, and the bandgap of the barrier layer 103 is larger than the bandgap of the channel layer 102. A two-dimensional electron gas (2DEG) 104 is formed at the interface between the channel layer 102 and the barrier layer 103. For example, when the underlying structure 10 is a GaN-based HEMT device thin film structure, forming a GaN-based HEMT device, the channel layer 102 is preferably a GaN channel layer, and the barrier layer 103 is preferably an AlGaN barrier layer. In an optional embodiment, the underlying structure 10 further includes a buffer layer 101 located between the semiconductor substrate 100 and the channel layer 102. The buffer layer 101 is used to release the stress caused by lattice mismatch and thermal mismatch between the epitaxially grown heterostructure and the semiconductor substrate layer 100.

[0053] As an example, such as Figure 8 As shown, a gate structure 13 is located on the upper surface of a portion of the underlying structure 10. The gate structure 13 includes a pGaN layer 130 on the barrier layer 103 and a gate metal layer 131 on the pGaN layer 130. Since the pGaN layer 130 is used to deplete the two-dimensional electron gas (2DEG) 104 located below it, the two-dimensional electron gas (2DEG) 104 formed at the interface between the channel layer 102 and the barrier layer 103 is disconnected below the gate structure 13. The gate metal layer 131 can be made of existing materials suitable for use as gate metal layers in HEMT devices, such as TiN or a Ni / Au stack. In some embodiments, the width of the pGaN layer 130 is greater than the width of the gate metal layer 131, that is, the projection of the gate metal layer 131 onto the underlying structure 10 is located within the area defined by the projection of the pGaN layer 130 onto the underlying structure 10. In this embodiment, the width of the pGaN layer 130 is equal to the width of the gate metal layer 131, that is, the projection of the gate metal layer 131 on the underlying structure coincides with the projection of the pGaN layer 130 on the underlying structure.

[0054] As an example, such as Figure 8As shown, the dielectric layer structure includes a first dielectric layer 17 located on the upper surface of the bottom layer structure 10, the first dielectric layer 17 covering the gate structure.

[0055] In other examples, not shown in the figures, the dielectric layer structure includes: a first dielectric layer located on the upper surface of the underlying structure, the first dielectric layer covering the gate structure; a second etch stop layer located on the first dielectric layer; and a second dielectric layer located on the second etch stop layer; wherein the second dielectric layer includes a first opening in the second etch stop layer for exposing a portion, the first opening being located between the gate structure and the drain structure, and wherein the etch selectivity ratio between the second etch stop layer and the second dielectric layer is not less than 5.

[0056] In other examples, not shown in the figures, the dielectric layer structure includes: a first dielectric layer located on the upper surface of the underlying structure, the first dielectric layer covering the gate structure; a second etch stop layer located on the first dielectric layer; and a second dielectric layer located on the second etch stop layer; wherein the second dielectric layer includes a first opening in the first dielectric layer for exposing a portion of the first dielectric layer, the first opening being located between the gate structure and the drain structure, and wherein the etch selectivity ratio between the second etch stop layer and the second dielectric layer is not less than 5.

[0057] In other examples, such as Figure 12 and Figure 15As shown, a dielectric layer structure 201 is located on the upper surface of the bottom layer structure 10, the dielectric layer structure 201 covers the gate structure 13, a second etch barrier layer 18 is located on the first dielectric layer 17, a second dielectric layer 19 is located on the second etch barrier layer 18, and a third dielectric layer 20 is located on the second dielectric layer 19. The third dielectric layer 20 includes a second opening 302 for exposing a portion of the second dielectric layer 19, and the second dielectric layer 19 includes a third opening 301 for exposing a portion of the second etch barrier layer 18. Both the second opening 302 and the third opening 301 are located between the gate structure 13 and the drain structure 15. The width of the second opening 302 is greater than the width of the third opening 301, and the projection of the second opening 302 on the bottom layer structure 10 completely covers the projection of the third opening 301 on the bottom layer structure 10. The etch selectivity ratio between the third dielectric layer 20 and the second dielectric layer 19 is not less than 5. In other words, the dielectric layer structure 201 includes two upper surfaces of different heights between the gate structure 13 and the drain structure 15. The second etch stop layer 18 acts as an etch stop layer during the etching of the second dielectric layer 19, allowing for precise control of the etching thickness to prevent over-etching that could lead to uneven thickness of the first dielectric layer 17 and affect the depletion of electrons below the field plate. As an example, the material of the first dielectric layer 17 is at least one of SiO2, Si3N4, SiON, and Al2O3, and the material of the second dielectric layer 19 is at least one of SiO2, Si3N4, SiON, and Al2O3. The materials of the first dielectric layer 17 and the second dielectric layer 19 can be the same or different, without limitation. The material of the second etch stop layer 18 is at least one of Al2O3, AlN, Si3N4, SiON, and SiO2. The materials of the second etch stop layer 18 and the first dielectric layer 17 are different, and the materials of the second etch stop layer 18 and the second dielectric layer 19 are different. The material of the third dielectric layer 20 is set to at least one of SiO2, Si3N4, SiON, and Al2O3. The materials of the second dielectric layer 19 and the third dielectric layer 20 can be the same or different, and there is no limitation on this.

[0058] In other examples, as described above Figure 12 and Figure 15 The difference lies in that the third dielectric layer 20 in the dielectric layer structure 201 includes a second opening 302 for exposing the second dielectric layer 19, and the second dielectric layer 19 includes a third opening 301 for exposing the first dielectric layer 17. That is, the third opening 301 is further penetrated to etch the second etch barrier layer 18 to expose the upper surface of the first dielectric layer 17.

[0059] As an example, the thickness of the second etch stop layer 18 is set to be greater than or equal to 20 Å and less than or equal to 50 Å. If the second etch stop layer 18 is too thick, it will affect the field modulation capability of the field plate; if the second etch stop layer 18 is too thin, there is a risk of etching through-through. Therefore, this thickness can achieve the effect of etch stopping while ensuring the electric field modulation effect.

[0060] As an example, the first dielectric layer 17 and the second dielectric layer 19 can also be in direct contact, that is, no second etch barrier layer 18 is provided between the first dielectric layer 17 and the second dielectric layer 19. In this case, the etch selectivity ratio between the second dielectric layer 19 and the first dielectric layer 17 needs to be not less than 5 to prevent over-etching of the first dielectric layer 17. For example, the material of the second dielectric layer 19 is set to silicon oxide, and the material of the first dielectric layer 17 is set to silicon nitride. The third opening 301 penetrates the second dielectric layer 19 to expose the upper surface of the first dielectric layer 17.

[0061] As an example, such as Figure 12 As shown, the exposed second etch barrier layer 18 or the exposed first dielectric layer 17, together with the exposed second dielectric layer 18, form a stepped structure between the gate structure 13 and the drain structure 15. That is, the dielectric layer structure 201 includes two upper surfaces of different heights.

[0062] In other examples, the exposed second etch barrier layer 18 or the exposed first dielectric layer 17, together with the exposed second dielectric layer 18 and the remaining third dielectric layer 20, form a stepped structure between the gate structure 13 and the drain structure 15. That is, the dielectric layer structure 201 includes three upper surfaces of different heights.

[0063] As an example, such as Figure 6 As shown, a field plate 21 is located on the dielectric layer structure, between the gate structure 13 and the drain structure 15, and the field plate 21 is made of TiN material. A first etch stop layer 22 is located on the field plate 21, wherein the material of the first etch stop layer is Al2O3.

[0064] In other examples, such as Figure 14As shown, a field plate 21 is located on the dielectric layer structure 201. The field plate 21 includes at least two upper surfaces of different heights. That is, the field plate 21 is formed on the upper surfaces of the dielectric layer structure 201 at different heights between the gate structure 13 and the drain structure 15. Therefore, the field plate 21 also has at least two upper surfaces of different heights. Here, the field plate 21 refers to the field plate metal layer located on the exposed first dielectric layer 17, the exposed second dielectric layer 18, and the remaining third dielectric layer 20. This field plate 21 is an uninterrupted field plate structure, that is, a continuous field plate 21. In this example, by setting two or even three stepped field plates 21 between the gate and the drain, the electric field distribution in the channel region below can be more finely controlled, enhancing the depletion control effect on charge carriers, thereby effectively optimizing the lateral electric field characteristics of the device and improving the overall breakdown voltage and withstand voltage performance. In this example, the field plate 21 is spaced apart from the drain structure 15.

[0065] Continue to refer to Figure 10 Furthermore, in this embodiment, the first etch barrier layer 22 located on the continuous field plate 21 is formed by patterning the first etch barrier material layer and the field plate metal material layer using the same mask, thereby forming the continuous field plate 21 and the first etch barrier layer 22 located on the continuous field plate 21. The material of the first etch barrier layer 22 is Al2O3.

[0066] As an example, such as Figure 8 As shown, the semiconductor device further includes an interlayer dielectric layer 25 located on the dielectric layer structure. The interlayer dielectric layer 25 covers the field plate 21, the first etch stop layer 22, and the source structure 14 and drain structure 15. The material of the interlayer dielectric layer 25 is set to either SiN or SiO2. The semiconductor device also includes a source contact hole, a gate contact hole, a drain contact hole, and at least one field plate contact hole located within the interlayer dielectric layer 25. In this example, there is only one field plate contact hole, which extends downward from the upper surface of the interlayer dielectric layer 25 to the upper surface of the first etch stop layer 22. Since the etch selectivity ratio between the first etch stop layer 22 and the interlayer dielectric layer 25 is not less than 40, when the field plate contact hole is formed within the interlayer dielectric layer 25, the field plate contact hole will accurately stop on the upper surface of the first etch stop layer 22. In addition, the source contact hole extends downward from the upper surface of the interlayer dielectric layer to the source structure, the drain contact hole extends downward from the upper surface of the interlayer dielectric layer to the drain structure, and the gate contact hole extends vertically downward from the upper surface of the interlayer dielectric layer to the gate structure. The source contact hole, drain contact hole, and gate contact hole are formed in the same step as the field plate contact hole, which can greatly save costs.

[0067] As an example, such as Figure 15 As shown, with Figure 8 The example differs in that when the number of field plate contact holes is greater than or equal to two, the multiple field plate contact holes extend downwards from the upper surface of the interlayer dielectric layer to at least two different heights on the upper surface of the first etch barrier layer 22. Similarly, since the etch selectivity ratio between the first etch barrier layer 22 and the interlayer dielectric layer 25 is not less than 40, when multiple field plate contact holes of different depths are formed within the interlayer dielectric layer 25, these multiple field plate contact holes of different depths will also accurately stop at the upper surface of the first etch barrier layer 22. This effectively avoids over-etching of the shallower field plate during the formation of field plate contact holes of different depths.

[0068] As an example, the source structure 14 and the drain structure 15 penetrate at least through the first dielectric layer 17, the second etch barrier layer 18, and the second dielectric layer 19. Further, the source structure 14 and the drain structure 15 extend into the interior of the underlying structure 10, preferably into the interior of the channel layer 102. The source structure 14 and the drain structure 15 are located on opposite sides of the gate structure 13 and neither is in contact with the gate structure 13.

[0069] As an example, the source structure 14 and the drain structure 15 are ohmic contact source and drain structures, respectively. Specifically, the method for forming the source structure 14 and the drain structure 15 includes: first, forming contact holes on both sides of the gate structure 13, wherein the contact holes penetrate at least the first dielectric layer 17, the second etch barrier layer 18, and the second dielectric layer 19; then, filling the contact holes with metal and annealing to form the ohmic contact of the source structure 14 and the drain structure 15. The annealing process parameters are set according to the actual situation, and the filling metal includes, but is not limited to, TiAlTi / TiAlTiTiN / NiAu, and is specifically selected according to actual needs.

[0070] Furthermore, as an example, such as Figure 8As shown, the semiconductor device further includes: a source conductive plug 232, a drain conductive plug 233, a gate conductive plug 231, and a field plate conductive plug; specifically, the source conductive plug 232 extends vertically downward from the upper surface of the interlayer dielectric layer 25 to the source structure 14 and is electrically connected to the source structure 14. The drain conductive plug 233 extends vertically downward from the upper surface of the interlayer dielectric layer 25 to the drain structure 15 and is electrically connected to the drain structure 15. The gate conductive plug 231 extends vertically downward from the upper surface of the interlayer dielectric layer 25 to the gate structure 13 and is electrically connected to the gate structure 13. The field plate conductive plug extends vertically downward from the upper surface of the interlayer dielectric layer 25 to the field plate 21 and is electrically connected to the field plate 21.

[0071] In other examples, such as Figure 15 As shown, multiple field plate conductive plugs extend vertically downwards from the upper surface of the interlayer dielectric layer 25 to the field plate 21 and are electrically connected to the field plate 21. Specifically, field plate conductive plug 241, field plate conductive plug 242, and field plate conductive plug 243 are electrically connected to the field plate 21. In other examples, the upper surfaces of the three field plates 21 at different heights may only have two field plate conductive plugs, for example, only field plate conductive plugs 241 and 243, that is, field plate conductive plug 241 and field plate conductive plug 243 are electrically connected to the field plate 21. Alternatively, only field plate conductive plugs 241 and 242 are provided, with field plate conductive plug 241 and field plate conductive plug 242 electrically connected to the field plate 21. The upper surface of the three field plates 21 at different heights may also be provided with only one field plate conductive plug, that is, only one of the field plate conductive plug 241, the field plate conductive plug 242, or the field plate conductive plug 243 is provided, and any one of the field plate conductive plug 241, the field plate conductive plug 242, or the field plate conductive plug 243 is electrically connected to the field plate 21.

[0072] Furthermore, as an example, such as Figure 8 As shown in Figure 15, the semiconductor device further includes a plurality of metal interconnect layers located on the interlayer dielectric layer 25. Specifically, the first metal interconnect layer 261 is electrically connected to the upper surface of the source conductive plug 232, the second metal interconnect layer 262 is electrically connected to the upper surface of the gate conductive plug 231, the third metal interconnect layer 263 is electrically connected to the upper surface of the field plate conductive plug, and the fourth metal interconnect layer 264 is electrically connected to the upper surface of the drain conductive plug 233.

[0073] In summary, by adding a first etch barrier layer 22 to the field plate in this application, when etching the contact holes within the interlayer dielectric layer 25 on the same photomask with a single photo layer, the field plate contact holes will stop on the upper surface of the first etch barrier layer 22, preventing over-etching and etching through the field plate, thus ensuring the integrity of the field plate and significantly reducing costs. Furthermore, by setting two or even three stepped field plates 21 between the gate and drain, the electric field distribution in the underlying channel region can be more precisely controlled, enhancing the depletion control of charge carriers and effectively optimizing the lateral electric field characteristics of the device, thereby improving the overall breakdown voltage and withstand voltage performance. Furthermore, when two or three stepped field plates 21 are provided between the gate and the drain, multiple field plate contact holes are typically formed on these stepped field plates. The depths of these field plate contact holes are usually inconsistent. In other words, when two or three field plate contact holes of different depths are formed on the upper surface of the field plate, due to the presence of the first etch barrier layer 22, the multiple field plate contact holes of different depths will accurately stop on the upper surface of the first etch barrier layer 22. This effectively avoids over-etching of the shallower field plate during the formation of field plate contact holes of different depths, resulting in a field plate with good electric field distribution and design flexibility.

[0074] The second aspect:

[0075] This embodiment provides a method for fabricating a semiconductor device. This method can be used to fabricate the semiconductor device described in Embodiment 1. However, the semiconductor device in Embodiment 1 is not limited to the fabrication method of this embodiment, but the fabrication method of this embodiment is superior.

[0076] Taking HEMT devices as an example of semiconductor devices, refer to Figures 1-8 Please provide an explanation.

[0077] refer to Figure 1 The underlying structure 10 is formed. Specifically, the method of forming the underlying structure 10 includes: forming a substrate 100, forming a channel layer 102 above the substrate 100, forming a barrier layer 103 on the channel layer 102, and forming a two-dimensional electron gas (2DEG) 104 at the contact surface between the channel layer 102 and the barrier layer 103.

[0078] It should be noted that the underlying structure 10 can be grown by epitaxial technology or purchased externally, as long as the structure can realize the HEMT semiconductor device in this embodiment.

[0079] As an example, the underlying structure 10 further includes a buffer layer 101 located between the semiconductor substrate layer 100 and the channel layer 102. The buffer layer 101 is used to release stress caused by lattice mismatch and thermal mismatch between the epitaxially grown heterostructure and the semiconductor substrate layer 100. For example, when the underlying structure 10 is a GaN-based HEMT device thin film structure, the buffer layer 101 can be selected as an AlGaN buffer layer.

[0080] As an example, the channel layer and the barrier layer comprise group III nitrides. The underlying structure 10 is a GaN-based HEMT device thin film structure, which is subsequently formed into a GaN-based HEMT device. Therefore, the channel layer 102 is a GaN channel layer, and the barrier layer 103 is an AlGaN barrier layer.

[0081] As an example, the semiconductor substrate 100 can be any suitable semiconductor substrate, such as a Si substrate, a SiC substrate, an aluminum nitride substrate, an aluminum oxide substrate, a gallium nitride substrate, or a sapphire substrate, etc. In this embodiment, the semiconductor substrate 100 is preferably selected as a Si substrate. In addition, the semiconductor substrate 100 can also be doped, such as N-type or P-type doping. In this embodiment, the Si substrate is selected as P-type doped.

[0082] refer to Figure 2 and Figure 3 As shown, a gate structure 13 is formed on a portion of the upper surface of the underlying structure 10. As a specific example, the method for forming the gate structure 13 includes: firstly, depositing the material layer required for the gate structure 13 on the barrier layer 103. It should be noted that the HEMT device fabricated in this embodiment is an enhancement-mode HEMT device (E-mode). The material layer required for the gate structure includes a p-type doped group III-V compound 130 and a gate metal layer 131; preferably, the p-type doped group III-V compound is p-type gallium nitride. Figure 2As shown, a hard mask is then formed in a predetermined region of the gate metal layer. Using the hard mask as a mask, an etching process is employed to etch the material layer required for the gate structure, thereby forming a gate structure 13 of a predetermined shape and size in the predetermined region. The gate structure 13 includes a p-type gallium nitride 130 and a gate metal layer 131. Here, the predetermined region refers to the location where the gate structure is expected to be set. In some embodiments, the projection width of the p-type gallium nitride 130 on the underlying structure 10 is greater than the projection width of the gate metal layer 131 on the underlying structure 10. That is, the projection of the gate metal layer 131 on the underlying structure 10 is located within the region defined by the projection of the p-type gallium nitride 130 on the underlying structure 10. In this embodiment, the projection width of the p-type gallium nitride 130 on the underlying structure 10 is equal to the projection width of the gate metal layer 131 on the underlying structure 10. That is, the projection of the gate metal layer 131 on the underlying structure 10 coincides with the projection of the p-type gallium nitride 130 on the underlying structure 10.

[0083] The gate metal layer 131 can be made of existing materials suitable for use as gate metal layers in HEMT devices. For example, it can be a Ni / Au stacked structure, in which the thickness of each metal layer can be set according to specific needs; TiN material can also be selected, and there is no limitation here.

[0084] refer to Figure 4 As shown, a dielectric layer structure is formed on the underlying structure, and the dielectric layer structure covers the gate structure 13. As an example, the dielectric layer structure includes a first dielectric layer 17, which covers the exposed upper surface of the underlying structure 10 and covers the gate structure. The material of the first dielectric layer 17 is at least one selected from SiO2, Si3N4, SiON, and Al2O3.

[0085] refer to Figures 5 to 6 As shown, a field plate 21 is formed on the dielectric layer structure, and a first etch barrier layer 22 is formed on the field plate 21. Specifically, a field plate metal layer 21 is formed on the first dielectric layer 17, and the first etch barrier layer 22 is formed on the field plate metal layer 21. Using the same mask, the first etch barrier layer 22 and the field plate metal layer 21 are simultaneously etched in a patterned manner to retain the first etch barrier layer 22 and the field plate metal layer 21 in a predetermined area. The remaining field plate metal layer 21 after etching is set as the field plate 21, and the first etch barrier layer 22 located on the upper surface of the field plate 21 is set as the first etch barrier layer. The field plate metal layer 21 is preferably made of TiN material. The material of the first etch barrier layer is preferably Al2O3.

[0086] As an example, the thickness of the first dielectric layer 17 is set to be greater than or equal to 250 Å and less than or equal to 500 Å. This thickness range is selected based on the following considerations: if the first dielectric layer 17 is too thick, it may weaken the field plate's ability to control the depletion of carriers in the channel below; conversely, if the thickness is too thin, it is prone to breakdown under high electric fields, affecting the reliability of the device. Therefore, this thickness can maintain the electric field modulation effect of the field plate while ensuring the voltage withstand capability of the first dielectric layer 17.

[0087] refer to Figure 7 As shown, a source structure 14 and a drain structure 15 are formed on both sides of the gate structure 13, and neither the source structure 14 nor the drain structure 15 is in contact with the gate structure 13. A field plate 21 is located between the gate structure 13 and the drain structure 15, and the field plate 21 is spaced apart from the drain structure 15. Specifically, the source structure 14 and the drain structure 15 at least penetrate the first dielectric layer 17. Further, the source structure 114 and the drain structure 15 extend into the interior of the bottom layer structure 10. Preferably, the source structure 114 and the drain structure 15 extend into the interior of the channel layer 102.

[0088] As an example, the source structure 14 and the drain structure 15 are ohmic contact source structures and ohmic contact drain structures. Specifically, the method for forming the source structure 14 and the drain structure 15 includes: first, forming contact holes on both sides of the gate structure 13, the contact holes penetrating at least the first dielectric layer 17; then, filling the contact holes with metal and annealing to form ohmic contacts for the source structure 14 and the drain structure 15. The annealing process parameters are set according to actual conditions, and the filling metal includes, but is not limited to, TiAlTi / TiAlTiTiN / NiAu, specifically selected according to actual needs.

[0089] An interlayer dielectric layer 25 is formed on the first dielectric layer 17, the interlayer dielectric layer 25 covering the field plate 21, the first etch barrier layer 22, the source structure 14, and the drain structure 15. The material of the interlayer dielectric layer 25 is either SiN or SiO2.

[0090] Using the same illumination, at least one field plate contact hole is formed inside the interlayer dielectric layer 25, while simultaneously forming source contact holes, drain contact holes, and gate contact holes inside the interlayer dielectric layer 25. The source contact hole extends vertically downwards from the upper surface of the interlayer dielectric layer 25 to the source structure; the drain contact hole extends vertically downwards from the upper surface of the interlayer dielectric layer 25 to the drain structure; the gate contact hole extends vertically downwards from the upper surface of the interlayer dielectric layer 25 to the gate structure; and the field plate contact hole extends downwards from the upper surface of the interlayer dielectric layer 25 to the upper surface of the first etch stop layer 22. Since the etch selectivity ratio between the first etch stop layer 22 and the interlayer dielectric layer 25 is not less than 40, when the field plate contact hole is formed within the interlayer dielectric layer 25, the field plate contact hole will accurately stop at the upper surface of the first etch stop layer 22. This prevents over-etching of the field plate 21. The source contact hole, drain contact hole, and gate contact hole are formed in the same step as the field plate contact hole, which can greatly save costs.

[0091] The first etching barrier layer inside the contact hole of the field plate is removed by dry etching. Specifically, in this example, the first etching barrier layer 22 is etched by a Cl-based gas. Since the material of the first etching barrier layer 22 is Al2O3, the field plate below it will not be over-etched.

[0092] Further reference Figure 7 As shown, while depositing conductive material in the field plate contact hole to form the field plate conductive plug 241, conductive material is also deposited in the source contact hole, the gate contact hole and the drain contact hole to form the source conductive plug 232, the gate conductive plug 231 and the drain conductive plug 233 respectively.

[0093] Furthermore, refer to Figure 8 As shown, a plurality of metal interconnect layers are formed on the interlayer dielectric layer 25, wherein the first metal interconnect layer 261 is electrically connected to the upper surface of the source conductive plug 232, the second metal interconnect layer 262 is electrically connected to the upper surface of the gate conductive plug 231, the third metal interconnect layer 263 is electrically connected to the upper surface of the field plate conductive plug 241, and the fourth metal interconnect layer 264 is electrically connected to the drain conductive plug 233.

[0094] In other embodiments, taking HEMT devices as an example, refer to... Figures 1-3 and Figures 9-15 An explanation is provided. Among them, Figures 1-3 The manufacturing method is the same as in the above embodiments, and will not be repeated here.

[0095] refer to Figures 9 to 12As shown, as an example, a dielectric layer structure 201 is formed on the underlying structure. The method of forming the dielectric layer structure differs from the above embodiment. Specifically, a first dielectric layer 17 is formed on the underlying structure 10, covering the exposed upper surface of the underlying structure 10, and the first dielectric layer 17 encapsulates the gate structure 13; a second etch stop layer 18 is formed on the first dielectric layer 17; a second dielectric layer 19 is formed on the second etch stop layer 18; a third dielectric layer 20 is formed on the second dielectric layer; a second etch window is defined, and the third dielectric layer 20 is patterned to form the exposed portion of the second dielectric layer 10. The second opening 302 of layer 9 defines a third etching window. The second dielectric layer 19 and the second etch barrier layer 18 are patterned and etched to form a third opening in the exposed portion of the first dielectric layer 17. Both the second opening 302 and the third opening 301 are located between the gate structure 13 and the drain structure 15. The width of the second opening 302 is greater than the width of the third opening 301, and the projection of the second opening 302 onto the underlying structure 10 completely covers the projection of the third opening 301 onto the underlying structure 10. The etching selectivity ratio between the third dielectric layer 20 and the second dielectric layer 19 is not less than 5. In other examples, only the second dielectric layer 19 can be patterned to form a third opening in the exposed portion of the second etch barrier layer 18. The thickness of the second etch barrier layer 18 is set to be greater than or equal to 20 Å and less than or equal to 50 Å. If the second etch barrier layer 18 is too thick, it will affect the ability of the field plate to control the electric field; if the second etch barrier layer 18 is too thin, there is a risk of etching through-through. Therefore, choosing this thickness can achieve the etching stop effect while ensuring the electric field modulation effect. As an example, the material of the first dielectric layer 17 is at least one of SiO2, Si3N4, SiON, and Al2O3, and the material of the second dielectric layer 19 is at least one of SiO2, Si3N4, SiON, and Al2O3. The materials of the first dielectric layer 17 and the second dielectric layer 19 can be the same or different, without limitation. The material of the second etch stop layer 18 is at least one of Al2O3, AlN, Si3N4, SiON, and SiO2. The materials of the second etch stop layer 18 and the first dielectric layer 17 are different, and the materials of the second etch stop layer 18 and the second dielectric layer 19 are different. The material of the third dielectric layer 20 is at least one of SiO2, Si3N4, SiON, and Al2O3. The materials of the second dielectric layer 19 and the third dielectric layer 20 can be the same or different, without limitation.

[0096] As an example, the thickness of the first dielectric layer 17 is set to be greater than or equal to 250 Å and less than or equal to 500 Å. This thickness range is selected based on the following considerations: if the first dielectric layer 17 is too thick, it may weaken the field plate's ability to control the depletion of carriers in the channel below; conversely, if the thickness is too thin, it is prone to breakdown under high electric fields, affecting the reliability of the device. Therefore, this thickness can maintain the electric field modulation effect of the field plate while ensuring the voltage withstand capability of the first dielectric layer 17.

[0097] As an example, the thickness of the second dielectric layer 19 is set to be greater than or equal to 300 Å and less than or equal to 800 Å, and the thickness of the third dielectric layer 20 is set to be greater than or equal to 300 Å and less than or equal to 800 Å. The area below the field plate near the drain structure 15 includes a stack of a first dielectric layer 17, a second etch barrier layer 18, a second dielectric layer 19, and a third dielectric layer 20. This region experiences the highest electric field strength. By setting a thicker stacked dielectric thickness, the insulation withstand voltage can be effectively improved, preventing dielectric breakdown and thus ensuring the reliability of the field plate under high voltage.

[0098] Therefore, as Figure 12 As shown, the exposed second etch barrier layer 18 or the exposed first dielectric layer 17, together with the exposed second dielectric layer 19 and the remaining third dielectric layer 20 after etching, form a stepped structure between the gate structure and the drain structure.

[0099] Continue to refer to Figure 13 and Figure 14 As shown, a field plate metal layer 21 is formed on the dielectric layer structure 201, and a first etch barrier layer 22 is formed on the field plate metal layer 21. Using the same mask, the first etch barrier layer 21 and the field plate metal layer 22 are patterned and etched to retain the field plate metal layer 21 and the first etch barrier layer 22 located between the gate structure and the drain structure. The retained field plate metal layer 21 and the first etch barrier layer 22 are located on the stepped structure. That is, the retained field plate metal layer 21 and the first etch barrier layer 22 are configured as field plates 21 and first etch barrier layers 22. Specifically, the field plate 21 at least covers the upper surface of the exposed first dielectric layer 17 or the upper surface of the second etch barrier layer 18, the exposed second dielectric layer 19, and the upper surface of the etched third dielectric layer 20.

[0100] Continue to refer to Figure 15As shown, a source structure 14 and a drain structure 15 are formed on both sides of the gate structure 13, respectively, wherein the field plate 21 is located between the gate structure 13 and the drain structure 15; the field plate 21 and the drain structure 15 are spaced apart. Specifically, the source structure 14 and the drain structure 15 penetrate at least through the first dielectric layer 17, the second etch stop 18, the second dielectric layer 19, and the third dielectric layer 20. Further, the source structure 14 and the drain structure 15 extend into the interior of the bottom layer 10, preferably into the interior of the channel layer 102. Neither the source structure 14 nor the drain structure 15 is in contact with the gate structure 13.

[0101] As an example, the source structure 14 and the drain structure 15 are ohmic contact source structures and ohmic contact drain structures. Specifically, the method for forming the source structure 14 and the drain structure 15 includes: first, forming contact holes on both sides of the gate structure 13, wherein the contact holes penetrate at least the first dielectric layer 17, the second etch stop 18, the second dielectric layer 19, and the third dielectric layer 20; then, filling the contact holes with metal and annealing to form ohmic contacts for the source structure 14 and the drain structure 15. The annealing process parameters are set according to actual conditions, and the filling metal includes, but is not limited to, TiAlTi / TiAlTiTiN / NiAu, and is selected according to actual needs.

[0102] Continue to refer to Figure 15 As shown, an interlayer dielectric layer 25 is formed on the dielectric layer structure 201. The material of the interlayer dielectric layer 25 is SiN or SiO2. The interlayer dielectric layer 25 covers the field plate 21, the first etch stop layer 22, the source structure 14, and the drain structure 15. Using a photomask, the interlayer dielectric layer 25 is etched to form source contact holes, gate contact holes, drain contact holes, and at least one field plate contact hole inside it. The field plate contact hole stops at the upper surface of the first etch stop layer. In this example, the number of field plate contact holes is three, that is, one field plate contact hole is formed on the upper surface of the field plate at each different height on the stepped field plate from the gate to the drain. In other examples, the number of field plate contact holes can also be two or one, that is, as long as the field plate is electrically connected to the subsequent metal interconnect layer. When the number of field plate contact holes is greater than or equal to two, the plurality of field plate contact holes extend downward from the upper surface of the interlayer dielectric layer to at least two different heights of the upper surface of the first etch stop layer.

[0103] Using the same illumination, three field plate contact holes are formed inside the interlayer dielectric layer 25, while simultaneously forming source contact holes, drain contact holes, and gate contact holes. The source contact hole extends vertically downwards from the upper surface of the interlayer dielectric layer to the source structure, the drain contact hole extends vertically downwards from the upper surface of the interlayer dielectric layer to the drain structure, and the gate contact hole extends vertically downwards from the upper surface of the interlayer dielectric layer to the gate structure. The three field plate contact holes extend downwards from the upper surface of the interlayer dielectric layer 25 to different heights on the upper surface of the first etch stop layer 22. The etch selectivity ratio between the first etch stop layer 22 and the interlayer dielectric layer 25 is not less than 40. When forming the three field plate contact holes, all three field plate contact holes can accurately stop on the upper surface of the first etch stop layer 22. Since the three field plate contact holes have different depths, without a first etching barrier layer 22 on the field plate 21, the shallowest field plate contact hole could easily be over-etched, or the deepest field plate contact hole could not be etched completely, preventing the field plate from electrically connecting to the subsequent metal interconnect layer. With the first etching barrier layer 22 on the field plate 21, all three field plate contact holes can accurately stop at the first etching barrier layer 22, preventing over-etching or insufficient etching and greatly reducing device risk.

[0104] Similarly, a dry etching method is used to remove the first etching barrier layer in the contact holes of the three field plates. Specifically, in this example, a Cl-based gas is used to etch the first etching barrier layer 22. Since the material of the first etching barrier layer 22 is Al2O3, the field plate 21 below it will not be over-etched.

[0105] Furthermore, while depositing conductive material in the field plate contact hole to form a field plate conductive plug, conductive material is also deposited in the source contact hole, the gate contact hole and the drain contact hole to form a source conductive plug 232, a gate conductive plug 231 and a drain conductive plug 233, respectively.

[0106] Furthermore, a plurality of metal interconnect layers are formed on the interlayer dielectric layer 25, wherein the first metal interconnect layer 261 is electrically connected to the upper surface of the source conductive plug 232, the second metal interconnect layer 262 is electrically connected to the upper surface of the gate conductive plug 231, the third metal interconnect layer 263 is electrically connected to the upper surfaces of the at least two field plate conductive plugs 241, 242, and 243, and the fourth metal interconnect layer 264 is electrically connected to the drain conductive plug 233.

[0107] In other examples, the method of forming the dielectric layer structure on the underlying structure differs from the above embodiment. Specifically, (not shown in the figures), a first dielectric layer is formed to cover the exposed upper surface of the underlying structure and encapsulate the gate structure; a second etch stop layer is formed on the first dielectric layer; a second dielectric layer is formed on the second etch stop layer; a first etch window is defined, and the second dielectric layer is patterned to form a first opening of the exposed portion of the second etch stop layer; wherein the first opening is located between the gate structure and the drain structure, and the etch selectivity ratio between the second etch stop layer and the second dielectric layer is not less than 5. Unlike the above example, the third dielectric layer forms a stepped structure between the gate structure and the drain structure with one less step than in the above embodiment. Of course, it is also possible to retain the second etch stop layer 18. No limitation is made here. That is, the exposed first dielectric layer 17 or the exposed second etch barrier layer 18, together with the exposed second dielectric layer 19, form a secondary step between the gate structure 13 and the drain structure 15. If the second etch barrier layer 18 is formed between the first dielectric layer 17 and the second dielectric layer 19, the materials of the first dielectric layer 17 and the second dielectric layer 19 can be the same or different, without limitation. In another embodiment, if the second etch barrier layer 18 is not formed between the first dielectric layer 17 and the second dielectric layer 19, i.e., the second dielectric layer 19 directly covers the upper surface of the first dielectric layer 17, then the etch selectivity ratio of the second dielectric layer 19 to the first dielectric layer 17 must be not less than 5.

[0108] The field plate metal layer 21 is preferably made of TiN material. The first etch barrier layer is preferably made of Al2O3. The field plate 21 extends at least from the lowest upper surface to the highest upper surface of the dielectric layer structure 201, that is, the field plate 21 at least covers the upper surface of the exposed first dielectric layer 17 or the upper surface of the second etch barrier layer 18 and the remaining second dielectric layer 19 after etching.

[0109] In summary, by forming a first etch barrier layer 22 on the continuous field plate 21, the etch selectivity of the interlayer dielectric layer 25 to the first etch barrier layer 22 is increased. This prevents over-etching during the etching of the field plate contact holes, effectively avoiding the risk of short circuits caused by over-etching of the field plate. Using a single photomask to etch the interlayer dielectric layer 25 to simultaneously form the field plate contact holes, source contact holes, drain contact holes, and gate contact holes significantly reduces costs. Forming a stepped field plate between the gate and drain effectively controls and homogenizes the lateral electric field distribution, thereby significantly improving the device's breakdown voltage. When forming multiple field plate contact holes on a stepped field plate between the gate and drain, the inconsistent depth of each contact hole can lead to over-etching of the smallest contact hole or under-etching of the largest contact hole during the etching of the interlayer dielectric layer. Neither of these situations is desirable. By setting a first etch barrier layer on the field plate, and ensuring that the etch selectivity ratio between the first etch barrier layer and the interlayer dielectric layer is not less than 40, the etching of multiple field plate contact holes of different depths will accurately stop on the upper surface of the first etch barrier layer, avoiding the two undesirable outcomes. This ensures precise control of the carriers in the channel layer below the field plate, thereby greatly improving the stability of the device.

[0110] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: Forming the underlying structure; A gate structure is formed on a portion of the upper surface of the underlying structure; A dielectric layer structure is formed on the underlying structure, and the dielectric layer structure covers the gate structure. A field plate is formed on the dielectric layer structure. A first etching barrier layer is formed on the field plate. A source structure and a drain structure are formed on both sides of the gate structure, wherein the field plate is located between the gate structure and the drain structure; An interlayer dielectric layer is formed on the dielectric layer structure, the interlayer dielectric layer covering the field plate, the first etch barrier layer, the source structure, and the drain structure. Using a photomask, the interlayer dielectric layer is etched to form source contact holes, gate contact holes, drain contact holes, and at least one field plate contact hole within it. The field plate contact hole stops at the upper surface of the first etch barrier layer. The etching selectivity ratio between the first etching barrier layer and the interlayer dielectric layer is not less than 40.

2. The manufacturing method according to claim 1, characterized in that, The method for forming the underlying structure includes: Forming a substrate, A channel layer is formed above the substrate; A barrier layer is formed on the channel layer. The channel layer and the barrier layer comprise group III nitrides.

3. The manufacturing method according to claim 2, characterized in that, A method for forming a gate structure on a portion of the upper surface of the underlying structure includes: A pGaN layer is formed on the barrier layer. A gate metal layer is formed on the pGaN layer. A hard mask is formed in a predetermined area of ​​the gate metal layer. Using the hard mask as a mask, the pGaN layer and the gate metal layer are etched to form the gate structure.

4. The manufacturing method according to claim 1, characterized in that, The method for forming a dielectric layer structure on the underlying structure includes: A first dielectric layer is formed to cover the exposed upper surface of the underlying structure and to encapsulate the gate structure.

5. The manufacturing method according to claim 1, characterized in that, The method for forming a dielectric layer structure on the underlying structure includes: A first dielectric layer is formed to cover the exposed upper surface of the underlying structure and to encapsulate the gate structure; A second etching barrier layer is formed on the first dielectric layer; A second dielectric layer is formed on the second etch barrier layer; Define a first etching window, and pattern the second dielectric layer to form a first opening in the exposed portion of the second etching barrier layer; Wherein, the first opening is located between the gate structure and the drain structure, and the etching selectivity between the second etch barrier layer and the second dielectric layer is not less than 5.

6. The manufacturing method according to claim 5, characterized in that, The method for forming the first opening further includes: Define a first etching window, and pattern the second dielectric layer and the second etching barrier layer to form a first opening in the first dielectric layer of the exposed portion.

7. The manufacturing method according to claim 1, characterized in that, The method for forming a dielectric layer structure on the underlying structure includes: A first dielectric layer is formed to cover the exposed upper surface of the underlying structure and to encapsulate the gate structure; A second etching barrier layer is formed on the first dielectric layer; A second dielectric layer is formed on the second etch barrier layer; A third dielectric layer is formed on the second dielectric layer; Define a second etching window, and pattern the third dielectric layer to form a second opening in the exposed portion of the second dielectric layer. Define a third etching window and pattern the second dielectric layer to form a third opening in the exposed portion of the second etching barrier layer; Wherein, the second opening and the third opening are both located between the gate structure and the drain structure; the width of the second opening is greater than the width of the third opening, and the projection of the second opening on the underlying structure completely covers the projection of the third opening on the underlying structure, and the etching selectivity between the third dielectric layer and the second dielectric layer is not less than 5.

8. The manufacturing method according to claim 5, 6, or 7, characterized in that, The exposed second etch barrier layer or the exposed first dielectric layer, together with the exposed second dielectric layer and the remaining third dielectric layer after etching, form a stepped structure between the gate structure and the drain structure.

9. The manufacturing method according to claim 8, characterized in that, A method for forming a field plate on the dielectric layer structure and forming a first etching barrier layer on the field plate includes: A field plate metal layer is formed on the dielectric layer structure. A first etching barrier layer is formed on the field plate metal layer. Using the same mask, the first etch barrier layer and the field plate metal layer are patterned and etched to retain the field plate metal layer and the first etch barrier layer located between the gate structure and the drain structure, wherein the retained field plate metal layer and the first etch barrier layer are located on the stepped structure.

10. The manufacturing method according to claim 9, characterized in that, When the number of contact holes in the field plate is greater than or equal to 2 The plurality of field plate contact holes extend downward from the upper surface of the interlayer dielectric layer to at least two different heights of the upper surface of the first etch barrier layer.

11. The manufacturing method according to claim 1, characterized in that, The source contact hole extends downward from the upper surface of the interlayer dielectric layer to the source structure, the drain contact hole extends downward from the upper surface of the interlayer dielectric layer to the drain structure, and the gate contact hole extends downward from the upper surface of the interlayer dielectric layer to the gate structure.

12. The manufacturing method according to claim 1, characterized in that, The method further includes: A conductive plug is formed by depositing conductive material in the contact hole.

13. The manufacturing method according to claim 12, characterized in that, Before depositing conductive material in the field plate contact hole to form a field plate conductive plug, the method further includes: removing a first etch barrier layer in the field plate contact hole so that the field plate conductive plug contacts the field plate.

14. The manufacturing method according to claim 12, characterized in that, The method further includes: Multiple metal connection layers are formed on the interlayer dielectric layer, wherein the first metal connection layer is electrically connected to the upper surface of the source conductive plug, the second metal connection layer is electrically connected to the upper surface of the gate conductive plug, the third metal connection layer is electrically connected to the upper surface of the at least two field plate conductive plugs, and the fourth metal connection layer is electrically connected to the drain conductive plug.

15. A semiconductor device, characterized in that, include: Underlying structure; The gate structure located on the upper surface of the bottom structure portion and the source and drain structures located on both sides of the gate structure; A dielectric layer structure located on the upper surface of the underlying structure, the dielectric layer structure covering the gate structure. A field plate located on the dielectric layer structure, A first etch barrier layer is located on the field plate, wherein the field plate is located between the gate structure and the drain structure; An interlayer dielectric layer is located on the dielectric layer structure, the interlayer dielectric layer covering the field plate, the first etch barrier layer, the source structure, and the drain structure. It also includes source contact holes, gate contact holes, drain holes, and at least one field plate contact hole located within the interlayer dielectric layer, wherein the field plate contact hole extends downward from the upper surface of the interlayer dielectric layer to the upper surface of the first etch barrier layer. The etching selectivity ratio between the first etching barrier layer and the interlayer dielectric layer is not less than 40.

16. The semiconductor device according to claim 15, characterized in that, The material of the first etching barrier layer is Al2O3.

17. The semiconductor device according to claim 15, characterized in that, The material of the interlayer medium includes at least one of SiN or SiO2.

18. The semiconductor device according to claim 15, characterized in that, The dielectric layer structure includes: A first dielectric layer is located on the upper surface of the underlying structure, and the first dielectric layer covers the gate structure.

19. The semiconductor device according to claim 15, characterized in that, The dielectric layer structure includes: A first dielectric layer is located on the upper surface of the underlying structure, and the first dielectric layer covers the gate structure. The second etch barrier layer is located on the first dielectric layer; The second dielectric layer is located on the second etch barrier layer; The second dielectric layer includes a first opening in the second etch barrier layer for exposing portions, the first opening being located between the gate structure and the drain structure. The etching selectivity ratio between the second etching barrier layer and the second dielectric layer is not less than 5.

20. The semiconductor device according to claim 19, characterized in that, in, The second dielectric layer includes a first opening in the first dielectric layer for exposing a portion of the first dielectric layer, the first opening being located between the gate structure and the drain structure.

21. The semiconductor device according to claim 15, characterized in that, The dielectric layer structure includes: A first dielectric layer is located on the upper surface of the underlying structure, and the first dielectric layer covers the gate structure. The second etch barrier layer is located on the first dielectric layer; The second dielectric layer is located on the second etch barrier layer; The third dielectric layer located on the second dielectric layer, The third dielectric layer includes a second opening in the second dielectric layer for exposing the exposed portion, and the second dielectric layer includes a third opening in the second etch barrier layer for exposing the exposed portion. Both the second opening and the third opening are located between the gate structure and the drain structure. The width of the second opening is greater than the width of the third opening, and the projection of the second opening on the underlying structure completely covers the projection of the third opening on the underlying structure. The etching selectivity between the third dielectric layer and the second dielectric layer is not less than 5.

22. The semiconductor device according to claim 19, 20, or 21, characterized in that, The exposed second etch barrier layer or the exposed first dielectric layer, together with the exposed second dielectric layer and the remaining third dielectric layer, form a stepped structure between the gate structure and the drain structure.

23. The semiconductor device according to claim 22, characterized in that, The field plate metal layer located on the upper surface of the stepped structure is configured as the field plate.

24. The semiconductor device according to claim 22, characterized in that, When the number of contact holes in the field plate is greater than or equal to 2 The plurality of field plate contact holes extend downward from the upper surface of the interlayer dielectric layer to at least two different heights of the upper surface of the first etch barrier layer.

25. The semiconductor device according to claim 15, characterized in that, The source contact hole extends downward from the upper surface of the interlayer dielectric layer to the source structure, the drain contact hole extends downward from the upper surface of the interlayer dielectric layer to the drain structure, and the gate contact hole extends vertically downward from the upper surface of the interlayer dielectric layer to the gate structure.

26. The semiconductor device according to claim 25, characterized in that, The device also includes a conductive plug located within the contact hole.

27. The semiconductor device according to claim 26, characterized in that, The conductive plug of the field plate is in contact with the field plate.

28. The semiconductor device according to claim 26, characterized in that, The semiconductor device further includes: Multiple metal interconnect layers are located on the interlayer dielectric layer, wherein the first metal interconnect layer is electrically connected to the upper surface of the source conductive plug, the second metal interconnect layer is electrically connected to the upper surface of the gate conductive plug, the third metal interconnect layer is electrically connected to the upper surface of the at least two field plate conductive plugs, and the fourth metal interconnect layer is electrically connected to the upper surface of the drain conductive plug.

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