A manufacturing process for a power mosfet structure with a reliability terminal

Abstract

The application discloses a manufacturing process of a power MOSFET structure with a reliable terminal, and relates to the technical field of semiconductors.The process sets a dynamic clamping potential in a P base region on the basis of a traditional source contact hole extension process, so that the P base region forms a changeable low-resistance path connected to the source, and a variable clamping is formed according to the current size.In actual application, when the current of the P base region is a small current, the clamping is weak, and the drain-source on-resistance is not affected;when the current of the P base region is a large current or a current avalanche occurs, the clamping is automatically strengthened, and parasitic BIT is strongly inhibited, so that low on-resistance and high avalanche resistance are realized.In normal use, the on-resistance is not increased, the efficiency is not decreased, and performance loss is avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a manufacturing process for a power MOSFET structure with reliable terminals. Background Technology

[0002] Parasitic NPN transistors exist inside MOSFETs. During avalanche, the avalanche current flowing through the P-base region resistor may generate a voltage drop, triggering the parasitic BJT to conduct, leading to current concentration and burnout.

[0003] In existing technical solutions, the contact hole is usually extended out of the P-base region and then heavily doped to reduce the resistance of the P-base region, suppress the false turn-on of parasitic BJTs, and thus improve the avalanche current withstand capability. However, in this technical solution, the contact hole is directly and completely extended to the P-base region, and the P-base region is heavily doped with P+. This makes the metal directly short-circuit the P-base region to the source, thus forming a static clamp. Its advantage is that it has a strong ability to suppress parasitic BJTs, but all clamps are completely fixed, which brings the following disadvantages. 1. Deterioration of on-resistance: In order to ensure the clamping effect, the contact hole needs to cover the P-base region in a large area. At the same time, the P-base region needs to be heavily doped with P+. At this time, the doping concentration near the channel increases, the carrier mobility decreases, resulting in a larger on-resistance and reduced efficiency. 2. Threshold voltage drift: Heavy doping of the P-base region directly changes the doping distribution in the channel region, making the device turn-on voltage unstable, prone to batch-to-batch deviations, and affecting the compatibility of the control circuit. 3. Increased leakage current: Large-area P+ injection and contact holes will create more leakage paths, resulting in increased leakage current in the off state and increased static power consumption, which is more pronounced at high temperatures. 5. It is impossible to achieve both low Rdson and high EAS. In order to improve avalanche tolerance, conduction performance must be sacrificed, and vice versa. It is impossible to achieve "low conduction loss" and "high avalanche robustness" on the same device at the same time. 6. The clamping strength is fixed and lacks adaptability. The P base region is completely short-circuited, and the clamping strength is fixed. During normal operation, the P base region is also forcibly clamped and cannot be dynamically adjusted according to the current, resulting in unnecessary performance loss. To address the aforementioned issues, a manufacturing process for a power MOSFET structure with reliable terminals is provided. Summary of the Invention

[0004] The purpose of this invention is to provide a manufacturing process for a power MOSFET structure with reliable terminals, in order to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a manufacturing process for a power MOSFET structure with reliable terminals, comprising the following steps: S1. Optimize the structure of the source contact hole, N+ source region and P base region, so that the source contact hole extends to the P base region and reduces the resistance of the P base region. S2. The terminal area is equipped with three-dimensional grooves to improve the terminal's pressure resistance. S3: The back of the overall package uses a single exposed metal plate as a heat dissipation conductor to achieve rapid heat reduction; The P-base region is configured with a dynamic clamping potential to form a variable low-resistance path to the source, thereby adapting to the current magnitude to form a variable clamp and improving avalanche current tolerance. The three-dimensional trenches are used to form multi-level steps in the high electric field region of the surface, so that the lateral voltage enters the three-dimensional trenches to weaken the peak electric field of the surface and suppress avalanche.

[0006] Preferably, in step S1, the source contact hole is extended from the N+ source region to above the P-base region, and then a source metal is formed in the source contact hole by a metal vapor deposition process. The source metal short-circuits the P-base region and the source potential through a dynamic clamping potential, thereby achieving P-base region potential clamping. At the same time, the P-base region is doped below the contact hole to significantly reduce the P-base region resistance and reduce the lateral potential difference caused by avalanche current.

[0007] Preferably, the dynamic clamping potential is formed by gradient doping of the P-based region, wherein; The P-based region near the source contact hole is heavily doped with P+ to form a low-resistivity region. The P-based region, located away from the source contact hole, is lightly doped with P to form a high-resistivity region. This allows low-density current to pass only through the high-resistance region without affecting the current; while when high-density current passes through, it flows through both the low-resistance and high-resistance regions, and the resistance is distributed through the low-resistance region, thus reducing the overall resistance.

[0008] Preferably, the dynamic clamping potential is achieved by differentiating the multiple source contact holes, including type A contact holes and type B contact holes; The type A contact hole is widened and lengthened based on the original contact hole size, so that the type A contact hole covers both the N+ source region and the P base region at the same time, and directly short-circuits the P base region to the source. The B-type contact hole retains the original process, covering only the N+ source region and not extending to the P-base region. The P-base region can only be connected to the source through the internal silicon resistance. This design ensures that under low current density conditions, the lateral current in the P-base region only flows to the nearest contact hole. At this time, most of the current is absorbed by the N+ source region of the B-type contact hole, and only a small portion flows to the P-base region near the A-type contact hole. In this case, the equivalent P-base region resistance is dominated by the resistance of silicon itself, resulting in a relatively high overall resistance. However, at high current density, the lateral current in the P-base region diffuses to all low-resistance paths. At this time, the extended via pulls the P-base region potential directly to the source potential, reducing the equivalent resistance of the P-base region. Even with a large current, Vbe is forced to be below 0.7V, preventing the parasitic BJT from opening, and the clamping strength automatically increases with the current.

[0009] Preferably, the type A contact holes and the type B contact holes are distributed alternately. During the etching process, the type B contact holes are formed by overall processing, and then the original type B contact holes are deepened to form the type A contact holes by interval positioning.

[0010] Preferably, the dynamic clamping potential is achieved by locating each cell and then forming an independent micro P+ injection point under each cell through heavy doping. The source contact hole passes through the N+ source region and is shorted to the micro P+ injection point. This creates numerous clamping potentials corresponding to each cell, ensuring that during avalanche, the current in the P-base region is uneven and hotspots are formed in local areas. The micro P+ injection point near the hotspot clamps the local P-base region potential directly to the source, instantly lowering the P-base region resistance in that area. In non-hotspot areas, the P-base region resistance remains high even with low current density, without affecting channel performance. Result: Local hotspots are precisely suppressed, parasitic BJTs will not turn on anywhere, and the overall Rdson ratio is not sacrificed.

[0011] Preferably, the three-dimensional groove includes independent spiral rings arranged around the periphery of the cell region. There are multiple sets of spiral rings, and the bottom of the spiral rings is rounded to avoid the concentration of electric field at sharp corners.

[0012] Preferably, the spacing between the inner loops is smaller than that between the outer loops, and the groove width of the inner loops is smaller than that of the outer loops. This creates a dense voltage-splitting zone on the inner side, providing multi-level buffering for the high electric field region. On the outer side, a smooth transition zone is formed to match the gradually decreasing electric field gradient. This makes the electric field distribution more closely match the actual potential change, effectively reducing the peak value of the inner loop. The outer loop does not require additional grooves, saving terminal area and achieving the dual benefits of "increased withstand voltage + optimized area".

[0013] Preferably, the etching depth of the inner loop is greater than that of the outer loop, so that the inner loop can quickly pull the high electric field into the silicon wafer and away from the surface, and then smoothly transition through the outer loop. This makes the electric field no longer concentrated at the bottom of a single trench, but dispersed in trenches of different depths, significantly reducing the surface electric field intensity and significantly improving the terminal withstand voltage and surface breakdown resistance.

[0014] Preferably, P-type field limiting rings are injected between the plurality of the loops to form a lateral potential gradient. The width and spacing of the field limiting rings adopt the same gradient design as the loops, thereby cooperating with the loops to divide the voltage and further smooth the surface electric field.

[0015] The technical effects and advantages of this invention are as follows: 1. The manufacturing process of this power MOSFET structure with reliable terminals, based on the traditional source contact hole extension process, sets a dynamic clamping potential in the P-base region to form a variable low-resistance path connecting to the source. This allows for adaptive current magnitude and variable clamping. In practical applications, when the current through the P-base region is small, the clamping is weak and does not affect the drain-source on-resistance. However, when the current through the P-base region is large or current avalanche occurs, the clamping automatically becomes stronger, strongly suppressing parasitic biting. This achieves low on-resistance and high avalanche tolerance. Under normal use, the on-resistance will not increase, and the efficiency will not decrease, avoiding performance loss.

[0016] 2. The manufacturing process of this power MOSFET structure with reliable terminals employs differentiated doping schemes for the P-base region. This allows small currents to flow only through the lightly doped high-resistance region during practical applications, while large currents or avalanche currents automatically extend to the heavily doped low-resistance region. This achieves an adaptive effect where the larger the current, the lower the resistance and the stronger the clamping. Most importantly, during normal operation, no additional low-resistance doping is introduced, and the on-resistance is not increased. Local heavy doping is applied near the contact hole, while the main channel region remains lightly doped, without interfering with channel doping. This results in good threshold voltage consistency and lower turn-off leakage current. During avalanche, the base region resistance is automatically reduced, and the voltage is quickly distributed through multiple low-resistance regions to avoid excessively high local potentials.

[0017] 3. The manufacturing process of this power MOSFET structure with reliable terminals involves first etching a B-type contact hole during the contact hole etching process, and then etching an A-type contact hole on the basis of the B-type contact hole and then performing a second etching to increase the depth. This ensures that under low current density, the lateral current of the P-base region will only flow to the nearest contact hole, and the equivalent P-base region resistance is dominated by the resistance of the silicon itself. At high current density, the lateral current of the P-base region will diffuse to all low-resistance paths. At this time, even if the current is large, the on-resistance is still very low, and the parasitic BJT cannot be turned on. This achieves automatic enhancement of clamping strength with current. Moreover, this solution can be further processed from the existing semi-finished product with completed basic source region contact hole etching, which is less difficult to manufacture and has a lower cost.

[0018] 4. The manufacturing process of this power MOSFET structure with reliable terminals utilizes dynamic clamping potentials. Each cell is positioned, and then a unique micro P+ injection point is formed below each cell through heavy doping. The source contact hole passes through the N+ source region and is shorted to the micro P+ injection point. This creates numerous clamping potentials corresponding to each cell, ensuring that during avalanche, the micro P+ injection point directly clamps the local P-base region potential to the source, instantly lowering the P-base region resistance in that area, rather than in hot spots. At low current densities, the P-base region resistance remains high, without affecting channel performance. This results in ultra-high precision and complete parasitic BJT suppression, with virtually no impact on the overall Rdson ratio, making it more suitable for high-end chip manufacturing. Attached Figure Description

[0019] Figure 1 This is a flowchart of the manufacturing process of the present invention; Figure 2 This is a schematic diagram of the chip surface manufactured using the manufacturing process of this invention; Figure 3 This is a schematic diagram illustrating how the dynamic clamping potential of the present invention is formed by gradient doping of the P-based region; Figure 4 This is a schematic diagram illustrating how the dynamic clamping potential of the present invention is formed by differentiating the multiple source contact holes. Figure 5 This is a schematic diagram illustrating the design of an independent micro P+ injection point for each cell based on the dynamic clamping potential of this invention. Figure 6 The diagrams show the spiral ring and the P-type field limiting ring of the present invention, respectively.

[0020] In the figure: 1. Cell region; 11. N+ source region; 12. P base region; 121. High-resistivity region; 122. Low-resistivity region; 123. Micro P+ injection point; 13. Source contact hole; 131. Type A contact hole; 132. Type B contact hole; 2. Hedge; 3. P-type field limiting ring. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention provides, for example Figure 1 , Figure 2 and Figure 6 The manufacturing process of a power MOSFET structure with reliable termination, as shown, includes the following steps: S1. Optimize the structure of source contact hole 13, N+ source region 11 and P base region 12, so that source contact hole 13 extends to P base region 12 and reduces the resistance of P base region 12. S2. The terminal area is equipped with three-dimensional grooves to improve the terminal's pressure resistance. S3: The back of the overall package uses a single exposed metal plate as a heat dissipation conductor to achieve rapid heat reduction; The P-base region 12 is set with a dynamic clamping potential so that it forms a variable low-resistance path to the source, thereby adapting to the current magnitude to form a variable clamp and improving the avalanche current tolerance. The three-dimensional trench is used to form multi-level steps in the high electric field region of the surface, so that the lateral voltage enters the three-dimensional trench to weaken the peak electric field of the surface and suppress avalanche.

[0023] In step S1, the source contact hole 13 is extended from the N+ source region 11 to above the P base region 12, and then the source metal is formed in the source contact hole 13 by metal vapor deposition. The source metal short-circuits the P base region 12 and the source potential through a dynamic clamping potential, thereby clamping the potential of the P base region 12. At the same time, the P base region 12 is doped below the contact hole, which significantly reduces the resistance of the P base region 12 and reduces the lateral potential difference caused by avalanche current.

[0024] The three-dimensional trench includes multiple independent loops 2 surrounding the periphery of the cell region 1. There are multiple sets of loops 2, and the bottom of the loops 2 is rounded to avoid the concentration of electric field at sharp corners.

[0025] The spacing of the inner loop 2 is smaller than that of the outer loop 2, and the groove width of the inner loop 2 is smaller than that of the outer loop 2. This creates a dense voltage-splitting zone on the inner side, providing multi-level buffering for the high electric field region. On the outer side, a smooth transition zone is formed to match the gradually decreasing electric field gradient. This makes the electric field distribution more closely match the actual potential change. The peak value of the inner loop is effectively reduced, and the outer loop does not require additional grooves, saving terminal area and achieving the dual benefits of "increased withstand voltage + area optimization".

[0026] The etching depth of the inner loop 2 is greater than that of the outer loop 2, so that the inner loop 2 can quickly pull the high electric field into the silicon wafer and away from the surface. Then, it is smoothly transitioned through the outer loop 2, so that the electric field is no longer concentrated at the bottom of a single trench, but is dispersed in trenches of different depths. The surface electric field intensity is greatly reduced, which significantly improves the terminal withstand voltage and surface breakdown resistance.

[0027] P-type field limiting rings are injected between multiple loops 2 to form a transverse potential gradient. The width and spacing of the field limiting rings adopt the same gradient design as the loops 2, so as to work with the loops 2 to divide the voltage and further smooth the surface electric field.

[0028] Working principle: In this process, based on the traditional source contact hole 13 extension process, a dynamic clamping potential is set in the P-base region 12 to form a variable low-resistance path to the source, thereby adapting to the current magnitude to form a variable clamp. In practical applications, when the current through the P-base region 12 is small, the clamping is weak and does not affect the drain-source on-resistance; while when the current through the P-base region 12 is large or current avalanche occurs, the clamping automatically becomes stronger, strongly suppressing parasitic BIT, thereby achieving low on-resistance and high avalanche tolerance. Under normal use, the on-resistance will not increase and the efficiency will not decrease, avoiding performance loss. Secondly, by setting three-dimensional trenches in the terminal area, and the three-dimensional trenches adopt a special design, including independent loops 2 surrounding the periphery of the cell region 1, there are multiple sets of loops 2, and the spacing of the loops 2 gradually increases from the inside to the outside, the width of the loops 2 gradually increases from the inside to the outside, and the etching depth gradually decreases from the inside to the outside. This makes a dense voltage division region formed on the inner side, providing multi-level buffering for the high electric field region; and a smooth transition region formed on the outer side. At the same time, the large depth on the inner side can quickly pull the high electric field into the silicon wafer and away from the surface, and then the outer loops 2 provide a smooth transition, matching the gradually decreasing electric field gradient. This makes efficient use of the limited area of ​​the terminal area to smoothly reduce the electric field gradient. Furthermore, a P-type field limiting ring is injected between two adjacent loops 2 to form a lateral potential gradient, which works with the loops 2 to further smooth the surface electric field through voltage division.

[0029] Example 1, as Figure 3As shown, the dynamic clamping potential is formed by gradient doping of the P-base region 12. The P-base region 12 near the source contact hole 13 is heavily doped with P+ to form a low-resistance region 122. The P-base region 12 away from the source contact hole 13 is lightly doped with P to form a high-resistance region 121. This ensures that low-density current passes only through the high-resistance region 121 without affecting the current. When high-density current passes through, it flows through the low-resistance region 122 and the high-resistance region 121, and the resistance is distributed through the low-resistance region 122, thus reducing the overall resistance.

[0030] In this embodiment, by employing a differentiated doping scheme for the P-base region 12, small currents flow only through the lightly doped high-resistivity region 121 during practical applications, while large currents or avalanche currents automatically extend to the heavily doped low-resistivity region 122. This achieves an adaptive effect where the larger the current, the lower the resistance and the stronger the clamping. Most importantly, during normal operation, no additional low-resistivity doping is introduced, and the on-resistance is not increased. Local heavy doping is applied near the contact hole, while the main channel region remains lightly doped, without interfering with channel doping. This results in good threshold voltage consistency and lower turn-off leakage current. During avalanche, the base region resistance is automatically reduced, and the potential is quickly distributed through multiple low-resistivity regions, avoiding excessively high local potentials. This significantly improves the uniformity of current distribution during avalanche, reducing the risk of thermal failure. Furthermore, during fabrication, only the window and dose of the P-type injection are adjusted to form a gradient distribution, eliminating the need for additional photomasks or complex processes. This process highly overlaps with existing trench MOSFET manufacturing processes, reducing manufacturing costs and difficulty.

[0031] Example 2, as Figure 4 As shown, the dynamic clamping potential is achieved by differentiating the design of multiple source contact holes 13, including type A contact hole 131 and type B contact hole 132. The A-type contact hole 131 is widened and lengthened based on the original contact hole size so that the A-type contact hole 131 covers both the N+ source region 11 and the P base region 12, and directly shorts the P base region 12 to the source. Type B contact hole 132 retains the original process, only covering the N+ source region 11 without extending to the P base region 12. The P base region 12 can only be connected to the source through the internal silicon resistance. Type A contact holes 131 and Type B contact holes 132 are alternately distributed. During the etching process, Type B contact holes 132 are formed through overall processing, and then the original Type B contact holes 132 are deepened to form Type A contact holes 131.

[0032] In this embodiment, the B-type contact hole 132 is first etched out as a whole during the etching process, and then the A-type contact hole 131 is positioned on the B-type contact hole 132 before a second etching is performed to increase the depth. This method can be further processed from an existing semi-finished product with completed basic source region contact hole etching. It has lower manufacturing difficulty and cost, and stronger adaptability. This ensures that under low-density current conditions, the lateral current of the P-base region 12 will only flow to the nearest contact hole. At this time, most of the current is absorbed by the B-type contact hole. The N+ source region 11 of the contact hole 132 absorbs the current, and only a small portion flows to the P-base region 12 near the A-type contact hole 131. At this time, the equivalent resistance of the P-base region 12 is dominated by the resistance of silicon itself, and the overall resistance is relatively high. However, at high current density, the lateral current of the P-base region 12 will diffuse to all low-resistance paths. At this time, the extension hole directly pulls the potential of the P-base region 12 to the source potential, and the equivalent resistance of the P-base region 12 decreases. At this time, even if the current is very large, Vbe is forced to be below 0.7V, the parasitic BJT cannot be turned on, and the clamping strength automatically increases with the current.

[0033] Example 3, as Figure 5 As shown, the dynamic clamping potential is achieved by positioning each cell and then forming an independent micro P+ injection point 123 under each cell through heavy doping. The source contact hole 13 passes through the N+ source region 11 and is shorted to the micro P+ injection point 123. This creates countless clamping potentials corresponding to each cell, so that during avalanche, the current in the P-base region 12 is uneven and hot spots will form in local areas. The micro P+ injection point 123 near the hot spot will clamp the local P-base region 12 potential directly to the source, instantly pulling down the resistance of the P-base region 12 in that area. In non-hot spot areas, when the current density is low, the resistance of the P-base region 12 remains high, which does not affect the channel performance. Local hot spots are precisely suppressed, parasitic BJTs will not turn on anywhere, and the overall Rdson is not sacrificed.

[0034] The dynamic clamping potential design scheme provided in this embodiment has ultra-high precision and complete parasitic BJT suppression effect, and has virtually no impact on the overall Rdson. However, it is relatively difficult to manufacture and is more suitable for high-end chip manufacturing.

[0035] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A manufacturing process for a power MOSFET structure with reliable terminals, characterized in that, Includes the following steps: S1. Optimize the layout of the source contact hole and N+ injection region, so that the source contact hole extends to the P base region and reduces the resistance of the P base region; S2. The terminal area is equipped with three-dimensional grooves to improve the terminal's pressure resistance. S3: The back of the overall package uses a single exposed metal plate as a heat dissipation conductor to achieve rapid heat reduction; The P-base region is configured with a dynamic clamping potential to form a variable low-resistance path to the source, thereby adapting to the current magnitude to form a variable clamp and improving avalanche current tolerance. The three-dimensional trenches are used to form multi-level steps in the high electric field region of the surface, so that the lateral voltage enters the three-dimensional trenches to weaken the peak electric field of the surface and suppress avalanche.

2. The manufacturing process of a power MOSFET structure with a reliable terminal according to claim 1, characterized in that, In step S1, the source contact hole is extended from the N+ source region to above the P base region, and then a source metal is formed in the source contact hole by a metal vapor deposition process. The source metal short-circuits the P base region and the source potential through a dynamic clamping potential, thereby clamping the P base region potential. At the same time, the P base region is doped below the contact hole to significantly reduce the P base region resistance and reduce the lateral potential difference caused by avalanche current.

3. The manufacturing process of a power MOSFET structure with a reliable terminal according to claim 2, characterized in that, The dynamic clamping potential is formed by gradient doping of the P-based region, wherein; The P-based region near the source contact hole is heavily doped with P+ to form a low-resistivity region. The P-based region, located away from the source contact hole, is lightly doped with P to form a high-resistivity region. This allows low-density current to pass only through the high-resistance region without affecting the current; while when high-density current passes through, it flows through both the low-resistance and high-resistance regions, and the resistance is distributed through the low-resistance region, thus reducing the overall resistance.

4. The manufacturing process of a power MOSFET structure with a reliable terminal according to claim 2, characterized in that, The dynamic clamping potential is formed by differentiating the multiple source contact holes, including type A contact holes and type B contact holes; The type A contact hole is widened and lengthened based on the original contact hole size, so that the type A contact hole covers both the N+ source region and the P base region at the same time, and directly short-circuits the P base region to the source. The B-type contact hole retains the original process, covering only the N+ source region and not extending to the P-base region. The P-base region can only be connected to the source through the internal silicon resistance. This ensures that under low current density conditions, the lateral current in the P-base region will only flow to the nearest contact hole, and most of the current will be absorbed by the N+ source region of the B-type contact hole, resulting in a relatively high overall resistance. However, under high current density conditions, the lateral current in the P-base region will diffuse to all low-resistance paths, the equivalent resistance of the P-base region will decrease, and the clamping strength will automatically increase with the current.

5. The manufacturing process of a power MOSFET structure with a reliable terminal according to claim 4, characterized in that, The type A contact holes and the type B contact holes are distributed alternately. During the etching process, the type B contact holes are formed by overall processing, and then the original type B contact holes are deepened to form the type A contact holes by interval positioning.

6. The manufacturing process of a power MOSFET structure with a reliable terminal according to claim 5, characterized in that, The dynamic clamping potential is achieved by locating each cell and then forming an independent micro P+ injection point under each cell through heavy doping. The source contact hole passes through the N+ source region and is shorted to the micro P+ injection point. In this way, countless clamping potentials corresponding to each cell are formed, so that when avalanche occurs, the current forms a hot spot at the clamping potential. The micro P+ injection point near the hot spot clamps the local P base region potential directly to the source.

7. The manufacturing process of a power MOSFET structure with a reliable terminal according to claim 1, characterized in that, The three-dimensional trench includes independent spiral rings arranged around the periphery of the cell region. There are multiple sets of spiral rings, and the bottom of the spiral rings is rounded to avoid the concentration of electric field at sharp corners.

8. The manufacturing process of a power MOSFET structure with a reliable terminal according to claim 7, characterized in that, The spacing between the inner loops is smaller than that between the outer loops, and the groove width of the inner loops is smaller than that of the outer loops, thus forming a dense voltage-dividing region on the inner side to provide multi-level buffering for the high electric field region; while a smooth transition region is formed on the outer side to match the gradually decreasing electric field gradient.

9. The manufacturing process of a power MOSFET structure with a reliable terminal according to claim 7, characterized in that, The inner loop has a greater etching depth than the outer loop, so that the inner loop can quickly pull the high electric field into the silicon wafer and away from the surface, and then smoothly transition through the outer loop, so that the electric field is no longer concentrated at the bottom of a single trench.

10. The manufacturing process of a power MOSFET structure with a reliable terminal according to claim 7, characterized in that, P-type field limiting rings are injected between the multiple loops to form a lateral potential gradient. The width and spacing of the field limiting rings adopt the same gradient design as the loops.

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