Method for manufacturing a semiconductor device and mask

Abstract

The application provides a preparation method of a semiconductor device and a mask plate. In the method, at least two MOS units are formed in a semiconductor substrate; and in a composite mask layer formed on the surface of the semiconductor substrate, regions corresponding to the at least two MOS units are formed into opening units with different opening rates. Through ion implantation and high-temperature push bonding processes performed on the opening units with different opening rates to the epitaxial layer of the semiconductor substrate, the doping concentration of the multiple doping regions formed in the body region is distributed differently according to the opening rate of the corresponding opening unit, thereby forming differentiated multi-stage opening units. In the method, the composite mask layer has high compactness and can meet the high energy requirement of ion implantation. Through one mask plate, the pattern of the light-transmitting region or the light-blocking region with different opening rates can be formed in multiple regions, the opening units with different opening rates are realized, and the ion implantation process is realized at one time, thereby greatly reducing the process cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for manufacturing a semiconductor device. This application also relates to another method for manufacturing a semiconductor device. This application further relates to a photomask. Background Technology

[0002] Traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) typically employ a single, fixed threshold voltage design. This single-threshold design often fails to balance conduction performance and switching dynamics when faced with complex switching processes, leading to a rigid trade-off in device performance. Specifically, while a low threshold voltage design can effectively reduce on-resistance, increase switching speed, and reduce switching losses, it is accompanied by an extremely fast current change rate (…). ) and voltage change rate ( Such drastic dynamic changes can easily trigger dynamic voltage and current stress and electromagnetic compatibility issues.

[0003] Conversely, if a high threshold voltage design is used to avoid dynamic voltage and current stress and electromagnetic compatibility issues, although the switching process will be smoother and effectively suppress [the problem], [the following is possible:] and However, this comes at the cost of sacrificing switching speed, resulting in a significant increase in switching losses and a reduction in the overall energy efficiency of the device.

[0004] Therefore, how to manufacture a MOSFET device that effectively suppresses high current change rate while ensuring low conduction loss and low switching loss? ) and high voltage change rate ( This leads to dynamic voltage and current stress and electromagnetic compatibility issues. Summary of the Invention

[0005] This application provides a method for manufacturing a semiconductor device that effectively suppresses high current change rate while ensuring low conduction loss and low switching loss. ) and high voltage change rate ( This application relates to dynamic voltage and current stress and electromagnetic compatibility issues caused by [the semiconductor device manufacturing process]. It also relates to another method for manufacturing semiconductor devices. Furthermore, this application relates to a photomask.

[0006] The specific plan is as follows: In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate in which at least two MOS cells are formed, wherein any MOS cell includes a first trench and a control gate formed in the first trench; forming a composite mask layer on the surface of the semiconductor substrate; forming opening cells with different aperture ratios in regions corresponding to the at least two MOS cells on the composite mask layer; performing ion implantation at target regions located on both sides of the control gate in the opening cells to form a body region; removing the composite mask layer in which the opening cells have been formed; and performing a high-temperature push-junction process to form multiple doped regions in the body region, wherein the doping concentration of the multiple doped regions is differentially distributed according to the aperture ratio of the target region corresponding to the corresponding target region.

[0007] Optionally, the control gate formed in the trench includes: a first conductive structure formed in the lower part of the trench, the lower part of the trench and the first conductive structure being isolated by a first oxide layer; a second conductive structure formed in the upper part of the trench, the upper part of the trench and the second conductive structure being isolated by a gate oxide layer; the first conductive structure and the second conductive structure being isolated by an inter-gate dielectric layer; the gate oxide layer being located on the upper sidewall of the trench and in the area of ​​the semiconductor substrate surface excluding the trench; a second oxide layer being formed on the surface of the second conductive structure; the first conductive structure serving as a shielding gate, and the second conductive structure serving as a control gate.

[0008] Optionally, forming a composite mask layer on the surface of the semiconductor substrate includes: forming a hard mask layer on the surface of the semiconductor substrate, and coating a photoresist layer on the surface of the hard mask layer, thereby forming the composite mask layer by combining the photoresist layer and the hard mask layer.

[0009] Optionally, forming a hard mask layer on the surface of the semiconductor substrate includes performing a deposition process to form a hard mask layer on the surface of the semiconductor substrate on which a gate oxide layer has been formed and on the surface of the second oxide layer.

[0010] Optionally, forming opening cells with different aperture ratios in the regions corresponding to the at least two MOS units on the composite mask layer includes: performing a photolithography process to form opening cells with different aperture ratios in the regions corresponding to the at least two MOS units on the photoresist layer; and performing an etching process to transfer the pattern of the opening cells formed in the photoresist layer to the hard mask layer.

[0011] Optionally, the at least two MOS units include at least a first MOS unit and a second MOS unit; the step of forming opening units with different aperture ratios in the regions corresponding to the at least two MOS units on the composite mask layer includes: forming a first opening unit with a first aperture ratio in the region corresponding to the first MOS unit on the composite mask layer, and forming a second opening unit with a second aperture ratio in the region corresponding to the second MOS unit, wherein the first aperture ratio is greater than the second aperture ratio.

[0012] Optionally, the step of performing ion implantation at the target regions located on both sides of the control gate in the opening unit to form a body region includes: performing ion implantation in the same ion implantation process at a first target region located on both sides of the first control gate in the first opening unit and at a second target region located on both sides of the second control gate in the second opening unit, respectively, to form the body region in the epitaxial layer of the semiconductor substrate; wherein the ion concentration implanted in the first target region is greater than the ion concentration implanted in the second target region.

[0013] Optionally, removing the composite mask layer that has formed the opening unit includes: performing dry and / or wet stripping processes to remove the photoresist layer that has formed the opening unit; and performing dry and / or wet etching processes to remove the hard mask layer that has formed the opening unit.

[0014] Optionally, the multiple doped regions include at least a first doped region corresponding to the first target region in the body region, and a second doped region corresponding to the second target region in the body region; the execution of the high-temperature push-junction process to form multiple doped regions in the body region, wherein the doping concentration of the multiple doped regions is differentially distributed with respect to the aperture ratio of the corresponding target region, includes: performing a high-temperature push-junction process on the ion-implanted semiconductor substrate according to a preset high-temperature push-junction distance and high-temperature push-junction time, so that the implanted ions in the first target region and the second target region undergo longitudinal and lateral diffusion, respectively, to form the first doped region and the second doped region; wherein the main doping concentration of the first doped region is greater than the main doping concentration of the second doped region.

[0015] Optionally, the opening unit includes a target opening unit with at least two windowed areas; wherein, in the at least two windowed areas of the target opening unit, the ratio between the opening size of the smallest windowed area and the thickness of the photoresist layer is greater than or equal to a first preset ratio, and the ratio between the minimum photoresist line width between two adjacent windowed areas and the high-temperature push-bonding distance set by the high-temperature push-bonding process is less than or equal to a second preset ratio.

[0016] Optionally, the hard mask layer includes a nitride layer including silicon nitride (SIN), silicon oxynitride (SION), silicon hydrogen nitride (SIHN), or other non-oxide film shielding layers that cannot react with hydrofluoric acid.

[0017] Optionally, the method further includes: determining the formation thickness of the hard mask layer based on the energy of the ions to be injected into the body region.

[0018] Optionally, the thickness of the hard mask layer can be any one of 2000 angstroms to 15000 angstroms.

[0019] Secondly, embodiments of this application provide a method for manufacturing a semiconductor device, characterized in that the method includes: providing a semiconductor substrate; forming a mask layer on an epitaxial layer of the semiconductor substrate; forming opening cells with different aperture ratios in different regions of the mask layer; performing ion implantation in the opening cells to form a body region; removing the mask layer from which the opening cells have been formed; and performing a high-temperature push-junction process to form multiple doped regions in the body region, wherein the doping concentration of the multiple doped regions is differentially distributed according to the aperture ratio of the opening cells corresponding to the respective target regions.

[0020] Thirdly, embodiments of this application provide a photomask, characterized in that it includes a first region and a second region; patterns of light-transmitting regions or light-blocking regions with different aperture ratios are formed in the first region and the second region respectively, wherein the semiconductor substrate regions corresponding to the first region and the second region respectively form two ion implantation regions with different concentrations.

[0021] Optionally, the photomask is used to manufacture the semiconductor device described in the first aspect embodiment.

[0022] Compared with the prior art, this application has the following advantages: The method for fabricating a semiconductor device provided in this application includes a semiconductor substrate in which at least two MOS cells are formed. Each MOS cell includes a trench and a control gate formed within the trench. A composite mask layer is formed on the surface of the semiconductor substrate. On the composite mask layer, opening cells with different aperture ratios are formed in regions corresponding to the at least two MOS cells. Ion implantation is performed in target regions located on both sides of the control gate within the opening cells to form a bulk region. This process requires the use of a high-energy ion implanter with energy exceeding a preset energy threshold. Because high-energy ions have extremely strong penetrating power, if only a single-layer mask layer is used during ion implantation, the high-energy ions will directly penetrate the single-layer mask layer, causing unintended doping in areas where ion implantation is not needed. The composite mask layer, with a thickness greater than that of a single-layer mask layer, possesses high density characteristics, ensuring that high-energy ions do not penetrate when implanted into the epitaxial layer of the semiconductor substrate from the target region corresponding to the opening region. Then, the composite mask layer that has formed the opening unit is removed; a high-temperature push-junction process is performed to form multiple doped regions in the body region. The doping concentration of these multiple doped regions varies with the aperture ratio of the opening unit corresponding to the target region. In this scheme, different opening units have different aperture ratios. Therefore, performing an ion implantation process into the epitaxial layer of the semiconductor substrate at opening units with different aperture ratios can form ion implantation regions with different ion implantation doses in the body region. Performing a high-temperature push-junction process can then form doped regions with different doping concentrations, thereby forming differentiated multi-level turn-on units. Therefore, it is possible to realize the parallel connection of multiple threshold voltage switching units on the same MOSFET device, achieving effective suppression of high current change rate (...) while ensuring low conduction loss and low switching loss. ) and high voltage change rate ( This leads to dynamic voltage and current stress and electromagnetic compatibility issues. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the first embodiment of this application.

[0024] Figure 2 This is a schematic diagram of a MOS cell formed on a semiconductor substrate, as provided in the first embodiment of this application.

[0025] Figure 3 This is a schematic diagram of the structure of forming a hard mask layer on the surface of a semiconductor substrate, as provided in the first embodiment of this application.

[0026] Figure 4 This is a schematic diagram of the structure of forming a photoresist layer on the surface of a hard mask layer, as provided in the first embodiment of this application.

[0027] Figure 5 This is a schematic diagram of the structure of forming an opening unit in the photoresist layer according to the first embodiment of this application.

[0028] Figure 6A This is a schematic diagram of a first example of a structure in which an opening unit is formed in a composite mask layer, as provided in the first embodiment of this application.

[0029] Figure 6B This is a schematic diagram of a second example of a structure in which an opening unit is formed in a composite mask layer, as provided in the first embodiment of this application.

[0030] Figure 7A This is a schematic diagram of a first example of an ion-forming region implanted in the epitaxial layer of a semiconductor substrate, provided in the first embodiment of this application.

[0031] Figure 7B This is a schematic diagram of a second example of an ion-forming region implanted in the epitaxial layer of a semiconductor substrate, provided in the first embodiment of this application.

[0032] Figure 8 This is a schematic diagram of the structure of the composite mask layer formed by removing the photoresist layer and the hard mask layer according to the first embodiment of this application.

[0033] Figure 9A This is a schematic diagram of the first example structure of forming a doped region in the in-body region according to the first embodiment of this application.

[0034] Figure 9B This is a schematic diagram of a second example of a structure in which a doped region is formed in the bulk region, as provided in the first embodiment of this application.

[0035] Figure 10 This is a schematic diagram of the structure of the opening unit formed by the composite mask layer provided in the first embodiment of this application.

[0036] Figure 11 This is a structural schematic diagram of the types of opening units provided in the first embodiment of this application.

[0037] Figure 12A This is a schematic diagram of the first example structure of a photomask provided in the third embodiment of this application.

[0038] Figure 12B This is a second example structural schematic diagram of a mask provided in the third embodiment of this application.

[0039] Figure 13 This is a schematic diagram of the pattern type of the opening area that can be formed on the mask provided in the third embodiment of this application.

[0040] In the attached figures, the following labels are used: 01-Semiconductor substrate; 02-Epipolar layer; 03-First trench; 04-First oxide layer; 05-Second trench; 06-First conductive structure; 07-Gate dielectric layer; 08-Gate oxide layer; 09-Second conductive structure; 10-Second oxide layer; 11-Hard mask layer; 12-Photoresist layer; 13-First MOS cell; 14-First aperture cell; 14-1-First control gate; 14-2-First portion of the first target region; 14-3-Second portion of the first target region; 15-Second MOS cell; 16-Second aperture cell; 16-1-First aperture cell Window area, 16-2-Second window area, 16-3-Third window area, 16-4-Fourth window area, 16-5-Fifth window area, 16-6-Second control gate, 16-7-First part of the second target area, 16-8-Second part of the second target area; 17-Body area, 17-1-First injection area, 17-2-Second injection area, 17-3-Third injection area, 17-4-Fourth injection area, 17-5-Fifth injection area, 17-6-Sixth injection area, 17-7-Seventh injection area, 17-8-Eighth injection area; 18 - First doped region, 18-1 - First part of the first doped region, 18-2 - Second part of the first doped region; 19 - Second doped region, 19-1 - First part of the second doped region, 19-2 - Second part of the second doped region; 20 - Lateral dimension of the minimum window area; 21 - Minimum photoresist line width; 22 - Thickness of the photoresist layer; 23 - First region, 23-1 - First part of the first region, 23-2 - Second part of the first region; 24 - Second region, 24-1 - Third part of the second region, 24-2 - [Missing information - likely a specific area or region] Four parts: 24-3 - the fifth part of the second region; 24-4 - the sixth part of the second region; 25 - the third opening cell; 25-1 - the sixth window region; 25-2 - the seventh window region; 25-3 - the eighth window region; 25-4 - the third control gate; 25-5 - the first part of the third target region; 25-6 - the second part of the third target region; 26 - the terminal region; 27 - the cell region; 28 - the third doped region; 28-1 - the first part of the third doped region; 28-2 - the second part of the third doped region; 29 - the third region; 30 - the fourth region. Detailed Implementation

[0041] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0042] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0043] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0044] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0045] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0046] To facilitate understanding of the various embodiments of this application, the application background of the embodiments will be explained.

[0047] Traditional MOSFET devices typically employ a single, fixed threshold voltage design. This single-threshold design often fails to balance conduction performance and switching dynamics when faced with complex switching processes, leading to a rigid trade-off in device performance. Specifically, while a low threshold voltage design can effectively reduce on-resistance (…),… This increases switching speed and reduces switching losses, but comes at the cost of an extremely fast rate of change of current ( ). ) and voltage change rate ( Such drastic dynamic changes can easily trigger dynamic voltage and current stress and electromagnetic compatibility issues. For example, current and voltage overshoot can cause gate oscillation and generate severe electromagnetic interference (EMI) noise, thereby affecting the stability of the circuit system.

[0048] Conversely, if a high threshold voltage design is used to avoid dynamic voltage and current stress and electromagnetic compatibility issues, although the switching process will be smoother and effectively suppress [the problem], [the following is possible:] and However, this comes at the cost of sacrificing switching speed, resulting in a significant increase in switching losses and a reduction in the overall energy efficiency of the device.

[0049] Therefore, how to manufacture a MOSFET device that effectively suppresses high current change rate while ensuring low conduction loss and low switching loss? ) and high voltage change rate ( This leads to dynamic voltage and current stress and electromagnetic compatibility issues.

[0050] To overcome the performance bottleneck caused by a single threshold voltage and achieve the best balance between switching losses, conduction losses and electromagnetic compatibility, this application provides a method for manufacturing a semiconductor device to realize the parallel connection of multiple threshold voltage switching units in the same MOSFET device.

[0051] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0052] First Embodiment Figure 1 The flowchart of a semiconductor device manufacturing method provided in the first embodiment of this application includes the following steps S101 to S106.

[0053] Step S101: Provide a semiconductor substrate in which at least two MOS cells are formed, wherein any MOS cell includes a trench and a control gate formed in the trench; Step S102: Form a composite mask layer on the surface of the semiconductor substrate; Step S103: On the composite mask layer, opening cells with different aperture ratios are formed in the regions corresponding to the at least two MOS cells respectively; Step S104: Ion implantation is performed in the target regions located on both sides of the control gate in the opening unit to form a bulk region; Step S105: Remove the composite mask layer that has formed the opening unit; Step S106: Perform a high-temperature push-junction process to form multiple doped regions in the body region. The doping concentration of the multiple doped regions is distributed differently according to the aperture ratio of the corresponding target region's opening unit.

[0054] The semiconductor device can be a metal-oxide-semiconductor field-effect transistor (MOSFET). This application uses a shielded gate trench power device as an example for illustration. Shielded gate trench power devices can be classified into various types according to the following methods: The first classification, based on the structure of the shielding gate, is divided into two types: top-bottom structure and left-right structure. In a top-bottom structure, the shielding gate is located at the bottom of the trench, directly below the gate. In a left-right structure, the shielding gate and gate are arranged side-by-side within the trench. The second classification, based on the semiconductor material, is divided into silicon-based shielding gate trench power devices and silicon carbide shielding gate trench power devices. The third classification, based on the type of charge carriers in the conductive channel and the polarity of the device's operating voltage, is divided into N-type shielding gate trench power devices (where the charge carrier type is electrons and a positive voltage is applied to the gate) and P-type shielding gate trench power devices (where the charge carrier type is holes and a negative voltage is applied to the gate).

[0055] This application uses a shielded grid trench type power device with an upper and lower structure as an example for illustration.

[0056] like Figures 2-11 The diagram shown is a structural schematic of a semiconductor device manufacturing method provided in the first embodiment of this application. The following is in conjunction with... Figures 2-11 The manufacturing method will be described in detail.

[0057] Step S101: Provide a semiconductor substrate in which at least two MOS cells are formed, which may include the first case of forming two MOS cells, such as... Figure 2 As shown, a second case can also be included, forming more than two MOS cells, such as... Figure 6B As shown, three MOS cells are formed in a semiconductor substrate, and aperture cells with three different aperture ratios are formed in the regions corresponding to these three MOS cells. Alternatively, more than three MOS cells can be formed in the semiconductor substrate, and so on. Each MOS cell includes a trench and a control gate formed within the trench.

[0058] The at least two MOS cells formed in the semiconductor substrate can be MOS cells with the same internal structure, for example, both being MOS cells with the same internal structure. Figure 2 The shielded gate trench power device shown may also contain MOS cells with different internal structures; for example, some MOS cells may only be control gates, while others may be... Figure 2 The shielded trench power device shown is illustrated below. The following explanation uses two identical shielded trench power devices as an example.

[0059] The control gate formed in the trench includes: a first conductive structure formed in the lower part of the trench, the lower part of the trench and the first conductive structure being isolated by a first oxide layer; a second conductive structure formed in the upper part of the trench, the upper part of the trench and the second conductive structure being isolated by a gate oxide layer; the first conductive structure and the second conductive structure being isolated by an inter-gate dielectric layer; the gate oxide layer being located on the upper sidewall of the trench and in the area of ​​the semiconductor substrate surface excluding the trench; a second oxide layer being formed on the surface of the second conductive structure; the first conductive structure serving as a shielding gate and the second conductive structure serving as a control gate.

[0060] like Figure 2 As shown, an epitaxial layer 02 is formed on a semiconductor substrate 01, and a trench, for example, a first trench 03, is formed on the epitaxial layer 02. A first oxide layer 04 is formed on the sidewalls and bottom wall of the first trench 03 through a thermal oxidation process and / or a deposition process, thereby forming a second trench 05 within the first trench 03. A first conductive material is filled into the second trench 05 to form a first conductive structure 06. Then, an inter-gate dielectric layer 07 is formed on the first conductive structure 06. A gate oxide layer 08 is formed on the sidewalls of the first trench 03 (where part of the first oxide layer has been removed) and on the surface of the semiconductor substrate 01, excluding the first trench 03. Finally, a second conductive material is filled over the inter-gate dielectric layer 07 within the first trench 03 and over the remaining first oxide layer 04 to form a second conductive structure 09. The first conductive structure 06 serves as a shielding gate, and the second conductive structure 09 serves as a control gate. Then, a second oxide layer 10 is formed on the surface of the second conductive structure 09, wherein the top surface of the second oxide layer 10 is lower than the top surface of the gate oxide layer 08 on the surface of the semiconductor substrate.

[0061] Generally, in semiconductor manufacturing, a semiconductor substrate is the base used to form semiconductor devices. Semiconductor substrate materials include, but are not limited to, pure single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The material of the semiconductor substrate can be selected according to actual needs during the fabrication process. Specifically, in this embodiment, silicon is used as the material for manufacturing the substrate, and semiconductor substrate 01 is provided.

[0062] An epitaxial layer 02 is grown on the semiconductor substrate 01; a first dielectric layer is formed on the top surface of the epitaxial layer 02; a trench pattern is formed in the first dielectric layer by photolithography; using the first dielectric layer with the trench pattern as a protective layer, the epitaxial layer not covered by the first dielectric layer is etched to form a first trench 03 in the epitaxial layer 02.

[0063] An epitaxial layer 02 is grown on the semiconductor substrate 01. Generally, the epitaxial layer 02 is a thin layer of material deposited on the substrate 01 by an epitaxial growth process. The material used for the epitaxial layer 02 can be the same as or different from the material used for the semiconductor substrate 01. Epitaxial growth techniques can include chemical vapor deposition (CVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and vapor phase epitaxy (VPE). Specifically, in this embodiment, CVD is used to grow the epitaxial layer 02. A first dielectric layer (not shown in the figure) is formed on the top surface of the epitaxial layer 02. The material of the first dielectric layer needs to have high corrosion resistance, thermal stability, and etching selectivity, and can include silicon oxide, silicon nitride, etc. In this embodiment, silicon oxide is used as an example for the first dielectric layer. The silicon oxide can be formed by thermal oxidation or deposition, which will not be elaborated here.

[0064] After forming the first dielectric layer, a trench pattern for forming the first trench 03 is defined using photolithography. Then, the trench pattern is transferred to the first dielectric layer through etching, and etching continues to form the first trench 03. Trench etching methods include deep reactive ion etching, wet etching, plasma etching, and reactive ion etching. The number of trenches can be arranged according to the functional requirements of the actual semiconductor device. In this embodiment, forming three first trenches 03 is used as an example for illustration. Figure 2 In the diagram, the first trench 03 is located in the terminal region 26, and the second and third trenches 03 are located in the cell region 27. The cell region 27 is a region formed by an array of first trenches 03 including a shielding gate and a control gate.

[0065] After forming the first trench 03, the first dielectric layer remaining on the top surface of the epitaxial layer is removed. In other processes, it is also possible to omit the first dielectric layer and instead use photoresist directly as a mask layer to form the subsequent first trench 03. After forming the first trench 03, the photoresist is removed.

[0066] Subsequently, a first oxide layer 04 is formed on the sidewalls and bottom wall of the first trench 03 by a thermal oxidation process and / or a deposition process, thereby forming a second trench 05 within the first trench 03.

[0067] After filling the second trench 05 with the first conductive material, an etching process is then performed to etch the first oxide layer 04 to a first predetermined depth and the first conductive material to a second predetermined depth, where the first predetermined depth is less than the second predetermined depth. The first conductive material and the subsequent second conductive material can be the same conductive material or different conductive materials. The conductive material can be polycrystalline silicon or other conductive materials, such as metals (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu)).

[0068] The first predetermined depth refers to the depth from the surface of the first oxide layer after etching to the top surface of the epitaxial layer of the semiconductor substrate. For example... Figure 2 As shown, based on the shape forming the control gate, the upper surface of the first oxide layer after etching is concave, wherein the depth at the edge of the first oxide layer 04 located on the two sidewalls of the first trench 03 is greater than the depth at the center. The second set depth is the depth of the top surface of the first conductive structure 06 from the top surface of the epitaxial layer of the semiconductor substrate. In this application, unless otherwise specified, the set depth is the dimension extending from the top surface of the epitaxial layer into the interior of the semiconductor substrate, using the top surface of the epitaxial layer as a reference point. Other set depths appearing in the following description are defined in this way. Of course, all set depths can also be described using other reference points.

[0069] Subsequently, a thermal oxidation process is performed on the top surface of the first conductive structure 06 to grow the inter-gate dielectric layer 07 in situ. The inter-gate dielectric layer 07 generated in this way has good density, which can effectively ensure the stability and reliability of transistor performance. The material of the inter-gate dielectric layer may include silicon dioxide.

[0070] Subsequently, a high-density plasma chemical vapor deposition process is performed to form a gate oxide layer 08 on the upper part of the sidewall within the first trench 03 and on the surface of the semiconductor substrate 01, excluding the first trench 03.

[0071] Subsequently, the upper portion of the first trench 03 is filled with a second conductive material to form a second conductive structure 09, which serves as a control gate. A thermal oxidation process is then performed on the surface of the control gate to form a second oxide layer 10.

[0072] The above describes the formation process of the control grid within the trench.

[0073] Step S102: Form a composite mask layer on the surface of the semiconductor substrate.

[0074] This step employs a composite mask layer to increase its thickness, thereby resisting the penetration of high-energy ions during ion implantation. With a single-layer mask, high-energy ions would directly penetrate it, causing unintended doping in areas where ion implantation is not intended. Therefore, a composite mask layer is used in this step to prevent penetration when high-energy ions are implanted into the epitaxial layer of the semiconductor substrate from the target area corresponding to the opening region of the composite mask layer in subsequent steps.

[0075] The composite mask layer is formed on the surface of the semiconductor substrate in one of the following ways: a hard mask layer is formed on the surface of the semiconductor substrate, and a photoresist layer is coated on the surface of the hard mask layer, thereby forming the composite mask layer by combining the photoresist layer and the hard mask layer.

[0076] like Figure 3 As shown, a deposition process is performed to form a hard mask layer 11 on the surface of a semiconductor substrate with a gate oxide layer 08 and on the surface of the second oxide layer 10. The hard mask layer 11 includes a nitride layer comprising any one of silicon nitride (SIN), silicon oxynitride (SION), or silicon hydrogen nitride (SIHN), or other non-oxide shielding layers that cannot react with hydrofluoric acid. Figure 4 As shown, a photoresist layer 12 is coated on the surface of the hard mask layer 11.

[0077] Generally, the thinner the photoresist layer, the shorter the scattering of light, the standing wave effect, and the lateral diffusion path of photogenerated acid within the layer, thus enabling clearer definition of micro-patterns and achieving higher resolution. However, if the photoresist layer is too thin, the pattern structure may lack strength, easily collapse, or develop pinhole defects, making it impossible to maintain the image structure in subsequent etching or ion implantation processes. Therefore, in this embodiment, the photoresist layer 12 and the hard mask layer 11 are chosen to form a composite mask layer. Opening units containing various sizes of openings are formed in corresponding areas on both the photoresist layer 12 and the hard mask layer 11. The thickness of the photoresist layer 12 is less than a first preset thickness, and the thickness of the hard mask layer 11 is greater than a second preset thickness, which in turn is greater than the first preset thickness. The thinner photoresist layer 12 is chosen here to form a small-sized window region on the photoresist layer 12, with a window size smaller than the preset window size. This ensures that the photoresist in this area is thoroughly cleaned during development after photolithography of the small-sized window region, avoiding development residue in the small-sized opening region due to excessively thick photoresist. Simultaneously, a thicker hard mask layer 11 is chosen because it possesses high density characteristics, preventing penetration when high-energy ions are implanted into the epitaxial layer of the semiconductor substrate from the target region corresponding to the opening region. Therefore, the thickness of the hard mask layer 11 is related to the ion energy required for implantation in the body region. The formation thickness of the hard mask layer 11 is determined based on the ion energy required for implantation in the body region. The formation thickness of the hard mask layer 11 is any value between 2000 angstroms and 15000 angstroms. For example, the thickness of the hard mask layer 11 can be 2000 angstroms, 3000 angstroms, 4000 angstroms, 5000 angstroms, 6000 angstroms, 7000 angstroms, 8000 angstroms, 9000 angstroms, 10000 angstroms, 11000 angstroms, 12000 angstroms, 13000 angstroms, 14000 angstroms, or 15000 angstroms, or other values ​​in the range of 2000 angstroms to 15000 angstroms.

[0078] Step S103: On the composite mask layer, an opening cell with different aperture ratios is formed in the region corresponding to the at least two MOS cells respectively.

[0079] Existing technologies typically employ multi-level gate oxide layers to achieve multiple aperture cells, thereby creating multi-level threshold switching voltages in the body region. Alternatively, multiple sets of masks are used during body implantation, with multi-level threshold voltages usually achieved by controlling the ion implantation dose of different memory cells or transistor channel regions. Here, the mask determines which cells need to be implanted with ions. For example, the first mask may only cover part of the cells to obtain a basic threshold voltage; the second mask then covers another part of the cells for secondary implantation, thereby obtaining a higher threshold voltage. Both of these existing technologies increase manufacturing costs. In this step, patterns containing transparent or opaque regions with different aperture ratios can be formed in multiple areas on a single mask. By processing multiple regions in a single mask, multiple aperture cells with different aperture ratios are formed in the composite mask layer on the semiconductor substrate, corresponding to multiple MOS cells. Subsequently, by performing a single ion implantation process, each aperture cell has a different dopant ion concentration in the doped region corresponding to the body region, thereby forming a multi-level threshold voltage parallel switching unit. Compared with the aforementioned existing technologies, this method saves manufacturing costs.

[0080] The accompanying drawings provided in this application illustrate a switching unit with two threshold voltages, formed by creating two doped regions with different ion concentration distributions using two open cells as an example. In actual manufacturing, multiple MOS cells with different aperture ratios can be formed in the cell region on the semiconductor substrate, thereby creating doped regions with various ion concentration distributions to achieve a multi-level threshold voltage parallel switching unit.

[0081] The following explanation uses an example of at least two MOS cells, including at least a first MOS cell and a second MOS cell. On the composite mask layer, a first aperture cell with a first aperture ratio is formed in the region corresponding to the first MOS cell, and a second aperture cell with a second aperture ratio is formed in the region corresponding to the second MOS cell. The first aperture ratio is greater than the second aperture ratio. Figure 6A In the composite mask layer, a first opening unit 14 is formed in the region corresponding to the first MOS unit 13, and a second opening unit 16 is formed in the region corresponding to the second MOS unit 15. The specific process of forming the opening units on the composite mask layer can be found in [reference needed]. Figure 5 and Figure 6A .

[0082] like Figure 5 As shown, a photolithography process is performed to form aperture cells with different aperture ratios in the regions corresponding to the at least two MOS cells on the photoresist layer 12. For example, Figure 5 The first opening unit 14 and the second opening unit 16 are in the middle. Figure 5Taking two open cells as an example, in practical applications, multiple MOS cells can be formed on a semiconductor substrate, and an open cell is formed in the region corresponding to each MOS cell.

[0083] The aperture ratio represents the ratio between the area of ​​the windowed region in an opening unit and the total area of ​​the opening unit. Various opening units with different aperture ratios can be formed by using different opening patterns and / or combinations of windowed region sizes. The opening patterns of the opening units can include various types. For example, the opening pattern can be any pattern selected from stripes, circles, squares, and polygons, such as... Figure 11 Various opening patterns for different opening units are shown. The opening size of the window region can also include multiple dimensions. For example, the opening size of the window region in the first opening unit 14 is such that the lateral dimension of the window region is the same as the total lateral dimension of the opening unit. As another example, the second opening unit 16 contains five window regions, where the lateral dimension of each window region is smaller than the total lateral dimension of the second opening unit. The lateral dimension is a dimension perpendicular to the depth direction of the semiconductor substrate.

[0084] In this embodiment, the opening pattern of the opening unit is a strip pattern as an example. The ratio between the area of ​​the window region in the first opening unit 14 and the total area of ​​the opening unit is 1, indicating that the opening unit contains a complete window region. The second opening unit 16 contains multiple small-sized window regions, such as... Figure 6A In this second opening unit 16, there are five opening areas (i.e., the first opening area 16-1, the second opening area 16-2, the third opening area 16-3, the fourth opening area 16-4, and the fifth opening area 16-5). Between any two opening areas, there is an unremoved photoresist layer and a corresponding hard mask layer. Therefore, the ratio of the area of ​​the opening area in the second opening unit 16 to the total area of ​​the opening units is less than 1.

[0085] After the required opening units are formed in the photoresist layer 12, such as Figure 6A As shown, an etching process is performed to transfer the pattern of the opening units formed in the photoresist layer 12 to the hard mask layer 11. Specifically, the first corresponding region of the hard mask layer 11 is etched along the first opening unit 14 formed in the photoresist layer 12, and the second corresponding region of the hard mask layer 11 is etched along the second opening unit 16 formed in the photoresist layer 12, until the surface of the gate oxide layer 08 or the second oxide layer 10 below the hard mask layer 11 is exposed. Thus, the first opening unit 14 and the second opening unit 16 are both opening units that penetrate different regions of the photoresist layer 12 and the hard mask layer 11.

[0086] The above describes the formation of two different aperture ratios in a semiconductor substrate using a single mask. Furthermore, it is also possible to form more than two different aperture ratios in a semiconductor substrate using a single mask, for example, as shown below. Figure 6B In this process, three types of aperture units with different aperture ratios are formed in a semiconductor substrate using a mask: a first aperture unit 14 with a first aperture ratio, a second aperture unit 16 with a second aperture ratio, and a third aperture unit 25 with a third aperture ratio. The first aperture unit 14 and the second aperture unit 16 are the aperture units described above. The third aperture unit 25 includes three window regions, for example, a sixth window region 25-1, a seventh window region 25-2, and an eighth window region 25-3. The seventh window region 25-2 corresponds to the region where the MOS cell is located in the epitaxial layer of the semiconductor substrate, and the sixth window region 25-1 and the eighth window region 25-3 are the operation regions for subsequent ion implantation.

[0087] As can be seen, compared with the first opening unit 14 and the second opening unit 16, the lateral dimensions of the sixth window region 25-1 and the eighth window region 25-3 in the third opening unit 25 are smaller than the dimensions of the ion implantation window region corresponding to the first opening unit 14, and larger than the lateral dimensions of the ion implantation window regions corresponding to the second opening unit 16 (i.e., the first window region 16-1, the second window region 16-2, the fourth window region 16-4, and the fifth window region 16-5).

[0088] Therefore, the order of the aperture ratios of the three aperture units from largest to smallest is as follows: the first aperture ratio corresponding to the first aperture unit 14, the third aperture ratio corresponding to the third aperture unit 25, and the second aperture ratio corresponding to the second aperture unit 16. The larger the aperture ratio, the higher the dopant ion concentration in the corresponding doped region, and consequently, the higher the turn-on voltage formed in that doped region. Thus, a MOS cell with three parallel turn-on voltages is formed in three doped regions on the epitaxial layer of the semiconductor substrate through a single process (forming three aperture units with different aperture ratios in one step using a mask and a single ion implantation process).

[0089] This explanation uses the example of forming a MOS cell with three parallel turn-on voltages in a semiconductor substrate. Furthermore, the method provided in this application can also be used to form MOS cells with multiple parallel turn-on voltages in multiple regions on the epitaxial layer of a semiconductor substrate in a single process, namely, forming multiple aperture cells with different aperture ratios in one step and performing a single ion implantation process. Compared to existing technologies, the method provided in this application significantly reduces manufacturing costs.

[0090] It should be noted that for an opening unit consisting of multiple small-sized window areas, the size of the window area is related to the thickness of the photoresist layer and the high-temperature push distance in the subsequent high-temperature push process as follows: The opening unit includes a target opening unit with at least two opening regions. In the at least two opening regions of the target opening unit, the ratio between the opening size of the smallest opening region and the thickness of the photoresist layer is greater than or equal to a first preset ratio, and the ratio between the minimum photoresist line width between two adjacent opening regions and the high-temperature push-bonding distance set by the high-temperature push-bonding process is less than or equal to a second preset ratio.

[0091] Target opening element, such as Figure 5 The second opening unit 16 includes five window areas. A schematic diagram of the opening unit can be found in [reference needed]. Figure 10 The ratio between the window size of the minimum window area and the thickness of the photoresist layer is greater than or equal to a first preset ratio (e.g., 1 / 4), which is expressed by the following formula 1: Formula 1 Where Space Cdmin represents the window size of the minimum window opening area, such as... Figure 10 In the middle, the lateral dimension of the smallest window area is 20, which is the dimension perpendicular to the depth direction of the semiconductor substrate.

[0092] : Indicates the thickness of the photoresist layer, 22, such as Figure 10 In this context, the thickness of the photoresist layer in the depth direction of the semiconductor substrate is considered.

[0093] The relationship between the minimum window size and the photoresist layer thickness, determined by Formula 1, ensures that the minimum window area formed by the photolithography process on the photoresist layer can be properly developed. Specifically, the photolithography process includes coating the photoresist layer, soft drying, alignment and exposure (precisely aligning the mask pattern with the wafer and irradiating it with a specific light source to induce a photochemical reaction in the photoresist, completing the pattern transfer), post-exposure baking, and development (using a developer to wash away the reacted portions of the photoresist, revealing a three-dimensional geometric pattern on the wafer, forming...). Figure 5 or Figure 10The aforementioned opening unit), hard baking, and inspection. Therefore, when the opening size of the minimum opening region is too small and the photoresist layer is too thick, the developer is difficult to smoothly penetrate into the bottom of the photoresist layer due to surface tension, easily resulting in developer residue; at the same time, during the rinsing and drying stages, the capillary pull between the slits can easily cause the slender, high aspect ratio photoresist structure in the minimum opening region to bend, collapse, or stick together; in addition, the light scattering effect in the thick photoresist layer will also reduce the effective exposure dose at the bottom of the pattern, resulting in sidewall tilting or incomplete development. Therefore, the proportional relationship between the opening size of the minimum opening region and the thickness of the photoresist layer, as determined by Formula 1, is a necessary process boundary to ensure that the micro-pattern can maintain structural stability and morphological integrity after development.

[0094] The ratio between the minimum photoresist line width between two adjacent windowed areas and the high-temperature push-bonding distance set in the high-temperature push-bonding process is less than or equal to a second preset ratio (e.g., 2), which is the following formula 2: Formula 2 in, This represents the minimum photoresist line width between two adjacent windowed areas, such as... Figure 10 In the figure, the minimum photoresist line width 21 represents the lateral dimension of the smallest unetched photoresist line between two adjacent windowed areas.

[0095] , represents the high-temperature push-bonding distance in the subsequent high-temperature push-bonding process. It indicates the distance between the final position of the ions and the initial implantation position after the longitudinal and lateral diffusion of the ions in the body region is completed following the high-temperature push-bonding process.

[0096] During the subsequent ion implantation process, ions enter the implantation region within the epitaxial layer of the semiconductor substrate through the windowed area. The photoresist lines between two adjacent windowed areas block the silicon wafer region between the corresponding two adjacent implantation regions within the epitaxial layer, thus preventing ion implantation in that silicon wafer region. In the subsequent high-temperature push-through process, ions in the implanted region diffuse both vertically and horizontally. Vertical diffusion refers to diffusion along the depth direction of the implantation region, while horizontal diffusion refers to diffusion along the lateral direction within the silicon wafer between two adjacent implantation regions, penetrating the silicon wafer to ensure uniform ion diffusion between adjacent implantation regions.

[0097] If the width of the photoresist line between two adjacent window areas ( Exceeding the high-temperature bonding distance ( If the number of implanted ions is twice that of the volume region, ions from two adjacent implanted regions in the volume region will be unable to penetrate the silicon wafer between the two adjacent implanted regions. This will result in blank areas without doped ions on the silicon wafer, leading to isolated doped regions inside the silicon wafer. This will prevent the formation of a continuous volume region and ultimately cause the failure of the device's electrical properties.

[0098] Therefore, the proportional value in Formula 2 is set so that after ions are injected into multiple adjacent window regions of the same opening unit into multiple corresponding adjacent injection regions of the body region, the doped ions in multiple corresponding adjacent injection regions can diffuse evenly in the lateral and longitudinal directions after the high-temperature push-junction process, thereby forming a doped region with uniform doped ion distribution.

[0099] The above describes the process of forming opening units with different aperture ratios in the composite mask layer in step S103. Based on the different aperture ratios of the various opening units, the ion implantation concentration at the opening unit is improved, thereby forming multiple doped regions in the bulk region to improve the carrier concentration distribution. This enables the formation of differentiated multi-level turn-on units by utilizing the equivalent carrier concentration differences of different doped regions, thereby achieving control of multi-level threshold voltages.

[0100] Step S104: Ion implantation is performed in the target regions located on both sides of the control gate in the opening unit to form a body region.

[0101] like Figure 7A As shown, in the same ion implantation process, ion implantation is performed at the first target region located on both sides of the first control gate 14-1 in the first opening unit 14 and at the second target region located on both sides of the second control gate 16-6 in the second opening unit 16, so as to form the body region 17 in the epitaxial layer of the semiconductor substrate; wherein the ion concentration implanted in the first target region is greater than the ion concentration implanted in the second target region.

[0102] like Figure 7A As shown, the first target region, including its first portion 14-2 and second portion 14-3, is a fully open region with no photoresist lines or hard mask layer lines obstructing the view. The second target region, including its first portion 16-7 and second portion 16-8, is composed of multiple different open-window regions, with composite mask layer lines obstructing the view between these regions. Therefore, the aperture ratio of the first target region is greater than that of the second target region.

[0103] During ion implantation, doped ions are implanted from two portions of the first target region into the corresponding implantation regions within the epitaxial layer, such as... Figure 7AThe first implantation region 17-1 and the second implantation region 17-2 are shown in the image. Neither of these two implantation regions contains any silicon wafer areas obscured by the composite mask layer; therefore, both implantation regions are implanted with dopant ions.

[0104] Doped ions implanted from multiple windowed regions of the second target region are implanted into corresponding regions within the epitaxial layer, such as... Figure 7A The third implantation region 17-3, the fourth implantation region 17-4, the fifth implantation region 17-5, and the sixth implantation region 17-6 are shown. There are shielded silicon wafer areas between the third implantation region 17-3 and the fourth implantation region 17-4 that have not been implanted with doped ions, and there are also shielded silicon wafer areas between the fifth implantation region 17-5 and the sixth implantation region 17-6 that have not been implanted with doped ions.

[0105] Therefore, the aperture ratio of the first target region is greater than that of the second target region. Consequently, the ion concentration of the injection regions corresponding to the first target region (i.e., the first injection region 17-1 and the second injection region 17-2) is greater than that of the injection regions corresponding to the second target region (i.e., the third injection region 17-3, the fourth injection region 17-4, the fifth injection region 17-5, and the sixth injection region 17-6).

[0106] The above describes what corresponds to Figure 6A The two open units perform the description process of ion implantation.

[0107] Correspondingly, with Figure 6B Corresponding to the three open units, Figure 7B In the same ion implantation process, ion implantation is performed at a first target region located on both sides of the first control gate 14-1 in the first opening unit 14, at a second target region located on both sides of the second control gate 16-6 in the second opening unit 16, and at a third target region located on both sides of the third control gate 25-4 in the third opening unit 25, so as to form the body region 17 in the epitaxial layer of the semiconductor substrate; wherein the ion concentration implanted in the first target region is greater than the ion concentration implanted in the third target region, and the ion concentration implanted in the third target region is greater than the ion concentration implanted in the second target region.

[0108] The descriptions of the first and second target areas can be found above.

[0109] The third target region comprises a first part 25-5 and a second part 25-6, each including a windowed area with composite mask layer lines blocking the windowed area on both sides. Therefore, the aperture ratio of the third target region is smaller than that of the first target region but larger than that of the second target region.

[0110] Therefore, after performing one ion implantation process, the doped ions implanted from the two parts of the third target region are respectively implanted into the corresponding regions within the epitaxial layer, such as... Figure 7B The seventh implantation region 17-7 and the eighth implantation region 17-8 are shown in the diagram. The two sides corresponding to the seventh implantation region 17-7 and the eighth implantation region 17-8 are respectively shielded silicon wafer areas that have not been implanted with doped ions. Therefore, the ion concentration obtained in the implantation region corresponding to the third target region is lower than the ion concentration in the implantation region corresponding to the first target region, but higher than the ion concentration in the implantation region corresponding to the second target region.

[0111] Step S105: Remove the composite mask layer that has formed the opening unit.

[0112] like Figure 8 As shown, a dry stripping and / or wet stripping process is performed to remove the photoresist layer 12 that has formed the opening unit; a dry etching and / or wet etching process is performed to remove the hard mask layer 11 that has formed the opening unit.

[0113] Step S106: Perform a high-temperature push-junction process to form multiple doped regions in the body region. The doping concentration of the multiple doped regions is distributed differently according to the aperture ratio of the corresponding target region's opening unit.

[0114] like Figure 9A As shown, the multiple doped regions include at least a first doped region 18 corresponding to the first target region in the body region, and a second doped region 19 corresponding to the second target region in the body region. The high-temperature push-bond process, which forms multiple doped regions in the body region, wherein the doping concentration of each multiple doped region is differentially distributed according to the aperture ratio of the corresponding target region's opening unit, includes: performing a high-temperature push-bond process on the ion-implanted semiconductor substrate according to a preset high-temperature push-bond distance and time, so that the implanted ions in the first target region and the second target region undergo longitudinal and lateral diffusion, respectively, to form the first doped region and the second doped region; wherein the main doping concentration of the first doped region is greater than the main doping concentration of the second doped region. The multiple doped regions correspond to different turn-on voltages.

[0115] Among them, such as Figure 9A As shown, the first doped region includes a first portion 18-1 and a second portion 18-2. The second doped region includes a first portion 19-1 and a second portion 19-2.

[0116] The high-temperature push-junction process diffuses dopant ions implanted in the body region to predetermined positions at high temperatures, repairing lattice damage and ultimately forming a stable PN junction. The set high-temperature push-junction time and distance are designed to ensure complete fusion of the implanted ions in the body region. Specifically, in the implantation region corresponding to the first target region of the first opening unit, the dopant ions implanted in the first implantation region 17-1 diffuse longitudinally to the predetermined push-junction depth and diffuse uniformly laterally, forming the first portion 18-1 of the first doped region. The dopant ions implanted in the second implantation region 17-2 diffuse longitudinally to the predetermined push-junction depth and diffuse uniformly laterally, forming the second portion 18-2 of the first doped region.

[0117] In the implantation region corresponding to the second target region of the second opening unit, the dopant ions implanted in the third implantation region 17-3 and the fourth implantation region 17-4 diffuse longitudinally to the predetermined push-junction depth and penetrate laterally through the silicon wafer between the third implantation region 17-3 and the fourth implantation region 17-4, achieving uniform lateral distribution and forming the first part 19-1 of the second doped region. The dopant ions implanted in the fifth implantation region 17-5 and the sixth implantation region 17-6 diffuse longitudinally to the predetermined push-junction depth and penetrate laterally through the silicon wafer between the fifth implantation region 17-5 and the sixth implantation region 17-6, achieving uniform lateral distribution and forming the second part 19-2 of the second doped region.

[0118] Therefore, the doped ion concentration in the second doped region is lower than that in the first doped region. Correspondingly, the equivalent carrier concentration in the second doped region is lower than that in the first doped region, thus achieving different aperture ratios in the opening units of different regions of the composite mask layer, and realizing the difference in equivalent carrier concentration in different doped regions of the bulk region. By connecting two threshold voltage switching units in parallel on the same MOSFET device, low conduction losses and low switching losses are achieved while effectively suppressing the effects of high current change rate (…). ) and high voltage change rate ( This leads to dynamic voltage and current stress and electromagnetic compatibility issues.

[0119] The above is with Figure 6A , Figure 7A Correspondingly, after simultaneously forming opening cells with two different aperture ratios in a semiconductor substrate, a doped region with two dopant ion concentrations is formed in the bulk region, thereby forming a MOS cell with two threshold turn-on voltages.

[0120] The following description and Figure 6B , Figure 7BCorrespondingly, after simultaneously forming opening cells with three different aperture ratios in a semiconductor substrate, a doped region with three different dopant ion concentrations is formed in the bulk region, thereby forming a MOS cell with three threshold turn-on voltages.

[0121] like Figure 9B As shown, the multiple doped regions include at least a first doped region 18 corresponding to the first target region in the body region, a second doped region 19 corresponding to the second target region in the body region, and a third doped region 28 corresponding to the third target region in the body region. The high-temperature push-junction process, which forms multiple doped regions in the body region, wherein the doping concentration of each multiple doped region is differentially distributed according to the aperture ratio of the corresponding target region's aperture unit, includes: performing a high-temperature push-junction process on the ion-implanted semiconductor substrate according to a preset high-temperature push-junction distance and time, so that the implanted ions in the first target region, second target region, and third target region undergo longitudinal and lateral diffusion, respectively, to form the first doped region, second doped region, and third doped region; wherein the main doping concentration of the first doped region is greater than the main doping concentration of the third doped region, and the main doping concentration of the third doped region is greater than the main doping concentration of the third doped region. The multiple doped regions correspond to different turn-on voltages.

[0122] Accordingly, the first doped region corresponds to the first threshold turn-on voltage, the second doped region corresponds to the second threshold turn-on voltage, and the third doped region corresponds to the third threshold turn-on voltage. The first threshold is greater than the third threshold, and the third threshold is greater than the second threshold.

[0123] Among them, such as Figure 9B As shown, the first doped region includes a first portion 18-1 and a second portion 18-2. The second doped region includes a first portion 19-1 and a second portion 19-2. The third doped region includes a first portion 28-1 and a second portion 28-2.

[0124] In the implantation region corresponding to the third target region of the third opening unit, the dopant ions implanted in the seventh implantation region 17-7 diffuse longitudinally to the predetermined push-junction depth and penetrate the silicon wafers on both sides of the seventh implantation region 17-7 laterally, achieving uniform lateral distribution and forming the first part 28-1 of the third doped region. The dopant ions implanted in the eighth implantation region 17-8 diffuse longitudinally to the predetermined push-junction depth and penetrate the silicon wafers on both sides of the eighth implantation region 17-8 laterally, achieving uniform lateral distribution and forming the second part 28-2 of the third doped region.

[0125] Therefore, the doped ion concentration in the first doped region is greater than that in the third doped region, and the doped ion concentration in the third doped region is greater than that in the second doped region. Correspondingly, the equivalent carrier concentration in the first doped region is greater than that in the third doped region, and the equivalent carrier concentration in the third doped region is greater than that in the second doped region. This allows for different aperture ratios in the opening units of different regions of the composite mask layer, achieving differences in the equivalent carrier concentration of different doped regions in the bulk region. By connecting three threshold voltage switching units in parallel on the same MOSFET device, low conduction losses and low switching losses are effectively suppressed by high current change rates (…). ) and high voltage change rate ( This leads to dynamic voltage and current stress and electromagnetic compatibility issues.

[0126] The method provided in this application is illustrated above by using the example of forming two-stage or three-stage threshold voltages in parallel. In fact, the method provided in this application can achieve the following effects: Through a single process, multiple regions on the composite mask layer are formed with aperture units of different aperture ratios. Based on the different aperture ratios of these multiple aperture units, a doped region with different ion implantation concentrations is formed within the semiconductor epitaxial layer corresponding to each aperture region, thereby forming parallel multi-stage threshold threshold voltages. Furthermore, the composite mask layer consists of a thinner photoresist layer and a thicker hard mask layer. Here, the photoresist layer meets the requirements for the opening area of ​​small-sized apertures, and the thickness of the composite mask layer can meet the penetration intensity of high-energy ions during the ion implantation process, avoiding ion implantation into other non-implanted areas.

[0127] Furthermore, in this application, opening cells with different aperture ratios are formed on the composite mask layer in regions corresponding to multiple MOS cells. This can be achieved by forming patterns of light-transmitting or light-blocking regions with different aperture ratios in multiple different regions on a single mask. The composite mask layer on the semiconductor substrate is etched to form the corresponding opening cells, and an ion implantation process is performed to implant ions into the corresponding regions of the body region in multiple corresponding opening cells. After a high-temperature push-bonding process, multiple levels of parallel turn-on voltages are formed in the multiple doped regions corresponding to the body region. The more patterns of light-transmitting or light-blocking regions with different aperture ratios formed on the same mask, the more opening cells with different aperture ratios formed on the composite mask layer on the epitaxial layer of a semiconductor substrate, and correspondingly, the more doped regions with different turn-on voltages formed in the body region, thus saving on manufacturing costs.

[0128] Second Embodiment The second embodiment of this application provides a method for manufacturing a semiconductor device. The method includes: providing a semiconductor substrate; forming a mask layer on an epitaxial layer of the semiconductor substrate; forming opening cells with different aperture ratios in different regions of the mask layer; performing ion implantation in the opening cells to form a body region; removing the composite mask layer from which the opening cells have been formed; and performing a high-temperature push-junction process to form multiple doped regions in the body region, wherein the doping concentration of the multiple doped regions is differentially distributed with respect to the opening size of the corresponding opening cell.

[0129] The method provided in the second embodiment can be applied to any opening unit with different aperture ratios in different regions of a semiconductor substrate, forming doped regions with different implanted ion concentrations in the bulk region, thereby achieving different carrier distributions in different doped regions, and thus forming differentiated multi-level threshold parallel switching voltages.

[0130] The mask layer provided in the second embodiment can be the composite mask layer provided in the first embodiment, for example, it is composed of a thinner photoresist layer and a thicker hard mask layer. The thinner photoresist layer can satisfy the requirement of forming small-sized window regions with an opening size smaller than a preset opening size threshold in some opening cells. In addition, the composite mask layer has a larger thickness and high density, which can ensure that high-energy ions are not penetrated when injected into the epitaxial layer of the semiconductor substrate from the target region corresponding to the opening region.

[0131] Third Embodiment The third embodiment of this application provides a photomask, such as Figure 12A As shown, the photomask is used to manufacture the semiconductor device described in the first embodiment. The photomask includes a first region 23 and a second region 24; patterns of light-transmitting or light-blocking regions with different aperture ratios are formed in the first region 23 and the second region 24, thereby enabling the first region 23 and the second region 24 to correspond to two ion implantation regions with different target concentrations on the semiconductor substrate.

[0132] Figure 12A This illustration is merely to demonstrate the existence of first and second regions with different aperture ratios in a photomask. In actual applications, the photomask contains multiple repeating first and second regions. The following description uses a single first and second region as an example.

[0133] The first aperture ratio corresponding to the pattern of the light-transmitting or light-blocking area of ​​the first region 23 is greater than the aperture ratio corresponding to the pattern of the light-transmitting or light-blocking area of ​​the second region 24. For example, the pattern of the first region 23 of the mask can form the first opening unit in the first embodiment, and the pattern of the second region 24 of the mask can form the second opening unit in the first embodiment.

[0134] Specifically, the first region 23 includes a first portion 23-1 and a second portion 23-2, both of which are complete light-transmitting or light-blocking areas. The first aperture ratio corresponding to the first region 23 is the ratio of the sum of the light-transmitting areas of the first portion 23-1 and the second portion 23-2 to the total area of ​​the first region 23, or the ratio of the sum of the light-blocking areas of the first portion 23-1 and the second portion 23-2 to the total area of ​​the first region 23.

[0135] The second region 24 includes a third part 24-1, a fourth part 24-2, a fifth part 24-3, and a sixth part 24-4. The area between any two adjacent parts is a patterned region that does not contain any light-transmitting or light-blocking areas. The second aperture ratio corresponding to the second region 24 is the ratio of the sum of the light-transmitting areas of the third part 24-1 to the sixth part 24-4 of the second region to the total area of ​​the second region 24, or the ratio of the sum of the light-blocking areas of the third part 24-1 to the sixth part 24-4 of the second region to the total area of ​​the second region 24.

[0136] The first region 23 and the second region 24 can be configured as patterns including light-transmitting regions or light-shielding regions. The specific configuration depends on the type of photoresist used: if a positive photoresist is used, the pattern is configured as a pattern for the light-transmitting region, where light passes through the light-transmitting region and irradiates the photoresist, causing the irradiated portion to dissolve during the development process, thereby forming the desired etching pattern on the semiconductor substrate; if a negative photoresist is used, the pattern is configured as a pattern for the light-shielding region, where light cannot pass through the light-shielding pattern, and the unirradiated photoresist dissolves during the development process, thereby obtaining the corresponding etching pattern.

[0137] In this embodiment, the specific pattern size and shape of the patterns used for light-transmitting or light-shielding areas in the first region 23 and the second region 24 correspond to the shape and size of the etching pattern of the photoresist layer 12 in the first embodiment. For details, please refer to the relevant description of the opening unit formed by the photoresist layer 12 and the relevant description of the etching pattern in the first embodiment.

[0138] Figure 12A This illustration merely demonstrates the existence of first and second regions with different aperture ratios in a photomask. In actual applications, a photomask may contain multiple regions with different aperture ratios, such as a first region 23 with a first aperture ratio, a second region 24 with a second aperture ratio, a third region 29 with a third aperture ratio, and a fourth region 30 with a fourth aperture ratio, etc. Figure 12B As shown in the figure. The opening ratios are ordered from largest to smallest as follows: first opening ratio, third opening ratio, fourth opening ratio, and second opening ratio.

[0139] By forming patterns of light-transmitting or light-blocking regions with different aperture ratios in multiple different areas of a mask, multiple aperture units with different aperture ratios can be formed in the mask layer on the epitaxial layer of the semiconductor substrate. Furthermore, by performing a single ion implantation process, different ion implantation doses are formed into corresponding regions within the epitaxial layer at the multiple aperture units with different aperture ratios on the mask layer. Compared to existing technologies that use multiple masks stacked to form multiple aperture units with different aperture ratios on the mask layer of the epitaxial layer of the semiconductor substrate, and that use multiple ion implantation processes to form multiple regions with different ion implantation doses in the bulk region, the mask provided in this application can significantly reduce process costs when used to manufacture the semiconductor device provided in the first embodiment.

[0140] This section uses a bar pattern as an example to illustrate a photomask. However, the patterns in different areas of the photomask can also be formed by combining other shapes and sizes, such as... Figure 13 Several areas with different pattern shapes are listed.

[0141] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided in which at least two MOS cells are formed, wherein any MOS cell includes a trench and a control gate formed in the trench; A composite mask layer is formed on the surface of the semiconductor substrate; On the composite mask layer, the regions corresponding to the at least two MOS units are formed with opening units containing different aperture ratios; Ion implantation is performed in the target regions located on both sides of the control gate within the opening unit to form a bulk region; Remove the composite mask layer that has formed the opening unit; A high-temperature push-junction process is performed to form multiple doped regions in the body region. The doping concentration of the multiple doped regions is distributed differently according to the aperture ratio of the corresponding target region's opening unit.

2. The method according to claim 1, characterized in that, The control gate formed within the trench includes: A first conductive structure is formed in the lower part of the trench, and the lower part of the trench is isolated from the first conductive structure by a first oxide layer; a second conductive structure is formed in the upper part of the trench, and the upper part of the trench is isolated from the second conductive structure by a gate oxide layer; the first conductive structure and the second conductive structure are isolated by an inter-gate dielectric layer; the gate oxide layer is located on the upper sidewall of the trench and on the surface of the semiconductor substrate excluding the trench; a second oxide layer is formed on the surface of the second conductive structure; the first conductive structure is used as a shielding gate, and the second conductive structure is used as a control gate.

3. The method according to claim 1, characterized in that, The step of forming a composite mask layer on the surface of the semiconductor substrate includes: forming a hard mask layer on the surface of the semiconductor substrate, and coating a photoresist layer on the surface of the hard mask layer, thereby forming the composite mask layer by combining the photoresist layer and the hard mask layer.

4. The method according to claim 3, characterized in that, The method of forming opening cells with different aperture ratios in the regions corresponding to the at least two MOS cells on the composite mask layer includes: A photolithography process is performed to form opening cells with different aperture ratios in the regions corresponding to the at least two MOS cells on the photoresist layer. An etching process is performed to transfer the pattern of the opening units formed in the photoresist layer to the hard mask layer.

5. The method according to claim 1, characterized in that, The at least two MOS units include at least a first MOS unit and a second MOS unit; The method of forming opening cells with different aperture ratios in the regions corresponding to the at least two MOS cells on the composite mask layer includes: On the composite mask layer, a first aperture cell with a first aperture ratio is formed in the region corresponding to the first MOS cell, and a second aperture cell with a second aperture ratio is formed in the region corresponding to the second MOS cell, wherein the first aperture ratio is greater than the second aperture ratio.

6. The method according to claim 5, characterized in that, The step of performing ion implantation at the target regions located on both sides of the control gate in the opening unit to form a body region includes: In the same ion implantation process, ion implantation is performed at a first target region located on both sides of the first control gate in the first opening unit and at a second target region located on both sides of the second control gate in the second opening unit, respectively, to form the bulk region in the epitaxial layer of the semiconductor substrate; The ion concentration injected into the first target region is greater than the ion concentration injected into the second target region.

7. The method according to claim 6, characterized in that, The multiple doped regions include at least a first doped region corresponding to the first target region in the body region, and a second doped region corresponding to the second target region in the body region; The high-temperature push-junction process forms multiple doped regions in the body region. The doping concentration of these multiple doped regions varies with the aperture ratio of the corresponding target region's opening unit, including: A high-temperature push-junction process is performed on the implanted semiconductor substrate according to a preset high-temperature push-junction distance and high-temperature push-junction time, so that the implanted ions in the first target region and the second target region diffuse longitudinally and laterally, respectively, to form a first doped region and a second doped region; wherein, the main doping concentration of the first doped region is greater than the main doping concentration of the second doped region.

8. The method according to claim 3, characterized in that, The opening unit includes a target opening unit with at least two opening regions; wherein, in the at least two opening regions of the target opening unit, the ratio between the opening size of the smallest opening region and the thickness of the photoresist layer is greater than or equal to a first preset ratio, and the ratio between the minimum photoresist line width between two adjacent opening regions and the high-temperature push-bonding distance set by the high-temperature push-bonding process is less than or equal to a second preset ratio.

9. The method according to claim 3, characterized in that, The method further includes determining the formation thickness of the hard mask layer based on the energy of the ions to be injected into the body region.

10. A method for manufacturing a semiconductor device, characterized in that, The method includes: Provide semiconductor substrates; A mask layer is formed on the epitaxial layer of the semiconductor substrate; Different regions on the mask layer are formed with opening units having different aperture ratios; Ion implantation is performed in the opening unit to form a bulk region; Remove the mask layer that has formed the opening unit; A high-temperature push-junction process is performed to form multiple doped regions in the bulk region. The doping concentration of the multiple doped regions is distributed differently according to the aperture ratio of the corresponding target region's opening unit.

11. A photomask, characterized in that, Including the first and second regions; Patterns of light-transmitting or light-blocking regions with different aperture ratios are formed in the first region and the second region, respectively, wherein the semiconductor substrate regions corresponding to the first region and the second region are formed with two ion implantation regions of different concentrations.

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