A method for fabricating a shield gate mosfet device with enhanced trench bottom breakdown

Abstract

This application discloses a method for fabricating a shielded gate MOSFET device with enhanced trench bottom breakdown voltage, relating to the field of semiconductor device manufacturing technology. The method involves forming an O-X-O composite shielded gate oxide layer on the inner wall of the trench, consisting of a first oxide layer, a high-k dielectric layer, and a second oxide layer stacked sequentially, replacing the traditional single SiO2 shielded gate oxide layer. The high-k dielectric layer uses a material with a relative permittivity greater than 20, such as hafnium oxide or zirconium oxide. This structure achieves a higher shielding effect than a single SiO2 layer even with a reduced shielded gate oxide layer thickness, thus significantly enhancing the trench bottom breakdown voltage. Simultaneously, reducing the thickness of the shielded gate oxide layer can further reduce the cell pitch and increase the doping concentration of the epitaxial layer, achieving a significant reduction in specific on-resistance from both the perspectives of increasing doping concentration and increasing device density. The method of this invention is compatible with standard power MOSFET manufacturing processes, and the fabrication process is stable and controllable.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor device manufacturing, and in particular to a method for fabricating a shielded gate MOSFET device with enhanced trench bottom breakdown. Background Technology

[0002] Shielded-gate trench MOSFETs (SGT MOSFETs) utilize a shielding electrode at the bottom of the trench. The depletion effect between the shielding electrode and the drift region flattens the electric field distribution at the bottom of the trench, achieving a higher breakdown voltage and lower specific on-resistance (Rsp) on a thinner epitaxial layer. Currently, the liner oxide layer between the trench inner wall and the shielding electrode in SGT MOSFETs is generally made of a single silicon dioxide (SiO2) material, formed through thermal oxidation or chemical vapor deposition. SiO2 material has advantages such as excellent interface properties and mature processing, making it the mainstream technology in current power semiconductor device manufacturing. In addition, some existing technologies propose using an ONO (Oxide-Nitride-Oxide) stack structure composed of silicon nitride and silicon dioxide to replace the single SiO2 layer. This aims to take advantage of the higher dielectric constant of silicon nitride (k≈7) compared to SiO2 (k≈3.9), allowing for a suitable reduction in the physical thickness of the shielding gate oxide layer while maintaining the same equivalent oxide layer thickness.

[0003] However, all the existing solutions mentioned above have significant performance bottlenecks. For a single SiO2 shielding gate oxide layer, its dielectric constant is low (k≈3.9). To obtain a higher trench bottom breakdown voltage, the physical thickness of the oxide layer must be increased. However, an excessively thick oxide layer will significantly increase the distance between the shielding electrode and the drift region, weakening the depletion capability of the shielding electrode on the drift region. This, in turn, limits the potential for increasing the epitaxial layer doping concentration and shrinking the cell pitch, hindering further reductions in specific on-resistance. For the ONO stacked structure, although it is an improvement over a single SiO2 layer, the dielectric constant of silicon nitride is still relatively low (k≈7), limiting the reduction in the physical thickness of the shielding gate oxide layer. This makes it difficult to meet the synergistic optimization requirements of high epitaxial doping concentration and small cell pitch for high-performance SGT MOSFETs. Therefore, how to maximize the reduction in the physical thickness of the shielding gate oxide layer to enhance depletion capability while ensuring sufficient breakdown reliability at the trench bottom, thereby supporting the increase in epitaxial layer doping concentration and the reduction in cell pitch, and ultimately achieving a significant reduction in specific on-resistance, has become a pressing technical challenge in this field. Summary of the Invention

[0004] This application provides a method for fabricating a shielded gate MOSFET device with enhanced trench bottom breakdown, which can solve the problem that the physical thickness of the shielded gate oxide layer in the existing SGT MOSFET device is difficult to reduce due to the low dielectric constant, thus creating a contradiction between breakdown voltage and depletion capability, and failing to simultaneously meet the requirements of high doping concentration of epitaxial layer and low specific on-resistance for cell pitch reduction.

[0005] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, this application provides a method for fabricating a shielded gate MOSFET device with enhanced trench bottom breakdown, the method comprising: A substrate is provided, and an epitaxial layer is formed on the substrate; Trenches are formed in the epitaxial layer; A composite shielding gate oxide layer is formed on the inner wall and bottom of the trench. The composite shielding gate oxide layer includes a first oxide layer, a high dielectric constant dielectric layer and a second oxide layer. The high dielectric constant dielectric layer is located between the first oxide layer and the second oxide layer. The dielectric constant of the high dielectric constant dielectric layer is greater than that of silicon dioxide. A shielding electrode is formed on the composite shielding gate oxide layer; A gate electrode is formed above the shielding electrode; A body region and a source region are formed on the top of the epitaxial layer; A dielectric layer is formed on the surface of the device, a contact hole is formed by etching the dielectric layer, and an electrode lead is formed in the contact hole and on the surface of the dielectric layer.

[0006] In one embodiment, the dielectric constant of the high dielectric constant dielectric layer is greater than 20.

[0007] In one embodiment, the materials of the first oxide layer and the second oxide layer are silicon dioxide.

[0008] In one embodiment, the material of the high dielectric constant dielectric layer is at least one of hafnium oxide or zirconium oxide.

[0009] In one embodiment, under the same breakdown voltage conditions, the total physical thickness of the composite shielding gate oxide layer is less than the physical thickness of the single-layer silicon dioxide shielding gate oxide layer.

[0010] In one embodiment, the doping concentration of the epitaxial layer is higher than that of the epitaxial layer when a single layer of silicon dioxide shielding gate oxide is used.

[0011] In one embodiment, the equivalent oxide layer thickness of the composite shielding gate oxide layer is not less than the equivalent oxide layer thickness of a single-layer silicon dioxide shielding gate oxide layer under the same breakdown voltage.

[0012] In one embodiment, the first oxide layer is formed by thermal oxidation or chemical vapor deposition, the high dielectric constant dielectric layer is formed by atomic layer deposition or chemical vapor deposition, and the second oxide layer is formed by chemical vapor deposition or thermal oxidation.

[0013] In one embodiment, a gate electrode is formed above the shielding electrode, including: A gate oxide layer is grown on the surface of the epitaxial layer and the sidewalls of the trench, polysilicon is deposited and etched back to form the gate electrode.

[0014] In one embodiment, the shielded gate MOSFET device is prepared using the shielded gate MOSFET device fabrication method with enhanced trench bottom breakdown described in the first aspect of the present application.

[0015] The beneficial effects of the technical solutions provided in this application include at least the following: This application provides a method for fabricating a shielded gate MOSFET device with enhanced trench bottom breakdown. The method involves providing a substrate, forming an epitaxial layer on the substrate, forming a trench in the epitaxial layer, and forming a composite shielded gate oxide layer on the inner wall and bottom of the trench. The composite shielded gate oxide layer includes a first oxide layer, a high-dielectric-constant dielectric layer, and a second oxide layer. The high-dielectric-constant dielectric layer is located between the first oxide layer and the second oxide layer, and its dielectric constant is greater than that of silicon dioxide. A shielding electrode is formed on the composite shielded gate oxide layer. A gate electrode is formed above the shielding electrode. A body region and a source region are formed on the top of the epitaxial layer. A dielectric layer is formed on the device surface, and contact holes are formed by etching the dielectric layer. Electrode leads are formed within the contact holes and on the surface of the dielectric layer.

[0016] This application constructs an OXO composite shielding gate oxide layer structure consisting of a "first oxide layer / high dielectric constant dielectric layer / second oxide layer" on the inner wall and bottom of the trench. Utilizing the dielectric constant of the high dielectric constant dielectric layer (e.g., HfO2, εr≈25; ZrO2, εr≈30) which is significantly higher than that of SiO2 (εr=3.9), an equivalent oxide layer thickness (EOT) no less than, and even higher than, that of a traditional single SiO2 layer can be achieved while significantly reducing the physical thickness of the shielding gate oxide layer. This ensures that the breakdown voltage at the bottom of the trench does not decrease but rather increases, while significantly shortening the physical distance between the shielding electrode and the drift region. This structural improvement qualitatively enhances the lateral depletion capability of the shielding electrode, allowing for higher doping concentrations in the epitaxial layer and supporting further miniaturization of the device cell pitch. Ultimately, this significantly reduces the specific on-resistance (Rsp) by increasing both the epitaxial doping concentration and the cell density per unit area. Attached Figure Description

[0017] Figure 1 A flowchart illustrating a method for fabricating a shielded gate MOSFET device with enhanced trench bottom breakdown, as provided in this application embodiment; Figure 2-9 This is a schematic diagram illustrating the fabrication process of a shielded gate MOSFET device with enhanced trench bottom breakdown provided in an embodiment of this application.

[0018] Figure label: 1-Substrate, 2-Epipolar layer, 3-Trench, 4-First oxide layer, 5-High dielectric constant dielectric layer, 6-Second oxide layer, 7-Polysilicon, 8-Polysilicon interlayer oxide, 9-Gate oxide layer, 10-Gate polysilicon, 11-Bulk region, 12-Source region, 13-Protective layer, 14-Ohmic contact layer, 15-Metal deposition layer, 16-Top metal, 17-Drain. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0021] In addition, the use of “based on” or “according to” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” or “according to” one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0022] This application provides a method for fabricating a shielded gate MOSFET device with enhanced trench bottom breakdown, such as... Figure 1 As shown, the method includes the following steps: Step 101: Provide a substrate 1 and form an epitaxial layer 2 on the substrate 1.

[0023] The substrate 1 can be an N-type heavily doped single-crystal silicon substrate 1, with a resistivity preferably of 0.001 to 0.01 Ω·cm and a crystal orientation preferably of... <100> To improve carrier mobility.

[0024] Of course, this application also applies to changing the doping element type to P-type to form a P-type SGT MOSFET.

[0025] like Figure 2 As shown, a lightly doped epitaxial layer 2 is grown on the heavily doped substrate 1 using processes such as chemical vapor deposition or molecular beam epitaxy. The doping type of epitaxial layer 2 is the same as that of substrate 1, and its doping concentration can be adjusted according to the device's voltage rating. For example, for devices with a voltage rating of 30V to 100V, the doping concentration of epitaxial layer 2 can be set to 1×10⁻⁶. 15 ~5×10 16 cm - ³, with a thickness that can be set to 2–8 μm. This epitaxial layer 2 will serve as the drift region of the device and bear the main withstand voltage function.

[0026] Step 102: Form a trench 3 in the epitaxial layer 2.

[0027] In this embodiment, such as Figure 3 As shown, cell trenches 3 are formed in the epitaxial layer 2 using photolithography and etching processes.

[0028] Specifically, firstly, a photoresist layer is coated on the wafer surface, and then a photomask is used to expose and develop the cell region to define the pattern of trench 3. Then, an anisotropic dry etching process (such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP)) is used to etch the exposed epitaxial layer 2, and after removing the photoresist, trench 3 with a predetermined depth and width is formed in the epitaxial layer 2.

[0029] The depth of the trench 3 can be determined according to the voltage rating of the device, preferably 2 to 6 μm, and the width of the trench 3 is preferably 0.5 to 2 μm. The trench 3 penetrates part of the thickness of the epitaxial layer 2, and its bottom is located inside the epitaxial layer 2. That is, a portion of the thickness of the epitaxial layer 2 is retained between the bottom of the trench 3 and the upper surface of the substrate 1 as the bottommost region of the drift region.

[0030] Step 103: A composite shielding grid oxide layer is formed on the inner wall and bottom of the trench 3.

[0031] In this embodiment, such as Figure 4 As shown, a composite shielding gate oxide layer is formed on the inner wall and bottom of the trench 3. The composite shielding gate oxide layer includes a first oxide layer 4, a high dielectric constant dielectric layer 5 and a second oxide layer 6 stacked sequentially. The high dielectric constant dielectric layer 5 is located between the first oxide layer 4 and the second oxide layer 6, and the dielectric constant of the high dielectric constant dielectric layer 5 is greater than that of silicon dioxide.

[0032] As a specific implementation method, the steps for forming the composite shielding gate oxide layer can be as follows: A first oxide layer 4 is formed on the inner wall and bottom of the trench 3 and on the surface of the epitaxial layer 2 by a thermal oxidation process or a chemical vapor deposition process. The material of the first oxide layer 4 is preferably silicon dioxide (SiO2), and its thickness can be set according to the voltage withstand requirements of the device, for example, 2nm to 10nm. The first oxide layer 4 formed by the thermal oxidation process has the advantages of being dense and having a low interface state density, which can ensure the interface quality between the high dielectric constant dielectric layer 5 and the silicon substrate 1.

[0033] A high-dielectric-constant dielectric layer 5 is formed on top of the first oxide layer 4. The material of this high-dielectric-constant dielectric layer 5 is an insulating material with a dielectric constant significantly higher than that of silicon dioxide (k=3.9), for example, hafnium oxide (HfO2, εr≈25) or zirconium oxide (ZrO2, εr≈30). The high-dielectric-constant dielectric layer 5 is preferably formed by atomic layer deposition (ALD), which has excellent step coverage capabilities and can form a uniform, dense, and precisely controllable high-k dielectric film on the inner wall of the trench 3 with a high aspect ratio.

[0034] The thickness of the high dielectric constant dielectric layer 5 can be set according to the device performance requirements, for example, from 5 nm to 30 nm. During atomic layer deposition, the film thickness can be precisely controlled by controlling the number of deposition cycles, achieving nanometer-level thickness accuracy.

[0035] A second oxide layer 6 is formed on top of the high-k dielectric layer 5. The material of the second oxide layer 6 is also preferably silicon dioxide (SiO2), which can be formed by chemical vapor deposition or thermal oxidation processes. The thickness of the second oxide layer 6 can be the same as or different from that of the first oxide layer 4, for example, set to 2 nm to 10 nm. The function of the second oxide layer 6 is twofold: firstly, to isolate the high-k dielectric layer 5 from the subsequently filled shielding electrode polysilicon 7, preventing interfacial reactions between the high-k material and the polysilicon 7; secondly, the second oxide layer 6 and the first oxide layer 4 together form a double-sided protection for the high-k dielectric layer, ensuring the overall insulation reliability and long-term stability of the composite layer.

[0036] The resulting OXO composite stack structure of "first oxide layer 4 (SiO2) / high dielectric constant dielectric layer 5 (HfO2 or ZrO2) / second oxide layer 6 (SiO2)" combines the advantages of high dielectric constant and excellent interface properties. By selecting appropriate high-k materials and the thickness of each layer, the physical thickness of the shielding gate oxide layer can be significantly reduced while achieving an equivalent oxide layer thickness (EOT) that is not lower than or even higher than that of a traditional single SiO2 shielding gate oxide layer, thus providing a structural basis for the strong depletion capability of the subsequent shielding electrode.

[0037] This application utilizes the high-k characteristics of the high-k dielectric layer 5 to enable the composite shielding gate oxide layer to still have excellent insulation and withstand voltage capabilities even with a significant reduction in physical thickness. At the same time, the SiO2 layers on both sides effectively suppress the interface reaction and leakage current channels between the high-k dielectric and the silicon substrate 1 and the polysilicon 7 electrode, thereby improving the long-term reliability of the device.

[0038] Step 104: Form a shielding electrode on the composite shielding gate oxide layer.

[0039] Optionally, after forming the composite shielding gate oxide layer, conductive material is deposited inside the trench 3 to form a shielding electrode.

[0040] Specifically, such as Figure 5 As shown, heavy-doped polysilicon 7 is filled in the trench 3 using a low-pressure chemical vapor deposition (LPCVD) process. The preferred doping concentration of the polysilicon 7 is 1×10⁻⁶. 19 ~1×10 20 cm - ³, to reduce the resistance of the shielding electrode. Subsequently, the polysilicon 7 is etched back so that the upper surface of the shielding electrode is lower than the upper surface of the epitaxial layer 2, that is, space is reserved in the upper part of the trench 3 to accommodate the gate electrode. The top position of the shielding electrode can be determined according to the device design, for example, so that the upper surface of the shielding electrode is located 0.5 to 1.5 μm below the upper surface of the epitaxial layer 2.

[0041] Above the etched shielding electrode, an inter-polysilicon oxide (IPO) structure is further formed. Specifically, an oxide layer is deposited on the top of the shielding electrode, the sidewalls of the trench 3, and the surface of the epitaxial layer 2. Excess oxide layers are then removed using photolithography and etch-back processes, leaving the IPO structure only above the shielding electrode. This IPO is used to achieve electrical isolation between the shielding electrode and the subsequently formed gate electrode.

[0042] This application achieves direct contact between the shielding electrode and the composite shielding gate oxide layer. Due to the thin physical thickness of the composite shielding gate oxide layer, the distance between the shielding electrode and the drift region is significantly reduced, thereby greatly enhancing the lateral depletion capability of the shielding electrode on the epitaxial layer 2. This creates conditions for increasing the doping concentration of the epitaxial layer 2 and reducing the cell pitch.

[0043] Step 105: Form a gate electrode above the shielding electrode.

[0044] like Figure 6As shown, after the shielding electrode and IPO are formed, the gate electrode is formed in the trench 3 region above the shielding electrode. First, a gate oxide layer 9 is grown on the surface of the epitaxial layer 2 and the inner wall of the trench 3 (i.e., the exposed sidewall of the trench 3 and the IPO surface). The gate oxide layer 9 is preferably silicon dioxide, and its thickness can be set according to the threshold voltage requirements of the device, for example, 20nm to 80nm.

[0045] The gate oxide layer 9 can be formed by a thermal oxidation process to ensure excellent interface characteristics and insulation performance. Subsequently, heavily doped gate polysilicon 10 is deposited to fill the remaining space of the trench 3, and the excess gate polysilicon 9 is removed by a etch-back process to form the gate electrode. The top of the gate electrode is preferably flush with or slightly lower than the upper surface of the epitaxial layer 2.

[0046] Vertical isolation between the gate electrode and the shield electrode is achieved through an IPO (Installation On-Board). The gate electrode is led out to the gate pad through subsequent contact holes and top metal 16. The vertically stacked structure of the gate electrode and shield electrode in this application makes full use of the depth space of the trench 3, maintaining sufficient channel width while reducing cell pitch, which helps to reduce the on-resistance and input capacitance of the device.

[0047] Step 106: Form a body region 11 and a source region 12 on the top of the epitaxial layer 2.

[0048] Optionally, after the gate electrode is formed, a body region 11 and a source region 12 are formed on the top of the epitaxial layer 2 (i.e., the mesa region between adjacent trenches 3).

[0049] The body region 11 can be formed by ion implantation into the active region 12 of the device using a photomask. For N-type MOSFET devices, the body region 11 implantation is P-type doped, and the implanted element can be boron (B) or boron difluoride (BF2), with a preferred implantation dose of 1×10⁻⁶. 13 ~1×10 14 cm - ², the injection energy is set according to the required junction depth. After injection, a high-temperature annealing process is performed to accelerate the diffusion of injected impurity atoms and form a body region 11 with a certain depth. The body region 11 serves as the channel turn-on voltage regulation region for the device.

[0050] like Figure 7 As shown, the source region 12 can be formed by ion implantation into the body region 11 using a photomask for positioning. For N-type MOSFET devices, the source region 12 is heavily N-type doped, and the implanted element can be arsenic (As) or phosphorus (P), with a preferred implantation dose of 1×10⁻⁶. 15 ~5×1×10 15 cm -², with a lower injection energy to form a shallow junction. After injection, a second high-temperature annealing is performed to repair the lattice damage caused by ion implantation and activate impurity ions, forming a high-concentration conductive power region 12, providing a channel for charge carriers.

[0051] The body region 11 and source region 12 of this application are formed by ion implantation and high-temperature annealing. The process is mature and controllable, and the channel length and threshold voltage can be precisely adjusted to ensure the consistency of the device's electrical parameters.

[0052] Step 107: Form a dielectric layer on the surface of the device, etch the dielectric layer to form contact holes, and form electrode leads in the contact holes and on the surface of the dielectric layer.

[0053] In this embodiment, a dielectric layer is first deposited on the wafer surface as a protective layer 13 and an insulating layer. This dielectric layer is preferably borosilicate glass (BPSG), formed by chemical vapor deposition. BPSG has good flowability and gap-filling ability, enabling the device surface to be planarized. Subsequently, the BPSG layer is reflowed to further improve surface flatness.

[0054] like Figure 8 and Figure 9 As shown, a photomask is used for positioning, and contact holes (CTs) are etched in the BPSG layer using photolithography and dry etching processes. The contact holes are located above the body region 11 and the source region 12, with the bottom of the contact holes exposing the surface of the source region 12. High-concentration ion implantation is performed on the bottom of the contact holes to form a good ohmic contact layer 14, reducing contact resistance. Subsequently, a metal layer is deposited inside the contact holes and on the surface of the BPSG layer to form a metal deposition layer 15 (e.g., a titanium / titanium nitride / aluminum silicon alloy stack). The metal layer is patterned using an etching process to form source and gate electrode leads, electrically connecting the body region 11 and the source region 12 and leading them to the device surface.

[0055] This application connects the body region 11 and the source region 12 by short-circuiting through contact holes, which effectively suppresses the turn-on of parasitic bipolar transistors and improves the avalanche tolerance of the device; at the same time, the BPSG layer, as an interlayer dielectric layer, ensures good insulation between the gate and the source.

[0056] This application achieves synergistic optimization of physical thickness reduction and breakdown voltage maintenance of the shielding gate oxide layer by introducing an OXO composite shielding gate oxide layer structure into the inner wall of the trench 3. This lays the foundation for subsequent increase of doping concentration of epitaxial layer 2 and cell pitch reduction, and ultimately reduces the specific on-resistance of the device from multiple dimensions.

[0057] Optionally, the dielectric layer 5 with a high dielectric constant has a dielectric constant greater than 20. The dielectric constant of this high-k dielectric material should be significantly different from that of conventional SiO2 (k=3.9) and Si3N4 (k≈7). Materials with a dielectric constant greater than 20 can provide a much greater equivalent oxide layer thickness than SiO2 at the same physical thickness, or, at the same equivalent oxide layer thickness requirement, the physical thickness can be reduced to less than about 1 / 5 of that of SiO2.

[0058] For example, the high dielectric layer 5 uses hafnium oxide (HfO2, εr≈25) or zirconium oxide (ZrO2, εr≈30), both of which have a dielectric constant greater than 20. Taking HfO2 as an example, when an insulation effect with an equivalent oxide layer thickness of 10 nm is required, SiO2 requires a physical thickness of 10 nm, while HfO2 only requires a physical thickness of about 4 nm (10 / 25×3.9≈1.56 nm; considering practical process factors, the actual required thickness is about 4-5 nm). This significant reduction in thickness results in a significant shortening of the distance between the shielding electrode and the drift region, leading to a qualitative improvement in depletion capability.

[0059] In addition, the high dielectric constant dielectric layer 5 can also be made of other materials with a dielectric constant greater than 20, such as alumina (Al2O3, k≈9, not satisfied), titanium oxide (TiO2, k≈40~80), strontium titanate (SrTiO3, k≈300), etc. Those skilled in the art can choose according to process compatibility and cost factors. However, considering compatibility with standard SGT MOSFET processes, hafnium oxide and zirconium oxide are preferred due to their good thermal stability and compatibility with traditional semiconductor processes.

[0060] This application ensures that the physical thickness reduction of the composite shielding gate oxide layer is significant enough by limiting the dielectric constant of the high dielectric constant dielectric layer 5 to greater than 20, thereby qualitatively improving the depletion capability of the shielding electrode to the drift region and providing sufficient process space for achieving high epitaxial doping concentration and small cell pitch design.

[0061] Optionally, the materials of the first oxide layer 4 and the second oxide layer 6 are silicon dioxide.

[0062] In other words, both the first oxide layer 4 and the second oxide layer 6 located on either side of the high dielectric layer 5 in the composite shielding gate oxide layer are made of silicon dioxide (SiO2). The selection of SiO2 as the material for the insulating layers on both sides is based on the following considerations: First, SiO2 exhibits excellent interface characteristics with the silicon substrate 1, resulting in a low interface state density. This effectively reduces the adverse effects of interface trap charges on the device threshold voltage and channel mobility. In particular, if the first oxide layer 4 is formed using a thermal oxidation process, the interface quality between it and the single-crystal silicon is extremely excellent, ensuring the interface stability between the high-k dielectric layer and the silicon substrate 1.

[0063] Second, SiO2 and polysilicon 7 electrodes also have stable interface characteristics, which can prevent the high-k dielectric material and polysilicon 7 from undergoing interface reactions or mutual diffusion in subsequent high-temperature processes, thereby avoiding the formation of interface defect layers or leakage channels.

[0064] Third, SiO2 materials are widely used in semiconductor manufacturing processes. Its preparation processes, such as thermal oxidation and chemical vapor deposition, are mature and stable, low in cost, and easy to achieve mass production.

[0065] In a specific implementation, the thickness of the first oxide layer 4 can be set to 2nm to 200nm, and the thickness of the second oxide layer 6 can be set to 2nm to 200nm. The thicknesses on both sides can be the same or different, and can be optimized according to the type of high-k dielectric material and the voltage withstand requirements of the device.

[0066] This application uses SiO2 as the double-sided insulating layer material. On the one hand, it leverages the excellent interface between SiO2 and silicon and polysilicon to suppress interface reactions and leakage current. On the other hand, it is fully compatible with the existing standard SGT MOSFET manufacturing process, eliminating the need for additional interface processing, thus reducing manufacturing costs and process complexity.

[0067] Optionally, the material of the high dielectric constant dielectric layer 5 is at least one of hafnium oxide or zirconium oxide.

[0068] In this embodiment, the high dielectric constant dielectric layer 5 is specifically selected from at least one of hafnium oxide (HfO2) or zirconium oxide (ZrO2). Both HfO2 and ZrO2 have high dielectric constants (εr of HfO2 is approximately 25, and εr of ZrO2 is approximately 30), which can meet the requirement of a dielectric constant greater than 20, and a large equivalent oxide layer thickness can be obtained with a small physical thickness. Both HfO2 and ZrO2 have good thermal stability, and can maintain their amorphous or microcrystalline structure and dielectric properties during the subsequent high-temperature annealing process (typically 800°C to 1100°C) in the SGT MOSFET manufacturing process, and are not prone to crystallization or chemical reactions with adjacent layers. Both HfO2 and ZrO2 can achieve high-quality thin film growth through atomic layer deposition (ALD) processes. Atomic layer deposition, based on self-limiting surface chemical reactions, can achieve 100% step coverage in trench 3 structures with high aspect ratios, ensuring uniform film thickness at the bottom and sidewalls of trench 3. This is crucial for the fabrication of the insulating layer in deep trench structures of SGT MOSFETs.

[0069] In addition, the high dielectric constant dielectric layer 5 can also be a stacked combination of HfO2 and ZrO2, for example, depositing a layer of ZrO2 first and then depositing a layer of HfO2, or using HfO2. x Zr 1-x O2 composite oxides to combine the advantages of both materials.

[0070] Optionally, under the same breakdown voltage conditions, the total physical thickness of the composite shielding gate oxide layer is less than the physical thickness of the single-layer silicon dioxide shielding gate oxide layer.

[0071] Under the same breakdown voltage requirements (e.g., all are 30V, 60V or 100V withstand voltage ratings), the total physical thickness required for the composite shielding gate oxide layer of this application is significantly less than the physical thickness of the traditional single SiO2 shielding gate oxide layer.

[0072] The following example illustrates this: Suppose an SGT MOSFET device requires a bottom breakdown voltage of 40V at the bottom of trench 3. In conventional solutions, using a single SiO2 shielding gate oxide layer, a SiO2 physical thickness of approximately 100nm or more is required to ensure bottom breakdown.

[0073] In an embodiment of the present invention, a composite stack of SiO2 (5nm) / HfO2 (20nm) / SiO2 (5nm) is used, with a total physical thickness of only 30nm. The equivalent oxide layer thickness EOT of this composite layer is EOT = 5 + 20 / 6.4 + 5 ≈ 13.1nm, where the equivalent thickness conversion factor of HfO2 is approximately 3.9 / 25 ≈ 0.156, and 20nm × 0.156 ≈ 3.1nm. However, it should be noted that the breakdown voltage depends not only on EOT but also on the electric field distribution and interface characteristics. The above calculation is only illustrative. Its breakdown voltage is not lower than or even better than the breakdown voltage of an 80nm single SiO2 layer, while the physical thickness is only about 37.5% of the latter.

[0074] Under the premise of obtaining the same breakdown voltage (e.g., 40V), the traditional SiO2 layer requires a thickness of about 100nm, while the total thickness of the OXO stack in this application can be controlled within the range of 20nm to 40nm, reducing the physical thickness by 60% to 80%. The direct effect of this thickness reduction is that the physical distance between the shielding electrode and the drift region is greatly shortened. According to Gauss's theorem, the lateral electric field strength of the shielding electrode to the epitaxial layer 2 is significantly enhanced at the same potential, the depletion width is increased, and the depletion capability is improved.

[0075] This application significantly reduces the physical thickness, thereby maintaining or even increasing the breakdown voltage while greatly enhancing the depletion capability of the shielding electrode, providing direct structural support for increasing the doping concentration of the epitaxial layer 2 and miniaturizing the device cell pitch.

[0076] Optionally, the doping concentration of the epitaxial layer 2 is higher than that of the epitaxial layer 2 when a single layer of silicon dioxide shielding gate oxide is used.

[0077] In traditional single-SiO2 shielded gate oxide schemes, the depletion capability of the shielding electrode is limited due to the relatively thick insulating layer. To ensure that the device can completely deplete the drift region and reach the target breakdown voltage under reverse bias, the doping concentration of epitaxial layer 2 must be controlled at a relatively low value. Taking a 30V withstand voltage SGT MOSFET as an example, the traditional scheme typically uses a doping concentration of approximately 1×10¹. 6 cm - ³ Epitaxial layer 2.

[0078] In the embodiments of this application, due to the significant reduction in the physical thickness of the OXO composite shielding gate oxide layer, the depletion capability of the shielding electrode to the drift region is greatly enhanced. Under the same trench 3 spacing and cell pitch conditions, the present invention allows the doping concentration of the epitaxial layer 2 to be reduced from approximately 1 × 10¹ in conventional schemes. 6 cm - ³Increased to approximately 2×10¹ 6 cm -³~3×10¹ 6 cm - ³, the improvement can reach 100% to 200%. Increasing the doping concentration of epitaxial layer 2 directly reduces the resistivity of the drift region, thereby significantly reducing the on-resistance of the device.

[0079] It should be noted that the specific increase in the doping concentration of epitaxial layer 2 depends on multiple factors, including the actual thickness reduction ratio of the composite shielding gate oxide layer, the dielectric constant of the high-k dielectric material, the geometry of trench 3, and the device breakdown voltage. Those skilled in the art can determine the optimal epitaxial doping concentration through conventional device simulation and process experiments based on the technical inspiration of this application.

[0080] Optionally, the equivalent oxide layer thickness of the composite shielding gate oxide layer is not less than the equivalent oxide layer thickness of a single-layer silicon dioxide shielding gate oxide layer under the same breakdown voltage.

[0081] The equivalent oxide layer thickness refers to the total thickness after converting the physical thickness of the high dielectric constant dielectric layer 5 into the thickness of SiO2 with the same capacitance effect. The formula for calculating the equivalent oxide layer thickness EOT of the composite shielding gate oxide layer is EOT=T_SiO2+T_highk × (k_SiO2 / k_highk), where T_SiO2 is the physical thickness of the SiO2 layer, T_highk is the physical thickness of the high k dielectric layer, and k_SiO2 and k_highk are the dielectric constants of the SiO2 and high k dielectric layers, respectively.

[0082] The EOT value of the composite shielding gate oxide layer in this application is designed to be no less than that of a single SiO2 shielding gate oxide layer under the same breakdown voltage conditions. This means that although the physical thickness of the composite shielding gate oxide layer is significantly reduced, its equivalent electrical insulation thickness is not reduced, and may even be increased. This is the electrical basis for ensuring that the breakdown voltage at the bottom of trench 3 does not decrease but increases.

[0083] Specifically, the EOT of the composite shielding gate oxide layer of the present invention is mainly determined by the following factors: the thickness of the first oxide layer 4 and the second oxide layer 6 (both are SiO2, which directly contribute to the EOT), the physical thickness of the high dielectric constant dielectric layer 5 and its dielectric constant (the equivalent thickness after conversion of the contribution of the high-k dielectric). By reasonably configuring the thickness of each layer, the total EOT can reach or even exceed the EOT of a traditional single SiO2 layer.

[0084] For example, in conventional schemes, the thickness of a single SiO2 shielding gate oxide layer is 80 nm, and its EOT = 80 nm. The OXO stack of this invention is SiO2 (5 nm) / HfO2 (20 nm) / SiO2 (5 nm), and its EOT = 5 + 20 × (3.9 / 25) + 5 = 5 + 3.12 + 5 = 13.12 nm, which is much smaller than 80 nm. Although the EOT is lower than in conventional schemes, the actual breakdown voltage may still be no lower than in conventional schemes because HfO2 has a higher intrinsic breakdown field strength (approximately 10-15 MV / cm, higher than SiO2's approximately 8-10 MV / cm). To ensure that the EOT is no less than 80 nm, it is necessary to increase the thickness of the high-k dielectric layer or select a material with a higher dielectric constant. Therefore, in some embodiments of this application, by selecting appropriate combinations of layer thicknesses, the EOT of the composite layer is made no less than that of a conventional single SiO2 layer, thereby completely covering or exceeding the conventional scheme in terms of electrical equivalent thickness. In practical device design, it is not necessary for the EOT to be exactly the same or higher; as long as the breakdown voltage meets the requirements, it is acceptable. This application can achieve flexible design for electrical equivalence by adjusting the thickness of each layer.

[0085] Optionally, the first oxide layer 4 is formed by thermal oxidation or chemical vapor deposition, the high dielectric constant dielectric layer 5 is formed by atomic layer deposition or chemical vapor deposition, and the second oxide layer 6 is formed by chemical vapor deposition or thermal oxidation.

[0086] In this embodiment, each layer of the composite shielding gate oxide layer is formed using different deposition processes to fully leverage the advantages of each process.

[0087] The formation process of the first oxide layer 4: The first oxide layer 4 is located on the inner wall and bottom of the trench 3 and is in direct contact with the single-crystal silicon epitaxial layer 2. In this embodiment, the first oxide layer 4 is preferably formed by a thermal oxidation process. The thermal oxidation process involves oxidizing the silicon surface in an oxygen-containing atmosphere at a high temperature (typically 800°C to 1100°C), causing silicon atoms to react with oxygen atoms to generate SiO2. The SiO2 layer formed by thermal oxidation is dense, uniform, and has a low interface state density, resulting in the best interface quality with the silicon substrate 1. As an alternative, the first oxide layer 4 can also be formed by chemical vapor deposition (CVD) of SiO2. The advantages of CVD are relatively low deposition temperature and fast deposition rate, but the interface quality is slightly inferior to that of thermal oxidation. In devices with high requirements, the thermal oxidation process is preferred.

[0088] Formation process of the high dielectric constant dielectric layer 5: The high dielectric constant dielectric layer 5 is located between the first oxide layer 4 and the second oxide layer 6, and needs to achieve uniform coverage in the trench 3 with a high aspect ratio. In this embodiment, the high dielectric constant dielectric layer 5 is preferably formed by atomic layer deposition (ALD).

[0089] The formation process of the second oxide layer 6: The second oxide layer 6 is located above the high-dielectric-constant dielectric layer 5 and is in contact with the subsequently filled shielding electrode polycrystalline silicon 7. In this embodiment, the second oxide layer 6 is preferably formed by chemical vapor deposition (CVD) of SiO2. CVD can deposit SiO2 at relatively low temperatures, avoiding thermal effects on the already formed high-k dielectric layer. As an alternative, the second oxide layer 6 can also be formed by thermal oxidation, but thermal oxidation requires a high-temperature oxygen-containing atmosphere, which may affect the performance of the high-k dielectric layer. Therefore, process parameters should be carefully selected in practice. In most embodiments, CVD is the more preferred method for forming the second oxide layer 6.

[0090] Optionally, forming a gate electrode above the shielding electrode includes: growing a gate oxide layer 9 on the surface of the epitaxial layer 2 and the sidewall of the trench 3, depositing polysilicon 7 and etching it back to form the gate electrode.

[0091] In this embodiment, the specific process steps for forming the gate electrode are detailed as follows: First, a gate oxide layer 9 is grown on the wafer surface where the shielding electrode and IPO have been formed. The gate oxide layer 9 is made of silicon dioxide and covers the top surface of the epitaxial layer 2 and the sidewalls of the trench 3 (i.e., the exposed sidewall area above the IPO). The gate oxide layer 9 is preferably formed by a thermal oxidation process, and its thickness is set according to the threshold voltage requirements of the device. For medium- and low-voltage SGT MOSFET devices, the thickness of the gate oxide layer 9 is typically 20 nm to 80 nm. The thermal oxidation process is carried out in a high-temperature oxygen-containing atmosphere, which can grow a dense, uniform SiO2 layer with few interface defects on the silicon surface of the trench 3 sidewalls. This gate oxide layer 9 will serve as the insulating medium between the gate electrode and the channel region, and its quality directly determines the threshold voltage stability, gate leakage current, and reliability of the device.

[0092] Next, heavily doped polysilicon 7 is deposited on the wafer surface where the gate oxide layer 9 has been grown. The deposition of polysilicon 7 is preferably performed using a low-pressure chemical vapor deposition (LPCVD) process, where silane (SiH4) or dichlorosilane (SiH2Cl2) is decomposed at a temperature of 580°C to 620°C to deposit the polysilicon 7 thin film. During or after deposition, the polysilicon 7 is heavily doped by diffusion or ion implantation. For N-type MOSFET devices, the doping element is phosphorus (P) or arsenic (As), and the doping concentration is preferably 1 × 10¹. 9 ~1×10² 0 cm - ³, to reduce the resistance of the gate electrode.

[0093] Next, a back-etching process is performed on the deposited polysilicon 7. Anisotropic dry etching (such as reactive ion etching) is used to remove excess polysilicon 7 from the outside and top of trench 3, leaving only a predetermined height of polysilicon 7 within the trench 3 above the shielding electrode as the gate electrode. The end point of the back-etching can be controlled by the etching time, ensuring that the top of the gate electrode is flush with or slightly below the upper surface of the epitaxial layer 2. This back-etching process isolates the gate electrode from the subsequently formed source metal.

[0094] After this step is completed, a vertically stacked structure of "shielding electrode + IPO + gate electrode" is formed inside trench 3. The shielding electrode is located at the bottom of trench 3 and is isolated from epitaxial layer 2 by a composite shielding gate oxide layer; the gate electrode is located at the top of trench 3 and is isolated from the channel region by gate oxide layer 9; the shielding electrode and the gate electrode are vertically isolated by IPO. This structure makes full use of the depth of trench 3 and integrates shielding and switching control functions while maintaining a small cell pitch.

[0095] This application also provides a shielded gate MOSFET device, which is prepared using the shielded gate MOSFET device fabrication method with bottom breakdown of enhanced trench 3 described in this application.

[0096] The device comprises a heavily doped substrate 1 and a lightly doped epitaxial layer 2 on the substrate 1. Cellular trenches 3 are formed in the epitaxial layer 2, and the inner walls and bottom of the trenches 3 are covered with a composite shielding gate oxide layer. The composite shielding gate oxide layer is an OXO three-layer stacked structure, including a first SiO2 insulating layer in contact with silicon, a high-k dielectric layer (such as HfO2 or ZrO2) in the middle, and a second SiO2 insulating layer in contact with the shielding electrode. The physical thickness of this composite shielding gate oxide layer is smaller than that of a conventional single SiO2 shielding gate oxide layer, but its equivalent oxide layer thickness is not less than that of conventional solutions; therefore, the bottom of the trench 3 exhibits excellent breakdown characteristics.

[0097] Inside trench 3, the shielding electrode is located at the bottom and is isolated from epitaxial layer 2 by a composite shielding gate oxide layer; the gate electrode is located above the shielding electrode and is longitudinally isolated from the shielding electrode by an IPO and laterally isolated from the channel region by the gate oxide layer 9. The top of the shielding electrode is lower than the upper surface of epitaxial layer 2, and the IPO covers the top of the shielding electrode. On the top of epitaxial layer 2 (the mesa region between adjacent trenches 3), a body region 11 and a source region 12 are formed, wherein the body region 11 is located inside epitaxial layer 2, and the source region 12 is located on top of the body region 11. A dielectric layer (BPSG) is formed on the device surface, and contact holes are formed in the dielectric layer. The bottom of the contact holes reaches the surface of the source region 12, and the contact holes are filled with metal plugs to electrically connect the source region 12 and the body region 11 and lead them out to the source metal layer on the surface. A metal layer is deposited on the back side of substrate 1 as a drain electrode 17.

[0098] The key electrical performance advantages of this device are as follows: due to the use of an OXO composite shielding gate oxide layer, the depletion capability of the shielding electrode to the epitaxial layer 2 is significantly enhanced, allowing the epitaxial layer 2 to use a higher doping concentration than conventional schemes, while the cell pitch can be further reduced. The synergistic effect of these two factors results in a device with a significantly lower specific on-resistance (Rsp) than devices using a conventional single SiO2 shielding gate oxide layer, while the breakdown voltage at the bottom of trench 3 does not decrease but increases.

[0099] The following explanation, based on the electrical working mechanism of the device, will provide further details: When the device is in forward conduction (positive voltage applied to the gate and drain 17), a conductive channel is formed on the surface of the epitaxial layer 2 below the gate oxide layer 9. Electrons enter the epitaxial layer 2 (drift region) from the source region 12 through the channel, and then flow to the drain 17 through the current path below the shielding electrode. Due to the high doping concentration of the epitaxial layer 2, the resistivity of the drift region is low, and the on-state voltage drop is small, resulting in a low specific on-resistance. At the same time, because the physical thickness of the composite shielding gate oxide layer is thin, the width of the trench 3 can be further reduced, the number of cells per unit area increases, the total on-state current increases, and the specific on-resistance is further reduced.

[0100] When the device is in reverse blocking state (zero or negative voltage applied to the gate and high voltage applied to the drain 17), the shielding electrode generates strong lateral depletion of the drift region through the composite shielding gate oxide layer, which makes the electric field distribution at the bottom of the trench 3 tend to flatten, avoiding the electric field concentration phenomenon at the bottom corner of the trench in the traditional trench MOSFET, thus achieving high breakdown voltage without increasing or even reducing the thickness of the epitaxial layer 2.

[0101] The SGT MOSFET device fabricated using the method for enhancing trench bottom breakdown of the shielded gate MOSFET device provided in this application has the combined advantages of high breakdown voltage, low specific on-resistance and high cell density, and can be widely used in power electronics fields such as power management, motor drive, and battery protection.

[0102] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a shielded gate MOSFET device with enhanced trench bottom breakdown, characterized in that, The method includes: A substrate is provided, and an epitaxial layer is formed on the substrate; Trenches are formed in the epitaxial layer; A composite shielding gate oxide layer is formed on the inner wall and bottom of the trench. The composite shielding gate oxide layer includes a first oxide layer, a high dielectric constant dielectric layer and a second oxide layer. The high dielectric constant dielectric layer is located between the first oxide layer and the second oxide layer. The dielectric constant of the high dielectric constant dielectric layer is greater than that of silicon dioxide. A shielding electrode is formed on the composite shielding gate oxide layer; A gate electrode is formed above the shielding electrode; A body region and a source region are formed on the top of the epitaxial layer; A dielectric layer is formed on the surface of the device, a contact hole is formed by etching the dielectric layer, and an electrode lead is formed in the contact hole and on the surface of the dielectric layer.

2. The method according to claim 1, characterized in that, The dielectric constant of the high dielectric constant dielectric layer is greater than 20.

3. The method according to claim 1, characterized in that, The materials of the first oxide layer and the second oxide layer are silicon dioxide.

4. The method according to claim 1, characterized in that, The material of the high dielectric constant dielectric layer is at least one of hafnium oxide or zirconium oxide.

5. The method according to claim 1, characterized in that, Under the same breakdown voltage conditions, the total physical thickness of the composite shielding gate oxide layer is less than the physical thickness of the single-layer silicon dioxide shielding gate oxide layer.

6. The method according to claim 1, characterized in that, The doping concentration of the epitaxial layer is higher than that of the epitaxial layer when a single layer of silicon dioxide shielding gate oxide is used.

7. The method according to claim 1, characterized in that, The equivalent oxide layer thickness of the composite shielding gate oxide layer is not less than the thickness of a single-layer silicon dioxide shielding gate oxide layer under the same breakdown voltage.

8. The method according to claim 1, characterized in that, The first oxide layer is formed by thermal oxidation or chemical vapor deposition, the high dielectric constant dielectric layer is formed by atomic layer deposition or chemical vapor deposition, and the second oxide layer is formed by chemical vapor deposition or thermal oxidation.

9. The method according to claim 1, characterized in that, A gate electrode is formed above the shielding electrode, including: A gate oxide layer is grown on the surface of the epitaxial layer and the sidewalls of the trench, polysilicon is deposited and etched back to form the gate electrode.

10. A shielded gate MOSFET device, characterized in that, The shielded gate MOSFET device is prepared using the shielded gate MOSFET device preparation method with enhanced trench bottom breakdown as described in any one of claims 1-9.

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