A method for manufacturing a silicon carbide MOSFET device

Abstract

The application discloses a preparation method of a silicon carbide MOSFET device and relates to the technical field of semiconductor devices.The technical scheme of the application comprises the following specific steps: collecting substrate cross-section detection data after groove etching of a silicon carbide wafer, dividing the internal wafer into sub-regions according to the substrate cross-section detection data to obtain process control sub-regions, and matching corresponding process standard process parameters and short-circuit resistance performance influence weights of each process control sub-region; collecting on-site measured process parameters of each process control sub-region, and calculating process adaptation coefficients of each region according to the measured process parameters, the process standard process parameters and the short-circuit resistance performance influence weights.The effect is that the process fault tolerance capability of different position structures can be matched, the process deviation of the quantitative shielding voltage resistance, heat dissipation capability and conduction current limiting is facilitated, the performance evaluation error caused by the structural attribute difference of different positions of the wafer is reduced, and the discrete interval of the short-circuit resistance performance of the same wafer device is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a method for fabricating a silicon carbide MOSFET device. Background Technology

[0002] Silicon carbide MOSFETs are widely used in new energy vehicle on-board converters, energy storage grid-connected converters, and high-voltage industrial power supplies due to their wider bandgap, excellent thermal conductivity, and high voltage withstand characteristics. The short-circuit withstand performance of the device is a core indicator that determines the reliability of the entire system.

[0003] In the current mass production process of trench-shielded silicon carbide MOSFETs, local process deviations are easily generated in the trench etching, shielding layer ion implantation, thermally conductive filler filling, and JFET annealing processes. The cell arrangement density varies at different locations on the wafer, and fluctuations in chamber pressure, uneven filler delivery velocity, and changes in lateral temperature gradient during annealing cause process errors at a single point to spread to surrounding blocks through lattice stress and thermal conduction, forming original defect points and latent defect points affected by crosstalk. This results in a large dispersion in the short-circuit withstand performance of devices produced from the same wafer, and an increase in the short-circuit failure rate of batch products. Moreover, existing conventional process control mostly uses a uniform sampling inspection of the entire wafer to determine the process qualification level, only judging the parameter deviation of the inspection point itself, without dividing and controlling sub-regions according to wafer cell arrangement, shielding layer layout, and heat dissipation channel distribution. It is impossible to separately statistically analyze the process adaptation level of the three types of blocks: shielding layer formation, heat dissipation channel processing, and current-limiting JFET doping. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, the purpose of this invention is to provide a method for fabricating silicon carbide MOSFET devices.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for fabricating a silicon carbide MOSFET device, the method comprising the following specific steps:

[0007] Data on the substrate cross-section after trench etching of silicon carbide wafers are collected. Based on the data on the substrate cross-section, the wafer interior is divided into process control sub-regions. Corresponding process standard process parameters and short-circuit withstand performance influence weights are matched to each process control sub-region.

[0008] Collect on-site measured process parameters for each process control sub-region, and calculate the process adaptation coefficient for each region based on the measured process parameters, standard process parameters, and the influence weight of short-circuit withstand performance. Match the process adaptation coefficient with the preset short-circuit performance qualification threshold to obtain the process mismatch control sub-region.

[0009] Extract the baseline process deviation index corresponding to the process mismatch control sub-region. Based on the wafer area spacing and the degree of process crosstalk between etching and doping processes, calculate the neighboring process offset caused by the diffusion of the baseline process deviation index to the surrounding area to obtain the process offset control sub-region.

[0010] Based on the area ratio of the process mismatch control sub-region and the process offset control sub-region, a comprehensive score for the short-circuit tolerance process of the entire wafer is generated by combining the preset grade weights.

[0011] Based on the comprehensive score, a standardized fabrication and control process for trench-shielded silicon carbide MOSFETs with high short-circuit tolerance index was obtained by adjusting the ion implantation dose of the bottom shielding layer of the trench, the filling and compaction parameters of the high thermal conductivity filler, and the annealing and holding time of the JFET region.

[0012] Preferably, the process control sub-region includes a shielding layer forming sub-region, a heat dissipation channel processing sub-region, and a current-limiting JFET doping process control sub-region.

[0013] Preferably, it further includes:

[0014] The process control sub-regions are divided according to the wafer cell arrangement, the layout of the bottom shielding layer of the trench, and the distribution of the lateral heat dissipation channels. Each process control sub-region is matched with the baseline process deviation range.

[0015] Process environmental parameters are obtained by collecting measured data on gas pressure fluctuations in the ion implantation chamber, flow rate in the chamber during the media filling process, and transverse temperature gradient during the high-temperature annealing process.

[0016] The sub-region spacing is obtained by calculating the planar spacing between adjacent process control sub-regions. Based on the sub-region spacing and process environment parameters, the process crosstalk attenuation coefficient corresponding to different sub-region spacing distances is determined.

[0017] A reference table for calculating adjacent area process offset is formed by integrating plane spacing, process crosstalk attenuation coefficient, and process environment parameters.

[0018] Preferably, the standard process parameters and short-circuit withstand performance influence weights of corresponding processes are matched to each process control sub-region, specifically including the following steps:

[0019] The deviation of each wafer process control sub-region is calculated based on the planar distribution of each process control sub-region and the area ratio of each wafer to obtain the single-region process deviation;

[0020] Based on the impact of single-region process deviation on device short-circuit withstand voltage, peak current, and high-temperature heat dissipation, the corresponding process standard parameters and their impact weights on short-circuit withstand performance are matched to different control sub-regions.

[0021] Preferably, the process parameters of each process control sub-region are collected on-site and measured. Based on the measured process parameters, standard process parameters, and the influence weight of short-circuit withstand performance, the process adaptation coefficient of each region is calculated. This specifically includes the following steps:

[0022] Calculate the difference between the actual measured process parameters of a single-zone control sub-region and the corresponding standard process parameters to obtain the process deviation values ​​corresponding to different process dimensions;

[0023] Based on the short-circuit tolerance performance impact weight configured in the corresponding dimension, the process deviation values ​​are weighted and calculated to obtain the process adaptation coefficient corresponding to the process control sub-region.

[0024] Preferably, the process mismatch control sub-region is obtained by matching the process adaptation coefficient with a preset short-circuit performance qualification threshold, specifically including the following steps:

[0025] When the single-zone process adaptation coefficient is greater than or equal to the preset short-circuit performance qualification threshold, it is determined that the molding quality of the corresponding process in the process control sub-zone meets the short-circuit tolerance design index.

[0026] If the process adaptation coefficient of a single area is less than the preset short-circuit performance qualification threshold, the forming quality of the process in the process control sub-area is determined to be substandard, and the process control sub-area is marked as a process mismatch control sub-area.

[0027] Preferably, the process mismatch control sub-region is obtained by extracting the baseline process deviation index corresponding to the process mismatch control sub-region, and calculating the neighboring process offset caused by the diffusion of the baseline process deviation index to the surrounding area based on the wafer area spacing and the degree of process crosstalk between etching and doping processes. This includes the following steps:

[0028] Extract the baseline process deviation index corresponding to the process mismatch control sub-region, and calculate the neighboring process offset caused by the diffusion of the baseline process deviation index to the surrounding area based on the wafer area spacing and the degree of process crosstalk between etching and doping processes.

[0029] The process offset of the neighboring area is added to the original process adaptation coefficient of the surrounding sub-region, and the corrected process adaptation coefficient of the surrounding area is calculated.

[0030] The process offset control sub-region is obtained by comparing the modified process adaptation coefficient with the preset short-circuit performance qualification threshold.

[0031] Preferably, the baseline process deviation index corresponding to the process mismatch control sub-region is extracted, and the neighboring process offset caused by the diffusion of the baseline process deviation index to the surrounding area is calculated based on the wafer area spacing and the degree of process crosstalk between etching and doping processes. Specifically, this includes the following steps:

[0032] Based on all adjacent process control sub-regions of the process mismatch control sub-region, extract the planar distance between the mismatch region and each adjacent region;

[0033] The process crosstalk attenuation coefficient for the corresponding grade in the reference table is calculated based on the measured plane spacing and the process offset of the adjacent area.

[0034] The process parameters are formed by collecting real-time data on air pressure fluctuations, packing conveying flow rate, and annealing transverse temperature gradient in the current process chamber. The process parameters are then matched with corresponding air pressure correction coefficients, flow rate correction coefficients, and temperature gradient correction coefficients to form process correction coefficients.

[0035] The preset crosstalk attenuation base weight, air pressure correction weight, flow rate correction weight, and temperature correction weight form the process correction weight. The process correction coefficient and the corresponding process correction weight are combined to calculate the single-area comprehensive crosstalk coefficient.

[0036] The neighboring process offset corresponding to the adjacent control sub-region is calculated based on the baseline process deviation index and the single-region comprehensive crosstalk coefficient.

[0037] Preferably, the process offset of the adjacent area is superimposed onto the original process adaptation coefficient of the surrounding sub-region, and the corrected process adaptation coefficient of the surrounding region is calculated. This specifically includes the following steps:

[0038] Obtain the original process adaptation coefficients of adjacent process control sub-regions;

[0039] The corrected process adaptation coefficient is obtained by calculating the original process adaptation coefficient and the process offset of the adjacent area.

[0040] Preferably, based on the area ratio of the process mismatch control sub-region and the process offset control sub-region, and combined with preset hierarchical weights, a comprehensive score for the short-circuit tolerance process of the entire wafer is generated, specifically including the following steps:

[0041] If the corrected process adaptation coefficient is less than the preset short-circuit performance qualification threshold, it is determined that the adjacent area is negatively affected by cross-regional process crosstalk and is marked as a process offset control sub-area.

[0042] Integrate the process control area of ​​the entire wafer, and calculate the proportion of the primary area corresponding to the process mismatch control sub-region and the proportion of the secondary area corresponding to the process offset control sub-region.

[0043] The mismatch weighting coefficient and offset weighting coefficient are preset, and the overall short-circuit tolerance score of the entire wafer is calculated based on the first-level area ratio, mismatch weighting coefficient, second-level area ratio, and offset weighting coefficient.

[0044] Compared with existing technologies, this invention has the following advantages: It achieves refined zoning control based on wafer cell arrangement, trench bottom shielding layer layout, and lateral heat dissipation channel distribution. It independently manages sub-regions for shielding layer forming, heat dissipation channel processing, and current-limiting JFET doping process control, solving the problem that uniform sampling inspection of the entire wafer cannot distinguish the process adaptation levels of different structural blocks. By matching exclusive process standard parameters and differentiated short-circuit withstand performance influence weights to various blocks in different regions, it can better match the process fault tolerance of different structural locations, facilitating quantified shielding. Process deviations in withstand voltage, heat dissipation, and conduction current limiting reduce performance evaluation errors caused by structural attribute differences at different locations on the wafer, narrowing the dispersion range of short-circuit withstand performance of devices on the same wafer. The process crosstalk attenuation coefficient is obtained by looking up a table based on the regional planar spacing. Real-time operating data such as chamber pressure fluctuations, packing flow rate, and annealing lateral temperature gradient are incorporated to solve for the comprehensive crosstalk coefficient of a single region, calculating the process offset of adjacent regions. This corrects the original process adaptation coefficients of surrounding points, facilitating the distinction between process mismatch control sub-regions caused by native defects and process offset control sub-regions induced by process crosstalk. It also facilitates the identification of hidden weak points derived from crosstalk, reducing the problem of missed detection of potential short-circuit failures within the wafer, and proactively locating hidden points prone to overheating breakdown and electric field concentration failures, thereby reducing the probability of batch short-circuit failures in finished devices. Attached Figure Description

[0045] Figure 1 This is a schematic diagram illustrating a method for fabricating a silicon carbide MOSFET device according to an embodiment of the present invention;

[0046] Figure 2 This is a schematic diagram illustrating the process adaptation coefficient obtained by a method for fabricating a silicon carbide MOSFET device according to an embodiment of the present invention. Detailed Implementation

[0047] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0049] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.

[0050] Reference Figures 1-2 As shown.

[0051] The embodiments further illustrate the fabrication method of a silicon carbide MOSFET device proposed in this invention.

[0052] A method for fabricating a silicon carbide MOSFET device, the method comprising the following specific steps:

[0053] Data on the substrate cross-section after trench etching of silicon carbide wafers are collected. Based on the data on the substrate cross-section, the wafer interior is divided into process control sub-regions. Corresponding process standard process parameters and short-circuit withstand performance influence weights are matched to each process control sub-region.

[0054] Collect on-site measured process parameters for each process control sub-region, and calculate the process adaptation coefficient for each region based on the measured process parameters, standard process parameters, and the influence weight of short-circuit withstand performance. Match the process adaptation coefficient with the preset short-circuit performance qualification threshold to obtain the process mismatch control sub-region.

[0055] Extract the baseline process deviation index corresponding to the process mismatch control sub-region. Based on the wafer area spacing and the degree of process crosstalk between etching and doping processes, calculate the neighboring process offset caused by the diffusion of the baseline process deviation index to the surrounding area to obtain the process offset control sub-region.

[0056] Based on the area ratio of the process mismatch control sub-region and the process offset control sub-region, a comprehensive score for the short-circuit tolerance process of the entire wafer is generated by combining the preset grade weights.

[0057] Based on the comprehensive score, a standardized fabrication and control process for trench-shielded silicon carbide MOSFETs with high short-circuit tolerance index was obtained by adjusting the ion implantation dose of the bottom shielding layer of the trench, the filling and compaction parameters of the high thermal conductivity filler, and the annealing and holding time of the JFET region.

[0058] The process control sub-region includes the shielding layer forming sub-region, the heat dissipation channel processing sub-region, and the current-limiting JFET doping process control sub-region.

[0059] The shielding layer forming sub-region corresponds to the shielding ion implantation related structure at the bottom of the trench. The short-circuit withstand performance of this region has a weight of 0.45. Since the doping dose deviation of the shielding layer directly changes the electric field distribution at the bottom of the trench, the weight value is relatively high. The process adaptation coefficient of the shielding layer forming sub-region = 1 - the absolute value of the measured implantation dose deviation ÷ the standard implantation dose reference value. When the adaptation coefficient is lower than the qualified threshold of 0.75, this region is judged as a process mismatch region. For example, if the standard ion implantation dose is set to 1.2E15 per square centimeter, and the measured value shows a 20% negative shift, the adaptation coefficient can be calculated as 0.80. This meets the qualified range and will not be marked as mismatch. If the shift reaches 30%, the adaptation coefficient will drop to 0.70, triggering the mismatch judgment. The process deviation in this region will also diffuse to the surrounding areas based on the lattice stress inside the wafer, resulting in a shift.

[0060] The heat dissipation channel processing sub-region controls the entire process of filling and compacting high thermal conductivity filler. The short-circuit withstand performance has an impact weight of 0.30. The heat dissipation structure determines the heat dissipation rate of the device under short-circuit conditions. The process adaptation coefficient of the heat dissipation channel processing sub-region = 1 - the absolute value of the measured compaction pressure deviation ÷ the standard compaction pressure reference value. For example, if the standard compaction pressure is set to 42 MPa, and the measured pressure is 7 MPa lower than the reference, the adaptation coefficient is approximately 0.83, which meets the qualified standard. Insufficient compaction pressure will increase the porosity inside the filler, and heat accumulation will shorten the short-circuit withstand time of the device. The process deviation generated in this region mainly relies on heat conduction to complete the offset transfer between adjacent regions.

[0061] The current-limiting JFET doping process control sub-region manages the doping and annealing processes in the JFET region. The short-circuit withstand performance has a weight of 0.25. The doping concentration and annealing holding time in the JFET region will regulate the channel on-resistance. The process adaptation coefficient of the current-limiting JFET doping process control sub-region is calculated as 1 - the absolute value of the deviation of the measured annealing holding time ÷ the standard annealing holding time baseline value. For example, if the standard holding time is 110 minutes and the measured time is 14 minutes less, the adaptation coefficient is calculated to be approximately 0.87, which meets the qualification requirements. Insufficient holding time will increase the lattice defect density, and local breakdown is more likely to occur at the current concentration location under short-circuit conditions.

[0062] After determining the single-region adaptation coefficient and screening process mismatch areas, the process offset of neighboring regions is calculated using the region spacing and the crosstalk intensity of the etching and doping processes. The neighboring region process offset = baseline process deviation index × region spacing attenuation coefficient × process crosstalk coefficient, thus defining process offset control sub-regions. Subsequently, a comprehensive wafer-wide scoring calculation is performed. The comprehensive score = shielding layer area ratio × 0.45 + heat dissipation area ratio × 0.30 + JFET area ratio × 0.25. Mismatched regions will have deductions added to the original weighted average, while offset regions will receive smaller deductions. Based on the final comprehensive score, the corresponding process parameters are iterated. The shielding layer forming sub-region fine-tunes the ion implantation dose according to the score, the heat dissipation channel processing sub-region corrects the filler compaction parameters, and the current-limiting JFET doping process control sub-region adjusts the annealing holding time. After iterative iteration, a standardized fabrication control process adapted to high short-circuit tolerance is output.

[0063] Also includes:

[0064] The process control sub-regions are divided according to the wafer cell arrangement, the layout of the bottom shielding layer of the trench, and the distribution of the lateral heat dissipation channels. Each process control sub-region is matched with the baseline process deviation range.

[0065] Process environmental parameters are obtained by collecting measured data on gas pressure fluctuations in the ion implantation chamber, flow rate in the chamber during the media filling process, and transverse temperature gradient during the high-temperature annealing process.

[0066] The sub-region spacing is obtained by calculating the planar spacing between adjacent process control sub-regions. Based on the sub-region spacing and process environment parameters, the process crosstalk attenuation coefficient corresponding to different sub-region spacing distances is determined.

[0067] A reference table for calculating adjacent area process offset is formed by integrating plane spacing, process crosstalk attenuation coefficient, and process environment parameters.

[0068] The system matches and binds the partitions and deviation ranges of the process control sub-regions. The partition determination relies on the physical structure of the wafer cell arrangement, the layout of the shielding layer at the bottom of the trench, and the distribution of the lateral heat dissipation channels. Different structures correspond to regions with different inherent process fault tolerance capabilities. According to the control requirements of short-circuit withstand performance, the system matches a dedicated baseline process deviation range for each partitioned sub-region. For example, the shielding structure corresponding to cells with lower cell density at the wafer edge can accept 7% process parameter fluctuation, while the tightly packed cells in the wafer center only allow parameter fluctuations within 4%. The difference in the range values ​​can adapt to the anti-deviation capabilities of different structural positions in advance, reducing the control errors caused by the initial region partitioning.

[0069] Three types of on-site measurements are collected and summarized to generate process environment parameters. The three monitoring objects are: pressure fluctuation in the ion implantation chamber, flow rate in the chamber during the media filling process, and lateral temperature gradient in the high-temperature annealing process. The process environment parameter is calculated as: pressure fluctuation correction value + flow rate fluctuation correction value + lateral temperature gradient correction value. The three sub-items are first converted into dimensionless fluctuation values ​​before being summed. For example, if a single mass production monitoring yields a pressure fluctuation correction value of 0.12, a flow rate fluctuation correction value of 0.08, and a lateral temperature gradient correction value of 0.15, substituting these values ​​into the formula will result in a process environment parameter of 0.35. A larger parameter value indicates stronger disturbances in the current production environment, making it easier for process deviations to spread to surrounding areas.

[0070] The lateral plane spacing between adjacent process control sub-regions is calculated to obtain the sub-region spacing. The process crosstalk attenuation coefficient is derived using two variables: sub-region spacing and process environment parameter. The process crosstalk attenuation coefficient = reference attenuation base - sub-region spacing × distance attenuation slope + process environment parameter × environmental disturbance amplification factor. For example, selecting a fixed reference attenuation base of 0.9, a distance attenuation slope of 0.002 per micrometer, and an environmental disturbance amplification factor of 0.4, with a sub-region spacing of 20 micrometers and a process environment parameter of 0.35, the process crosstalk attenuation coefficient is calculated as 0.9 - 20 × 0.002 + 0.35 × 0.4 = 0.9. As the sub-region spacing increases, the attenuation coefficient decreases, indicating that the transmission effect of deviations at distant locations is weakened. Stronger operating disturbances will increase the attenuation coefficient, extending the crosstalk influence range.

[0071] The process crosstalk attenuation coefficient and process environment parameters corresponding to all points are structurally summarized to construct a reference table for neighboring area process offset calculation. The table is divided into multiple rows according to the spacing level, and each row is associated with the attenuation coefficient value under the corresponding operating condition. When calculating the neighboring area process offset, the matching coefficient is directly retrieved from the table. The neighboring area process offset = baseline process deviation index × process crosstalk attenuation coefficient obtained from the table. The neighboring area process offset calculation reference table can save the step of repeated calculation in a single production run, improve the efficiency of the whole wafer deviation diffusion measurement, and also ensure that the offset calculation standard of different production batches remains consistent, providing a standardized data reference for the full-domain deviation investigation of silicon carbide MOSFET wafer short-circuit withstand performance.

[0072] The process control sub-regions are matched with the corresponding standard process parameters and the weights of short-circuit withstand performance, which specifically include the following steps:

[0073] The deviation of each wafer process control sub-region is calculated based on the planar distribution of each process control sub-region and the area ratio of each wafer to obtain the single-region process deviation;

[0074] Based on the impact of single-region process deviation on device short-circuit withstand voltage, peak current, and high-temperature heat dissipation, the corresponding process standard parameters and their impact weights on short-circuit withstand performance are matched to different control sub-regions.

[0075] Quantitative calculations of single-area process deviations are performed based on two fundamental attributes of the process control sub-regions: the sub-region's location on the wafer plane and its area percentage within the entire wafer. The planar location is used to introduce a position deviation correction factor. The wafer center region experiences structural stress concentration, resulting in a larger position deviation correction factor. Wafer edges are affected by edge field disturbances from equipment. Therefore, single-area process deviation = inherent baseline deviation of the region × position deviation correction factor × area percentage of the region. Taking the wafer center shielding layer forming sub-region as an example, the inherent reference deviation of the region is set to 0.03, the center position deviation correction coefficient is 1.3, and the area of ​​this region accounts for 0.22 of the entire wafer. Substituting into the formula, the single-region process deviation can be calculated as 0.03 × 1.3 × 0.22 = 0.00858. If we change it to the wafer edge heat dissipation channel sub-region with an area ratio of 0.11, the edge position deviation correction coefficient is 1.1, and the calculated single-region process deviation will drop back to 0.00363. The numerical difference can intuitively reflect the effect of position and area scale on the magnitude of regional deviation.

[0076] After quantifying the process deviation in a single region, and considering the varying degrees of impact of the deviation on the three key short-circuit performance characteristics of the device, the influence weights of the standard process parameters and short-circuit withstand performance are matched in different regions. The three affected performance characteristics are, in order, short-circuit withstand voltage, peak current, and high-temperature heat dissipation. A higher single-region process deviation value indicates that process fluctuations in that region are more likely to worsen the device's short-circuit performance. A decline in withstand voltage increases the probability of short-circuit breakdown, an imbalance in peak current can cause localized current overload and structural ablation, and poor high-temperature heat dissipation accelerates heat accumulation and shortens the device's short-circuit withstand duration. When matching the standard process parameters, the allowable fluctuation range for process parameters is tightened in sub-regions with high deviations. For example, in the central shielding layer region with a deviation of approximately 0.008, the allowable fluctuation range for ion implantation dose is limited to 4%, while in the edge heat dissipation region with low deviations, the filler compaction pressure can be relaxed to a fluctuation range of 7%.

[0077] The weighting of short-circuit withstand performance is determined by assigning values ​​based on the disturbance intensity of short-circuit withstand voltage, peak current, and high-temperature heat dissipation. The total score for a region is obtained by adding the contributions of withstand voltage disturbance, current disturbance, and heat dissipation disturbance. The weight of each item is then calculated by dividing the total score by the individual item's weight. For example, if the withstand voltage disturbance contribution is 42, the current disturbance contribution is 33, and the heat dissipation disturbance contribution is 25, the total score is 42 + 33 + 25 = 100. The weight corresponding to withstand voltage is 42 ÷ 100 = 0.42, the weight corresponding to current is 33 ÷ 100 = 0.33, and the weight corresponding to heat dissipation is 25 ÷ 100 = 0.25. A higher weighting for a performance dimension indicates that this region is more sensitive to short-circuit failures. Subsequent process adaptation coefficient calculations and comprehensive wafer scoring will rely on this regional weighting for weighted calculations. Differentiated parameter constraints and weight assignments for different regions can correct for natural process disturbance differences in different locations on the wafer, reduce the batch dispersion of short-circuit withstand performance of finished silicon carbide wafer devices, and improve the yield level of mass production.

[0078] Collect on-site measured process parameters for each process control sub-region, and calculate the process adaptation coefficient for each region based on the measured process parameters, standard process parameters, and the influence weight of short-circuit withstand performance. This process includes the following steps:

[0079] Calculate the difference between the actual measured process parameters of a single-zone control sub-region and the corresponding standard process parameters to obtain the process deviation values ​​corresponding to different process dimensions;

[0080] Based on the short-circuit tolerance performance impact weight configured in the corresponding dimension, the process deviation values ​​are weighted and calculated to obtain the process adaptation coefficient corresponding to the process control sub-region.

[0081] Batch data collection was performed on-site for each process control sub-region, including on-site measured data for shielding layer ion implantation dose, thermally conductive filler compaction pressure, and JFET annealing holding time. These data were then matched with pre-set standard process parameters for each sub-region to perform difference calculations, breaking down the process deviation values ​​for different process dimensions. The single process deviation value is calculated as: single-dimensional on-site measured process parameter - single-dimensional standard process parameter. A negative difference indicates that the measured parameter is lower than the standard reference, while a positive difference indicates that the measured parameter exceeds the reference range. Taking a shielding layer forming sub-region within the wafer as an example, the standard ion implantation dose for the shielding layer is set to 1.2 × 10¹. 5 The actual measured dose per square centimeter was 1.02 × 10¹ 5 Substituting the values ​​into the formula, we can obtain the process deviation value per square centimeter as 1.02 × 10¹. 5 -1.2×10¹ 5 =-0.18×10¹ 5The standard compaction pressure of the thermally conductive filler per square centimeter is 42 MPa, while the actual measured pressure is 39 MPa. The corresponding process deviation is 39 - 42 = -3 MPa. The standard annealing holding time in the JFET zone is set to 110 minutes, while the actual measured time is 100 minutes. The process deviation is 100 - 110 = -10 minutes. Different sub-deviations can individually reflect the deviation of a single process from the design baseline.

[0082] After solving for the individual deviations, a weighted calculation is performed based on the pre-allocated short-circuit withstand performance influence weights for each process dimension. The original deviations with units are converted into dimensionless deviation proportions. The single-dimensional dimensionless deviation proportion = absolute value of process deviation value ÷ standard process parameter of process. Then, a weighted sum is performed based on the individual deviation weights. The process adaptation coefficient = 1 - (first dimensionless deviation proportion × first weight + second dimensionless deviation proportion × second weight + third dimensionless deviation proportion × third weight). For example, the weight of the shielding layer dimension is 0.45, and the deviation ratio is calculated to be 0.18 ÷ 1.2 = 0.15. The weight of the heat dissipation filler dimension is 0.30, and the deviation ratio is 3 ÷ 42 ≈ 0.0714. The weight of the JFET annealing dimension is 0.25, and the deviation ratio is 10 ÷ 110 ≈ 0.0909. Substituting these values ​​into the formula, the process adaptation coefficient is 1 - (0.15 × 0.45 + 0.0714 × 0.30 + 0.0909 × 0.25). Expanding each item, we get a process adaptation coefficient of ≈ 0.89.

[0083] The process fit coefficient is fixed between 0 and 1. The closer the calculated result is to 1, the higher the compatibility between the measured operating conditions and the standard process in this controlled sub-region, and the closer the short-circuit withstand performance of the devices in this region is to the design expectations. Regions with a fit coefficient below the preset acceptable threshold are marked as process mismatch controlled sub-regions. When the shielding layer process, which has a higher weight, experiences a significant deviation, the fit coefficient will drop more significantly, consistent with the stronger influence of the shielding layer structure on the short-circuit withstand performance of silicon carbide devices. This distinguishes the severity of deviations in different processes, avoids uniformly classifying process deviations of the same magnitude into risk levels, quantifies the process acceptance level of individual sub-regions, and provides standardized and quantitative data support for subsequent deviation diffusion extrapolation across the entire wafer and comprehensive short-circuit withstand performance scoring of the whole wafer.

[0084] The process mismatch control sub-region is obtained by matching the process adaptation coefficient with the preset short-circuit performance qualification threshold, which specifically includes the following steps:

[0085] When the single-zone process adaptation coefficient is greater than or equal to the preset short-circuit performance qualification threshold, it is determined that the molding quality of the corresponding process in the process control sub-zone meets the short-circuit tolerance design index.

[0086] If the process adaptation coefficient of a single area is less than the preset short-circuit performance qualification threshold, the forming quality of the process in the process control sub-area is determined to be substandard, and the process control sub-area is marked as a process mismatch control sub-area.

[0087] The process adaptation coefficient for a single region is compared with the preset short-circuit performance qualification threshold to complete the quality classification and mismatch point marking of the controlled sub-region. The process adaptation coefficient ranges from 0 to 1. The closer the value is to 1, the smaller the deviation of various process parameters in the region from the standard reference, and the better the molding quality performance related to the short-circuit tolerance of the device. The short-circuit performance qualification threshold is preset according to the performance level of the silicon carbide MOSFET product. In this mass production case, the short-circuit performance qualification threshold is set to 0.75.

[0088] Control measures are implemented for sub-regions where the process adaptation coefficient is greater than or equal to the threshold. Taking the shielding layer forming sub-region as an example, the process adaptation coefficient of this point was previously calculated to be 0.89. 0.89-0.75=0.14. The difference is positive and meets the judgment condition of being greater than or equal to the qualified threshold. The system will determine that the forming quality corresponding to the ion implantation filler compaction annealing in this region is all up to standard. The device short circuit, withstand voltage peak, and current carrying high temperature heat dissipation performance can reach the predetermined short circuit withstand design index. This region will not be included in the process mismatch point for subsequent deviation diffusion calculation. It will only be used as a benchmark normal region to participate in the routine weighting of the overall wafer comprehensive score.

[0089] Control measures are applied to sub-regions where the process adaptation coefficient is less than the threshold. Taking a heat dissipation channel processing sub-region at the wafer edge as an example, the thermal filler compaction pressure in this region is significantly lower than expected. The final calculated process adaptation coefficient is 0.68, and 0.68 - 0.75 = -0.07, resulting in a negative difference that does not meet the acceptance standard. The system determines that the process forming quality of this sub-region is substandard and directly marks this region as a process mismatch control sub-region. The process deviation in this region will be used as a baseline process deviation index and substituted into the calculation formula for the process offset of adjacent regions to complete the deviation diffusion calculation. Process offset = baseline process deviation index × process crosstalk attenuation coefficient. This is used to locate the surrounding process offset control sub-regions indirectly affected by the deviation. Mismatched regions will be given an additional deduction weight in the overall wafer scoring stage, with a weight value higher than that of ordinary offset regions.

[0090] This facilitates rapid quality screening of all subdivided control points within the wafer, enabling the identification of areas with inherent defects in short-circuit withstand performance and avoiding missed points due to manual sampling. Standardized numerical comparison rules unify the criteria for judging non-conforming points across different wafer batches. This provides clear guidance for localized process rework and offers a clear classification basis for the deduction rules in the overall short-circuit withstand process evaluation of the entire wafer. It helps staff identify the types of high-frequency mismatch processes, enabling reverse optimization of the control standards for the three core processes: shielding layer ion implantation, filler compaction, and JFET annealing, continuously improving the short-circuit withstand yield of silicon carbide MOSFET finished products.

[0091] Extract the baseline process deviation index corresponding to the process mismatch control sub-region. Based on the wafer area spacing and the degree of process crosstalk between etching and doping processes, calculate the neighboring process offset caused by the diffusion of the baseline process deviation index to the surrounding area to obtain the process offset control sub-region. The specific steps include:

[0092] Extract the baseline process deviation index corresponding to the process mismatch control sub-region, and calculate the neighboring process offset caused by the diffusion of the baseline process deviation index to the surrounding area based on the wafer area spacing and the degree of process crosstalk between etching and doping processes.

[0093] The process offset of the neighboring area is added to the original process adaptation coefficient of the surrounding sub-region, and the corrected process adaptation coefficient of the surrounding area is calculated.

[0094] The process offset control sub-region is obtained by comparing the modified process adaptation coefficient with the preset short-circuit performance qualification threshold.

[0095] The baseline process deviation index corresponding to the location is retrieved, and a quantitative conversion is performed based on the wafer area spacing and the degree of process crosstalk between the etching and doping processes. The adjacent area process offset = baseline process deviation index × distance attenuation factor × process crosstalk coefficient. For example, if the baseline process deviation index is 0.22, the distance attenuation factor corresponding to the adjacent sub-region spacing is set to 0.71, and the trench etching and shielding layer ion doping processes have strong mutual interference, with a process crosstalk coefficient of 0.83, substituting these values ​​into the formula yields the adjacent area process offset = 0.22 × 0.71 × 0.83 ≈ 0.13. As the area spacing increases, the distance attenuation factor will decrease accordingly, naturally weakening the deviation diffusion amplitude received by distant locations. The stronger the thermal stress and plasma disturbance in the etching and doping processes, the higher the process crosstalk coefficient, and the greater the force of deviation transmission to the surrounding areas.

[0096] The adaptation coefficient of surrounding points is corrected using a calculation. The corrected process adaptation coefficient = original process adaptation coefficient of surrounding area - process offset of neighboring area. Deviation propagation will reduce the original process adaptation level of surrounding areas. The larger the offset value, the greater the reduction in adaptation coefficient. For example, the original process adaptation coefficient of the affected adjacent heat dissipation channel sub-region was 0.84. Substituting it into the formula, we get the corrected process adaptation coefficient = 0.84 - 0.13 = 0.71, which is a significant drop compared to the initial level. If the surrounding points are farther away from the source of mismatch, the generated offset will be smaller, and the reduction in adaptation coefficient will be narrower accordingly.

[0097] A secondary judgment is performed by comparing the sample to a preset short-circuit performance qualification threshold. A comparison and verification are conducted based on a fixed threshold of 0.75. After correction, the resulting fit coefficient of 0.71 is less than 0.75. This area, which initially met the process requirements, is designated as a process offset control sub-region. For these locations, there are no direct process errors in the original process; the defects originate from stress and parameter disturbances transmitted from the mismatched area. In the overall wafer evaluation, the deduction weight set for the process offset control sub-region is lower than that for the process mismatch control sub-region at the source. This step-by-step calculation mode can capture hidden performance defects, avoiding missed performance risks caused by only screening original mismatched points. It comprehensively marks all weak points within the entire wafer affected by process crosstalk, making the subsequent wafer short-circuit tolerance comprehensive evaluation and process parameter correction control results more closely reflect the actual performance distribution of the wafer, improving the completeness of short-circuit failure risk identification in the mass production stage of silicon carbide MOSFETs.

[0098] Extract the baseline process deviation index corresponding to the process mismatch control sub-region. Based on the wafer region spacing and the degree of process crosstalk between etching and doping processes, calculate the neighboring region process offset caused by the diffusion of the baseline process deviation index to the surrounding region. This includes the following steps:

[0099] Based on all adjacent process control sub-regions of the process mismatch control sub-region, extract the planar distance between the mismatch region and each adjacent region;

[0100] The process crosstalk attenuation coefficient for the corresponding grade in the reference table is calculated based on the measured plane spacing and the process offset of the adjacent area.

[0101] The process parameters are formed by collecting real-time data on air pressure fluctuations, packing conveying flow rate, and annealing transverse temperature gradient in the current process chamber. The process parameters are then matched with corresponding air pressure correction coefficients, flow rate correction coefficients, and temperature gradient correction coefficients to form process correction coefficients.

[0102] The preset crosstalk attenuation base weight, air pressure correction weight, flow rate correction weight, and temperature correction weight form the process correction weight. The process correction coefficient and the corresponding process correction weight are combined to calculate the single-area comprehensive crosstalk coefficient.

[0103] The neighboring process offset corresponding to the adjacent control sub-region is calculated based on the baseline process deviation index and the single-region comprehensive crosstalk coefficient.

[0104] Data collection is conducted by using the process mismatch control sub-region as the source of deviation propagation. The system systematically filters all process control sub-regions adjacent to the mismatched region and measures the planar distance between the mismatch point and each adjacent region. Different distances represent the distance attenuation effect of the deviation during spatial propagation; the higher the distance value, the stronger the loss caused by the deviation as it propagates through space. For example, the planar distances between a mismatched shielding layer sub-region and two adjacent points are 18 micrometers and 35 micrometers, respectively. The two points will subsequently be matched with different base attenuation parameters.

[0105] Based on the measured planar spacing, a pre-compiled reference table for calculating process offset in adjacent areas was retrieved to determine the specific process crosstalk attenuation coefficient for that spacing level. The process crosstalk attenuation coefficient for 18 micrometers was set at 0.74, while the coefficient for the larger 35-micrometer spacing dropped to 0.51, directly reflecting the weakening of deviation propagation intensity as the distance increased. Three types of on-site operating conditions were collected to construct process correction coefficients. The three monitoring objects were, in order, real-time air pressure fluctuations in the process chamber, packing conveying flow rate, and annealing lateral temperature gradient. The sub-process correction coefficients were standardized and converted according to the magnitude of deviation from the standard values. For example, the air pressure correction coefficient was set at 1.08, the flow rate correction coefficient at 1.03, and the temperature gradient correction coefficient at 1.11.

[0106] The weighted calculation of the process correction weights is used to obtain the single-region comprehensive crosstalk coefficient. The single-region comprehensive crosstalk coefficient = process crosstalk attenuation coefficient × crosstalk attenuation base weight + pressure correction coefficient × pressure correction weight + flow rate correction coefficient × flow rate correction weight + temperature gradient correction coefficient × temperature correction weight. For example, if the crosstalk attenuation base weight is 0.52, the pressure correction weight is 0.18, the flow rate correction weight is 0.12, and the temperature correction weight is 0.18, and the parameters are substituted into adjacent regions with a spacing of 18 micrometers, the single-region comprehensive crosstalk coefficient = 0.74 × 0.52 + 1.08 × 0.18 + 1.03 × 0.12 + 1.11 × 0.18 ≈ 0.86. Stronger operating disturbances will increase the individual correction coefficients, ultimately resulting in a positive increase in the comprehensive crosstalk coefficient, amplifying the outward diffusion of deviations.

[0107] The process offset of adjacent areas is calculated as follows: Adjacent area process offset = baseline process deviation index × single-region comprehensive crosstalk coefficient. The baseline process deviation index for the mismatched region is fixed at 0.21. Substituting this into the formula, the adjacent area process offset is calculated as 0.21 × 0.86 ≈ 0.18. This offset is used to adjust the original process adaptation coefficient of adjacent areas to determine whether a point should be classified as a process offset control sub-region. It can simultaneously incorporate two influencing dimensions: spatial distance and real-time production conditions. This allows for better understanding of dynamic crosstalk changes caused by chamber pressure flow, packing material transport, and heat conduction, reducing the probability of missing latent process defects in silicon carbide MOSFET wafers and ensuring that the calculated deviation diffusion amplitude closely matches the actual process disturbance patterns on the wafer.

[0108] The process offset of the neighboring region is added to the original process adaptation coefficient of the surrounding sub-region, and the corrected process adaptation coefficient of the surrounding region is calculated. The specific steps include:

[0109] Obtain the original process adaptation coefficients of adjacent process control sub-regions;

[0110] The corrected process adaptation coefficient is obtained by calculating the original process adaptation coefficient and the process offset of the adjacent area.

[0111] The original process compatibility coefficients of adjacent process control sub-regions are retrieved in advance. These original values ​​are calculated solely based on the measured process parameters of the region itself, without incorporating the influence of process disturbances transmitted from surrounding mismatched points. This objectively reflects the original process compatibility level of the point. Taking the heat dissipation channel control sub-region of the adjacent mismatched shielding layer region as an example, the original process compatibility coefficient of this point was calculated separately in the early stage to be 0.83. Before the superposition of external disturbances, comparing it alone with the short-circuit performance qualification threshold of 0.75 can determine that the original process status meets the standard.

[0112] The corrected process adaptation coefficient is obtained by calculating the original process adaptation coefficient and the adjacent process offset. The corrected process adaptation coefficient = original process adaptation coefficient - adjacent process offset. For example, if the adjacent process offset is 0.18, the corrected process adaptation coefficient = 0.83 - 0.18 = 0.65. The magnitude of the adjacent process offset is determined by the spatial distance between the two points and the intensity of the chamber's operating condition disturbance. The closer the point is to the mismatch source and the stronger the fluctuation in the production environment, the higher the offset value, and the greater the reduction in the adaptation coefficient.

[0113] The corrected adaptation coefficient is then compared to the preset short-circuit performance pass threshold for quality assessment. If the corrected adaptation coefficient is less than the preset short-circuit performance pass threshold, the points that were originally qualified by the original process are classified into the process offset control sub-region. These regions do not have obvious process errors in their direct processes; the performance degradation is caused by lattice stress, thermal disturbance, and plasma crosstalk transmitted from adjacent mismatch points. In the overall short-circuit tolerance scoring of the entire wafer, the deduction weight of the process offset control sub-region is lower than that of the original process mismatch control sub-region, thus distinguishing the severity level of the defect source.

[0114] The revised and updated adaptation coefficients can restore the true global performance distribution of the wafer, reducing the problem of missing short-circuit failure hazards caused by only screening native mismatch points. This provides a higher quantitative basis for subsequent whole-wafer grading and scoring, and iterative optimization of process parameters. It also makes it easier for staff to distinguish between native process defects and crosstalk-derived defects, and to make targeted adjustments to the process control standards related to wafer local shielding layer injection, thermal filler compaction, and JFET annealing, thereby improving the batch consistency of short-circuit withstand performance in the mass production stage of silicon carbide MOSFET devices.

[0115] Based on the area ratio of the process mismatch control sub-region and the process offset control sub-region, a comprehensive score for the short-circuit tolerance process of the entire wafer is generated by combining preset hierarchical weights. The specific steps include:

[0116] If the corrected process adaptation coefficient is less than the preset short-circuit performance qualification threshold, it is determined that the adjacent area is negatively affected by cross-regional process crosstalk and is marked as a process offset control sub-area.

[0117] Integrate the process control area of ​​the entire wafer, and calculate the proportion of the primary area corresponding to the process mismatch control sub-region and the proportion of the secondary area corresponding to the process offset control sub-region;

[0118] The mismatch weighting coefficient and offset weighting coefficient are preset, and the overall short-circuit tolerance score of the entire wafer is calculated based on the first-level area ratio, mismatch weighting coefficient, second-level area ratio, and offset weighting coefficient.

[0119] Regional classification is based on the process adaptation coefficient. For example, if the short-circuit performance pass threshold is 0.75, and the process adaptation coefficient of a point is lower than 0.75, it means that this adjacent area is excessively interfered with by cross-regional process crosstalk from surrounding mismatched points, resulting in a significant decline in short-circuit tolerance performance reserves. This area will be officially designated as a process deviation control sub-region. For example, if the process adaptation coefficient of a surrounding point is 0.65, which is less than 0.75, the point is marked as a secondary defective area. The performance defect at this point is not caused by its own original process error, but by stress and heat conduction disturbances from adjacent mismatched areas. The inherent hazard of the defect is weaker than that of the originally non-conforming point.

[0120] The total area of ​​all controlled areas on the entire wafer is calculated, and the proportion of two types of defective areas is converted. The first-level area proportion = the sum of the areas of all process mismatch controlled sub-regions ÷ the total area of ​​the controlled area on the entire wafer; the second-level area proportion = the sum of the areas of all process offset controlled sub-regions ÷ the total area of ​​the controlled area on the entire wafer. For example, if the total controlled area of ​​the entire wafer is set to 100 square millimeters, the total area of ​​the process mismatch controlled sub-regions is taken as 7 square millimeters, and the total area of ​​the process offset controlled sub-regions is taken as 11 square millimeters, the first-level area proportion is calculated as 7 ÷ 100 = 0.07, and the second-level area proportion is calculated as 11 ÷ 100 = 0.11. These two proportions can intuitively reflect the coverage scale of defects of different hazard levels within the wafer.

[0121] Two types of differentiated weighting coefficients are pre-configured. The failure risk caused by native defects is higher, so the mismatch weighting coefficient is set to 0.72. The risk of crosstalk-derived defects is lower, so the offset weighting coefficient is set to 0.28. The full score of the comprehensive scoring benchmark is set to 100 points. The comprehensive score of the whole wafer short-circuit tolerance process is = 100 - first-level area ratio × mismatch weighting coefficient × 100 - second-level area ratio × offset weighting coefficient × 100. Substituting the previously calculated ratios, the comprehensive score of the whole wafer short-circuit tolerance process is = 100 - 0.07 × 0.72 × 100 - 0.11 × 0.28 × 100 = 93.08.

[0122] The closer the final score is to 100, the better the process control related to short-circuit tolerance of the entire wafer. This indicates a lower probability of short-circuit failures in mass-produced devices. The score can differentiate between risk levels of native process errors and cross-regional crosstalk-derived defects, without imposing the same deduction on both types of defects. The score accurately reflects the true overall process quality of the wafer. Based on the comprehensive score, staff can determine the wafer yield level and then optimize the process control parameters for three core processes: shielding layer ion implantation, thermally conductive filler compaction, and JFET annealing. This will improve the standardized manufacturing control process for silicon carbide MOSFET devices and continuously reduce the probability of mass failures under short-circuit conditions.

[0123] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a silicon carbide MOSFET device, characterized in that, The method includes the following specific steps: Data on the substrate cross-section after trench etching of silicon carbide wafers are collected. Based on the data on the substrate cross-section, the wafer interior is divided into process control sub-regions. Corresponding process standard process parameters and short-circuit withstand performance influence weights are matched to each process control sub-region. Collect on-site measured process parameters for each process control sub-region, and calculate the process adaptation coefficient for each region based on the measured process parameters, standard process parameters, and the influence weight of short-circuit withstand performance. Match the process adaptation coefficient with the preset short-circuit performance qualification threshold to obtain the process mismatch control sub-region. Extract the baseline process deviation index corresponding to the process mismatch control sub-region. Based on the wafer area spacing and the degree of process crosstalk between etching and doping processes, calculate the neighboring process offset caused by the diffusion of the baseline process deviation index to the surrounding area to obtain the process offset control sub-region. Based on the area ratio of the process mismatch control sub-region and the process offset control sub-region, a comprehensive score for the short-circuit tolerance process of the entire wafer is generated by combining the preset grade weights. Based on the comprehensive score, a standardized fabrication and control process for trench-shielded silicon carbide MOSFETs with high short-circuit tolerance index was obtained by adjusting the ion implantation dose of the bottom shielding layer of the trench, the filling and compaction parameters of the high thermal conductivity filler, and the annealing and holding time of the JFET region.

2. The method for fabricating a silicon carbide MOSFET device according to claim 1, characterized in that, The process control sub-region includes the shielding layer forming sub-region, the heat dissipation channel processing sub-region, and the current-limiting JFET doping process control sub-region.

3. The method for fabricating a silicon carbide MOSFET device according to claim 2, characterized in that, Also includes: The process control sub-regions are divided according to the wafer cell arrangement, the layout of the bottom shielding layer of the trench, and the distribution of the lateral heat dissipation channels. Each process control sub-region is matched with the baseline process deviation range. Process environmental parameters are obtained by collecting measured data on gas pressure fluctuations in the ion implantation chamber, flow rate in the chamber during the media filling process, and transverse temperature gradient during the high-temperature annealing process. The sub-region spacing is obtained by calculating the planar spacing between adjacent process control sub-regions. Based on the sub-region spacing and process environment parameters, the process crosstalk attenuation coefficient corresponding to different sub-region spacing distances is determined. A reference table for calculating adjacent area process offset is formed by integrating plane spacing, process crosstalk attenuation coefficient, and process environment parameters.

4. The method for fabricating a silicon carbide MOSFET device according to claim 3, characterized in that, The process control sub-regions are matched with the corresponding standard process parameters and the weights of short-circuit withstand performance, which specifically include the following steps: The deviation of each wafer process control sub-region is calculated based on the planar distribution of each process control sub-region and the area ratio of each wafer to obtain the single-region process deviation; Based on the impact of single-region process deviation on device short-circuit withstand voltage, peak current, and high-temperature heat dissipation, the corresponding process standard parameters and their impact weights on short-circuit withstand performance are matched to different control sub-regions.

5. The method for fabricating a silicon carbide MOSFET device according to claim 4, characterized in that, Collect on-site measured process parameters for each process control sub-region, and calculate the process adaptation coefficient for each region based on the measured process parameters, standard process parameters, and the influence weight of short-circuit withstand performance. This process includes the following steps: Calculate the difference between the actual measured process parameters of a single-zone control sub-region and the corresponding standard process parameters to obtain the process deviation values ​​corresponding to different process dimensions; Based on the short-circuit tolerance performance impact weight configured in the corresponding dimension, the process deviation values ​​are weighted and calculated to obtain the process adaptation coefficient corresponding to the process control sub-region.

6. The method for fabricating a silicon carbide MOSFET device according to claim 5, characterized in that, The process mismatch control sub-region is obtained by matching the process adaptation coefficient with the preset short-circuit performance qualification threshold, which specifically includes the following steps: When the single-zone process adaptation coefficient is greater than or equal to the preset short-circuit performance qualification threshold, it is determined that the molding quality of the corresponding process in the process control sub-zone meets the short-circuit tolerance design index. If the process adaptation coefficient of a single area is less than the preset short-circuit performance qualification threshold, the forming quality of the process in the process control sub-area is determined to be substandard, and the process control sub-area is marked as a process mismatch control sub-area.

7. The method for fabricating a silicon carbide MOSFET device according to claim 6, characterized in that, Extract the baseline process deviation index corresponding to the process mismatch control sub-region. Based on the wafer area spacing and the degree of process crosstalk between etching and doping processes, calculate the neighboring process offset caused by the diffusion of the baseline process deviation index to the surrounding area to obtain the process offset control sub-region. The specific steps include: Extract the baseline process deviation index corresponding to the process mismatch control sub-region, and calculate the neighboring process offset caused by the diffusion of the baseline process deviation index to the surrounding area based on the wafer area spacing and the degree of process crosstalk between etching and doping processes. The process offset of the neighboring area is added to the original process adaptation coefficient of the surrounding sub-region, and the corrected process adaptation coefficient of the surrounding area is calculated. The process offset control sub-region is obtained by comparing the modified process adaptation coefficient with the preset short-circuit performance qualification threshold.

8. The method for fabricating a silicon carbide MOSFET device according to claim 7, characterized in that, Extract the baseline process deviation index corresponding to the process mismatch control sub-region. Based on the wafer region spacing and the degree of process crosstalk between etching and doping processes, calculate the neighboring region process offset caused by the diffusion of the baseline process deviation index to the surrounding region. This includes the following steps: Based on all adjacent process control sub-regions of the process mismatch control sub-region, extract the planar distance between the mismatch region and each adjacent region; The process crosstalk attenuation coefficient for the corresponding grade in the reference table is calculated based on the measured plane spacing and the process offset of the adjacent area. The process parameters are formed by collecting real-time data on air pressure fluctuations, packing conveying flow rate, and annealing transverse temperature gradient in the current process chamber. The process parameters are then matched with corresponding air pressure correction coefficients, flow rate correction coefficients, and temperature gradient correction coefficients to form process correction coefficients. The preset crosstalk attenuation base weight, air pressure correction weight, flow rate correction weight, and temperature correction weight form the process correction weight. The process correction coefficient and the corresponding process correction weight are combined to calculate the single-area comprehensive crosstalk coefficient. The neighboring process offset corresponding to the adjacent control sub-region is calculated based on the baseline process deviation index and the single-region comprehensive crosstalk coefficient.

9. The method for fabricating a silicon carbide MOSFET device according to claim 8, characterized in that, The process offset of the neighboring region is added to the original process adaptation coefficient of the surrounding sub-region, and the corrected process adaptation coefficient of the surrounding region is calculated. The specific steps include: Obtain the original process adaptation coefficients of adjacent process control sub-regions; The corrected process adaptation coefficient is obtained by calculating the original process adaptation coefficient and the process offset of the adjacent area.

10. The method for fabricating a silicon carbide MOSFET device according to claim 9, characterized in that, Based on the area ratio of the process mismatch control sub-region and the process offset control sub-region, a comprehensive score for the short-circuit tolerance process of the entire wafer is generated by combining preset hierarchical weights. The specific steps include: If the corrected process adaptation coefficient is less than the preset short-circuit performance qualification threshold, it is determined that the adjacent area is negatively affected by cross-regional process crosstalk and is marked as a process offset control sub-area. Integrate the process control area of ​​the entire wafer, and calculate the proportion of the primary area corresponding to the process mismatch control sub-region and the proportion of the secondary area corresponding to the process offset control sub-region; The mismatch weighting coefficient and offset weighting coefficient are preset, and the overall short-circuit tolerance score of the entire wafer is calculated based on the first-level area ratio, mismatch weighting coefficient, second-level area ratio, and offset weighting coefficient.

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