Method for manufacturing a semiconductor device, semiconductor device

Abstract

The application discloses a semiconductor device preparation method and a semiconductor device. The semiconductor device preparation method comprises the following steps: providing a semiconductor body, wherein the semiconductor body comprises a first surface and a second surface arranged oppositely; the semiconductor body comprises a plurality of cells; obtaining thickness distribution information of the semiconductor body; the thickness distribution information comprises thickness values of a plurality of scanning residence areas of the semiconductor body; performing scanning thinning on the first surface according to the thickness distribution information; wherein during the scanning thinning, a thinning process is sequentially applied to the plurality of scanning residence areas, and a residence time of the thinning process is negatively correlated with the thickness values of the scanning residence areas; forming a gate insulating layer on the first surface after the scanning thinning; and forming a gate on the gate insulating layer. The application can improve the carrier mobility of the semiconductor device and reduce the on-resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) are widely used in power electronics, automotive, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] Silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) in related technologies have advantages such as high current density and small cell spacing. However, silicon carbide MOSFETs in related technologies have low carrier mobility and high on-resistance, meaning that the performance of silicon carbide MOSFETs needs to be improved. Summary of the Invention

[0004] This invention provides a method for fabricating a semiconductor device and a semiconductor device, thereby improving the carrier mobility and reducing the on-resistance of the semiconductor device.

[0005] According to one aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body includes a plurality of cells; Obtain the thickness distribution information of the semiconductor body; the thickness distribution information includes the thickness values ​​of multiple scanning dwell areas of the semiconductor body; The first surface is thinned by scanning according to the thickness distribution information; wherein, during the scanning thinning process, the thinning process is applied sequentially to multiple scanning dwell areas, and the dwell time of the thinning process is negatively correlated with the thickness value of the scanning dwell area; A gate insulating layer is formed on the first surface after the scanning thinning process; A gate is formed on the gate insulating layer.

[0006] Optionally, the thinning process includes: The first surface is etched using an ion beam.

[0007] Optionally, the ion beam includes an argon ion beam.

[0008] Optionally, the diameter of the outer circle of the scanning dwell area is smaller than the diameter of the outer circle of the semiconductor body.

[0009] Optionally, the plurality of scanning dwell areas are divided into multiple rows of scanning dwell areas; The step of performing scanning thinning of the first surface based on the thickness distribution information includes: The scanning dwell area of ​​the multiple rows is scanned row by row, and the scanning directions corresponding to the scanning dwell areas of two adjacent rows are opposite.

[0010] Optionally, the dwell time is an integer multiple of a preset time.

[0011] Optionally, when performing scanning thinning of the first surface based on the thickness distribution information, the method further includes: After thinning the scanning dwell area using the aforementioned thinning process, the actual thickness of the thinned scanning dwell area is detected. If the actual thickness of the scanning dwell area does not meet the target thinning requirement, the thinning process is performed in the scanning dwell area according to the actual thickness of the scanning dwell area.

[0012] Optionally, obtaining the thickness distribution information of the semiconductor body includes: The thickness of the semiconductor body is measured at multiple preset measurement points; The thickness value of the scanning dwell area is fitted based on the thickness of multiple preset measurement points in the same scanning dwell area.

[0013] Optionally, after forming the gate on the gate insulating layer, the method further includes: A source electrode is formed on the first surface, and a drain electrode is formed on the second surface.

[0014] According to another aspect of the present invention, a semiconductor device is provided, which is prepared by the semiconductor device preparation method described above.

[0015] The technical solution of this invention employs a semiconductor device fabrication method comprising: providing a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body including multiple cells; acquiring thickness distribution information of the semiconductor body; the thickness distribution information including thickness values ​​of multiple scanning dwell regions of the semiconductor body; performing scanning thinning on the first surface according to the thickness distribution information; wherein, during the scanning thinning process, the thinning process is sequentially applied to multiple scanning dwell regions, and the dwell time of the thinning process is negatively correlated with the thickness value of the scanning dwell region; forming a gate insulating layer on the first surface after scanning thinning; and forming a gate on the gate insulating layer. By thinning the first surface, the first surface becomes flatter, thereby improving the carrier mobility of the semiconductor device and reducing the on-resistance. Furthermore, the thinning method is scanning thinning, which can precisely target the scanning dwell regions for thinning, ultimately achieving global flatness; since it is not a simultaneous global thinning, but only applies to one region at a time, serious heat accumulation and other problems can be avoided, thereby ensuring the stability of the semiconductor body.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 2 A top view of a semiconductor body provided in an embodiment of the present invention; Figures 3-5 This is a schematic diagram of the product structure corresponding to the main steps of a semiconductor device fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 2 This is a top view of a semiconductor body provided in an embodiment of the present invention. Figures 3-5 This is a schematic diagram of the product structure corresponding to the main steps of a semiconductor device fabrication method provided in an embodiment of the present invention, with reference to... Figures 1 to 5 Methods for fabricating semiconductor devices include: Step S110: Provide a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body includes a plurality of cells; Specifically, the semiconductor device can be a SiC MOSFET device, meaning the material of the semiconductor body 100 can be SiC. In some embodiments, the semiconductor device can be an N-type MOSFET device; in other embodiments, the semiconductor device can also be a P-type MOSFET device. This embodiment uses an N-type MOSFET device as an example.

[0022] The semiconductor body 100 may include a substrate 10 and an epitaxial layer located on the substrate 10. However, in some embodiments, the semiconductor body 100 may not include the substrate 10. The substrate 10 may be an N-type substrate, and the epitaxial layer 20 may be an N-type epitaxial layer. Multiple cells CE are formed in the epitaxial layer. Each cell CE includes a source contact region Q1, a well region QP, and a source P+ region Q2. The source contact region Q1 is N-type doped with a doping concentration greater than that of the epitaxial layer itself; the well region QP is P-type doped; and the source P+ region Q2 is P-type doped with a doping concentration greater than that of the well region QP. The specific structure and working principle of the cell CE are well known to those skilled in the art and will not be described in detail here. It should be noted that regions with N-type conductivity can be formed by N-type doping, and the doping ions for N-type doping can be phosphorus (P) ions or nitrogen (N) ions; regions with P-type conductivity can be formed by P-type doping, and the doping ions for P-type doping can be aluminum (Al) ions or boron (B) ions. The portion of the epitaxial layer other than the cell CE can be understood as the drift region Q3.

[0023] The first surface S1 of the semiconductor body 100 is the surface of the epitaxial layer away from the substrate 10. Subsequently, a gate insulating layer and a gate are formed on the first surface S1.

[0024] After the semiconductor body 100 is formed, its first surface S1 will have many defects, such as defects caused by epitaxial growth, etching, and ion implantation. Figure 3 As shown, the defects on the first surface S1 can be represented by bumps 21. Bumps 21 consume a portion of the charge carriers in the channel, resulting in a lower charge carrier mobility.

[0025] Step S120: Obtain thickness distribution information of the semiconductor body; the thickness distribution information includes the thickness values ​​of multiple scanning dwell areas of the semiconductor body; Specifically, such as Figure 2 As shown, the thickness of each region of the semiconductor body 100 can be measured first to obtain thickness distribution information. This thickness distribution information can be used to characterize the thickness variation of the semiconductor body 100, thus providing a reference for subsequent scanning thinning processes.

[0026] In this embodiment, the scanning dwell area QZ refers to the surface area that the thinning process can cover at any given moment during the subsequent scanning thinning process, and that continuously thins the first surface S1 during that moment. In other words, the scanning dwell area QZ is the basic unit of the thinning process. Each scanning dwell area QZ corresponds to a thickness value, and the thickness values ​​corresponding to different scanning dwell areas QZ can be the same or different.

[0027] Step S130: Perform scanning thinning on the first surface according to the thickness distribution information; wherein, during the scanning thinning process, the thinning process is applied sequentially to multiple scanning dwell areas, and the dwell time of the thinning process is positively correlated with the thickness value of the scanning dwell area; Specifically, after obtaining the thickness values ​​of each scanning dwell region QZ, a corresponding dwell time can be assigned to each scanning dwell region QZ. The dwell time of the thinning process is also the thinning time. It can be understood that the longer the dwell time, the greater the amount of thinning; the shorter the dwell time, the smaller the amount of thinning. For scanning dwell regions with larger thickness, the corresponding dwell time is larger, and the corresponding amount of thinning is also larger; for scanning dwell regions with smaller thickness, the corresponding dwell time is smaller, and the corresponding amount of thinning is also smaller. By configuring corresponding dwell times for different scanning dwell regions, the thickness of each scanning dwell region eventually tends to be consistent. In addition, the thinning method of the first surface S1 in this embodiment is scanning thinning, not global simultaneous thinning, which can accurately target the thinning of the scanning dwell region and ultimately achieve global planarization; furthermore, since it is not global simultaneous thinning, it only acts on one region at a time, which can avoid serious heat accumulation and other problems, thereby ensuring the stability of the semiconductor body.

[0028] Step S140: A gate insulating layer is formed on the first surface after scanning thinning; Specifically, such as Figure 4 As shown, after scanning thinning, the bumps 21 on the first surface S1 are removed. At this point, the first surface S1 is a relatively flat surface, and the number of defects is greatly reduced, resulting in higher carrier mobility and lower on-resistance. Figure 5 As shown, the gate insulating layer 31 can be formed by any of the following methods: chemical vapor deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, and thermal oxidation. The material of the gate insulating layer 31 includes silicon oxide, silicon nitride, silicon oxynitride, or other materials with high dielectric constants. Furthermore, because the first surface S1 is relatively flat, the formed gate insulating layer 31 is also relatively flat, resulting in high consistency in the thickness of the gate insulating layer 31 corresponding to different cells CE, thereby ensuring the consistency of the threshold voltage at different locations in the semiconductor device.

[0029] Step S150: A gate is formed on the gate insulating layer.

[0030] Specifically, the gate 32 can be made of polysilicon or similar materials, providing good conductivity and good interface compatibility with the gate insulating layer 31. Alternatively, the gate 32 can be made of metal or similar materials. The gate insulating layer 31 isolates the gate 32 from the semiconductor body 100. When the voltage applied to the gate 32 is less than the threshold voltage of the semiconductor device, the majority carriers on the surface of the well region QP cannot be inverted; that is, the majority carriers in the well region QP are still holes, while the majority carriers in the source contact region Q1 and the drift region Q3 are still electrons, and the channel of the semiconductor device is turned off. However, when the voltage applied to the gate 32 is greater than or equal to the threshold voltage, electrons in the well region QP are attracted by the high electric field, making the majority carriers in the region near the channel in the well region QP electrons. At this time, the channel is turned on, and the semiconductor device is turned on. Because the first surface S1 is flatter, the electric field distribution in the channel is more uniform, thus avoiding problems such as localized overheating caused by excessive electric field concentration.

[0031] The technical solution of this embodiment employs a semiconductor device fabrication method that includes providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body comprising multiple cells; acquiring thickness distribution information of the semiconductor body; the thickness distribution information including thickness values ​​of multiple scanning dwell regions of the semiconductor body; performing scanning thinning on the first surface according to the thickness distribution information; wherein, during the scanning thinning process, the thinning process is sequentially applied to multiple scanning dwell regions, and the dwell time of the thinning process is negatively correlated with the thickness value of the scanning dwell region; forming a gate insulating layer on the first surface after scanning thinning; and forming a gate on the gate insulating layer. By thinning the first surface, the first surface becomes flatter, thereby improving the carrier mobility of the semiconductor device and reducing the on-resistance. Furthermore, the thinning method is scanning thinning, which can precisely target the scanning dwell regions for thinning, ultimately achieving global flatness; since it is not a simultaneous global thinning, but only applies to one region at a time, serious heat accumulation and other problems can be avoided, thereby ensuring the stability of the semiconductor body.

[0032] Optionally, in some embodiments, the target thickness of each scanning dwell area after thinning is the same. This target thickness can be the thickness of the scanning dwell area with the largest number of identical thickness values. That is, the thickness values ​​of multiple scanning dwell areas are statistically analyzed, and the thickness value with the largest number is the target thickness of each scanning dwell area. After obtaining the target thickness, the thickness to be thinned can be determined based on the thickness corresponding to the scanning dwell area and the target thickness, and the dwell time can be determined based on the thickness to be thinned.

[0033] Alternatively, in some implementations, such as Figure 2As shown, multiple semiconductor devices can be fabricated simultaneously on a single wafer. In this case, the thickness distribution information of the semiconductor body on the wafer can be obtained.

[0034] Optionally, such as Figure 5 As shown, after forming the gate on the gate insulating layer, the method further includes: forming a source on a first surface; and forming a drain on a second surface.

[0035] Specifically, after forming the gate 32, an interlayer dielectric layer 33 can be formed on the gate 32. The material of the interlayer dielectric layer 33 can be silicon oxide or silicon nitride, etc. It can be formed by processes such as chemical vapor deposition. The interlayer dielectric layer 33 is used to isolate the gate 32 and the source 34 to prevent short circuits. Both the source 34 and the drain 35 can be metals. When the channel of the semiconductor device is turned on, a voltage is applied between the source 34 and the drain 35 to generate current.

[0036] Optionally, the thinning process includes etching the first surface using an ion beam.

[0037] Specifically, the thinning process in this embodiment is, for example, IBS (Ion Beam Shaping). This involves bombarding the first surface S1 with an ion beam. During thinning, an ion source generates a high-energy ion beam in a vacuum chamber. More specifically, a working gas (preferably argon) is introduced into the ion source, and under the influence of an electric field and / or magnetic field, gas discharge occurs, ionizing to form argon ions. These argon ions are accelerated in a high-voltage electric field applied by the accelerating electrode system of the ion source, forming a high-energy ion beam with directional kinetic energy, which is directed towards the first surface S1 of the semiconductor body 100 along a predetermined direction. When the high-energy argon ion beam bombards the first surface S1, the incident ions transfer some of their kinetic energy to surface atoms through collisions. When the recoil energy acquired by a surface atom exceeds its lattice binding energy, the atom detaches from the material surface and is "sputtered" into the vacuum environment as a neutral or charged particle, and is then extracted from the chamber by a vacuum pump system. This process is essentially a purely physical thinning process and does not involve any chemical reactions. As a large number of surface atoms are removed layer by layer by sputtering, the thickness of the semiconductor body can be precisely and controllably reduced locally.

[0038] In this embodiment, the irradiation area of ​​the ion beam on the first surface is also known as the scanning dwell area QZ. The size of the scanning dwell area QZ is much smaller than the total area of ​​the first surface. Through the relative scanning motion between the ion beam and the semiconductor body, the ion beam sequentially passes through each scanning dwell area QZ of the first surface S1 along a preset scanning path. At any given scanning moment, the ion beam irradiates only a local area of ​​the first surface S1, that is, only one scanning dwell area QZ. The dwell time of the ion beam in each scanning dwell area is independently set according to the thickness value corresponding to that scanning dwell area in the aforementioned thickness distribution information. Areas with larger thicknesses correspond to longer dwell times, resulting in a larger ion dose per unit area and a correspondingly larger thickness of material removed by sputtering; areas with smaller thicknesses correspond to shorter dwell times, resulting in a smaller ion dose and a correspondingly smaller thickness of material removed.

[0039] Furthermore, since IBS is a physical sputtering process, its thinning rate is independent of surface morphology or pattern density, and there is no loading effect caused by differences in pattern density. At the same time, the energy and beam current density of the ion beam can be adjusted independently, and the ion beam energy divergence can usually be controlled within 5 eV, exhibiting extremely high energy monochromaticity and directional collimation, which is beneficial for achieving nanoscale precision thinning control.

[0040] It should be noted that while chemical mechanical polishing (CMP) can be used to thin semiconductor structures, the ion beam thinning process used in this embodiment is a purely physical sputtering process. The substrate surface has no physical contact with the ion source, completely avoiding scratches, subsurface damage, and residual particulate contaminants caused by mechanical friction. Furthermore, in the ion beam thinning process, the ion beam current density and ion energy are precisely controlled by the ion source power supply. The thinning amount equals the sputtering yield multiplied by the ion flux. Atomic-level removal control can be achieved through precise programming of the residence time, enabling sub-nanometer-level thinning precision. The material removal rate of CMP is affected by various parameters such as abrasive particle size, polishing pad condition, slurry flow rate, temperature, and pressure. Real-time precise control of the removal rate is difficult, and endpoint detection often relies on indirect signals such as motor current or optical reflectivity, with control precision typically on the order of several nanometers to tens of nanometers. In addition, CMP exhibits strong material selectivity. For hard or chemically inert materials such as silicon carbide, gallium nitride, and diamond, CMP results in extremely low thinning rates, long processing times, and high abrasive particle consumption. Ion beam thinning achieves thinning through high-energy ion bombardment. The sputtering yield increases with the increase of ion energy. It is equally effective for hard materials and chemically inert materials, and has a wider range of applicable materials.

[0041] It should be noted that the above embodiments use an argon ion beam as an example. In some embodiments, the ion beam can also be an ion beam made of other materials.

[0042] Optionally, the diameter of the outer circle of the scanning dwell region QZ is smaller than the diameter of the outer circle of the semiconductor body 100.

[0043] Specifically, in this embodiment, the outer contour of the ion beam can be circular. The semiconductor body 100 corresponds to the semiconductor body of the wafer, and its contour is also circular. Therefore, it can be understood that the diameter of the scanning dwell area QZ is smaller than the diameter of the wafer, for example, it can be smaller than 1 / 10 of the wafer diameter. The maximum size of the ion beam contour is also smaller than the diameter of the wafer, which allows the area of ​​the scanning dwell area to be smaller, thereby achieving higher thinning accuracy in both the row and column directions of the wafer. At the same time, the overall size of the ion beam is small, and the energy difference between the edge and center of the ion beam is also small, which can avoid the problem of uneven thinning caused by the unevenness of the ion beam corresponding to the scanning dwell area at the edge of the wafer.

[0044] Optionally, the multiple scanning dwell areas QZ are divided into multiple rows of scanning dwell areas. Scanning thinning of the first surface based on thickness distribution information includes: The scanning dwell area of ​​multiple lines is scanned line by line, and the scanning directions of adjacent scanning dwell areas are opposite.

[0045] Specifically, such as Figure 2 As shown, multiple scanning residence regions QZ are arranged in an array along both the row and column directions. Scanning can begin from the first row of scanning residence regions QZ and proceed row by row. After the current row is scanned, the next row is scanned in the opposite direction, resulting in an "S"-shaped scanning path. This configuration ensures scanning continuity and avoids issues such as ion beam tailing caused by large distances between two scanning residence regions at adjacent scan times, thus guaranteeing the accuracy of the thinning process.

[0046] Optionally, in some implementations, the dwell time is an integer multiple of a preset time.

[0047] Specifically, the preset time is, for example, the basic unit of ion beam residence time in the thinning process. In this embodiment, the residence time is a discrete value. The thinning amount corresponding to the preset time is a preset value; for example, the thinning amount corresponding to the preset time is 30 nm. That is, if the residence time is twice the preset time, the corresponding thinning amount is 30 nm; if the residence time is twice the preset time, the corresponding thinning amount is 60 nm, and so on. Compared to a continuous residence time, the control logic corresponding to a discrete value is simpler, which helps to reduce the control difficulty.

[0048] Optionally, when performing scanning thinning of the first surface based on thickness distribution information, the method further includes: After thinning the scanning dwell area using a thinning process, the actual thickness of the thinned scanning dwell area is detected; if the actual thickness of the scanning dwell area does not meet the target thinning requirements, a thinning process is performed in the scanning dwell area according to the actual thickness of the scanning dwell area.

[0049] Specifically, in this embodiment, after the ion beam has resided in each scanning residence region QZ for the corresponding residence time, it does not immediately scan to the next scanning residence region QZ. Instead, it performs an actual thickness detection to determine whether the actual thickness meets the requirements. If the actual thickness meets the requirements, it scans to the next scanning residence region QZ. If the actual thickness does not meet the requirements, the ion beam thinning step based on the thickness of the scanning residence region is performed again until the actual thickness of the scanning residence region meets the requirements. In this embodiment, the actual thickness of the scanning residence region can be fed back in a timely manner, allowing for timely correction and ensuring that the actual thickness of all scanning residence regions meets the corresponding requirements after one scan, avoiding the time waste caused by repeated scans.

[0050] Optionally, obtaining the thickness distribution information of the semiconductor body includes: Measure the thickness of multiple preset measurement points on the semiconductor body; Specifically, such as Figure 2 As shown, the thickness of preset measurement points CL can be measured using the Optical Critical Dimension (OCD) method. Specifically, a broadband polarized light beam can be incident on each preset measurement point CL. By receiving the diffraction spectra of each preset measurement point CL and fitting them to a pre-established physical model, the thickness value corresponding to each preset measurement point CL can be obtained. Obtaining thickness distribution information through the OCD measurement method has the advantage of being non-destructive, allowing for thickness characterization without affecting subsequent processes before the thinning process.

[0051] The thickness value of the scanning area is fitted based on the thickness of multiple preset measurement points in the same scanning area.

[0052] Specifically, the scanning dwell area QZ has a certain area, while the size of the preset measurement points CL is relatively small. A scanning dwell area QZ contains multiple preset measurement points CL. The thickness of different preset measurement points CL within the same scanning dwell area QZ may differ. A fitting formula can be used to fit the thickness of the preset measurement points CL to obtain an overall thickness value. This overall thickness value is then used as the thickness value of the scanning dwell area, thereby improving the accuracy of the thickness measurement. The fitting relationship could be, for example, a weighted average.

[0053] It should be noted that in some implementations, the thickness of multiple preset measurement points can be determined first, and then the number and distribution of preset measurement points corresponding to each scanning dwell area can be calculated based on the distribution of the preset measurement points and the distribution of the scanning dwell area. For example, if multiple preset measurement points are arranged in an array, the number of preset measurement points CL corresponding to different scanning dwell areas QZ may be different. Of course, after determining the distribution of the scanning dwell area QZ, preset measurement points can be independently divided within each scanning dwell area QZ, in which case the number and relative positional relationship of preset measurement points in each scanning dwell area QZ can be the same.

[0054] Based on the same inventive concept, the present invention also provides a semiconductor device, which is prepared by the semiconductor device preparation method provided in any embodiment of the present invention and has the same beneficial effects, which will not be repeated here.

[0055] Based on the same inventive concept, the present invention also provides a power module. The power module includes a substrate and at least one semiconductor device as described in any embodiment of the present invention, with the substrate serving to support the semiconductor device. Therefore, the beneficial effects of this power module including any semiconductor device as described in any embodiment of the present invention will not be elaborated further here.

[0056] Based on the same inventive concept, this invention also provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this invention, with the semiconductor device electrically connected to the circuit board. Therefore, the beneficial effects of this power conversion circuit including any semiconductor device as described in any embodiment of this invention will not be elaborated further here.

[0057] Based on the same inventive concept, the present invention also provides a vehicle, which includes a load and the aforementioned power conversion circuit. The power conversion circuit is used to convert alternating current to direct current, alternating current to alternating current, direct current to direct current, or direct current to alternating current, and then input the converted direct current to the load. Therefore, the beneficial effects of the vehicle including the semiconductor device described in any embodiment of the present invention will not be elaborated further here.

[0058] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0059] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body includes a plurality of cells; Obtain the thickness distribution information of the semiconductor body; the thickness distribution information includes the thickness values ​​of multiple scanning dwell areas of the semiconductor body; The first surface is thinned by scanning according to the thickness distribution information; wherein, during the scanning thinning process, the thinning process is applied sequentially to multiple scanning dwell areas, and the dwell time of the thinning process is negatively correlated with the thickness value of the scanning dwell area; A gate insulating layer is formed on the first surface after the scanning thinning process; A gate is formed on the gate insulating layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thinning process includes: The first surface is etched using an ion beam.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The ion beam includes an argon ion beam.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The diameter of the outer circle of the scanning dwell area is smaller than the diameter of the outer circle of the semiconductor body.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The multiple scanning dwell areas are divided into multiple rows of scanning dwell areas; The step of performing scanning thinning of the first surface based on the thickness distribution information includes: The scanning dwell area of ​​the multiple rows is scanned row by row, and the scanning directions corresponding to the scanning dwell areas of two adjacent rows are opposite.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The dwell time is an integer multiple of the preset time.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process of performing scanning thinning on the first surface based on the thickness distribution information also includes: After thinning the scanning dwell area using the aforementioned thinning process, the actual thickness of the thinned scanning dwell area is detected. If the actual thickness of the scanning dwell area does not meet the target thinning requirement, the thinning process is performed in the scanning dwell area according to the actual thickness of the scanning dwell area.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process of obtaining the thickness distribution information of the semiconductor body includes: The thickness of the semiconductor body is measured at multiple preset measurement points; The thickness value of the scanning dwell area is fitted based on the thickness of multiple preset measurement points in the same scanning dwell area.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming the gate on the gate insulating layer, the method further includes: A source electrode is formed on the first surface, and a drain electrode is formed on the second surface.

10. A semiconductor device, characterized in that, The semiconductor device is prepared by the method for preparing a semiconductor device according to any one of claims 1-9.

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