Semiconductor power device and method of manufacturing the same

Abstract

The application provides a semiconductor power device and a preparation method thereof. The semiconductor power device comprises a semiconductor substrate layer, a drift layer, a well region and a doped region. The drift layer is located on one side of the semiconductor substrate layer along a first direction. The well region is located in the drift layer. A first source region is located in part of the well region. The well region comprises a channel region located on a side of the first source region along a direction perpendicular to the first direction. The doped region is located in the well region between the channel region and at least part of the first source region along a direction perpendicular to the first direction. The doping type of the doped region and the doping type of the first source region are the same as the doping type of the drift layer, and the doping concentration of the doped region is less than the doping concentration of the first source region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor power device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) materials have advantages such as large bandgap, high critical breakdown electric field, high thermal conductivity, and high carrier saturation drift velocity. Metal-oxide-semiconductor field-effect transistors (MOSFETs) based on SiC materials have broad application prospects in high-power, high-frequency application scenarios such as new energy vehicles, photovoltaic inverters, energy storage conversion, power supply systems, and rail transportation. Summary of the Invention

[0003] The present invention provides a semiconductor power device, comprising: a semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer along a first direction; a well region located in the drift layer and including a channel region; a first source region located in a portion of the well region; and a doped region located in the well region between the channel region and at least a portion of the first source region along a direction perpendicular to the first direction; the doping type of the doped region and the doping type of the first source region are the same as the doping type of the drift layer, and the doping concentration of the doped region is less than the doping concentration of the first source region.

[0004] Optionally, a plurality of first source regions are arranged at intervals along a second direction; a doped region is located between the channel region and at least a portion of the first source regions along a third direction; wherein the first direction, the second direction, and the third direction are perpendicular to each other.

[0005] Optionally, the well region extends along a second direction, and the size of the well region along the second direction is larger than the size of the well region along a third direction; wherein, the doped region extends along the second direction, and the size of the doped region along the second direction is larger than the size of the doped region along a third direction.

[0006] Optionally, the semiconductor power device further includes a second source region located in a well region adjacent to the first source region along a second direction. The doping type of the second source region is opposite to that of the first source region, and the doping concentration of the second source region is greater than that of the well region. The doped region is also located between the channel region and at least a portion of the second source region along a third direction.

[0007] Optionally, the plurality of first source regions include a first source region of a first type and a first source region of a second type, wherein the length of the second type of first source region along a third direction is greater than the length of the first type of first source region along a third direction; wherein the doped region along a third direction is located between the first type of first source region and the channel region, and on the side of the second type of first source region along a second direction; and / or, the plurality of second source regions include a second source region of a first type and a second source region of a second type, wherein the length of the second type of second source region along a third direction is greater than the length of the first type of second source region along a third direction; wherein the doped region is also located along a third direction between the first type of second source region and the channel region, and on the side of the second type of second source region along a second direction.

[0008] Optionally, the plurality of first source regions include first source regions of a first type and first source regions of a second type, and the plurality of second source regions include second source regions of a first type and second source regions of a second type; wherein, the first source regions of a second type and the second source regions of a second type are spaced apart, or, the second source regions of a second type are in contact with the first source regions of a second type; or, a portion of the first source regions of a second type are in contact with a portion of the second source regions of a second type, and another portion of the first source regions of a second type are in contact with a spaced-apart contact.

[0009] Optionally, the doped region surrounds the first source region in a direction perpendicular to the first direction; wherein, the channel region is located on the side of the doped region opposite to the first source region in a direction perpendicular to the first direction.

[0010] Optionally, the projection pattern of the well region onto the semiconductor substrate along the first direction includes a polygon.

[0011] Optionally, the semiconductor power device further includes a second source region located in a well region on the side of the first source region perpendicular to the first direction. The doping type of the second source region is opposite to that of the first source region, and the doping concentration of the second source region is greater than that of the well region. In the well region, the entire first and second source regions are surrounded by a doped region in a direction perpendicular to the first direction.

[0012] Optionally, for the entire first source region and the second source region surrounded by the doped region, the entire first source region and the second source region have a first projection pattern on the semiconductor substrate along a first direction, and the well region has a second projection pattern on the semiconductor substrate along the first direction; wherein, the first projection pattern and the second projection pattern are similar patterns.

[0013] Optionally, the semiconductor power device further includes a third source region located in the well region of the first source region along the first direction toward the semiconductor substrate and in contact with the first source region. The doping type of the third source region is the same as that of the second source region, and the doping concentration of the third source region is greater than that of the well region.

[0014] Optionally, the third source region includes: a first portion and a second portion, wherein the dimension of the second portion along the first direction is greater than the dimension of the first portion along the first direction; wherein the portion of the first source region located on one side of the first portion along the first direction has a first dimension along the first direction, and the portion of the first source region located on one side of the second portion along the first direction has a second dimension along the first direction; wherein the first dimension is greater than the second dimension.

[0015] This application also provides a method for fabricating a semiconductor power device, comprising: forming a drift layer on one side of a semiconductor substrate along a first direction; forming a well region in the drift layer; forming a doped region and a first source region in a portion of the well region, wherein the doping type of the doped region and the doping type of the first source region are the same as the doping type of the drift layer, and the doping concentration of the doped region is less than the doping concentration of the first source region; wherein the well region includes a channel region; and the doped region is located between the channel region and at least a portion of the first source region along a direction perpendicular to the first direction.

[0016] Optionally, a doped region and a first source region are formed in a portion of the well region, including: forming an initial doped region in a portion of the well region; and forming a first source region in a portion of the initial doped region, wherein the portion of the initial doped region located between the first source region and the channel region forms a doped region.

[0017] Optionally, it further includes: forming a first mask layer on the side of the drift layer away from the semiconductor substrate layer, the first mask layer having a first mask aperture; forming a sidewall on the sidewall of the first mask aperture; wherein forming a well region in the drift layer includes: forming a well region in the drift layer through the first mask aperture using the first mask layer as a mask before forming the sidewall; wherein forming an initial doped region in a portion of the well region includes: forming an initial doped region in a portion of the well region through the first mask aperture using the first mask layer and the sidewall as masks; wherein the channel region is located on the side of the sidewall along a first direction.

[0018] Optionally, forming a first source region in a portion of the well region includes: forming a plurality of first source regions spaced apart along a second direction in a portion of the well region; wherein the doped region is located between the channel region and at least a portion of the first source regions along a third direction; the first direction, the second direction, and the third direction are perpendicular to each other.

[0019] Optionally, the method for fabricating a semiconductor power device further includes: forming a second source region located in a well region adjacent to the first source region along a second direction, wherein the doping type of the second source region is opposite to that of the first source region, and the doping concentration of the second source region is greater than that of the well region; wherein the doped region is also located between the channel region and at least a portion of the second source region along a third direction.

[0020] Optionally, the doped region surrounds the first source region in a direction perpendicular to the first direction; wherein, the channel region is located on the side of the doped region opposite to the first source region in a direction perpendicular to the first direction.

[0021] Optionally, the method for fabricating a semiconductor power device further includes: forming a second source region located in a well region on the side of the first source region perpendicular to the first direction; the doping type of the second source region is opposite to that of the first source region; and the doping concentration of the second source region is greater than that of the well region; wherein, in the well region, the entire first and second source regions are surrounded by a doped region in a direction perpendicular to the first direction.

[0022] Optionally, the method for fabricating a semiconductor power device further includes: forming a third source region, wherein the third source region is located in a well region of the first source region along a first direction toward the semiconductor substrate and is in contact with the first source region, the doping type of the third source region is the same as that of the second source region, and the doping concentration of the third source region is greater than that of the well region.

[0023] The semiconductor power device and its fabrication method provided in this application, by setting a doped region between the channel region and at least a portion of the first source region, and the doping type of the doped region is the same as that of the first source region and the drift layer, and the doping concentration of the doped region is less than that of the first source region, the position and morphology of the first source region are no longer strictly limited by the channel region formation process, which is beneficial to reduce the cell width and reduce the specific resistance; at the same time, it can reduce the damage to the lattice caused during the formation of the first source region and improve the performance and process stability of the semiconductor power device. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figures 1 to 12 This is a schematic diagram of the fabrication process of a semiconductor power device; Figures 13 to 24 This is a schematic diagram of the fabrication process of a semiconductor power device in one embodiment of this application; Figures 25 to 29 This is a schematic diagram of the fabrication process of a semiconductor power device in another embodiment of this application; Figures 30 to 33 This is a schematic diagram of the fabrication process of a semiconductor power device in another embodiment of this application; Figures 34 to 36 This is a schematic diagram of the fabrication process of a semiconductor power device in another embodiment of this application. Detailed Implementation

[0026] Figures 1 to 12This is a schematic diagram of the fabrication process of a semiconductor power device.

[0027] refer to Figures 1 to 3 , Figure 2 For along Figure 1 Cross-sectional view of the tangent line M1-N1. Figure 3 For along Figure 1 A cross-sectional view along the cutting line M2-N2 shows that a first mask layer 120 is formed on one side of the drift layer 100 along the first direction Z; a trap region 110 is formed in the drift layer 100 using the first mask layer 120 as a mask.

[0028] The first mask layer 120 includes a first mask portion and a second mask portion. The first mask portion extends along a second direction Y, and a plurality of second mask portions are arranged along the second direction Y and located between adjacent first mask portions along a third direction X. The second mask portions are used to define the location of the second source region, and the location of the second source region is reserved in the subsequent formation of the first source region 130.

[0029] refer to Figures 4 to 6 , Figure 5 For along Figure 4 Cross-sectional view of the tangent line M1-N1. Figure 6 For along Figure 4 A cross-sectional view along the cut line M2-N2 shows a sidewall 140 formed on the sidewall of the first mask layer 120; a first source region 130 is formed in the trap region 110 using the first mask layer 120 and the sidewall 140 as masks.

[0030] The first sidewall portion of the sidewall 140 contacts the first mask portion and extends along the second direction Y. The second sidewall portion of the sidewall 140 surrounds the second mask portion and contacts the second mask portion. The second sidewall portion is spaced from the first sidewall portion. The sidewall 140 is used to define the location of the trench area.

[0031] The doping type of the first source region 130 is the same as that of the drift layer 100. The doping concentration of the first source region 130 is greater than that of the drift layer 100.

[0032] refer to Figures 7 to 9 , Figure 8 For along Figure 7 Cross-sectional view of the tangent line M1-N1. Figure 9 For along Figure 7 A cross-sectional view of the cutting line M2-N2 shows that after removing the second mask portion, a second source region 150 is formed in the drift layer 100. The doping type of the second source region 150 is opposite to that of the first source region 130.

[0033] The first source region 130 surrounds the second source region 150 in a direction perpendicular to the first direction Z.

[0034] refer to Figures 10 to 12 , Figure 11 For along Figure 10 Cross-sectional view of the tangent line M1-N1. Figure 12 For along Figure 10 A cross-sectional view of the cutting line M2-N2, with sidewall 140 and the first mask removed.

[0035] Research has found that the semiconductor power devices formed by the above method have poor performance, and the reason is as follows: 1. At the location of the cutting line M2-N2, there are four sidewalls 140 along the third direction X. The first mask layer 120 also has a certain spacing along the third direction X. Due to the limitations of the photolithography process, as well as the limitations of the spacing of the first mask layer 120 and the size of the sidewalls 140 along the third direction X, the further reduction of the cell width is restricted, and the resistivity is difficult to further reduce.

[0036] 2. At the location of dicing line M2-N2, the number of sidewalls 140 along the third direction X is relatively large, while at the location of dicing line M1-N1, the number of sidewalls 140 along the third direction X is relatively small. Consequently, under the same deposition process, the dimensions of the sidewalls 140 formed at the locations of dicing lines M2-N2 and M1-N1 differ along the third direction X. Since the sidewalls 140 define the location of the channel region, this results in different dimensions of the channel region along the third direction X at the locations of dicing lines M2-N2 and M1-N1. The dimensional uniformity of the channel region along the third direction X is poor. This not only affects the electrical consistency of different regions within a single semiconductor power device chip but also the performance consistency between chip regions at different locations on the same wafer, thus adversely affecting the parallel application and overall reliability of semiconductor power devices.

[0037] Based on this, embodiments of this application provide a semiconductor power device and a method for fabricating the same.

[0038] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0041] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0042] Figures 13 to 24 This is a schematic diagram illustrating the fabrication process of a semiconductor power device in one embodiment of this application.

[0043] refer to Figure 13 and Figure 14 , Figure 14 For along Figure 13 A cross-sectional view along the dicing line M11-N11 shows a drift layer 200 formed on one side of the semiconductor substrate layer (not shown) along the first direction Z; a well region 210 is formed in the drift layer 200.

[0044] In some embodiments, the method for fabricating a semiconductor power device further includes forming a first mask layer 230 on the side of the drift layer 200 facing away from the semiconductor substrate layer, the first mask layer 230 having a first mask opening. The material of the first mask layer 230 may be an insulating dielectric material.

[0045] For example, the first mask opening extends along the second direction Y, and the size of the first mask opening along the second direction Y is larger than the size of the first mask opening along the third direction X. The first mask opening is a strip structure along the second direction Y.

[0046] The formation of a well region 210 in the drift layer 200 includes: forming the well region 210 in the drift layer 200 through the first mask aperture, using the first mask layer 230 as a mask. The process for forming the well region 210 includes an ion implantation process. The doping type of the well region 210 is opposite to that of the drift layer 200. For example, the well region 210 is p-type doped, while the drift layer 200 is n-type doped.

[0047] In some embodiments, reference Figure 13 The well region 210 extends along the second direction Y, and the size of the well region 210 along the second direction Y is larger than the size of the well region 210 along the third direction X. The well region 210 has a strip-shaped structure extending along the second direction Y.

[0048] The first direction Z, the second direction Y, and the third direction X are all perpendicular to each other. The first direction Z is perpendicular to the second direction Y, the first direction Z is perpendicular to the third direction X, and the second direction Y is perpendicular to the third direction X.

[0049] refer to Figures 15 to 19 A doped region 220 and a first source region 270 are formed in a portion of the well region 210. The doping type of the doped region 220 and the doping type of the first source region 270 are the same as the doping type of the drift layer 200, and the doping concentration of the doped region 220 is less than the doping concentration of the first source region 270.

[0050] refer to Figure 15 and Figure 16 , Figure 16 For along Figure 15 A cross-sectional view of the cutting line M11-N11 shows that an initial doped region 2200 is formed in a portion of the well region 210.

[0051] In some embodiments, the method for fabricating a semiconductor power device further includes forming a sidewall 240 on the sidewall of a first mask aperture. Exemplarily, the sidewall 240 is formed on the sidewalls of the first mask aperture on both sides in a third direction (X). The sidewall 240 is formed after the well region 210 is formed.

[0052] In some embodiments, the dimensional variation of the first mask aperture along the second direction Y is small at each location. For example, the dimensional variation of the first mask aperture along the third direction X is the same at each location along the second direction Y. Because the dimensional variation of the first mask aperture along the third direction X is small at each location along the second direction Y, the dimensional variation of the sidewall 240 along the third direction X is also small at each location along the second direction Y. For example, the dimensional variation of the sidewall 240 along the third direction X is the same at each location along the second direction Y. The sidewall 240 is used to define the location of the channel region; correspondingly, the dimensional variation of the channel region along the third direction X at each location along the second direction Y is less than or equal to 8% of the width of the sidewall 240 along the third direction X. For example, the dimensional variation of the channel region along the third direction X is the same at each location along the second direction Y. The width of the sidewall 240 is perpendicular to the first direction Z.

[0053] The sidewall 240 can be made of an insulating dielectric material. The material of the sidewall 240 is different from the material of the first mask layer 230.

[0054] The formation of an initial doped region 2200 in a portion of the well region 210 includes: using a first mask layer 230 and a sidewall 240 as a mask, and forming the initial doped region 2200 in the portion of the well region 210 through a first mask aperture. The process for forming the initial doped region 2200 includes an ion implantation process.

[0055] The trap region 210 includes a channel region. The channel region is located on one side of the sidewall 240 along the first direction Z.

[0056] refer to Figure 15 and Figure 16 The channel region is located on both sides of the initial doped region 220 along the third direction X.

[0057] refer to Figure 17 and Figure 19 , Figure 18 For along Figure 17 Cross-sectional view of the tangent line M12-N12. Figure 19 For along Figure 17 A cross-sectional view of the cutting line M11-N11 shows that a first source region 270 is formed in a portion of the initial doped region 2200, wherein the portion of the initial doped region 2200 located between the first source region 270 and the channel region forms the doped region 220.

[0058] In some embodiments, the process of forming the first source region 270 includes an ion implantation process.

[0059] A first ion is implanted into a portion of the initial doped region 2200. The doping type of the first ion is the same as that of the initial doped region 2200. The region of the initial doped region 2200 implanted with the first ion forms the first source region 270.

[0060] In some embodiments, reference Figure 17 Forming a first source region 270 in a portion of the well region 210 includes forming a plurality of first source regions 270 spaced apart along a second direction Y in a portion of the well region 210.

[0061] The doped region 220 is located between the channel region and the first source region 270 along a direction perpendicular to the first direction Z. For example, the doped region 220 is located between the channel region and the first source region 270 along a third direction X.

[0062] refer to Figure 17 The doped region 220 extends along the second direction Y, and the size of the doped region 220 along the second direction Y is larger than the size of the doped region 220 along the third direction X.

[0063] In some embodiments, reference Figure 17 and Figure 18 The method for fabricating a semiconductor power device further includes: forming a second source region 250, which is located in a well region 210 adjacent to a first source region 270 along a second direction Y. The doping type of the second source region 250 is opposite to that of the first source region 270, and the doping concentration of the second source region 250 is greater than that of the well region 210. The process for forming the second source region 250 includes an ion implantation process.

[0064] Among them, the doped region 220 is located between the channel region and the second source region 250 along the third direction X.

[0065] A second ion is implanted into a portion of the initial doped region 2200. The doping type of the second ion is opposite to that of the initial doped region 2200, and the region of the initial doped region 2200 implanted with the second ion forms the second source region 250. Since the doping concentration of the initial doped region 2200 is much smaller than that of the second source region 250, overcompensation and lattice damage can be avoided when implanting a second ion into a portion of the initial doped region 2200.

[0066] The regions where the first ion is implanted in the initial doped region 2200 are different from the regions where the second ion is implanted in the initial doped region 2200. This makes the implantation of the first ion and the implantation of the second ion independent of each other, and the implantation of the first ion and the implantation of the second ion are less likely to compensate for each other. This helps to reduce the damage to the crystal lattice caused by multiple implantations and improve device performance and process stability.

[0067] refer to Figures 17 to 19In the well region 210, the doped region 220 is located on both sides of the second source region 250 and the first source region 270 along the third direction X.

[0068] In some embodiments, reference Figure 19 The method for fabricating a semiconductor power device further includes: forming a third source region 260, wherein the third source region 260 is located in a well region 210 of the first source region 270 along the first direction Z toward the semiconductor substrate and is in contact with the first source region 270; the doping type of the third source region 260 is the same as that of the second source region 250; and the doping concentration of the third source region 260 is greater than that of the well region 210. The process for forming the third source region 260 includes an ion implantation process.

[0069] In some embodiments, the first source region 270 is formed after the second source region 250 is formed, or the second source region 250 is formed after the first source region 270 is formed.

[0070] In some embodiments, a third source region 260 is formed after the second source region 250 is formed, or a second source region 250 is formed after the third source region 260 is formed.

[0071] refer to Figures 17 to 19 The third source region 260 is located at the bottom of the first source region 270 along the first direction Z, and the second source region 250 is located between the first source region 270 along the second direction Y. In this way, the third source region 260 and the second source region 250 wrap around the two sidewalls of the first source region 270 along the second direction Y and the one side surface of the first source region 270 along the first direction Z, reducing the risk of parasitic transistors turning on. The parasitic transistor refers to an NPN transistor composed of the first source region 270, the third source region 260 at the bottom of the first source region 270, the well region 210 at the bottom of the first source region 270, and the drift layer 200 at the bottom of the third source region 260.

[0072] In some embodiments, along the first direction Z, the distance from the side surface of the third source region 260 facing the semiconductor substrate along the first direction Z to the semiconductor substrate is greater than the distance from the side surface of the well region 210 facing the semiconductor substrate along the first direction Z to the semiconductor substrate. This reduces the breakdown voltage of the semiconductor power device.

[0073] refer to Figure 19 The third source region 260 has a uniform size in the first direction Z along the third direction X.

[0074] refer to Figure 20 , Figure 20 For along Figure 17 Another cross-sectional view of the middle cutting line M11-N11. Figure 20 and Figure 19The difference lies in that the third source region 260 includes a first part and a second part, and the size of the second part along the first direction Z is larger than the size of the first part along the first direction Z; wherein, the portion of the first source region 270 located on the side of the first part along the first direction Z has a first size along the first direction Z, and the portion of the first source region 270 located on the side of the second part along the first direction Z has a second size along the first direction Z; wherein, the first size is larger than the second size. The advantage is that it further reduces the risk of parasitic transistor activation. The parasitic transistor refers to an NPN transistor composed of the first source region 270, the third source region 260 at the bottom of the first source region 270, the well region 210 at the bottom of the first source region 270, and the drift layer 200 at the bottom of the third source region 260.

[0075] refer to Figures 21 to 24 , Figure 22 For along Figure 21 Cross-sectional view of the tangent line M12-N12. Figure 23 For along Figure 21 A cross-sectional view of the tangent line M11-N11. Figure 24 For along Figure 21 Another cross-sectional view of the middle cutting line M11-N11. Figure 21 In order to be in Figure 17 A basic diagram. Figure 22 In order to be in Figure 18 A basic diagram. Figure 23 In order to be in Figure 19 A basic diagram. Figure 24 In order to be in Figure 20 The schematic diagram is based on the previous one, with the sidewalls 240 and the first mask layer 230 removed.

[0076] In some embodiments, the process of removing the sidewall 240 and the first mask layer 230 includes an etching process.

[0077] In this embodiment, two sidewalls 240 are formed above each well region 210. Reducing the number of sidewalls 240 allows for a smaller cell width along the third direction X, resulting in lower resistivity. In this embodiment, the distribution of the sidewalls 240 along the second direction Y tends to be consistent, improving the uniformity of the sidewalls 240's dimensions along the third direction X, thus enhancing the dimensional uniformity of the channel region along the third direction X.

[0078] Figures 25 to 29 This is a schematic diagram illustrating the fabrication process of a semiconductor power device in another embodiment of this application.

[0079] refer to Figures 25 to 29 , Figure 25 In order to be in Figure 15 A basic diagram. Figure 26 For along Figure 25A schematic diagram of the tangent line M22-N22. Figure 27 For along Figure 25 A schematic diagram of the tangent line M21-N21. Figure 28 For along Figure 25 A schematic diagram of the tangent line M23-N23. Figure 29 For along Figure 25 A schematic diagram of the dicing lines M24-N24, showing the removal of sidewalls 240 and the first mask layer 230; after removing sidewalls 240 and the first mask layer 230, in the partially initial doped region 2200 ( Figure 15 A first source region 270 is formed in the first source region 270. A plurality of first source regions 270 are arranged at intervals along the second direction Y. The plurality of first source regions 270 include first source regions of the first type and first source regions of the second type. The length of the second type of first source region along the third direction X is greater than the length of the first type of first source region along the third direction X. The portion of the initial doped region 2200 located between the first source region 270 of the first type and the channel region forms the doped region 220.

[0080] In some embodiments, the process of forming the first source region 270 includes an ion implantation process.

[0081] Specifically, a portion of the initial doped region 2200 is implanted with first ions of the same doping type as the initial doped region 2200. The region of the initial doped region 2200 implanted with the first ions forms a first source region 270 of the first type. A portion of the initial doped region 2200 and a well region 210 of the initial doped region 2200 along the third X-direction are also implanted with first ions. The regions of the initial doped region 2200 and the well region 210 implanted with the first ions form a second type of first source region 270.

[0082] The doped region 220 is located between the first source region 270 and the channel region of the first type along the third direction X, and on the side of the first source region 270 of the second type along the second direction Y.

[0083] refer to Figure 25 The doped region 220 extends along the second direction Y, and the size of the doped region 220 along the second direction Y is larger than the size of the doped region 220 along the third direction X.

[0084] In some embodiments, reference Figures 25 to 29 The method for fabricating a semiconductor power device further includes: forming a second source region 250, which is located in a well region 210 adjacent to a first source region 270 along a second direction Y. The doping type of the second source region 250 is opposite to that of the first source region 270, and the doping concentration of the second source region 250 is greater than that of the well region 210. The process for forming the second source region 250 includes an ion implantation process.

[0085] refer to Figure 25 The plurality of second source regions 250 include a first type of second source region and a second type of second source region, wherein the length of the second type of second source region along the third direction X is greater than the length of the first type of second source region along the third direction X. The doped region 220 is also located along the third direction X between the first type of second source region 250 and the channel region, and on the side of the second type of second source region 250 along the second direction Y.

[0086] In some embodiments, the plurality of first source regions 270 include first source regions of a first type and first source regions of a second type, wherein the length of the second type of first source region along the third direction X is greater than the length of the first type of first source region along the third direction X; and / or, the plurality of second source regions 250 include second source regions of a first type and second source regions of a second type, wherein the length of the second type of second source region along the third direction X is greater than the length of the first type of second source region along the third direction X.

[0087] refer to Figure 25 Taking as an example a plurality of first source regions 270 including first source regions of a first type and second source regions of a second type, and a plurality of second source regions 250 including second source regions of a first type and second source regions of a second type. The second type of first source regions and second type of second source regions may be spaced apart. Alternatively, a second type of second source region may be in contact with a second type of first source region. Alternatively, a portion of the second type of first source region may be in contact with a portion of the second type of second source region, while other portions of the second type of first source region may be in contact with spaced-apart regions.

[0088] Specifically, a second ion is implanted into a portion of the initial doped region 2200, and the doping type of the second ion is opposite to that of the initial doped region 2200. The region of the initial doped region 2200 implanted with the second ion forms a second source region of the first type. A second ion is implanted into a portion of the initial doped region 2200 and into the well region 210 of the initial doped region 2200 along the third X-direction. The region of the initial doped region 2200 and the well region 210 implanted with the second ion forms a second source region 250 of the second type.

[0089] In some embodiments, reference Figure 27 and Figure 29 The method for fabricating a semiconductor power device further includes: forming a third source region 260, wherein the third source region 260 is located in a well region 210 of the first source region 270 along the first direction Z toward the semiconductor substrate and is in contact with the first source region 270; the doping type of the third source region 260 is the same as that of the second source region 250; and the doping concentration of the third source region 260 is greater than that of the well region 210. The process for forming the third source region 260 includes an ion implantation process.

[0090] In some embodiments, the first source region 270 is formed after the second source region 250 is formed, or the second source region 250 is formed after the first source region 270 is formed.

[0091] In some embodiments, a third source region 260 is formed after the second source region 250 is formed, or a second source region 250 is formed after the third source region 260 is formed.

[0092] refer to Figure 27 and Figure 29 The third source region 260 has a uniform size in the first direction Z along the third direction X.

[0093] It should be noted that in other embodiments, the third source region may include a first part and a second part, wherein the size of the second part along the first direction Z is greater than the size of the first part along the first direction Z; wherein the portion of the first source region 270 located on the side of the first part along the first direction Z has a first size along the first direction Z, and the portion of the first source region 270 located on the side of the second part along the first direction Z has a second size along the first direction Z; wherein the first size is greater than the second size.

[0094] Figures 30 to 33 This is a schematic diagram of the fabrication process of a semiconductor power device in another embodiment of this application.

[0095] refer to Figure 30 A drift layer 200 is formed on one side of the semiconductor substrate along the first direction Z.

[0096] refer to Figure 31 , Figure 31 In order to be in Figure 30 The schematic diagram shows a trap region 210 formed in the drift layer 200.

[0097] In some embodiments, the method for fabricating a semiconductor power device further includes: forming a first mask layer on the side of the drift layer 200 opposite to the semiconductor substrate layer; the first mask layer having a first mask aperture. The material of the first mask layer can be an insulating dielectric material. Forming a well region 210 in the drift layer 200 includes: using the first mask layer as a mask, forming the well region 210 in the drift layer 200 via the first mask aperture. The process for forming the well region 210 includes an ion implantation process.

[0098] The first mask aperture is used to define the location of the well region 210. The projection pattern of the first mask aperture on the semiconductor substrate along the first direction Z includes a polygon. For example, the projection pattern of the first mask aperture on the semiconductor substrate along the first direction Z is a rectangle.

[0099] The projection pattern of the well region 210 along the first direction Z onto the semiconductor substrate includes polygons. Figure 31The projection pattern of the well region 210 along the first direction Z onto the semiconductor substrate is a rectangle, which is used as an example.

[0100] Multiple well regions 210 are arranged at intervals along the second direction Y and the third direction X.

[0101] refer to Figures 32 to 33 A doped region 220 and a first source region 270 are formed in a portion of the well region 210. The doping type of the doped region 220 and the doping type of the first source region 270 are the same as the doping type of the drift layer 200, and the doping concentration of the doped region 220 is less than the doping concentration of the first source region 270.

[0102] refer to Figure 32 An initial doped region 2200 is formed in a portion of the well region 210.

[0103] In some embodiments, the method for fabricating a semiconductor power device further includes: forming a sidewall on the sidewall of the first mask aperture, the sidewall being an annular structure; and a first mask layer surrounding the sidewall in a direction perpendicular to the first direction Z. The sidewall 240 is formed after the well region 210 is formed. The material of the sidewall 240 can be an insulating dielectric material. The material of the sidewall 240 is different from the material of the first mask layer 230.

[0104] Forming an initial doped region 2200 in a portion of the well region 210 includes: using a first mask layer 230 and sidewalls 240 as masks, and forming the initial doped region 2200 in the portion of the well region 210 through a first mask aperture. The process for forming the initial doped region 2200 includes an ion implantation process.

[0105] The projection pattern of the initial doped region 2200 along the first direction Z on the semiconductor substrate is similar to the projection pattern of the well region 210 along the first direction Z on the semiconductor substrate.

[0106] The projection pattern of the initial doped region 2200 along the first direction Z onto the semiconductor substrate includes polygons. Figure 32 The projection pattern of the initial doped region 2200 along the first direction Z onto the semiconductor substrate is taken as a rectangle as an example.

[0107] Well region 210 includes a channel region. The channel region is located on one side of sidewall 240 along the first direction Z. The channel region has a ring-shaped structure. The channel region is located on the side of initial doped region 220 along the direction perpendicular to the first direction Z.

[0108] refer to Figure 33 A first source region 270 is formed in a portion of the initial doped region 2200, wherein the portion of the initial doped region 2200 located between the first source region 270 and the channel region forms the doped region 220.

[0109] In some embodiments, the process of forming the first source region 270 includes an ion implantation process.

[0110] A first ion is implanted into a portion of the initial doped region 2200. The doping type of the first ion is the same as that of the initial doped region 2200. The region of the initial doped region 2200 implanted with the first ion forms the first source region 270. Since the doping concentration of the initial doped region 2200 is much smaller than that of the first source region 270, lattice damage can be reduced when a first ion is implanted into a portion of the initial doped region 2200.

[0111] The doped region 220 is located between the channel region and the first source region 270 in a direction perpendicular to the first direction Z. The doped region 220 surrounds the first source region 270 in a direction perpendicular to the first direction Z. The channel region is located on the side of the doped region 220 that is away from the first source region 270 in a direction perpendicular to the first direction Z.

[0112] In some embodiments, reference Figure 33 The method for fabricating a semiconductor power device further includes: forming a second source region 250, the second source region 250 being located in a well region 210 on the side of the first source region 270 perpendicular to the first direction Z, the doping type of the second source region 250 being opposite to the doping type of the first source region 270, and the doping concentration of the second source region 250 being greater than the doping concentration of the well region 210; wherein, in the well region 210, the entire first source region 270 and the second source region 250 are surrounded by a doped region 220 in a direction perpendicular to the first direction Z.

[0113] The arrangement directions of the first source region 270 and the second source region 250 in adjacent well regions 210 can be different, or they can be the same. The shapes of the first source region 270 in adjacent well regions 210 can be different, or they can be the same. The shapes of the second source region 250 in adjacent well regions 210 can be different, or they can be the same.

[0114] refer to Figure 33 In one portion of the well region 210, the projection pattern of the first source region 270 along the first direction Z onto the semiconductor substrate is a triangle, and the projection pattern of the second source region 250 along the first direction Z onto the semiconductor substrate is a triangle. In another portion of the well region 210, the projection pattern of the first source region 270 along the first direction Z onto the semiconductor substrate is a rectangle, and the projection pattern of the second source region 250 along the first direction Z onto the semiconductor substrate is a rectangle.

[0115] For the entire first source region 270 and second source region 250 surrounded by the doped region 220, the entire first source region 270 and second source region 250 have a first projected pattern on the semiconductor substrate along the first direction Z, and the well region 210 has a second projected pattern on the semiconductor substrate along the first direction Z; wherein, the first projected pattern and the second projected pattern are similar patterns. When the second projected pattern is rectangular, the first projected pattern is rectangular.

[0116] In some embodiments, the method for fabricating a semiconductor power device further includes: forming a third source region, wherein the third source region is located in the well region of the first source region along the first direction toward the semiconductor substrate and is in contact with the first source region, the doping type of the third source region is the same as the doping type of the second source region, and the doping concentration of the third source region is greater than the doping concentration of the well region.

[0117] In some embodiments, the third source region is uniform in size in the first direction Z at various locations along a direction perpendicular to the first direction Z.

[0118] In some embodiments, the third source region includes a first portion and a second portion, wherein the size of the second portion along the first direction Z is greater than the size of the first portion along the first direction Z; wherein the portion of the first source region 270 located on the side of the first portion along the first direction Z has a first size along the first direction Z, and the portion of the first source region 270 located on the side of the second portion along the first direction Z has a second size along the first direction Z; wherein the first size is greater than the second size.

[0119] In some embodiments, the method for fabricating a semiconductor power device further includes: after forming a first source region 270, a second source region 250 and a third source region, removing the sidewalls 240 and the first mask layer 230.

[0120] In this embodiment, each well region 210 has one sidewall 240, which is ring-shaped. Reducing the number of sidewalls 240 allows for a smaller cell width along the direction perpendicular to the first direction Z, thus lowering the resistivity. In this embodiment, the sidewalls 240 are evenly distributed, improving the uniformity of their dimensions along the direction perpendicular to the first direction Z, thereby enhancing the uniformity of the channel region along this direction.

[0121] Figures 34 to 36 This is a schematic diagram of the fabrication process of a semiconductor power device in another embodiment of this application.

[0122] refer to Figure 34 , Figure 34 In order to be in Figure 30 The schematic diagram shows a trap region 210 formed in the drift layer 200.

[0123] In some embodiments, the method for fabricating a semiconductor power device further includes: forming a first mask layer on the side of the drift layer 200 opposite to the semiconductor substrate layer; the first mask layer having a first mask aperture. The material of the first mask layer can be an insulating dielectric material. Forming a well region 210 in the drift layer 200 includes: using the first mask layer as a mask, forming the well region 210 in the drift layer 200 via the first mask aperture. The process for forming the well region 210 includes an ion implantation process.

[0124] The first mask aperture is used to define the location of the well region 210. The projection pattern of the first mask aperture on the semiconductor substrate along the first direction Z includes a polygon. For example, the projection pattern of the first mask aperture on the semiconductor substrate along the first direction Z is a hexagon.

[0125] The projection pattern of the well region 210 along the first direction Z onto the semiconductor substrate includes polygons. Figure 34 The projection pattern of the well region 210 along the first direction Z onto the semiconductor substrate is a hexagon as an example.

[0126] Multiple well regions 210 are arranged at intervals along the second direction Y and the third direction X.

[0127] refer to Figures 35 to 36 A doped region 220 and a first source region 270 are formed in a portion of the well region 210. The doping type of the doped region 220 and the doping type of the first source region 270 are the same as the doping type of the drift layer 200, and the doping concentration of the doped region 220 is less than the doping concentration of the first source region 270.

[0128] refer to Figure 35 An initial doped region 2200 is formed in a portion of the well region 210.

[0129] In some embodiments, the method for fabricating a semiconductor power device further includes: forming a sidewall on the sidewall of the first mask aperture, the sidewall being an annular structure; and a first mask layer surrounding the sidewall in a direction perpendicular to the first direction Z. The sidewall 240 is formed after the well region 210 is formed. The material of the sidewall 240 can be an insulating dielectric material. The material of the sidewall 240 is different from the material of the first mask layer 230.

[0130] Forming an initial doped region 2200 in a portion of the well region 210 includes: using a first mask layer 230 and sidewalls 240 as masks, and forming the initial doped region 2200 in the portion of the well region 210 through a first mask aperture. The process for forming the initial doped region 2200 includes an ion implantation process.

[0131] The projection pattern of the initial doped region 2200 along the first direction Z on the semiconductor substrate is similar to the projection pattern of the well region 210 along the first direction Z on the semiconductor substrate.

[0132] The projection pattern of the initial doped region 2200 along the first direction Z onto the semiconductor substrate includes polygons. Figure 35 The projection pattern of the initial doped region 2200 along the first direction Z onto the semiconductor substrate is a hexagon as an example.

[0133] Well region 210 includes a channel region. The channel region is located on one side of sidewall 240 along the first direction Z. The channel region has a ring-shaped structure. The channel region is located on the side of initial doped region 220 along the direction perpendicular to the first direction Z.

[0134] refer to Figure 36 In the initial doped region 2200 ( Figure 35 A first source region 270 is formed in the channel region, wherein the portion of the initial doped region 2200 located between the first source region 270 and the channel region forms the doped region 220.

[0135] In some embodiments, the process of forming the first source region 270 includes an ion implantation process.

[0136] The doped region 220 is located between the channel region and the first source region 270 in a direction perpendicular to the first direction Z. The doped region 220 surrounds the first source region 270 in a direction perpendicular to the first direction Z. The channel region is located on the side of the doped region 220 that is away from the first source region 270 in a direction perpendicular to the first direction Z.

[0137] In some embodiments, reference Figure 36 The method for fabricating a semiconductor power device further includes: forming a second source region 250, the second source region 250 being located in a well region 210 on the side of the first source region 270 perpendicular to the first direction Z, the doping type of the second source region 250 being opposite to the doping type of the first source region 270, and the doping concentration of the second source region 250 being greater than the doping concentration of the well region 210; wherein, in the well region 210, the entire first source region 270 and the second source region 250 are surrounded by a doped region 220 in a direction perpendicular to the first direction Z.

[0138] The arrangement directions of the first source region 270 and the second source region 250 in adjacent well regions 210 can be different, or they can be the same. The shapes of the first source region 270 in adjacent well regions 210 can be different, or they can be the same. The shapes of the second source region 250 in adjacent well regions 210 can be different, or they can be the same.

[0139] For the entire first source region 270 and second source region 250 surrounded by the doped region 220, the entire first source region 270 and second source region 250 have a first projected pattern on the semiconductor substrate along the first direction Z, and the well region 210 has a second projected pattern on the semiconductor substrate along the first direction Z; wherein, the first projected pattern and the second projected pattern are similar patterns. When the second projected pattern is hexagonal, the first projected pattern is hexagonal.

[0140] In some embodiments, the method for fabricating a semiconductor power device further includes: forming a third source region, wherein the third source region is located in the well region of the first source region along the first direction toward the semiconductor substrate and is in contact with the first source region, the doping type of the third source region is the same as the doping type of the second source region, and the doping concentration of the third source region is greater than the doping concentration of the well region.

[0141] In some embodiments, the third source region is uniform in size in the first direction Z at various locations along a direction perpendicular to the first direction Z.

[0142] In some embodiments, the third source region includes a first portion and a second portion, wherein the size of the second portion along the first direction Z is greater than the size of the first portion along the first direction Z; wherein the portion of the first source region 270 located on the side of the first portion along the first direction Z has a first size along the first direction Z, and the portion of the first source region 270 located on the side of the second portion along the first direction Z has a second size along the first direction Z; wherein the first size is greater than the second size.

[0143] In some embodiments, the method for fabricating a semiconductor power device further includes: after forming a first source region 270, a second source region 250 and a third source region, removing the sidewalls 240 and the first mask layer 230.

[0144] In the semiconductor power device fabrication methods provided in the embodiments of this application, the formation processes of the first source region 270 and the second source region 250 are decoupled from the formation process of the sidewall 240, so that the position and morphology of the first source region 270 and the second source region 250 are no longer strictly limited by the size or morphology of the sidewall 240. Therefore, the first source region 270 and the second source region 250 can be formed independently according to device design requirements, and the arrangement and morphology of the first source region 270 and the second source region 250 can have various choices.

[0145] In the semiconductor power device fabrication methods provided in the various embodiments of this application, since the implantation processes of the first source region 270 and the second source region 250 are independent of each other, it is not easy for the first source region 270 and the second source region 250 to compensate each other, which is beneficial to reduce the damage to the lattice caused by multiple implantations and improve device performance and process stability.

[0146] Another embodiment of this application also provides a semiconductor power device, see reference. Figures 21 to 24 , Figure 22 For along Figure 21 Cross-sectional view of the tangent line M12-N12. Figure 23 For along Figure 21 A cross-sectional view of the tangent line M11-N11. Figure 24 For along Figure 21 Another cross-sectional view of the cut line M11-N11, the semiconductor power device includes: Semiconductor substrate (not shown); The drift layer 200 is located on one side of the semiconductor substrate layer along the first direction Z; Trap region 210 is located in drift layer 200 and includes channel region; The first source region 270 is located within a portion of the well region 210; and The doped region 220 is located in the well region 210 between the channel region and at least part of the first source region 270 in a direction perpendicular to the first direction Z; the doping type of the doped region 220 and the doping type of the first source region 270 are the same as the doping type of the drift layer 200, and the doping concentration of the doped region 220 is less than the doping concentration of the first source region 270.

[0147] In this embodiment, by setting a doped region between the channel region and at least a portion of the first source region, and the doping type of the doped region is the same as that of the first source region and the drift layer, and the doping concentration of the doped region is less than that of the first source region, the position and morphology of the first source region are no longer strictly limited by the channel region formation process, which is beneficial to reduce the cell width and reduce the specific resistance; at the same time, it can reduce the damage to the lattice caused when forming the first source region and improve the performance and process stability of the semiconductor power device.

[0148] In this embodiment, the semiconductor power device is a MOSFET semiconductor power device.

[0149] In this embodiment, a SiC-based semiconductor power device is used as an example for illustration. Accordingly, the semiconductor substrate is silicon carbide (SiC) doped with conductive ions. New-generation semiconductor power devices based on SiC exhibit higher reverse breakdown voltage, lower forward conduction loss, faster switching frequency, and stronger environmental tolerance. It should be noted that the material of the semiconductor substrate is not limited in this embodiment.

[0150] In one embodiment, the semiconductor substrate is N-type doped.

[0151] In one embodiment, the doping type of the drift layer 200 is the same as that of the semiconductor substrate. The doping concentration of the drift layer 200 is lower than that of the semiconductor substrate.

[0152] In one embodiment, the drift layer 200 is N-type doped, and further, the material of the drift layer 200 is silicon carbide doped with N-type conductive ions. It should be noted that in other embodiments, the material of the drift layer can also be other materials. The N-type conductive ions can be phosphorus ions or nitrogen ions.

[0153] In one embodiment, the doping type of the well region 210 is opposite to that of the drift layer 200. For example, the well region 210 is doped with P-type and the drift layer 200 is doped with N-type.

[0154] In one embodiment, the doping type of the first source region 270 is the same as that of the drift layer 200, but the doping concentration of the first source region 270 is greater than that of the drift layer 200. For example, the drift layer 200 is doped with N-type, and the first source region 270 is also doped with N-type.

[0155] In some embodiments, reference Figure 21 The well region 210 extends along the second direction Y, and the size of the well region 210 along the second direction Y is larger than the size of the well region 210 along the third direction X. The well region 210 has a strip-shaped structure extending along the second direction Y.

[0156] The first direction Z, the second direction Y, and the third direction X are all perpendicular to each other. The first direction Z is perpendicular to the second direction Y, the first direction Z is perpendicular to the third direction X, and the second direction Y is perpendicular to the third direction X.

[0157] In some embodiments, reference Figure 21 Multiple first source regions 270 are arranged at intervals along the second direction Y; the doped region 220 is located between the channel region and the first source region 270 along the third direction X.

[0158] refer to Figure 21 The doped region 220 extends along the second direction Y, and the size of the doped region 220 along the second direction Y is larger than the size of the doped region 220 along the third direction X.

[0159] In some embodiments, reference Figures 21 to 24 The semiconductor power device also includes a second source region 250, which is located in a well region 210 adjacent to the first source region 270 along the second direction Y. The doping type of the second source region 250 is opposite to that of the first source region 270, and the doping concentration of the second source region 250 is greater than that of the well region 210. A doped region 220 is also located along the third direction X between the channel region and the second source region 250.

[0160] For example, the first source region 270 is doped with N-type and the second source region 250 is doped with P-type.

[0161] refer to Figures 21 to 24 In the well region 210, the doped region 220 is located on both sides of the second source region 250 and the first source region 270 along the third direction X.

[0162] In some embodiments, Figure 23 and Figure 24 The semiconductor power device also includes a third source region 260, which is located in the well region 210 of the first source region 270 along the first direction Z toward the semiconductor substrate and is in contact with the first source region 270. The doping type of the third source region 260 is the same as that of the second source region 250, and the doping concentration of the third source region 260 is greater than that of the well region 210.

[0163] For example, the second source region 250 is doped with P-type, and the third source region 260 is doped with P-type.

[0164] Figure 23 and Figure 24 The third source region 260 is located at the bottom of the first source region 270 along the first direction Z, and the second source region 250 is located between the first source region 270 along the second direction Y. In this way, the third source region 260 and the second source region 250 wrap around the two sidewalls of the first source region 270 along the second direction Y and the one side surface of the first source region 270 along the first direction Z, reducing the risk of parasitic transistors turning on. The parasitic transistor refers to an NPN transistor composed of the first source region 270, the third source region 260 at the bottom of the first source region 270, the well region 210 at the bottom of the first source region 270, and the drift layer 200 at the bottom of the third source region 260.

[0165] refer to Figure 23 The third source region 260 has a uniform size in the first direction Z along the third direction X.

[0166] refer to Figure 24 The third source region 260 includes a first portion and a second portion, wherein the dimension of the second portion along the first direction Z is larger than the dimension of the first portion along the first direction Z; wherein, the portion of the first source region 270 located on the side of the first portion along the first direction Z has a first dimension along the first direction Z, and the portion of the first source region 270 located on the side of the second portion along the first direction Z has a second dimension along the first direction Z; wherein, the first dimension is larger than the second dimension. The advantage is that it further reduces the risk of parasitic transistor activation. A parasitic transistor refers to an NPN transistor composed of the first source region 270, the third source region 260 at the bottom of the first source region 270, the well region 210 at the bottom of the first source region 270, and the drift layer 200 at the bottom of the third source region 260.

[0167] Figures 25 to 29 This illustration shows a semiconductor power device provided in another embodiment of this application. Figure 25 In order to be in Figure 15 A basic diagram. Figure 26 For along Figure 25 A schematic diagram of the tangent line M22-N22. Figure 27 For along Figure 25 A schematic diagram of the tangent line M21-N21. Figure 28 For along Figure 25 A schematic diagram of the tangent line M23-N23. Figure 29 For along Figure 25 A schematic diagram of the cutting line M24-N24.

[0168] Figures 25 to 29 Schematic embodiments and Figures 21 to 24 The difference in the illustrated embodiment is that: a plurality of first source regions 270 arranged at intervals along the second direction Y include first source regions of a first type and first source regions of a second type, wherein the length of the second type of first source region along the third direction X is greater than the length of the first type of first source region along the third direction X, wherein the doped region 220 is located along the third direction X between the first type of first source region 270 and the channel region, and on the side of the second type of first source region 270 along the second direction Y; and a plurality of second source regions 250 include second source regions of a first type and second source regions of a second type, wherein the length of the second type of second source region along the third direction X is greater than the length of the first type of second source region along the third direction X, wherein the doped region 220 is also located along the third direction X between the first type of second source region 250 and the channel region, and on the side of the second type of second source region 250 along the second direction Y.

[0169] In other embodiments, the plurality of first source regions 270 include first source regions of a first type and first source regions of a second type, wherein the length of the second type of first source region along a third direction X is greater than the length of the first type of first source region along a third direction X, wherein the doped region 220 is located along a third direction X between the first type of first source region 270 and the channel region, and on the side of the second type of first source region 270 along a second direction Y; or, the plurality of second source regions 250 include second source regions of a first type and second source regions of a second type, wherein the length of the second type of second source region along a third direction X is greater than the length of the first type of second source region along a third direction X, wherein the doped region 220 is also located along a third direction X between the first type of second source region 250 and the channel region, and on the side of the second type of second source region 250 along a second direction Y.

[0170] refer to Figure 25Taking, for example, a plurality of first source regions 270 including first source regions of a first type and second source regions of a second type, and a plurality of second source regions 250 including second source regions of a first type and second source regions of a second type. The second type of first source regions and second type of second source regions may be spaced apart. Alternatively, the second type of second source regions may be in contact with the second type of first source regions. Alternatively, a portion of the second type of first source regions may be in contact with a portion of the second type of second source regions, while other portions of the second type of first source regions may be in contact with each other but spaced apart.

[0171] refer to Figure 25 The doped region 220 extends along the second direction Y, and the size of the doped region 220 along the second direction Y is larger than the size of the doped region 220 along the third direction X.

[0172] refer to Figure 27 and Figure 29 The semiconductor power device further includes forming a third source region 260, which is located in a well region 210 of the first source region 270 along the first direction Z toward the semiconductor substrate and is in contact with the first source region 270. The doping type of the third source region 260 is the same as that of the second source region 250, and the doping concentration of the third source region 260 is greater than that of the well region 210.

[0173] refer to Figure 27 and Figure 29 The third source region 260 has a uniform size in the first direction Z along the third direction X.

[0174] It should be noted that in other embodiments, the third source region may include a first part and a second part, wherein the size of the second part along the first direction Z is greater than the size of the first part along the first direction Z; wherein the portion of the first source region 270 located on the side of the first part along the first direction Z has a first size along the first direction Z, and the portion of the first source region 270 located on the side of the second part along the first direction Z has a second size along the first direction Z; wherein the first size is greater than the second size.

[0175] In this embodiment, the portion of the first source region 270 of the second type that extends beyond the first source region 270 of the first type is called the first feature extension, and the portion of the second source region 250 of the second type that extends beyond the second source region 250 of the first type along the third direction X is called the second feature extension. The first feature extension can form a space charge region with the second feature extension and / or the channel region, thereby causing a local depletion effect. Based on this local depletion effect, the channel region can achieve inversion at a lower gate voltage to form an inversion layer, and the channel region achieves forward conduction. The lower gate voltage weakens the electric field strength of the channel region in the first direction, so that the electrons in the inversion layer are not excessively bound near the interface between the channel region and the gate dielectric layer. The electrons in the inversion layer are distributed in a wider region, that is, the size of the inversion layer in the first direction is increased, the mobility of the channel region is improved, and the channel resistance is reduced.

[0176] When multiple second source regions 250 include second source regions of the first type and second source regions, the robustness of short circuits can be improved.

[0177] Figure 33 This illustration shows a semiconductor power device provided in another embodiment of this application. (Reference) Figure 33 Semiconductor power devices include: Semiconductor substrate (not shown); The drift layer 200 is located on one side of the semiconductor substrate layer along the first direction Z; Trap region 210 is located in drift layer 200 and includes channel region; The first source region 270 is located within a portion of the well region 210; and The doped region 220 is located in the well region 210 between the channel region and the first source region 270 along a direction perpendicular to the first direction Z. The doping type of the doped region 220 and the doping type of the first source region 270 are the same as the doping type of the drift layer 200, and the doping concentration of the doped region 220 is less than the doping concentration of the first source region 270.

[0178] refer to Figure 33 The doped region 220 surrounds the first source region 270 in a direction perpendicular to the first direction Z; wherein, the channel region is located on the side of the doped region 220 opposite to the first source region 270 in a direction perpendicular to the first direction Z. The channel region has a ring-shaped structure.

[0179] refer to Figure 33 The projection pattern of the well region 210 along the first direction Z onto the semiconductor substrate includes a polygon. For example, the projection pattern of the well region 210 along the first direction Z onto the semiconductor substrate is a rectangle.

[0180] Multiple well regions 210 are arranged at intervals along the second direction Y and the third direction X.

[0181] refer to Figure 33The semiconductor power device further includes a second source region 250, which is located in the well region 210 on the side of the first source region 270 perpendicular to the first direction Z. The doping type of the second source region 250 is opposite to that of the first source region 270, and the doping concentration of the second source region 250 is greater than that of the well region 210. In the well region 210, the entire first source region 270 and the second source region 250 are surrounded by a doped region 220 in a direction perpendicular to the first direction Z.

[0182] The arrangement directions of the first source region 270 and the second source region 250 in adjacent well regions 210 can be different, or they can be the same. The shapes of the first source region 270 in adjacent well regions 210 can be different, or they can be the same. The shapes of the second source region 250 in adjacent well regions 210 can be different, or they can be the same.

[0183] refer to Figure 33 In one portion of the well region 210, the projection pattern of the first source region 270 along the first direction Z onto the semiconductor substrate is a triangle, and the projection pattern of the second source region 250 along the first direction Z onto the semiconductor substrate is a triangle. In another portion of the well region 210, the projection pattern of the first source region 270 along the first direction Z onto the semiconductor substrate is a rectangle, and the projection pattern of the second source region 250 along the first direction Z onto the semiconductor substrate is a rectangle.

[0184] refer to Figure 33 For the entire first source region 270 and second source region 250 surrounded by the doped region 220, the entire first source region 270 and second source region 250 have a first projected pattern on the semiconductor substrate along the first direction Z, and the well region 210 has a second projected pattern on the semiconductor substrate along the first direction Z; wherein, the first projected pattern and the second projected pattern are similar patterns. When the second projected pattern is rectangular, the first projected pattern is rectangular.

[0185] In some embodiments, the semiconductor power device further includes a third source region located in the well region of the first source region along the first direction toward the semiconductor substrate and in contact with the first source region. The doping type of the third source region is the same as that of the second source region, and the doping concentration of the third source region is greater than that of the well region.

[0186] In some embodiments, the third source region is uniform in size in the first direction Z at various locations along a direction perpendicular to the first direction Z.

[0187] In some embodiments, the third source region includes a first portion and a second portion, wherein the size of the second portion along the first direction Z is greater than the size of the first portion along the first direction Z; wherein the portion of the first source region 270 located on the side of the first portion along the first direction Z has a first size along the first direction Z, and the portion of the first source region 270 located on the side of the second portion along the first direction Z has a second size along the first direction Z; wherein the first size is greater than the second size.

[0188] Figure 36 This illustration shows a semiconductor power device provided in another embodiment of this application. Figure 36 Schematic semiconductor power devices and Figure 33 The differences in the illustrated semiconductor power devices include: the projection pattern of the well region 210 along the first direction Z on the semiconductor substrate is hexagonal; for the entire first source region 270 and second source region 250 surrounded by the doped region 220, the entire first source region 270 and second source region 250 have a first projection pattern along the first direction Z on the semiconductor substrate, and the well region 210 has a second projection pattern along the first direction Z on the semiconductor substrate; wherein, the first projection pattern and the second projection pattern are similar patterns. When the second projection pattern is hexagonal, the first projection pattern is hexagonal.

[0189] Other content in this embodiment is referred to Figure 33 The illustrated semiconductor power device, in this embodiment and Figure 33 The same details for the illustrated semiconductor power devices will not be elaborated further.

[0190] In the semiconductor power devices provided in the embodiments of this application, the doping concentration of the channel region is less than the doping concentration of the portion of the well region located in the channel region along the first direction Z toward the drift layer, and the doping concentration of the channel region is less than the doping concentration of the portion of the well region located in the doped region 220 along the first direction Z toward the drift layer.

[0191] In the semiconductor power devices provided in the embodiments of this application, the first source region 270 and the second source region 250 are decoupled, thereby reducing the restrictions on the positional distribution and morphology of the first source region 270 and the second source region 250. The positional arrangement of the first source region 270 and the second source region 250 can be selected in various ways, and the morphology of the first source region 270 and the second source region 250 can also be selected in various ways.

[0192] The semiconductor power devices provided in the embodiments of this application are applicable to a variety of cell morphologies and layout structures, such as bar, square, hexagonal and other regular or irregular cell structures.

[0193] In various embodiments of this application, the semiconductor power device further includes a JFET region located between adjacent well regions 210.

[0194] In the semiconductor power devices provided in the various embodiments of this application, the electron flow direction is as follows: from the first source region 270 through the doped region 220, from the doped region 220 through the channel region, from the channel region through the JFET region, and from the JFET region towards the semiconductor substrate layer along the first direction Z.

[0195] In various embodiments of this application, the semiconductor power device further includes a gate structure, which comprises a gate dielectric layer and a gate electrode layer. The gate dielectric layer covers the channel region, the doped region 220, the JFET region, and a portion of the first source region 270. The gate electrode layer is located on the side of the gate dielectric layer opposite to the drift layer along the first direction Z. The material of the gate dielectric layer is, for example, silicon oxide. The material of the gate electrode layer includes polysilicon.

[0196] In one embodiment, the semiconductor power device further includes a front electrode (not shown) that contacts a first source region 270 and a second source region 250. The semiconductor power device also includes a drain metal layer located on a side surface of the semiconductor substrate layer opposite to the drift layer. The semiconductor power device further includes an isolation dielectric layer (not shown) that surrounds a side surface and a top surface of the gate electrode layer. The front electrode covers the gate electrode layer, and the isolation dielectric layer isolates the front electrode and the gate electrode layer. The material of the isolation dielectric layer includes silicon oxide.

[0197] Figure 36 and Figure 33 In this configuration, a portion of the multiple well regions 210 may contain a first source region 270 and a second source region 250. Another portion of the multiple well regions 210 may contain a first source region 270 but not a second source region 250, and yet another portion of the multiple well regions 210 may contain a second source region 250 but not a first source region 270. Alternatively, all of the multiple well regions 210 may contain both a first source region 270 and a second source region 250.

[0198] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor power device, characterized in that, include: Semiconductor substrate layer; A drift layer is located on one side of the semiconductor substrate layer along the first direction; The trap region is located in the drift layer and includes a channel region; The first source region is located in part of the well region; as well as The doped region is located in the well region between the channel region and at least a portion of the first source region in a direction perpendicular to the first direction; the doping type of the doped region and the doping type of the first source region are the same as the doping type of the drift layer, and the doping concentration of the doped region is less than the doping concentration of the first source region.

2. The semiconductor power device according to claim 1, characterized in that, A plurality of first source regions are arranged at intervals along a second direction; the doped region is located between the channel region and at least a portion of the first source regions along a third direction; Wherein, the first direction, the second direction, and the third direction are perpendicular to each other.

3. The semiconductor power device according to claim 2, characterized in that, The well region extends along the second direction, and the size of the well region along the second direction is greater than the size of the well region along the third direction; wherein, the doped region extends along the second direction, and the size of the doped region along the second direction is greater than the size of the doped region along the third direction.

4. The semiconductor power device according to claim 2, characterized in that, The semiconductor power device further includes: The second source region is located in the well region adjacent to the first source region along the second direction. The doping type of the second source region is opposite to that of the first source region, and the doping concentration of the second source region is greater than that of the well region. The doped region is also located along the third direction between the channel region and at least a portion of the second source region.

5. The semiconductor power device according to claim 4, characterized in that, The plurality of first source regions include a first source region of a first type and a first source region of a second type, wherein the length of the second type of first source region along the third direction is greater than the length of the first type of first source region along the third direction; wherein the doped region is located along the third direction between the first type of first source region and the channel region, and on the side of the second type of first source region along the second direction; And / or, the plurality of second source regions include a first type of second source region and a second type of second source region, wherein the length of the second type of second source region along the third direction is greater than the length of the first type of second source region along the third direction; wherein, the doped region is also located along the third direction between the first type of second source region and the channel region, and on the side of the second type of second source region along the second direction.

6. The semiconductor power device according to claim 5, characterized in that, The plurality of first source regions include first source regions of a first type and first source regions of a second type, and the plurality of second source regions include second source regions of a first type and second source regions of a second type; In this configuration, the first source region of the second type and the second source region of the second type are separated, or the second source region of the second type is in contact with the first source region of the second type; or, a portion of the first source region of the second type is in contact with a portion of the second source region of the second type, and another portion of the first source region of the second type is in contact with another portion of the second source region of the second type, with the contact spaced apart.

7. The semiconductor power device according to claim 1, characterized in that, The doped region surrounds the first source region in a direction perpendicular to the first direction; wherein the channel region is located on the side of the doped region opposite to the first source region in a direction perpendicular to the first direction.

8. The semiconductor power device according to claim 7, characterized in that, The projection pattern of the well region onto the semiconductor substrate along the first direction includes a polygon.

9. The semiconductor power device according to claim 7, characterized in that, The semiconductor power device further includes: The second source region is located in the well region on the side of the first source region perpendicular to the first direction. The doping type of the second source region is opposite to that of the first source region, and the doping concentration of the second source region is greater than that of the well region. In the well region, the entire first source region and the second source region are surrounded by the doped region in a direction perpendicular to the first direction.

10. The semiconductor power device according to claim 9, characterized in that, For the entire first source region and the second source region surrounded by the doped region, the entire first source region and the second source region have a first projection pattern on the semiconductor substrate along the first direction, and the well region has a second projection pattern on the semiconductor substrate along the first direction; wherein the first projection pattern and the second projection pattern are similar patterns.

11. The semiconductor power device according to claim 4 or 9, characterized in that, The semiconductor power device further includes: The third source region is located in the well region on the side of the first source region facing the semiconductor substrate along the first direction and is in contact with the first source region. The doping type of the third source region is the same as that of the second source region, and the doping concentration of the third source region is greater than that of the well region.

12. The semiconductor power device according to claim 11, characterized in that, The third source region includes: a first part and a second part, wherein the dimension of the second part along the first direction is greater than the dimension of the first part along the first direction; Wherein, the portion of the first source region located on one side of the first part along the first direction has a first size along the first direction, and the portion of the first source region located on one side of the second part along the first direction has a second size along the first direction; wherein, the first size is larger than the second size.

13. A method for fabricating a semiconductor power device, characterized in that, include: A drift layer is formed on one side of the semiconductor substrate along the first direction; A trap region is formed in the drift layer; A doped region and a first source region are formed in a portion of the well region. The doping type of the doped region and the doping type of the first source region are the same as the doping type of the drift layer, and the doping concentration of the doped region is less than that of the first source region. The well region includes a channel region; the doped region is located between the channel region and at least a portion of the first source region in a direction perpendicular to the first direction.

14. The method for fabricating a semiconductor power device according to claim 13, characterized in that, Forming the doped region and the first source region in a portion of the well region includes: An initial doped region is formed in a portion of the well region; The first source region is formed in a portion of the initial doped region, wherein the portion of the initial doped region located between the first source region and the channel region forms the doped region.

15. The method for fabricating a semiconductor power device according to claim 14, characterized in that, Also includes: A first mask layer is formed on the side of the drift layer opposite to the semiconductor substrate layer, and the first mask layer has a first mask opening; A sidewall is formed on the sidewall of the first mask opening; The formation of a trap region in the drift layer includes: before forming the sidewall, using the first mask layer as a mask, forming the trap region in the drift layer through the first mask opening; The initial doped region is formed in a portion of the well region by: using the first mask layer and the sidewall as masks, and forming the initial doped region in a portion of the well region via the first mask opening; The trench area is located on one side of the sidewall along the first direction.

16. The method for fabricating a semiconductor power device according to claim 13, characterized in that, Forming the first source region in a portion of the well region includes: forming a plurality of first source regions spaced apart along a second direction in a portion of the well region; The doped region is located between the channel region and at least a portion of the first source region along a third direction; the first direction, the second direction, and the third direction are perpendicular to each other.

17. The method for fabricating a semiconductor power device according to claim 16, characterized in that, The method for fabricating the semiconductor power device further includes: A second source region is formed, which is located in the well region adjacent to the first source region along the second direction. The doping type of the second source region is opposite to that of the first source region, and the doping concentration of the second source region is greater than that of the well region. The doped region is also located along the third direction between the channel region and at least a portion of the second source region.

18. The method for fabricating a semiconductor power device according to claim 13, characterized in that, The doped region surrounds the first source region in a direction perpendicular to the first direction; wherein the channel region is located on the side of the doped region opposite to the first source region in a direction perpendicular to the first direction.

19. The method for fabricating a semiconductor power device according to claim 18, characterized in that, The method for fabricating the semiconductor power device further includes: A second source region is formed, which is located in the well region on the side of the first source region perpendicular to the first direction. The doping type of the second source region is opposite to that of the first source region, and the doping concentration of the second source region is greater than that of the well region. In the well region, the entire first source region and the second source region are surrounded by the doped region in a direction perpendicular to the first direction.

20. The method for fabricating a semiconductor power device according to claim 17 or 19, characterized in that, The method for fabricating the semiconductor power device further includes: A third source region is formed, which is located in the well region of the first source region along the first direction toward the semiconductor substrate and is in contact with the first source region. The doping type of the third source region is the same as that of the second source region, and the doping concentration of the third source region is greater than that of the well region.

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