Transistor and method of manufacturing the same

Abstract

A transistor and a preparation method thereof, and relate to the field of transistor preparation technology. The preparation method comprises the following steps: preparing a substrate, forming a composite body in which a first superlattice layer and a second superlattice layer are alternately arranged in sequence on the substrate, and forming a groove, and depositing an isolation body at the bottom of the groove; depositing a sacrificial layer in the groove, forming a channel in the sacrificial layer, depositing a dielectric layer in the channel, and isolating the composite bodies on both sides of the dielectric layer; removing the first superlattice layer and the sacrificial layer; and depositing a gate dielectric layer and a metal gate to form a transistor in which the metal gate is wrapped around the second superlattice layer. According to the application, the sacrificial layer is deposited first, then the dielectric layer is deposited, the sacrificial layer is removed, and the dielectric layer is retained, so that a dielectric layer is established to isolate the N-type metal oxide semiconductor and the P-type metal oxide semiconductor, the NP boundary offset phenomenon and the lateral etching phenomenon under the mask are effectively avoided, and the full-surrounding gate transistor structure in which the gate is surrounded on four sides is retained.

Description

Technical Field

[0001] This application relates to the field of transistor fabrication technology, and in particular to a transistor and a method for fabricating the same. Background Technology

[0002] With the development of semiconductor technology, the critical linewidth dimensions of semiconductor devices have been reduced from the micrometer level to the nanometer level. This miniaturization can lead to short-channel effects and large leakage currents.

[0003] In the integration process of Gate All Around Field Effect Transistor (GAAFET), in order to achieve Multi-threshold Voltage (Multi Vt) technology, multiple selective wet etching processes are required on the work function metal (WFM) layer in different regions.

[0004] See Figure 1 As shown, due to the isotropic nature of wet etching, transistors will exhibit positive / negative channel metal oxide semiconductor boundary shift (NPB shift) and mask undercut. The positive / negative channel boundary shift is also known as the NP boundary shift, which can damage the work function metal layer of adjacent transistors in severe cases.

[0005] Currently, see Figure 2 As shown, a dielectric wall can be placed between N-type metal-oxide-semiconductor (NMOS) and P-type metal-oxide-semiconductor (PMOS) to prevent NP boundary shift and lateral etching under the mask during transistor fabrication. However, the dielectric wall is in contact with the channel, preventing the gate from surrounding the channel on all four sides, only on three sides, thus sacrificing the characteristics of a GAAFET. The inner side of the channel near the dielectric wall is no longer surrounded by the gate, affecting the gate control capability of the GAAFET. Summary of the Invention

[0006] This application provides a transistor and a method for fabricating the same, which isolates N-type metal-oxide semiconductor and P-type metal-oxide semiconductor by establishing a dielectric layer, thereby preserving the full-ring gate structure in the transistor.

[0007] In a first aspect, this application provides a method for fabricating a transistor, comprising the following steps:

[0008] Prepare a substrate and form a composite on the substrate, the composite comprising alternating layers of a first superlattice layer and a second superlattice layer;

[0009] A groove is formed on the composite, the groove dividing the composite into two parts, the two parts of the composite located on opposite sides of the groove;

[0010] An insulator is deposited at the bottom of the trench;

[0011] A sacrificial layer is deposited in the trench to form a channel, such that the sacrificial layer comprises two parts respectively distributed on both sides of the channel, and each part of the sacrificial layer is connected to the composite.

[0012] A medium layer is deposited within the channel;

[0013] Remove the first superlattice layer and the sacrificial layer;

[0014] A gate dielectric layer and a metal gate are deposited on both sides of the dielectric layer, and the gate dielectric layer on each side of the dielectric layer surrounds the second superlattice layer, and the metal gate on each side of the dielectric layer surrounds the gate dielectric layer, wherein the metal gate on each side of the dielectric layer is located between the second superlattice layer and the dielectric layer.

[0015] This application establishes a dielectric layer to isolate N-type and P-type metal-oxide-semiconductor (MOS) nanosheets, thereby forming a higher-density all-around gate transistor structure. During transistor fabrication, after forming the fin-shaped active region pattern, a dielectric layer is deposited to form a dielectric isolation wall between the N-type and P-type MOS semiconductors, followed by a multi-threshold voltage (MTV) process. The presence of the dielectric layer effectively blocks lateral etching during wet etching in the MTV module, avoiding issues such as NP boundary shift and under-mask lateral etching. Furthermore, while avoiding NP boundary shift and under-mask lateral etching, the spacing between the N-type and P-type MOS semiconductors can be correspondingly reduced, with the positive and negative channel spacing less than 20 nm.

[0016] Furthermore, before forming the dielectric layer, this application first deposits a sacrificial layer and forms channels between the sacrificial layers. A dielectric layer is then deposited within these channels, and the sacrificial layers are removed using an etch-back method, retaining the dielectric layer between the N-type and P-type metal-oxide-semiconductor semiconductors. Before forming the gate dielectric layer and metal gate, the etched-back sacrificial layers create a gap between the dielectric layer and the second superlattice layer, allowing the formed gate dielectric layer and metal gate to surround the second superlattice layer. This achieves a four-sided complete enclosure of the channel by the transistor's gate. Compared to FinFETs and forksheets (FS), the GAAFET fabricated in this application exhibits a higher effective gate width and superior gate control capability per unit area. This architecture achieves higher performance and lower power consumption per unit area. Moreover, unlike the "digital" limitation of FinFET channel width, GAAFETs allow for continuous adjustment of the nanosheet width according to design requirements, achieving synergistic optimization of performance and area.

[0017] In one possible implementation, when forming the composite on the substrate, the side of the composite facing away from the substrate is the first superlattice layer. This ensures that the second superlattice layer is not damaged during transistor fabrication, resulting in a transistor with an intact channel.

[0018] In one possible implementation, the side of the composite closest to the substrate is the first superlattice layer. In this embodiment, the stacked structure of the substrate, the first superlattice layer, and the second superlattice layer ensures that after the first superlattice layer is etched away, none of the multiple second superlattice layers will adhere to the substrate. This allows each second superlattice layer to surround a metal gate, resulting in a higher effective gate width and better gate control capability per unit area of ​​the transistor. This architecture achieves higher performance and lower power consumption per unit area.

[0019] In one possible implementation, before removing the first superlattice layer and the sacrificial layer, the transistor fabrication method further includes: removing a portion of the sacrificial layer located between the bottom of the trench and the substrate, so that the dielectric layer deposited within the channel contacts the insulator. The dielectric layer completely isolates the composites on both sides. With the dielectric layer and the insulator in contact, and the spaces on both sides of the dielectric layer completely isolated, lateral etching under the mask can be effectively prevented, and the transistor can be guaranteed to have good insulation properties.

[0020] In one possible implementation, the dielectric layer comprises a silicon compound Si containing at least one element selected from N, C, and O. k O x Cy N z Where k is greater than 0, and at least one of x, y, and z is greater than 0; or, the dielectric layer comprises aluminum oxide Al. m O n , where m and n are greater than 0.

[0021] In one possible implementation, the substrate is prepared from one of silicon, germanium, silicon carbide, silicon germanium, and diamond.

[0022] In one possible implementation, the materials used to prepare the second superlattice layer, the first superlattice layer, and / or the sacrificial layer include at least one of silicon, germanium, silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium carbon, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide.

[0023] In one possible implementation, the sacrificial layer is made of the same material as the first superlattice layer, and the sacrificial layer and the first superlattice layer can be etched simultaneously.

[0024] In one possible implementation, the material used to prepare the sacrificial layer is different from the material used to prepare the first superlattice layer; when removing the first superlattice layer and the sacrificial layer, the first superlattice layer and the sacrificial layer are removed simultaneously or in stages, thereby achieving diverse options for etching the sacrificial layer and the first superlattice layer.

[0025] In one possible implementation, the gate dielectric layer includes an interface layer and a high dielectric constant layer, wherein the interface layer is located between the high dielectric constant layer and the second superlattice layer.

[0026] In a second aspect, this application provides a transistor, including a substrate, multiple layers of second superlattice layers, a gate dielectric layer and a metal gate, wherein the multiple layers of second superlattice layers are stacked at intervals on the substrate, the gate dielectric layer surrounds the second superlattice layers, and the metal gate surrounds the gate dielectric layer.

[0027] In one possible implementation, two sets of the multilayer second superlattice layers are provided on the substrate, and a dielectric layer is provided between the two sets of the multilayer second superlattice layers. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the NP boundary offset phenomenon and the lateral etching phenomenon under the mask described in this application;

[0029] Figure 2 This is a schematic diagram of the three-sided surrounding channel of the gate as described in this application;

[0030] Figure 3This is a schematic diagram of the transistor fabrication process provided in the embodiments of this application;

[0031] Figure 4 This is a schematic diagram of the transistor fabrication method provided in the embodiments of this application;

[0032] Figure 5 This is a schematic diagram of the gate dielectric layer and the second superlattice layer structure provided in the embodiments of this application;

[0033] Figure 6 This is a schematic diagram of the structure of the substrate, the first superlattice layer, and the second superlattice layer provided in the embodiments of this application;

[0034] Figure 7 This is a schematic diagram of the sacrificial layer, channel, and dielectric layer provided in the embodiments of this application;

[0035] Figure 8 This is a schematic diagram of the transistor portion structure provided in the embodiments of this application. Detailed Implementation

[0036] The embodiments of this application are described below with reference to the accompanying drawings.

[0037] For ease of understanding, the English abbreviations and related technical terms used in the embodiments of this application will be explained and described below.

[0038] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0039] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0040] It should be understood that the term "and / or" used in this document is merely a description of the same field in the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0041] In the description of this application, the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0042] It should be understood that the terms "first," "second," etc., used in this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order.

[0043] See Figure 1 As shown, Figure 1 This illustrates the NP boundary shift phenomenon and under-mask lateral etching phenomenon that occur in the integrated circuit process of a fully all-around gate transistor. During the etching of the work function metal layer 230 of the P-type metal-oxide-semiconductor 210, due to the isotropic nature of wet etching, the NP boundary 240 shifts towards the N-type metal-oxide-semiconductor 220 side. In severe cases, this damages the work function metal layer 230 on the N-type metal-oxide-semiconductor 220 side, resulting in the NP boundary shift phenomenon in the transistor. (See also...) Figure 1 As shown, under normal circumstances, the NP boundary is located at NP boundary 240. When a shift occurs, it shifts to the position shown at the first NP boundary 241, or even to the position shown at the second NP boundary 242, severely damaging the work function metal layer 230 on one side of the N-type metal-oxide semiconductor 220. Furthermore, lateral etching under the mask also occurs at the bottom of the NP boundary 240. (See [reference needed]). Figure 1 The right-pointing arrow at the bottom of the NP boundary 240.

[0044] Therefore, in the traditional GAAFET architecture design, a certain spacing needs to be maintained between the P-type metal-oxide-semiconductor 210 and the N-type metal-oxide-semiconductor 220; otherwise, severe NP boundary offset and lateral etching under the mask will occur. Simultaneously, if the spacing between adjacent nanosheets (NS) in the transistor is too close, the source / drain (S / D) epitaxial growth may overlap, potentially leading to a short circuit. These factors limit the minimum distance between NMOS and PMOS in the traditional GAAFET structure, reducing device density.

[0045] See Figure 2As shown, in the GAAFET architecture, a dielectric wall 250 can be deposited within the trench between the P-type metal-oxide semiconductor 210 and the N-type metal-oxide semiconductor 220. The dielectric wall 250 prevents NP boundary shift and lateral etching under the mask during transistor fabrication. However, during the deposition of the dielectric wall 250, it contacts the channel 260, preventing the gate 270 from completely surrounding the channel on all four sides; it can only surround three sides of the channel 260. Figure 2 In the P-type metal-oxide semiconductor 210 (corresponding to the upper, left, and lower sides of the channel 260), the gate 270, located on the right side of the channel 260, cannot surround the channel 260, thus losing the full gate surround characteristic of the GAAFET. The inner side of the channel 260 near the dielectric wall 250 is no longer surrounded by the gate 270, making the transistor structure similar to a Si-on-insulator (SOI) FinFET structure, affecting the gate control capability of the GAAFET.

[0046] See Figure 3 and Figure 4 As shown, this application provides a method for fabricating a transistor, comprising the following steps:

[0047] Step S100: Prepare substrate 110 and form composite 120 on substrate 110. Composite 120 includes alternating layers of first superlattice layer 121 and second superlattice layer 122.

[0048] Specifically, after the substrate 110 is prepared, a first superlattice layer 121 and a second superlattice layer 122 are sequentially deposited on the substrate 110. The materials of the first superlattice layer 121 and the second superlattice layer 122 can be different, forming a composite 120 in which the first superlattice layer 121 and the second superlattice layer 122 are alternately stacked.

[0049] Step S200: A groove 130 is formed on the composite 120, the groove 130 divides the composite 120 into two parts, and the two parts of the composite 120 are located on both sides of the groove 130.

[0050] The entire composite 120 can be deposited on the substrate 110, and two parts of the composite 120 can be formed by etching. The two parts of the composite 120 can be used to form a P-type metal oxide semiconductor 210 and an N-type metal oxide semiconductor 220.

[0051] The groove 130 penetrates the composite 120 and extends to the base 110 to form two protrusions 111 on the base 110, and the groove 130 includes a partial groove between the two protrusions 111.

[0052] The protrusion 111 is part of the base 110, and its shape is an upward protrusion, and the shape of the protrusion 111 is not limited to... Figure 3 The square structure shown.

[0053] Step S300: Deposit isolator 131 at the bottom of trench 130. Isolator 131 is also called shallow trench isolation (STI).

[0054] Step S400: Deposit a sacrificial layer 140 in the trench 130 and form a channel 141, such that the sacrificial layer 140 includes two parts distributed on both sides of the channel 141, and each part of the sacrificial layer 140 is connected to the composite 120.

[0055] A sacrificial layer 140 is deposited within the trench 130, and the sacrificial layer 140 is in contact with the sidewalls of the composite 120. The sacrificial layer 140 deposited within the trench 130 has a channel 141 extending from the top to the bottom of the trench 130, dividing the sacrificial layer 140 into two parts, each part of the sacrificial layer 140 contacting the sidewalls of the two sides of the composite 120.

[0056] Two sidewall-shaped sacrificial layers 140 with channels 141 can be deposited directly, or the entire sacrificial layer 140 can be deposited first, and the channels 141 can be formed by etching.

[0057] Step S500: Deposit a medium layer 150 in channel 141; after forming channel 141, deposit a medium layer 150 in channel 141, the medium layer 150 fills the channel 141, and the medium layer 150 is separated from the composite 120 by the sacrificial layer 140.

[0058] Between two adjacent composites 120, the structures are arranged in the order of composite 120-sacrificial layer 140-dielectric layer 150-sacrificial layer 140-composite 120.

[0059] Step S600: Remove the first superlattice layer 121 and the sacrificial layer 140. The first superlattice layer 121 and the sacrificial layer 140 can be removed by etching to expose the second superlattice layer 122. The first superlattice layer 121 between the second superlattice layers 122 is etched, and multiple second superlattice layers 122 are arranged at intervals to form multiple spaced-layered channels.

[0060] In step S700, a gate dielectric layer 160 and a metal gate 170 are deposited on both sides of the dielectric layer 150, and the gate dielectric layer 160 on each side of the dielectric layer 150 surrounds the second superlattice layer 122, and the metal gate 170 on each side of the dielectric layer 150 surrounds the gate dielectric layer 160. On each side of the dielectric layer 150, the metal gate 170 is located between the second superlattice layer 122 and the dielectric layer 150.

[0061] On both the P-type metal-oxide semiconductor 210 and the N-type metal-oxide semiconductor 220 side, the metal gate 170 surrounds its corresponding second superlattice layer 122 on all four sides. A portion of the metal gate 170 is located between the second superlattice layer 122 and the dielectric layer 150 to form a metal gate fully surrounding transistor.

[0062] This application establishes a dielectric layer 150 to isolate N-type and P-type metal-oxide-semiconductor nanosheets, thereby forming a higher-density all-around gate transistor structure. During transistor fabrication, after forming the fin-shaped active region pattern, a dielectric layer 150 is deposited to form a dielectric isolation wall between the N-type and P-type metal-oxide-semiconductor, followed by a multi-threshold voltage (MTV) process. The presence of the dielectric layer 150 effectively blocks lateral etching during wet processing in the MTV module, avoiding issues such as NP boundary shift and under-mask lateral etching. Furthermore, while avoiding NP boundary shift and under-mask lateral etching, the spacing between the N-type and P-type metal-oxide-semiconductor can be correspondingly reduced, with the positive and negative channel spacing less than 20 nm.

[0063] Furthermore, before forming the dielectric layer 150, this application first deposits a sacrificial layer 140 and forms a channel 141 between the sacrificial layers 140. The dielectric layer 150 is then deposited within the channel 141. The sacrificial layer 140 is then removed by etching back, leaving the dielectric layer 150 between the N-type and P-type metal-oxide-semiconductor semiconductors. Before forming the gate dielectric layer 160 and the metal gate 170, the etched-away sacrificial layer 140 creates a gap between the dielectric layer 150 and the second superlattice layer 122, allowing the formed gate dielectric layer 160 and the metal gate 170 to surround the second superlattice layer 122. This achieves a four-sided complete enclosure of the transistor's gate to the channel (see [reference]). Figure 5(As shown). Compared to FinFETs and Forksheets (FS), the transistors fabricated in this application exhibit a higher effective gate width and better gate control per unit area. This architecture can achieve higher performance and lower power consumption per unit area. Furthermore, compared to the "digital" limitation of FinFET channel width, GAAFETs allow for continuous adjustment of the nanosheet width according to design requirements, achieving synergistic optimization of performance and area.

[0064] In one possible implementation, see [reference] Figure 6 As shown, in step S100, when the first superlattice layer 121 and the second superlattice layer 122 are sequentially deposited on the substrate 110, a first superlattice layer 121 is first deposited on the substrate 110, a second superlattice layer 122 is deposited on the first superlattice layer 121, and then a first superlattice layer 121 is deposited on the second superlattice layer 122. The layers are deposited alternately to form a composite 120 in which the first superlattice layer 121 and the second superlattice layer 122 are stacked alternately.

[0065] In this embodiment, the stacked structure of substrate 110, first superlattice layer 121, and second superlattice layer 122 ensures that after etching away the first superlattice layer 121, none of the multiple second superlattice layers 122 will adhere to the substrate 110. This allows each second superlattice layer 122 to surround a metal gate, resulting in a higher effective gate width and better gate control capability per unit area of ​​the transistor. Within a unit area, this architecture can achieve higher performance and lower power consumption.

[0066] In this embodiment, four layers of first superlattice layer 121 and three layers of second superlattice layer 122 are deposited as an example. After etching away the first superlattice layer 121, three spaced-apart second superlattice layers 122 remain to form a three-channel transistor. This embodiment is not limited to having three layers of second superlattice layer 122; the number of layers of second superlattice layer 122 can be set according to the desired transistor structure.

[0067] In one possible implementation, see [reference] Figure 6 As shown, the side of the composite 120 facing away from the substrate 110 is formed by a deposited first superlattice layer 121.

[0068] See Figure 6As shown, when depositing the first superlattice layer 121 and the second superlattice layer 122 layer by layer on the substrate 110, the last layer of the first superlattice layer 121 is deposited to form the outermost lattice layer of the composite 120, so that all the first superlattice layers 121 are sandwiched in the middle by the second superlattice layer 122, ensuring that the second superlattice layer 122 is not damaged during the fabrication of the transistor, and the fabricated transistor has an intact channel.

[0069] In one possible implementation, see [reference] Figure 6 As shown, the side of the composite 120 closest to the substrate 110 is formed by a deposited first superlattice layer 121. A first superlattice layer 121 is present between the substrate 110 and the second superlattice layer 122. After the first superlattice layer 121 is subsequently etched away, a gap exists between the second superlattice layer 122 and the substrate 110, and the metal gate 170 can surround the second superlattice layer 122 on all sides.

[0070] In one possible implementation, see [reference] Figure 7 As shown, in step S400, when the sacrificial layer 140 is deposited in the trench 130, the sacrificial layer 140 will first form a layer on the upper side of a portion of the composite 120 on one side of the trench 130, for example, in Figure 7 A layer is formed on the left-side composite 120; and gradually extends downward along the left sidewall of the trench 130 to form a vertically extending sacrificial layer 140 located on the left side of the trench 130. Then, it extends laterally to the right along the bottom of the trench 130 to the right-side composite 120, and then extends upward along the right sidewall of the trench 130 to form another vertically extending partial sacrificial layer 140, forming a channel 141 between the two vertically extending portions. Afterward, the sacrificial layer 140 extends to the upper side of the right-side partial composite 120 to form another layer.

[0071] In this embodiment, a portion of the sacrificial layer 140 located between the bottom of the trench 130 and the substrate 110 is first removed by etching, so that the dielectric layer 150 deposited in the channel 141 comes into contact with the isolator 131, and there is no gap between the dielectric layer 150 and the isolator 131. In subsequent etching, there will be no lateral etching phenomenon under the mask between the dielectric layer 150 and the isolator 131. Furthermore, after the metal gate is deposited, the dielectric layer 150 can achieve insulation between the two parts of the composite 120, that is, ensure that the N-type metal oxide semiconductor and the P-type metal oxide semiconductor are mutually insulated.

[0072] In one possible implementation, before removing the first superlattice layer 121 and the sacrificial layer 140, the transistor fabrication method further includes removing a portion of the sacrificial layer 140 located between the bottom of the trench 130 and the substrate 110, so that the dielectric layer 150 deposited in the channel 141 contacts the insulator 131.

[0073] In step S400, after depositing the sacrificial layer 140 in the trench 130, a portion of the sacrificial layer 140 at the bottom of the trench 130 is removed by dry etching, so that the dielectric layer 150 deposited in the channel 141 comes into contact with the insulator 131, and the dielectric layer 150 completely isolates the composites 120 on the left and right sides. After the dielectric layer 150 and the insulator 131 come into contact and the spaces on the left and right sides of the dielectric layer 150 are completely isolated, the occurrence of lateral etching under the mask can be effectively prevented, and the transistor can be guaranteed to have good insulation.

[0074] In one possible implementation, the substrate 110 is made of one of the following materials: silicon (Si), germanium (Ge), silicon carbide (SiC), silicon-germanium (SiGe), and diamond. Alternatively, the substrate 110 may also include a silicon-on-insulator (SOI) structure and / or may have other suitable reinforcing components.

[0075] In one possible implementation, the material used to prepare the second superlattice layer 122 includes at least one of silicon (Si), germanium (Ge), compound semiconductors, and alloy semiconductors.

[0076] Among them, compound semiconductors include at least one of silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb); alloy semiconductors include at least one of silicon germanium carbon (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP).

[0077] It should be noted that in the same composite 120, the first superlattice layer 121 and the second superlattice layer 122 are made of different materials. The second superlattice layer 122 can be exposed by etching the first superlattice layer 121. Etching away the first superlattice layer 121 will not cause etching damage to the second superlattice layer 122, thus forming a fully all-around gate transistor.

[0078] It should be noted that "at least one" refers to the fact that the second superlattice layer 122 can have multiple layers. In the same composite 120, the materials used to prepare different layers of the second superlattice layer 122 can be different, but the materials used to prepare the same layer of the second superlattice layer 122 are the same. Furthermore, when both silicon (Si) and germanium (Ge) are included, it refers to forming a silicon-germanium (SiGe) alloy, not a double-layer structure of silicon and germanium layers.

[0079] In one possible implementation, the material used to prepare the first superlattice layer 121 includes at least one of silicon (Si), germanium (Ge), compound semiconductors, and alloy semiconductors.

[0080] Among them, compound semiconductors include at least one of silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb); alloy semiconductors include at least one of silicon germanium carbon (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP).

[0081] It should be noted that in the same composite 120, the first superlattice layer 121 and the second superlattice layer 122 are made of different materials. The second superlattice layer 122 can be exposed by etching the first superlattice layer 121. Etching away the first superlattice layer 121 will not cause etching damage to the second superlattice layer 122, thus forming a fully all-around gate transistor.

[0082] It should be noted that "at least one" refers to the fact that the first superlattice layer 121 can have multiple layers. In the same composite 120, the materials used to prepare the first superlattice layer 121 in different layers can be different, but the materials used to prepare the first superlattice layer 121 in the same layer are the same. Furthermore, when both silicon (Si) and germanium (Ge) are included, it refers to forming a silicon-germanium (SiGe) alloy, not a double-layer structure of silicon and germanium layers.

[0083] In one possible implementation, the material used to prepare the sacrificial layer 140 includes at least one of silicon (Si), germanium (Ge), compound semiconductors, and alloy semiconductors.

[0084] Among them, compound semiconductors include at least one of silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb); alloy semiconductors include at least one of silicon germanium carbon (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP).

[0085] The materials used to prepare the first superlattice layer 121 and the sacrificial layer 140 can be the same, and the first superlattice layer 121 and the sacrificial layer 140 can be etched simultaneously.

[0086] It should be noted that "at least one" means that the sacrificial layer 140 can have multiple layers. In the same composite 120, the materials used to prepare the sacrificial layers 140 in different layers can be different, but the materials used to prepare the sacrificial layers 140 in the same layer are the same. Furthermore, when both silicon (Si) and germanium (Ge) are included, it refers to forming a silicon-germanium (SiGe) alloy, not a double-layer structure of silicon and germanium layers.

[0087] In one possible implementation, the materials used to fabricate the first superlattice layer 121 and the sacrificial layer 140 can be different. The first superlattice layer 121 and the sacrificial layer 140 can be etched in stages, for example, first etching the first superlattice layer 121 and then etching the sacrificial layer 140; or first etching the sacrificial layer 140 and then etching the first superlattice layer 121; or first etching a portion of the first superlattice layer 121, then etching a portion of the sacrificial layer 140, and then etching the first superlattice layer 121 again, etc. Alternatively, the first superlattice layer 121 and the sacrificial layer 140 can be etched simultaneously.

[0088] In one possible implementation, the dielectric layer 150 comprises a silicon compound Si containing at least one element selected from nitrogen (N), carbon (C), and oxygen (O). k O x C y N z Where k is greater than 0, and at least one of x, y, and z is greater than 0, it can be silicon oxide, silicon carbide, or silicon carbide; or, the dielectric layer 150 comprises aluminum oxide (Al). m O n , where m and n are greater than 0.

[0089] In one possible implementation, see [reference] Figure 5 As shown, the gate dielectric layer 160 includes an interface layer 161 (IL) and a high-k metal gate (HK) layer 162, with the interface layer 161 located between the high-k metal gate 162 and the second superlattice layer 122.

[0090] Specifically, the high dielectric constant layer 162 has a high dielectric constant, which is greater than or equal to 20.

[0091] In this embodiment, the gate dielectric layer 160 surrounds the second superlattice layer 122 in four directions: up, down, left, and right. After depositing the metal gate, a transistor structure is formed in which the metal gate surrounds the second superlattice layer 122.

[0092] In one possible implementation, see [reference] Figure 8As shown, this application provides a transistor in which at least two sets of multilayer second superlattice layers 122 are disposed on a substrate 110. Each set of multilayer second superlattice layers 122 forms a semiconductor structure 180, and the two semiconductor structures 180 can respectively constitute an N-type metal-oxide-semiconductor (MOS) 220 and a P-type MOS 210 structure. Each semiconductor structure 180 includes a substrate 110 and multilayer second superlattice layers 122, which are stacked at intervals on the substrate 110. A gate dielectric layer 160 is disposed around the outer wall of the second superlattice layers 122, and a metal gate 170 surrounds the gate dielectric layer 160. (See reference [reference needed] in this application.) Figure 8 As shown, the surrounding arrangement means that the second superlattice layer 122 is surrounded by the gate dielectric layer 160 in at least four directions (up, down, left, and right), and the gate dielectric layer 160 is surrounded by the metal gate 170 in at least four directions (up, down, left, and right).

[0093] It should be noted that, Figure 8 Only a partial structure of the transistor is shown as an example to illustrate the structure of the transistor in this application, which can form a gate-all-around transistor with a higher effective gate width and better gate control capability per unit area. This architecture can achieve higher performance and lower power consumption per unit area. Furthermore, compared to the "digital" limitation of the channel width of the fin field-effect transistor, the width of the nanosheet can be continuously adjusted according to design requirements to achieve synergistic optimization of performance and area.

[0094] Specifically, an isolator 131 is provided between two adjacent semiconductor structures 180. The isolator 131 is located at the bottom of the trench 130 between the two adjacent semiconductor structures 180. A dielectric layer 150 is provided on the isolator 131, and the dielectric layer 150 separates the two semiconductor structures 180.

[0095] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for fabricating a transistor, characterized in that, Includes the following steps: Prepare a substrate, and form a composite on the substrate, the composite comprising alternating layers of a first superlattice layer and a second superlattice layer; A groove is formed on the composite, the groove dividing the composite into two parts, the two parts of the composite located on opposite sides of the groove; An insulator is deposited at the bottom of the trench; A sacrificial layer is deposited in the trench to form a channel, such that the sacrificial layer comprises two parts respectively distributed on both sides of the channel, and each part of the sacrificial layer is connected to the composite. A medium layer is deposited within the channel; Remove the first superlattice layer and the sacrificial layer; A gate dielectric layer and a metal gate are deposited on both sides of the dielectric layer, and the gate dielectric layer on each side of the dielectric layer surrounds the second superlattice layer, and the metal gate on each side of the dielectric layer surrounds the gate dielectric layer, wherein the metal gate on each side of the dielectric layer is located between the second superlattice layer and the dielectric layer.

2. The transistor fabrication method according to claim 1, characterized in that, When the composite is formed on the substrate, the side of the composite closest to the substrate is the first superlattice layer.

3. The transistor fabrication method according to any one of claims 1-2, characterized in that, Before removing the first superlattice layer and the sacrificial layer, the transistor fabrication method further includes: The portion of the sacrificial layer located between the bottom of the trench and the substrate is removed so that the medium layer deposited within the channel comes into contact with the insulator.

4. The transistor fabrication method according to any one of claims 1-3, characterized in that, The dielectric layer comprises a silicon compound Si containing at least one element selected from N, C, and O. k O x C y N z Where k is greater than 0, and at least one of x, y, and z is greater than 0; or, the dielectric layer comprises aluminum oxide Al. m O n , where m and n are greater than 0.

5. The transistor fabrication method according to any one of claims 1-4, characterized in that, The substrate is prepared from one of the following materials: silicon, germanium, silicon carbide, silicon germanium, and diamond.

6. The transistor fabrication method according to any one of claims 1-5, characterized in that, The materials used to prepare the second superlattice layer, the first superlattice layer, and / or the sacrificial layer include at least one of silicon, germanium, silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium carbon, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide.

7. The transistor fabrication method according to any one of claims 1-6, characterized in that, The sacrificial layer is made of the same material as the first superlattice layer.

8. The transistor fabrication method according to any one of claims 1-6, characterized in that, The material used to prepare the sacrificial layer is different from the material used to prepare the first superlattice layer; When removing the first superlattice layer and the sacrificial layer, the first superlattice layer and the sacrificial layer are removed simultaneously or in stages.

9. The transistor fabrication method according to any one of claims 1-7, characterized in that, The first superlattice layer and the second superlattice layer are made of different materials, and / or the sacrificial layer is made of different materials than the second superlattice layer.

10. The transistor fabrication method according to any one of claims 1-9, characterized in that, The gate dielectric layer includes an interface layer and a high dielectric constant layer, wherein the interface layer is located between the high dielectric constant layer and the second superlattice layer.

11. A transistor, characterized in that, It includes a substrate, multiple layers of second superlattice, a gate dielectric layer and a metal gate. The multiple layers of second superlattice are stacked on the substrate at intervals. The gate dielectric layer surrounds the second superlattice layer and the metal gate surrounds the gate dielectric layer.

12. The transistor according to claim 11, characterized in that, The substrate has two sets of the multilayer second superlattice layers, and a dielectric layer is provided between the two sets of the multilayer second superlattice layers.

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