VDMOS device, semiconductor power chip and manufacturing method of semiconductor power chip

Abstract

The application provides a VDMOS device, a semiconductor power chip and a manufacturing method of the semiconductor power chip, wherein the first gate region of the VDMOS device comprises integrally-formed planar electrode regions and trench electrode regions, the edges of the planar electrode regions are provided with first isolation side walls, the first light-doped regions are arranged below the first isolation side walls, and the first light-doped regions are in contact with the first source regions, thereby forming the VDMOS device with the planar electrode regions and the trench electrode regions in the gate region. In addition, the application also provides a semiconductor power chip integrating a control device and a power device.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a VDMOS device, a semiconductor power chip, and a method for manufacturing the semiconductor power chip. Background Technology

[0002] With the growth of semiconductor device technology, the demand for metal-oxide-semiconductor field-effect transistors (MOSFETs) is increasing. MOSFETs are the most widely used type of power device in power semiconductors. As switching devices, they connect the power supply and the load, and are characterized by easy driving, fast switching speed, integrability, and simple manufacturing process, making them widely applicable.

[0003] In the prior art, based on different device structures, MOSFETs can include laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOS) and vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS). Among them, LDMOS is mainly suitable for high-frequency and high-speed applications, while VDMOS is suitable for high-current and high-power applications. Moreover, LDMOS and VDMOS have different manufacturing processes and application ranges.

[0004] However, in some applications, it is necessary to use both LDMOS and VDMOS. To address this, this application provides a solution that integrates LDMOS and VDMOS onto the same chip. Summary of the Invention

[0005] This application provides a VDMOS device, a semiconductor power chip, and a method for manufacturing the semiconductor power chip, for integrating LDMOS and VDMOS.

[0006] In a first aspect, this application provides a VDMOS device, including an N+ substrate, an N-type epitaxial layer, a first P-type substrate region, a first gate region, a first drain region, and a first source region;

[0007] Wherein, the N-type epitaxial layer is located above the N+ substrate, the first drain region is located below the N+ substrate, the first P-type substrate region and the first gate region are both formed in the N-type epitaxial layer and the first P-type substrate region is located between the first gate regions, and the first source region is formed on the first P-type substrate region;

[0008] The first gate region includes an integrally formed planar electrode region and a trench electrode region. A first isolation sidewall is formed at the edge of the planar electrode region. A first lightly doped region is located below the first isolation sidewall. The first lightly doped region is in contact with and connected to the first source region.

[0009] Optionally, a first oxide layer is provided between the first gate region and the N-type epitaxial layer, wherein the first oxide layer below the planar electrode region is stepped, and the thickness of the first oxide layer near the trench electrode region is greater than the thickness of the first oxide layer near the first source region.

[0010] Optionally, the VDMOS device further includes a shielding gate located below the trench electrode region.

[0011] Optionally, the first P-type substrate region is formed by implanting P-type ions into the N-type epitaxial layer through the gap between the first gate regions, and the planar electrode region and the first P-type substrate region overlap in the vertical direction to form a planar channel, the length of which is controlled by the diffusion length of the first P-type substrate region.

[0012] Optionally, the VDMOS device further includes a P-type heavily doped region located between the first source regions.

[0013] Optionally, if the width of the trench electrode region is less than or equal to twice the thickness of the planar electrode region, then the lowest upper surface of the trench electrode region is higher than the upper surface of the N-type epitaxial layer; or,

[0014] If the width of the trench electrode region is greater than twice the thickness of the planar electrode region, then the lowest upper surface of the trench electrode region is lower than the upper surface of the N-type epitaxial layer.

[0015] A second aspect of this application provides a semiconductor power chip formed on an N-type epitaxial layer above an N+ substrate, wherein the semiconductor power chip integrates power devices and control devices;

[0016] The power device includes a first gate region, a first drain region, a first P-type substrate region, and a first source region. The first drain region is located below the N+ substrate. The first P-type substrate region and the first gate region are both formed in the N-type epitaxial layer, with the first P-type substrate region located between the first gate regions. The first source region is disposed above the first P-type substrate region and led out through a source contact region. The first gate region includes an integrally formed planar electrode region and a trench electrode region. A first isolation sidewall is formed at the edge of the planar electrode region. A first lightly doped region is located below the first isolation sidewall and is in contact with the first source region.

[0017] The control device includes a second gate region, a second drain region, a second source region, and a high-voltage P-type well region; the high-voltage P-type well region is formed in the N-type epitaxial layer, the second gate region is located above the high-voltage P-type well region, the second drain region and the second source region are both formed in the high-voltage P-type well region, a second isolation sidewall is formed at the edge of the second gate region, a second lightly doped region is provided below the second isolation sidewall, the second lightly doped region is in contact with the second source region, and the second drain region and the second source region are located on both sides of the second gate region in the vertical direction;

[0018] The second gate region and the first gate region are formed simultaneously, the first lightly doped region and the second lightly doped region are formed simultaneously, and the first isolation sidewall and the second isolation sidewall are formed simultaneously.

[0019] Optionally, the control device includes a complementary metal-oxide-semiconductor (CMOS), which includes an NMOS and a PMOS; wherein the NMOS is formed in the P-type well region of the high-voltage P-type well region, and the PMOS is formed in the N-type well region of the high-voltage P-type well region.

[0020] Optionally, a first oxide layer is provided between the first gate region and the N-type epitaxial layer, and a second oxide layer is provided between the gate region of the CMOS and the high-voltage P-type well region;

[0021] The first oxide layer below the planar electrode region is stepped, the thickness of the first oxide layer near the first source region is less than the thickness of the first oxide layer near the trench electrode region, and the thickness of the second oxide layer is less than the thickness of the first oxide layer near the trench electrode region.

[0022] Optionally, the control device includes a laterally diffused metal-oxide-semiconductor LDMOS, wherein the source region of the LDMOS is formed in the P-type substrate region of the high-voltage P-type well region, and the drain region of the LDMOS is formed in the high-voltage N-type well region of the high-voltage P-type well region.

[0023] Optionally, a first oxide layer is provided between the first gate region and the N-type epitaxial layer, and a second oxide layer is provided between the gate region of the LDMOS and the high-voltage P-type well region; wherein, the first oxide layer below the planar electrode region is stepped, and the thickness of the first oxide layer near the first source region is less than the thickness of the first oxide layer near the trench electrode region; the second oxide layer is stepped, and the thickness of the second oxide layer near the source region of the LDMOS is less than the thickness of the second oxide layer near the drain region of the LDMOS.

[0024] Thirdly, embodiments of this application provide a method for manufacturing a semiconductor power chip, comprising:

[0025] Provide N+ substrate;

[0026] An N-type epitaxial layer is formed on the N+ substrate, and a high-voltage P-type well region is formed on the N-type epitaxial layer;

[0027] A first gate region is formed on the N-type epitaxial layer, and a second gate region is formed on the high-voltage P-type well region. The first gate region includes an integrally formed planar electrode region and a trench electrode region. The second gate region, the planar electrode region, and the trench electrode region are formed simultaneously.

[0028] A first P-type substrate region and a first source region are formed between the first gate region, and a second drain region and a second source region are formed in the high-voltage P-type well region, with the second drain region and the second source region distributed on both sides of the second gate region;

[0029] A first drain region is formed beneath the N+ substrate.

[0030] Optionally, a first gate region is formed on the N-type epitaxial layer, and a second gate region is formed on the high-voltage P-type well region, including:

[0031] A first deep trench is dug in the N-type epitaxial layer;

[0032] A first insulating material and a first conductive material are formed within the first deep trench, on the N-type epitaxial layer, and on the high-voltage P-type well region;

[0033] The first conductive material and the first insulating material formed on the N-type epitaxial layer and the high-voltage P-type well region are etched in segments to form a trench electrode region in the first deep trench, a planar electrode region on the N-type epitaxial layer, and a second gate region on the high-voltage P-type well region.

[0034] Optionally, a first gate region is formed on the N-type epitaxial layer, and a second gate region is formed on the high-voltage P-type well region, including:

[0035] A first deep trench is dug in the N-type epitaxial layer;

[0036] A first insulating material is formed in the first deep trench, on the N-type epitaxial layer and on the high-voltage P-type well region, and the first insulating material located between the first deep trench and on the first insulating material on the high-voltage P-type well region is etched.

[0037] A second insulating material is formed in the first deep trench, on the N-type epitaxial layer and on the high-voltage P-type well region, so as to form a stepped first oxide layer on the N-type epitaxial layer, wherein the thickness of the first oxide layer away from the first deep trench is less than the thickness of the first oxide layer near the first deep trench.

[0038] A first conductive material is deposited on the first insulating layer;

[0039] The first conductive material is etched in segments to form a trench electrode region in the first deep trench, a planar electrode region in the N-type epitaxial layer, and a second gate region on the high-voltage P-type well region.

[0040] Optionally, a first gate region is formed on the N-type epitaxial layer, and a second gate region is formed on the high-voltage P-type well region, including:

[0041] A first deep trench is dug in the N-type epitaxial layer;

[0042] A first insulating material and a first conductive material are formed within the first deep trench, on the N-type epitaxial layer, and on the high-voltage P-type well region;

[0043] The first conductive material and the first insulating material are etched to form a shielding gate and a field oxide layer in the first deep trench, the field oxide layer being located below and on both sides of the shielding gate;

[0044] A second insulating material and a second conductive material are formed above the shielding grid, the N-type epitaxial layer, and the high-voltage P-type well region within the first deep trench;

[0045] The second conductive material is etched to form a trench electrode region in the first deep trench, a planar electrode region on the N-type epitaxial layer, and a second gate region on the high-voltage P-type well region.

[0046] Optionally, a first P-type substrate region and a first source region are formed between the first gate regions, and a second drain region and a second source region are formed in the high-voltage P-type well region, including:

[0047] P-type ions are implanted into the N-type epitaxial layer through the gap between the first gate regions to form the first P-type substrate region between the first gate regions. The overlap region between the first P-type substrate region and the planar electrode region in the vertical direction forms a planar channel. The length of the channel is controlled by the diffusion length of the first P-type substrate region.

[0048] A first lightly doped region and a second lightly doped region are formed, as well as a first isolation sidewall and a second isolation sidewall. The first isolation sidewall is located above the first lightly doped region and is in contact with the edge of the first gate region. The second isolation sidewall is located above the second lightly doped region and is in contact with the edge of the second gate region.

[0049] A first source region is formed on the first P-type substrate region, and a second source region and a second drain region are formed on the high-voltage P-type well region and on both sides of the second gate region.

[0050] This application provides a VDMOS device, a semiconductor power chip, and a method for manufacturing the semiconductor power chip. The VDMOS device includes an integrally formed planar electrode region and a trench electrode region. A first isolation sidewall is formed at the edge of the planar electrode region, and a first lightly doped region is located below the first isolation sidewall. The first lightly doped region is in contact with and connected to a first source region, thus forming a VDMOS device that simultaneously has a planar electrode region and a trench electrode region. Furthermore, this application also provides a semiconductor power chip that integrates a control device and a power device, and the gate manufacturing process, lightly doped ion implantation process, sidewall process, and source manufacturing process of the control device and the power device are compatible. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0052] Figure 1a This is a schematic diagram of the structure of the VDMOS device provided in the first embodiment of this application;

[0053] Figure 1b and Figure 1c These are schematic diagrams of two different shapes of the first gate region;

[0054] Figure 2 This is a schematic diagram of the structure of the VDMOS device provided in the second embodiment of this application;

[0055] Figure 3 This is a schematic diagram of the structure of the VDMOS device provided in the third embodiment of this application;

[0056] Figure 4This is a schematic diagram of the structure of the semiconductor power chip provided in the first embodiment of this application;

[0057] Figure 5 This is a schematic diagram of the structure of the semiconductor power chip provided in the second embodiment of this application;

[0058] Figure 6 This is a schematic diagram of the structure of the semiconductor power chip provided in the third embodiment of this application;

[0059] Figure 7 This is a schematic flowchart of a method for manufacturing a semiconductor power chip according to an embodiment of this application;

[0060] Figures 8a to 8m This is a schematic diagram of the process technology of the semiconductor power chip provided in the embodiments of this application.

[0061] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0063] The terms "comprising" and "having," and any variations thereof, appearing in this application specification, claims, and drawings, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0064] Furthermore, the terms "first," "second," and "third," etc., are used to distinguish different objects, not to describe a specific order. The electrical connections in this application include direct electrical connections and indirect electrical connections. Indirect electrical connections refer to connections where other electronic components, pins, etc., may exist between the two connected components. The "XX terminal" mentioned in this application may or may not be an actual terminal; for example, it may simply be one end of a component or one end of a wire. The "and / or" mentioned in this application includes three cases; for example, A and / or B includes A, B, and A and B.

[0065] In electronic power systems, metal-oxide-semiconductor field-effect transistors (MOSFETs) are a widely used class of power devices, typically including vertical MOSFETs (VDMOS) and lateral MOSFETs (LDMOS). LDMOS has a simple fabrication process and is widely used in high-frequency, low-power applications. VDMOS, on the other hand, is suitable for high-current, high-power applications. However, in some applications, LDMOS and VDMOS may not be sufficient to meet the requirements of high-frequency power switching applications on their own, necessitating the combined use of both.

[0066] To address this, this application provides a VDMOS device and a power semiconductor chip for integrating LDMOS and VDMOS. The VDMOS device includes a first P-type substrate region, a first gate region, a first drain region, and a first source region. The first gate region includes an integrally formed planar electrode region and a trench electrode region. A first isolation sidewall is formed at the edge of the planar electrode region. Below the first isolation sidewall is a first lightly doped region, which is in contact with the first source region. This forms a VDMOS device where the gate region simultaneously has both a planar electrode region and a trench electrode region, laying the foundation for subsequent integration of LDMOS and VDMOS.

[0067] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0068] For example, Figure 1a This is a schematic diagram of the VDMOS device provided in the first embodiment of this application. The VDMOS device can be an N-type MOS, a P-type MOS, etc., and an N-type MOS is used as an example in the illustration. Figure 1a As shown, in this embodiment, the VDMOS device includes an N+ substrate 10, an N-type epitaxial layer 20, a first P-type substrate region 31, a first gate region 32, a first drain region 33, and a first source region 34.

[0069] The N-type epitaxial layer 20 is located above the N+ substrate 10, the first drain region 33 is located below the N+ substrate 10, the first P-type substrate region 31 and the first gate region 32 are both formed in the N-type epitaxial layer 20, and the first P-type substrate region 31 is located between the first gate regions 32. The first source region 34 is formed on the first P-type substrate region 31.

[0070] Continue to refer to Figure 1a As shown, the first gate region 32 includes an integrally formed planar electrode region 321 and a trench electrode region 322. A first isolation sidewall 35 is formed at the edge of the planar electrode region 321. A first lightly doped region 36 is located below the first isolation sidewall 35. The first lightly doped region 36 is in contact with the first source region 34.

[0071] In this embodiment, when manufacturing a VDMOS device, a planar electrode region 321 and a trench electrode region 322 can be formed simultaneously. For example, the VDMOS device can be manufactured according to the following steps: First, an N+ substrate 10 is provided, and an N-type epitaxial layer 20 is formed on the N+ substrate 10. Then, a first gate region 32 and a first P-type substrate region 31 are sequentially formed on the N-type epitaxial layer 20. The first P-type substrate region 31 is located between the first gate regions 32. The first gate region 32 includes an integrally formed planar electrode region 321 and a trench electrode region 322. Next, a first lightly doped region 36 is formed in the first P-type substrate region 31. A first isolation sidewall 35 is formed above the first lightly doped region 36, and the first isolation sidewall 35 contacts the planar electrode region 321. Then, a first source region 34 is formed in the first P-type substrate region 31, and the first source region 34 contacts the first lightly doped region 36. Finally, a first drain region 33 is formed below the N+ substrate 10.

[0072] Understandably, to generate an integrally formed planar electrode region 321 and trench electrode region 322, when forming the first gate region 321 and the first P-type substrate region 31 on the N-type epitaxial layer 20, first deep trenches are first dug on the N-type epitaxial layer 20. Multiple first deep trenches are then formed. Subsequently, a first insulating material is formed on the inner surface of all the first deep trenches and the upper surface of the N-type epitaxial layer 20. This first insulating material does not completely fill the first deep trenches. Then, a first conductive material is filled on the first insulating material. Understandably, the first conductive material can fill the first deep trenches. A deep trench may or may not be completely filled. Finally, the first conductive material and the first insulating material on the N-type epitaxial layer 20 are etched in segments. Specifically, a portion of the first conductive material and a portion of the first insulating material located between the first deep trenches on the N-type epitaxial layer 20 are etched away to complete the etching of the first gate region 32. This results in multiple independent first gate regions 32, each including an integrally formed planar electrode region 321 and a trench electrode region 322, with a pre-defined gap between adjacent first gate regions 32. (Refer to...) Figure 1a As shown.

[0073] Optional, Figure 1b and Figure 1cThese are schematic diagrams of two different shapes of the first gate region. In embodiments of this application, when the width d of the trench electrode region 322 is less than or equal to twice the thickness d0 of the planar electrode region (d≦2d0), the lowest upper surface of the trench electrode region 322 is higher than the upper surface of the N-type epitaxial layer 20. For example, as... Figure 1b As shown, when the width of the first deep trench is less than or equal to twice the thickness of the first conductive material deposited on the N-type epitaxial layer 20, the first conductive material filling the first deep trench overflows from the first deep trench, thus in the formed first gate region, the lowest upper surface of the trench electrode region 322 ( Figure 1b The dashed line x1 in the diagram indicates that the trench electrode region 322 is higher than the upper surface of the N-type epitaxial layer 20, which can also be interpreted as the lowest upper surface of the trench electrode region 322 being higher than the lower surface of the planar electrode region 321. In other embodiments of this application, when the width of the trench electrode region is greater than twice the thickness of the planar electrode region, the lowest upper surface of the trench electrode region 322 is lower than the upper surface of the N-type epitaxial layer 20. For example, as shown... Figure 1c As shown, when the width of the first deep trench is greater than twice the thickness of the first conductive material deposited on the N-type epitaxial layer, the first conductive material filling the first deep trench does not completely fill the first deep trench. Therefore, in the formed first gate region 32, the lowest upper surface of the trench electrode region 322 ( Figure 1c The dashed line x2 in the figure is lower than the upper surface of the N-type epitaxial layer 20, which can also be interpreted as the lowest upper surface of the trench electrode region 322 being lower than the lower surface of the planar electrode region 321.

[0074] Continue to refer to Figure 1a As shown, in this embodiment, the first P-type substrate region 31 is formed in the N-type epitaxial layer 20 between the first gate regions 32. For example, the first P-type substrate region 31 is formed by implantation through the gap between the first gate regions 32 after the pattern of the first gate regions 32 is etched. Specifically, the first P-type substrate region 31 is formed by implanting P-type ions into the N-type epitaxial layer 20 through the gap between the first gate regions 32. The planar electrode region 321 and the first P-type substrate region 31 overlap in the vertical direction to form a planar channel. The length of the planar channel is controlled by the diffusion length of the first P-type substrate region 31, that is, the planar channel is formed by a self-aligned scheme.

[0075] In this embodiment, before forming the first source region 34, a first lightly doped region 36 can be formed in the first P-type substrate region 31, and a first isolation sidewall 35 can be formed at the edge of the planar electrode region 321 and above the first lightly doped region 36.

[0076] For example, after forming the first P-type substrate region 31, a lightly doped ion implantation process is performed from top to bottom along the edge of the planar electrode region 321 to form a first lightly doped region 36 of a certain width. Then, a first isolation sidewall 35 is formed at the edge of the planar electrode region 321 using sidewall technology. In this scheme, the first lightly doped region 36 is located directly below the first isolation sidewall 35.

[0077] For example, continue to refer to Figure 1a As shown, the VDMOS device also includes a P-type heavily doped region located between the first source regions 34.

[0078] Optionally, in this embodiment, after the first isolation sidewall 35 is formed, N-type ions can be injected into the first P-type substrate region 31 through the gap between the first isolation sidewalls 35 to form the first source region 34, and P-type ions can be injected between the first sources to form a heavily doped P-type region. The heavily doped P-type region is used to bring out the first P-type substrate region 31.

[0079] In one possible design of this application, the first source region 34 and the first P-type substrate region 31 are alternately arranged in the direction of the first deep trench (i.e., parallel to the plane of the paper), as shown in the reference. Figure 1a As shown.

[0080] In another possible design of this application, the first source region 34 and the heavily doped P-type region are arranged alternately in a direction that is perpendicular to both the horizontal and depth directions of the N-type epitaxial layer 20 (i.e., perpendicular to the plane of the paper).

[0081] In one possible design of this application, reference is made to Figure 1a As shown, a first oxide layer 320 is provided between the first gate region 32 and the N-type epitaxial layer 20. Similar to the first gate region 32 including a planar electrode region and a trench electrode region, the first oxide layer 320 also includes a planar portion and a vertical portion. The planar portion of the first oxide layer 320 is located between the planar electrode region 321 of the first gate region 32 and the N-type epitaxial layer 20, and the vertical portion of the first oxide layer 320 is located between the trench electrode region 322 of the first gate region 32 and the N-type epitaxial layer 20.

[0082] Optionally, in embodiments of this application, the first gate region 32 may be the control gate portion of a trench-type power device, and the first oxide layer 320 may also be interpreted as a gate oxide layer. Optionally, the first oxide layer 320 may also be integrally formed, that is, the planar portion and the vertical portion of the first oxide layer 320 are formed simultaneously to achieve isolation between the first gate region 32 and the N-type epitaxial layer 20. Optionally, the planar portion and the vertical portion of the first oxide layer 320 have the same thickness.

[0083] In the VDMOS device provided in the embodiments of this application, the first gate region includes an integrally formed planar electrode region and a trench electrode region. A first isolation sidewall is formed at the edge of the planar electrode region, and a first lightly doped region is provided below the first isolation sidewall. The first lightly doped region is in contact with and connected to the first source region.

[0084] Reference Figure 1a As shown, if the thickness of the first oxide layer below the planar electrode region 321 is uniform, the oxide layer between the channel and the first gate region is thicker. Although this ensures the withstand voltage characteristics between the gate and drain, it results in a higher turn-on voltage for the generated VDMOS device, limiting the application of the VDMOS device. Therefore, based on the first embodiment, this application provides a second embodiment.

[0085] For example, Figure 2 This is a schematic diagram of the VDMOS device provided in the second embodiment of this application. Figure 2 As shown, a first oxide layer 320 is present between the first gate region 31 and the N-type epitaxial layer 10. The first oxide layer below the planar electrode region 321 is stepped, and the thickness of the first oxide layer near the trench electrode region 322 is greater than the thickness of the first oxide layer near the first source region 34.

[0086] For example, the planar portion 32a of the first oxide layer 320 is located between the planar electrode region 321 of the first gate region 32 and the N-type epitaxial layer 20, and the vertical portion of the first oxide layer 320 is located between the trench electrode region 322 of the first gate region 32 and the N-type epitaxial layer 20. The planar portion 32a of the first oxide layer 320 includes a first thickness oxide layer and a second thickness oxide layer, with the first thickness oxide layer closer to the trench electrode region 322 and the second thickness oxide layer farther from the trench electrode region 322. In this case, the thickness of the first thickness oxide layer is greater than the thickness of the second thickness oxide layer. Optionally, the width of the vertical portion of the first oxide layer 320 is substantially equal to the thickness of the first thickness oxide layer.

[0087] In this embodiment, the method for generating the first gate region 32 is as follows: First, a first deep trench is dug on the N-type epitaxial layer 20, and the number of first deep trenches is multiple. Then, a first insulating material is formed on the inner surface of all the first deep trenches and the upper surface of the N-type epitaxial layer 20. The first insulating material does not completely fill the first deep trenches. Then, a portion of the first insulating material located between the first deep trenches is etched away, leaving a portion of the first insulating material on the upper surface of the N-type epitaxial layer 20 and near the first deep trenches, as well as the first insulating material on the sidewalls of the first deep trenches. Then, a second insulating material is grown on the first deep trenches and the N-type epitaxial layer to form a second insulating material on the N-type epitaxial layer 20. A stepped first oxide layer is formed, comprising a first thickness oxide layer near the first deep trench and a second thickness oxide layer away from the first deep trench, the second thickness oxide layer being less than the thickness of the first thickness oxide layer; then a first conductive material is deposited on the first insulating layer, and finally a portion of the first conductive material between the first deep trenches is etched to form a first gate region 32, the first gate region comprising a trench electrode region 322 formed in the first deep trench and a planar electrode region 321 formed on the N-type epitaxial layer 20, such that there is a gap between the planar electrode regions 321 exposing the N-type epitaxial layer 20.

[0088] In this embodiment, the generation scheme for the first P-type substrate region, the first source region, and other regions is the same as... Figure 1a The embodiments shown are consistent with those described above; for details, please refer to the above. Figure 1a The descriptions in the illustrated embodiments will not be repeated here.

[0089] In this embodiment, by forming a stepped first oxide layer between the planar electrode region of the first gate region and the N-type epitaxial layer, and by making the thickness of the first oxide layer away from the trench electrode region thinner than that of the first oxide layer near the trench electrode region, the turn-on voltage of the VDMOS device generated in this embodiment is reduced while ensuring the gate-drain withstand voltage, making the VDMOS device easier to turn on and solving the problem of limited application of VDMOS device.

[0090] In practical applications, to achieve a higher breakdown voltage while reducing the drift region resistance, the VDMOS device provided in this application embodiment may further include a shield-gate (SGT) below the trench electrode region. Since the shield-gate is composed of polysilicon filled in the first deep trench, and the polysilicon constituting the shield-gate is typically connected to the source, it can eliminate the charge in the device's drift region, thereby establishing a charge balance structure and reducing the electric field in the drift region. This reduces or eliminates the limitation on the impurity concentration in the drift region and lowers the drift region resistance, resulting in a VDMOS device with a shield-gate structure exhibiting lower on-resistance and higher breakdown voltage.

[0091] For example, Figure 3This is a schematic diagram of the VDMOS device provided in the third embodiment of this application. Figure 3 As shown, in this embodiment, the VDMOS device further includes a shielding gate 323, which is located below the trench electrode region 322 of the first gate region 32. Optionally, a spacer oxide layer is provided between the trench electrode region 322 of the first gate region 32 and the shielding gate 323 to achieve isolation between the trench electrode region 322 and the shielding gate 323. Moreover, field oxide layers are provided on both sides of the shielding gate 323, and the field oxide layer and the spacer oxide layer enclose the shielding gate 323.

[0092] In this embodiment, the thickness of the first oxide layer 320 is less than the thickness of the field oxide layer.

[0093] Optionally, the method for generating the first gate region 32 is as follows: First, a first deep trench is dug on the N-type epitaxial layer 20, and the number of first deep trenches is multiple. Then, the inner surface of all the first deep trenches and the upper surface of the N-type epitaxial layer 20 are oxidized and / or deposited to form a first insulating material. The first insulating material does not fill the first deep trenches. Next, a first conductive material is deposited on the upper surface of the first insulating layer. The first conductive material is, for example, N-type polysilicon. Then, the first conductive material is etched. The first conductive material located outside the first deep trenches is completely etched away, and part of the first conductive material in the first deep trenches is also etched away to form a shielding gate 323. Then, the first insulating material is etched. The unetched portion of the first insulating material inside the first deep trenches forms a field oxide layer. A second insulating material is formed by oxidation or deposition on the inner surface of the first deep trench, the upper surface of the shielding gate 323, and the N-type epitaxial layer 20. The thickness of the second insulating material is less than that of the first insulating material. Subsequently, a second conductive material is deposited on the upper surface of the second insulating material, so that the second conductive material fills and overflows the first deep trench. The second conductive material is, for example, N-type polysilicon. Finally, a portion of the second conductive material and a portion of the second insulating material between the first deep trenches are etched to form a first oxide layer 320 on the sidewall of the first deep trench and the N-type epitaxial layer 20. A trench electrode region 322 of the first gate region 32 is formed in the first deep trench. A planar electrode region 321 of the first gate region 32 is formed above the first oxide layer on the N-type epitaxial layer 20.

[0094] In this embodiment, the generation scheme of the first P-type substrate region 31, the first source region 34, etc., is different from that of the previous embodiment. Figure 1a The embodiments shown are consistent with those described above, and will not be repeated here.

[0095] In this embodiment, a shielding gate is first formed in the first deep trench, and then a second insulating material is deposited or oxidized to form a second conductive material to form a first oxide layer and a first gate region. In this way, the thickness of the first oxide layer below the planar electrode region is usually thin, which can reduce the turn-on voltage of the VDMOS device while ensuring that the VDMOS device has a low on-resistance and a high breakdown voltage.

[0096] Optionally, in some application scenarios, both power devices and control devices are required. Therefore, in order to improve the overall performance of the circuit, the power devices and control devices can be integrated onto the same chip. For example, this application provides a semiconductor power chip that includes both power devices and control devices. The structure and manufacturing process of the semiconductor power chip will be explained and described below through specific embodiments.

[0097] For example, Figure 4 This is a schematic diagram of the semiconductor power chip provided in the first embodiment of this application. Figure 4 As shown, in this embodiment, the semiconductor power chip is formed on an N-type epitaxial layer 20 above an N+ substrate 10, and the semiconductor power chip integrates power devices and control devices.

[0098] Optionally, the power device includes a first gate region 32, a first drain region 33, a first P-type substrate region 31, and a first source region 34. The first drain region 33 is located below the N+ substrate 10. The first P-type substrate region 31 and the first gate region 32 are both formed in the N-type epitaxial layer 20, with the first P-type substrate region 31 located between the first gate regions 32. The first source region 34 is disposed above the first P-type substrate region 31. The first gate region 32 includes an integrally formed planar electrode region 321 and a trench electrode region 322. A first isolation sidewall 35 is formed at the edge of the planar electrode region 321. Below the first isolation sidewall 35, there is a first lightly doped region 36, which is in contact with the first source region 34.

[0099] Continue to refer to Figure 4As shown, the control device includes a second gate region 42, a second drain region 42, a second source region 43, and a high-voltage P-type well region 40. The high-voltage P-type well region 40 is formed in the N-type epitaxial layer 20. The second gate region is located above the high-voltage P-type well region 40. The second drain region 42 and the second source region 43 are both formed in the high-voltage P-type well region 40. A second isolation sidewall 45 is formed at the edge of the second gate region. A second lightly doped region 46 is located below the second isolation sidewall 45. The second lightly doped region 46 is in contact with the second source region 43, and the second drain region 42 and the second source region 43 are located on opposite sides of the second gate region in the vertical direction. The second gate region and the first gate region 32 are formed in the same process, the first lightly doped region 36 and the second lightly doped region 46 are formed simultaneously, and the first isolation sidewall 35 and the second isolation sidewall 45 are formed simultaneously.

[0100] It is understood that the power devices are N-type VDMOS devices, and the control devices include CMOS and / or laterally diffused metal-oxide-semiconductor (LDMOS). CMOS includes NMOS and PMOS. Optionally, Figure 4 The control devices mentioned here include CMOS and LDMOS. In practical applications, the required type of control device can be generated according to actual needs, which will not be elaborated here.

[0101] Optionally, in this embodiment, the doping concentration of the N+ substrate 10 is greater than the doping concentration of the N-type epitaxial layer 20. The N-type epitaxial layer 20 can be divided into a power device formation region and a control device formation region. That is, the power device formation region is used to form an N-type VDMOS device (power device), and the control device formation region is used to form at least one of CMOS and LDMOS.

[0102] In this embodiment, since the power device and the control device are formed on the same N-type epitaxial layer 20, in order to avoid mutual interference between the power device and the control device, for example, refer to... Figure 4 As shown, a high-voltage P-type well region 40 can be first formed on the N-type epitaxial layer 20 in the region where the control device is formed, and then a power device can be formed in the N-type epitaxial layer 20, while the control device is formed on the high-voltage P-type well region 40. It can be understood that when the control device includes both CMOS and LDMOS, the CMOS and LDMOS are located in different high-voltage P-type well regions 40 on the N-type epitaxial layer 20.

[0103] Optionally, the process steps for forming the first deep trench and the high-voltage P-type well region 40 on the N-type epitaxial layer 20 may differ and can be determined according to actual needs. As one example, firstly, a first deep trench is dug in the power device formation region, then a high-voltage P-type well region 40 is formed in the control device formation region using a high-voltage process. Subsequently, a trench electrode region 322 is formed in the first deep trench, a planar electrode region 321 is formed on the N-type epitaxial layer 20, and a second gate region is formed in the high-voltage P-type well region 40. As another example, firstly, a high-voltage P-type well region 40 is formed in the control device formation region using a high-voltage process, then a first deep trench is dug in the power device formation region. Finally, a trench electrode region 322 is formed in the first deep trench, a planar electrode region 321 is formed on the N-type epitaxial layer 20, and a second gate region is formed in the high-voltage P-type well region 40. It is understood that at least some steps in the process of forming the trench electrode region 322, the planar electrode region 321, and the second gate region are compatible with each other.

[0104] Optional, refer to Figure 4 As shown, if the control device includes both CMOS and LDMOS, the gate regions of CMOS (NMOS and PMOS) and LDMOS (collectively referred to as the second gate region) are generated simultaneously with the first gate region 32. The NMOS and PMOS are located in a high-voltage P-type well region 40 on the N-type epitaxial layer 20, and the LDMOS is located in another high-voltage P-type well region 40 on the N-type epitaxial layer 20.

[0105] Optionally, before forming the first source region 34 and the second source region 43, lightly doped ions are first implanted from top to bottom along the edge of the planar electrode region 321 and the edge of the second gate region to form a first lightly doped region 36 in the region below the planar electrode region 321 and a second lightly doped region 46 in the region below the second gate region. Then, a first isolation sidewall 35 is formed at the edge of the planar electrode region 321 and a second isolation sidewall 45 is formed at the edge of the second gate region using sidewall technology.

[0106] It is understood that when the control device and the power device are of the same type, for example, both are N-type MOS, the second source region 43 and the first source region 34 can be formed simultaneously. That is, after forming the first gate region 32 and the second gate region, the first source region 34 can be formed in the power device formation region and the second source region 43 can be formed in the control device formation region through the same process. In this embodiment, the gate manufacturing process, lightly doped ion implantation process, sidewall process, and source manufacturing process of the control device and the power device can be compatible.

[0107] Continue to refer to Figure 4As shown, in this embodiment, the control device includes CMOS and LDMOS. At this time, the drain and source regions of NMOS, PMOS, and LDMOS are generated simultaneously with the first source region 34. The drain and source regions of NMOS are symmetrically distributed on both sides of the gate region of NMOS in the vertical direction, and the drain and source regions of PMOS are symmetrically distributed on both sides of the gate region of PMOS in the vertical direction.

[0108] For example, such as Figure 4 As shown, in this embodiment, the CMOS includes NMOS and PMOS. To reduce mutual interference between NMOS and PMOS, the NMOS can be formed in the P-type well region of the high-voltage P-type well region 40, and the PMOS can be formed in the N-type well region of the high-voltage P-type well region 40. That is, the NMOS and PMOS are formed in different well regions, avoiding potential mutual interference problems and improving the performance of the CMOS.

[0109] As an example, when power devices and CMOS (NMOS and PMOS) need to be simultaneously formed on the N-type epitaxial layer 20, a P-type well region and an N-type well region are first formed within the high-voltage P-type well region 40. Then, multiple first deep trenches are dug in the power device formation region, and a first gate region 32 of the power device is formed within the first deep trenches and on the N-type epitaxial layer. An NMOS gate region 411 is formed on the P-type well region, and a PMOS gate region 412 is formed on the N-type well region. Subsequently, a first P-type substrate region 31 is formed between the first gate regions 32. Then, a first lightly doped region 36, a first isolation sidewall 35, and an NMOS gate are formed in the power device formation region. A second lightly doped region 46 and a second isolation sidewall 45 are formed on both sides of region 411 and on both sides of gate region 412 of PMOS, respectively. Then, a first source region (n+) 34 is formed on the first P-type substrate region 31, a source region (n+) 431 and a drain region (n+) 421 of NMOS are formed on the P-type well region, and a well contact region (n+) of PMOS is formed on the N-type well region. Finally, a substrate contact region (p+) of the first P-type substrate region is formed between the first source regions (n+) 34, a well contact region (p+) of NMOS is formed on the P-type well region, and a source region (p+) 432 and a drain region (p+) 422 of PMOS are formed on the N-type well region.

[0110] Understandable, refer to Figure 4As shown, when power devices and LDMOS need to be simultaneously formed on the N-type epitaxial layer 20, a high-voltage N-type well region (HVNW) is first formed within the high-voltage P-type well region 40. The depth of the high-voltage N-type well region is less than the depth of the high-voltage P-type well region 40. Then, multiple first deep trenches are dug in the power device formation area, and the first gate region 32 of the power device is formed in the first deep trenches and on the N-type epitaxial layer. The gate region 413 of the LDMOS is formed on the high-voltage P-type well region 40. The gate region 413 of the LDMOS overlaps with the high-voltage N-type well region in the vertical direction. Then, a first P-type substrate region 31 is formed between the first gate regions. A second P-type substrate region is formed on the side of the LDMOS gate region away from the high-voltage N-type well region. Subsequently, the first P-type substrate region is formed. A first lightly doped region 36 is formed on the body region 31, a first isolation sidewall 35 is formed above the first lightly doped region 36, and a second lightly doped region 46 is formed within the second P-type substrate region 44 of the LDMOS, with a second isolation sidewall 45 formed above the second lightly doped region 46. Subsequently, a first source region (n+) 34 is formed on the first P-type substrate region 34, a source region 433 of the LDMOS is formed on the second P-type substrate region 44, and a drain region 423 of the LDMOS is formed on the high-voltage N-type well region. Finally, a substrate contact region (p+) of the first P-type substrate region is formed between the first source regions (n+) 34, and a substrate contact region (p+) of the second P-type substrate region 44 is formed between the source regions (n+) 433 of the LDMOS. The source region 433 of the LDMOS is in contact with the second lightly doped region 46, while the drain region 423 of the LDMOS is not in contact with the gate region 413 of the LDMOS in the vertical direction.

[0111] It is understandable that the implementation principle of simultaneously generating power devices, CMOS, and LDMOS on the N-type epitaxial layer 20 is similar, and will not be elaborated here.

[0112] For example, in one possible design of this application, a first oxide layer 320 is provided between the first gate region 32 and the N-type epitaxial layer 20, and a second oxide layer is provided between the second gate region and the high-voltage P-type well region. Optionally, the first oxide layer and the second oxide layer are formed simultaneously, and the thickness of the first oxide layer and the thickness of the second oxide layer are the same.

[0113] Reference Figure 4 As shown, the thickness of the oxide layer in the second gate region of control devices such as NMOS, PMOS, and LDMOS is basically the same as the thickness of the first oxide layer in the planar electrode region 321 of the power device. This process is simple and easy to implement.

[0114] For example, in order to reduce the turn-on voltage of the devices on the semiconductor power chip provided in this application and expand the application scope, in Figure 4 Based on the embodiments shown, this application provides second and third embodiments.

[0115] Optional, Figure 5 This is a schematic diagram of the semiconductor power chip provided in the second embodiment of this application. Figure 5 As shown, in this embodiment, a first oxide layer 320 is provided between the first gate region 32 and the N-type epitaxial layer 20, and a second oxide layer is provided between the second gate region and the high-voltage P-type well region; wherein, the first oxide layer below the planar electrode region 321 is stepped, and the thickness of the first oxide layer near the first source region 34 is less than the thickness of the first oxide layer near the trench electrode region 322.

[0116] Optionally, when the controller includes CMOS, the thickness of the second oxide layer is less than the thickness of the first oxide layer near the trench electrode region. For example, the thickness of the second oxide layer is equal to the thickness of the first oxide layer near the first source region.

[0117] Optionally, when the control device includes an LDMOS, the second oxide layer is stepped, and the thickness of the second oxide layer near the second source region is less than the thickness of the second oxide layer near the second drain region. For example, the thickness of the second oxide layer near the second source region is equal to the thickness of the first oxide layer near the first source region, and the thickness of the second oxide layer near the second drain region is equal to the thickness of the first oxide layer near the trench electrode region.

[0118] Optionally, in embodiments of this application, when forming the gate region of a semiconductor power chip on the N-type epitaxial layer 20, after oxidizing or depositing on the inner surface of the first deep trench, the N-type epitaxial layer 20, and the high-voltage P-type well region 40 to form a first insulating material, before forming the first conductive material, the portion of the first insulating material on the N-type epitaxial layer 20 away from the first deep trench, the first insulating material on the high-voltage P-type well region 40 used for forming CMOS, and the portion of the first insulating material on the high-voltage P-type well region 40 used for forming LDMOS are first etched away. Then, the inner surface of the first deep trench, the N-type epitaxial layer 20, and the high-voltage P-type well region 40 are oxidized or deposited to form a second insulating material, so as to form a stepped first oxide layer 320 on the N-type epitaxial layer 20 (for example, the thickness of the first oxide layer away from the first deep trench is smaller than the thickness of the first oxide layer near the first deep trench), and a second oxide layer is formed on the high-voltage P-type well region 40 used for forming CMOS. A stepped second oxide layer is formed on the P-type well region 40 (for example, the thickness of the second oxide layer away from the high-voltage N-well is less than the thickness of the second oxide layer near the high-voltage N-well); then a first conductive material is deposited, which may fill and overflow the first deep trench, or may not fill the first deep trench. Finally, the first conductive material is etched in segments to form a trench electrode region 322 in the first deep trench, a planar electrode region 321 in the N-type epitaxial layer 20, and a second gate region on the high-voltage P-type well region 40 (specifically, a CMOS gate region is formed on the high-voltage P-type well region 40 for generating CMOS, and an LDMOS gate region is formed on the high-voltage P-type well region 40 for generating LDMOS). In the gate region formed in this way, the first oxide layer below the planar electrode region and the second oxide layer below the LDMOS gate region are both stepped, which reduces the turn-on voltage of the device while ensuring the voltage withstand capability of the VDMOS device and the LDMOS device.

[0119] It is understood that in this embodiment, after the gate region is formed, a gap is formed between the planar electrode regions 321 and a gap is formed between the second gate regions. The gap between the planar electrode regions 321 allows the first P-type substrate region 31 and the first source region 34 to be formed sequentially between the planar electrode regions 321. The gap between the second gate regions allows the second source region 43 and the second drain region 42 to be formed on the high-voltage P-type well region 40.

[0120] In this embodiment, the thickness of the first oxide layer below the planar electrode region and the thickness of the second oxide layer below the second gate region can be adjusted based on the application scenario of the semiconductor power chip, adapting to the application scenario of the semiconductor power chip and improving device performance.

[0121] Optional, Figure 6 This is a schematic diagram of the structure of the semiconductor power chip provided in the third embodiment of this application. Figure 6 As shown, in this embodiment, the embodiments of this application are similar to... Figure 4 The difference in the illustrated embodiment is that a shielding gate is also included below the trench electrode region of the first gate region. In this case, the thickness of the second oxide layer below the planar electrode region is the same as the thickness of the second oxide layer below the second gate region.

[0122] In this embodiment, the control devices include NMOS, PMOS, and LDMOS for explanation and illustration. It is understood that the implementation schemes are similar when the control devices include one or two of NMOS, PMOS, and LDMOS, and this embodiment is not limited thereto. For solutions not detailed in this embodiment, please refer to the above. Figures 1a to 4 The descriptions in the illustrated embodiments will not be repeated here.

[0123] Optionally, in this embodiment, when forming the gate region of the semiconductor power chip on the N-type epitaxial layer 20, after forming the first insulating material and depositing the first conductive material on the inner surface of the first deep trench, the N-type epitaxial layer 20, and the high-voltage P-type well region 40, during the etching of the first conductive material and the first insulating material, the first conductive material and the first insulating material located outside the first deep trench (on the N-type epitaxial layer 20 and the high-voltage P-type well region 40) are completely etched away, and a portion of the first conductive material in the first deep trench is also etched away to form the shielding gate 323. The first insulating material on the sidewall of the first deep trench is isotropically etched until the first insulating material on the sidewall of the first deep trench is higher than the shielding gate. The first insulating material of the gate 323 is completely etched away, so that the first insulating material located inside the first deep trench forms a field oxide layer; then, after oxidation to form a second insulating material and deposit a second conductive material on the inner surface of the first deep trench, the upper surface of the shielding gate 323, the N-type epitaxial layer 20, and the high-voltage P-type well region 40, a portion of the second conductive material and a portion of the second insulating material between the first deep trenches are etched, so that a first oxide layer can be formed on the sidewall of the first deep trench and the N-type epitaxial layer 20, a first gate region is formed in the first deep trench and above the first oxide layer, a second oxide layer is formed on the high-voltage P-type well region 40, and a second gate region is formed on the second oxide layer.

[0124] In this embodiment, since the first oxide layer and the second oxide layer are formed by directly etching segments of the insulating material formed in the same step, the thickness of the second oxide layer (including the oxide layer of the gate region in CMOS and the oxide layer of the gate region in LDMOS) is basically the same as the thickness of the first oxide layer, and is usually thinner. This results in both the planar electrode region and the second gate region having thinner insulating layers, reducing the turn-on voltage of the device on the semiconductor power chip.

[0125] Optionally, embodiments of this application also provide a method for manufacturing a semiconductor power chip, the method being used to generate... Figures 4 to 6The semiconductor power chip shown is an example. Figure 7 This is a schematic flowchart of a method for manufacturing a semiconductor power chip according to an embodiment of this application. Figures 8a to 8m This is a schematic diagram of the process technology of the semiconductor power chip provided in the embodiments of this application. The following is a description of the process technology of the chip. Figure 7 The manufacturing process is explained and illustrated, and simultaneously... Figures 8a to 8m The manufacturing process of semiconductor power chips is explained.

[0126] Reference Figure 7 As shown, the manufacturing method includes:

[0127] S701 provides an N+ substrate 10.

[0128] Optional, please see Figure 8a As shown, a low-resistivity N+ substrate 10 is first provided as the substrate.

[0129] S702. An N-type epitaxial layer 20 is formed on the N+ substrate 10, and a high-voltage P-type well region 40 is formed on the N-type epitaxial layer 20.

[0130] Please see Figure 8b As shown, firstly, an N-type epitaxial layer 20 of a certain thickness is grown on an N+ substrate 10, with a doping concentration lower than that of the N+ substrate 10. Subsequently, p-type ion implantation is performed in the device formation region of the N-type epitaxial layer 20 using a high-voltage process, i.e., p-type impurities are doped in the first and second regions of the N-type epitaxial layer 20 to form a first high-voltage P-type well region 401 and a second high-voltage P-type well region 402. The first high-voltage P-type well region 401 is used to generate CMOS, and the second high-voltage P-type well region 402 is used to generate LDMOS.

[0131] Reference Figures 4 to 6 As shown, CMOS includes NMOS and PMOS. Therefore, continuing to refer to... Figure 8c As shown, p-type ions and n-type ions are implanted in different regions of the first high-pressure P-type well region 401 to form a P-type well region (PW) and an N-type well region (NW). For example, the P-type well region and the N-type well region are in contact and connected, and the depth of the P-type well region and the N-type well region are both less than the depth of the first high-pressure P-type well region 401.

[0132] Optional, refer to Figure 8c As shown, n-type ion implantation can also be performed on the second high-pressure P-type well region 40 using a high-pressure process to form a high-pressure N-type well region (HVNW) in the second high-pressure P-type well region 40. The depth of the high-pressure N-type well region is less than the depth of the second high-pressure P-type well region 40.

[0133] S703. A first gate region 32 is formed on the N-type epitaxial layer 20, and a second gate region is formed on the high-voltage P-type well region 40. The first gate region 32 includes an integrally formed planar electrode region 321 and a trench electrode region 322. The second gate region, the planar electrode region 321 and the trench electrode region 322 are formed simultaneously.

[0134] Reference Figures 4 to 6 As shown, the semiconductor power chip includes power devices and control devices (NMOS, PMOS and LDMOS). Figures 4 to 6 The difference lies in the thickness of the oxide layer in the gate region.

[0135] As an example, if generated Figure 4 The semiconductor power chip shown in this embodiment forms a first gate region 32 on the N-type epitaxial layer 20 and a second gate region on the high-voltage P-type well region 40 as follows: First, a first deep trench is dug in the N-type epitaxial layer 20. Then, a first insulating material and a first conductive material are formed in the first deep trench, on the N-type epitaxial layer 20, and on the high-voltage P-type well region 40. Finally, the first conductive material and the first insulating material formed on the N-type epitaxial layer 20 and the high-voltage P-type well region 40 are etched in segments to form a trench electrode region 322 in the first deep trench, a planar electrode region 321 on the N-type epitaxial layer 20, and a second gate region on the high-voltage P-type well region 40. (Refer to...) Figure 4 As shown.

[0136] As another example, if generated Figure 5 The semiconductor power chip shown in this embodiment has a scheme in which a first gate region 32 is formed on the N-type epitaxial layer 20 and a second gate region is formed on the high-voltage P-type well region 40, as described below: (Refer to...) Figure 8d As shown, firstly, a first deep trench 323 is dug in the N-type epitaxial layer 20. The number of first deep trenches 323 can be multiple, determined according to actual needs. Then, as shown... Figure 8e As shown, a first insulating material is formed within the first deep trench 323, on the N-type epitaxial layer 20, and on the high-voltage P-type well region 40. Subsequently, a portion of the first insulating material on the N-type epitaxial layer 20 and a portion of the first insulating material on the high-voltage P-type well region 40 are etched away. (Refer to...) Figure 8f As shown. Subsequently, a second insulating material is formed within the first deep trench 323, on the N-type epitaxial layer 20, and on the high-voltage P-type well region 40, to form a stepped first oxide layer on the N-type epitaxial layer 20, and a second oxide layer on the high-voltage P-type well regions 401 and 402, as shown. Figure 8g As shown, the first oxide layer includes a first-thickness oxide layer near the first deep trench and a second-thickness oxide layer away from the first deep trench, wherein the thickness of the second-thickness oxide layer is less than that of the first-thickness oxide layer. It can be understood that when the control device includes an LDMOS, the second oxide layer in the second high-voltage P-type well region 402 is stepped, such as... Figure 8g As shown; subsequently, a first conductive material is deposited on the first oxide layer and the second oxide layer, for example, as shown. Figure 8h As shown, the first conductive material fills and overflows the first deep trench. Finally, the first conductive material is etched in segments to form a trench electrode region 322 in the first deep trench, a planar electrode region 321 in the N-type epitaxial layer 20, and a second gate region on the high-voltage P-type well region 40, as shown in the figure. Figure 8i As shown.

[0137] As another example, if generated Figure 6 In the semiconductor power chip shown, the scheme for forming a first gate region 32 on the N-type epitaxial layer 20 and a second gate region on the high-voltage P-type well region 40 in this embodiment is as follows: First, a first deep trench is dug in the N-type epitaxial layer 20; second, a first insulating material and a first conductive material are formed in the first deep trench, on the N-type epitaxial layer 20 and the high-voltage P-type well region 40, and the first conductive material and the first insulating material are etched to form a shielding gate 323c and field oxide layers located on both sides and below the shielding gate 323c in the first deep trench. For example, the first conductive material located outside the first deep trench is completely etched away, and part of the first conductive material in the first deep trench is also etched away to form a shielding gate 323c in the first deep trench. The shielding gate 323 is formed by completely etching away the first insulating material located outside the first deep trench. Then, the first insulating material on the sidewall of the first deep trench is isotropically etched until the first insulating material on the sidewall of the first deep trench above the shielding gate 323 is completely etched away, thereby forming a field oxide layer on both sides and below the shielding gate 323. Subsequently, a second insulating material and a second conductive material are formed above the shielding gate 323 in the first deep trench, on the N-type epitaxial layer 20 and the high-voltage P-type well region 40. The second conductive material and the second insulating material are etched to form a trench electrode region 322 in the first deep trench, a planar electrode region 321 in the N-type epitaxial layer 20, and a second gate region in the high-voltage P-type well region 40.

[0138] Understandable Figures 4 to 6 In different embodiments, due to the different thicknesses of the oxide layer, the turn-on voltage of the semiconductor power chip formed is different, and the applicable range is different. It can be selected according to the specific application scenario.

[0139] S704, a first P-type substrate region 31 and a first source region 34 are formed between the first gate region 32, and a second drain region and a second source region are formed in the high-voltage P-type well region 40. The second drain region and the second source region are located on both sides of the second gate region in the vertical direction.

[0140] Optionally, refer to the above. Figure 8jAs shown, after the first gate region 32 and the second gate region are formed, a gap is formed between the planar electrode regions 321 and between the second gate regions. Therefore, in this embodiment, p-type impurities can be doped into the N-type epitaxial layer 20 through the gaps between the first gate regions 32, forming a first P-type substrate region 31 between the first gate regions 32. The p-type impurity is a trivalent element, such as boron. In this embodiment, the lower surface of the first P-type substrate region 31 is higher than the lower surface of the first gate region. The overlapping area of ​​the first P-type substrate region 31 and the planar electrode region 321 in the vertical direction forms a planar channel, and the length of the channel is controlled by the diffusion length of the first P-type substrate region 31.

[0141] Optionally, when the control device includes an LDMOS, during the formation of the first P-type substrate region 31, p-type impurities can be doped into the high-voltage P-type well region 402 along the edge of the LDMOS gate region 413 on the side away from the high-voltage N-well, thereby forming a second P-type substrate region 44, the lower surface of which is higher than the lower surface of the high-voltage N-type well region. Correspondingly, the overlap region between the second P-type substrate region 44 and the LDMOS gate region 413 in the vertical direction forms a channel, the length of which is controlled by the diffusion length of the second P-type substrate region.

[0142] Then refer to Figure 8k As shown, a first lightly doped region 36 and a second lightly doped region 46 are formed, as well as a first isolation sidewall 35 and a second isolation sidewall 45. The first isolation sidewall 35 is located above the first lightly doped region 36 and is in contact with the edge of the first gate region 32, and the second isolation sidewall 45 is located above the second lightly doped region 46 and is in contact with the edge of the second gate region.

[0143] Finally refer to Figure 8l As shown, a first source region 34 is formed on the first P-type substrate region 31, and a second source region and a second drain region are formed on the high-voltage P-type well region 40 and on both sides of the second gate region.

[0144] Specifically, the first source region 34 is formed by doping the two sides of the upper part of the first P-type matrix region 31 with n-type impurities, which are pentavalent elements such as phosphorus and arsenic.

[0145] Optionally, when the controller is CMOS, n-type impurities of a five-valent element, such as phosphorus or arsenic, are doped into the P-type well region along the edge of the second isolation sidewall 45 of the gate region of the NMOS to form the source region 431(n+) and drain region 421(n+) of the NMOS on both sides of the gate region of the NMOS. N-type impurities are doped into the N-type well region at a position away from the gate region of the PMOS to form the well contact region (n+) of the PMOS. Subsequently, p-type impurities are doped into the P-type well region on the side of the P-type well region close to the source region 431(n+) to form the well contact region (p+) of the NMOS. P-type impurities are doped into the N-type well region along the edge of the second isolation sidewall 45 of the gate region of the PMOS to form the source region 432(p+) and drain region 422(p+) of the PMOS on both sides of the gate region of the PMOS.

[0146] Optionally, when the controller is an LDMOS, in accordance with the process steps of forming the first source region 34, the source region 433 of the LDMOS can be formed above the second P-type substrate region 44, and n-type impurities can be doped into the high-voltage N-type well region on the other side of the second gate region to form the drain region 423 of the LDMOS.

[0147] S705, A first drain region 33 is formed below the N+ substrate 10.

[0148] In this embodiment, refer to Figure 8m As shown, a metal layer is deposited below the N+ substrate 10 to form the first drain region 33.

[0149] Therefore, based on the above steps S701 to S705, and in conjunction with the above... Figures 8a to 8m This has led to the development of semiconductor power chips that integrate power devices and control devices.

[0150] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0151] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A VDMOS device, characterized in that, It includes an N+ substrate, an N-type epitaxial layer, a first P-type substrate region, a first gate region, a first drain region, and a first source region; Wherein, the N-type epitaxial layer is located above the N+ substrate, the first drain region is located below the N+ substrate, the first P-type substrate region and the first gate region are both formed in the N-type epitaxial layer and the first P-type substrate region is located between the first gate regions, and the first source region is formed on the first P-type substrate region; The first gate region includes an integrally formed planar electrode region and a trench electrode region. A first isolation sidewall is formed at the edge of the planar electrode region. A first lightly doped region is located below the first isolation sidewall. The first lightly doped region is in contact with and connected to the first source region.

2. The VDMOS device according to claim 1, characterized in that, A first oxide layer is provided between the first gate region and the N-type epitaxial layer, wherein the first oxide layer below the planar electrode region is stepped, and the thickness of the first oxide layer near the trench electrode region is greater than the thickness of the first oxide layer near the first source region.

3. The VDMOS device according to claim 1, characterized in that, It also includes a shielding grid located below the trench electrode region.

4. The VDMOS device according to any one of claims 1 to 3, characterized in that, The first P-type substrate region is formed by implanting P-type ions into the N-type epitaxial layer through the gap between the first gate regions. The planar electrode region and the first P-type substrate region overlap in the vertical direction to form a planar channel. The length of the channel is controlled by the diffusion length of the first P-type substrate region.

5. The VDMOS device according to any one of claims 1 to 3, characterized in that, It also includes a P-type heavily doped region, which is located between the first source regions.

6. The VDMOS device according to any one of claims 1 to 3, characterized in that, If the width of the trench electrode region is less than or equal to twice the thickness of the planar electrode region, then the lowest upper surface of the trench electrode region is higher than the upper surface of the N-type epitaxial layer. or, If the width of the trench electrode region is greater than twice the thickness of the planar electrode region, then the lowest upper surface of the trench electrode region is lower than the upper surface of the N-type epitaxial layer.

7. A semiconductor power chip, formed on an N-type epitaxial layer above an N+ substrate, characterized in that, The semiconductor power chip integrates power devices and control devices; The power device includes a first gate region, a first drain region, a first P-type substrate region, and a first source region. The first drain region is located below the N+ substrate. The first P-type substrate region and the first gate region are both formed in the N-type epitaxial layer, with the first P-type substrate region located between the first gate regions. The first source region is disposed above the first P-type substrate region and led out through a source contact region. The first gate region includes an integrally formed planar electrode region and a trench electrode region. A first isolation sidewall is formed at the edge of the planar electrode region. A first lightly doped region is located below the first isolation sidewall and is in contact with the first source region. The control device includes a second gate region, a second drain region, a second source region, and a high-voltage P-type well region; the high-voltage P-type well region is formed in the N-type epitaxial layer, the second gate region is located above the high-voltage P-type well region, the second drain region and the second source region are both formed in the high-voltage P-type well region, a second isolation sidewall is formed at the edge of the second gate region, a second lightly doped region is provided below the second isolation sidewall, the second lightly doped region is in contact with the second source region, and the second drain region and the second source region are located on both sides of the second gate region in the vertical direction; The second gate region and the first gate region are formed simultaneously, the first lightly doped region and the second lightly doped region are formed simultaneously, and the first isolation sidewall and the second isolation sidewall are formed simultaneously.

8. The semiconductor power chip according to claim 7, characterized in that, The control device includes a complementary metal-oxide-semiconductor (CMOS), which includes an NMOS and a PMOS; wherein the NMOS is formed in the P-type well region of the high-voltage P-type well region, and the PMOS is formed in the N-type well region of the high-voltage P-type well region.

9. The semiconductor power chip according to claim 8, characterized in that, A first oxide layer is provided between the first gate region and the N-type epitaxial layer, and a second oxide layer is provided between the gate region of the CMOS and the high-voltage P-type well region; The first oxide layer below the planar electrode region is stepped, the thickness of the first oxide layer near the first source region is less than the thickness of the first oxide layer near the trench electrode region, and the thickness of the second oxide layer is less than the thickness of the first oxide layer near the trench electrode region.

10. The semiconductor power chip according to claim 7, characterized in that, The control device includes a laterally diffused metal-oxide semiconductor LDMOS, wherein the source region of the LDMOS is formed in the P-type substrate region of the high-voltage P-type well region, and the drain region of the LDMOS is formed in the high-voltage N-type well region of the high-voltage P-type well region.

11. The semiconductor power chip according to claim 10, characterized in that, A first oxide layer is provided between the first gate region and the N-type epitaxial layer, and a second oxide layer is provided between the gate region of the LDMOS and the high-voltage P-type well region; wherein, the first oxide layer below the planar electrode region is stepped, and the thickness of the first oxide layer near the first source region is less than the thickness of the first oxide layer near the trench electrode region; the second oxide layer is stepped, and the thickness of the second oxide layer near the source region of the LDMOS is less than the thickness of the second oxide layer near the drain region of the LDMOS.

12. A method for manufacturing a semiconductor power chip, characterized in that, include: Provide N+ substrate; An N-type epitaxial layer is formed on the N+ substrate, and a high-voltage P-type well region is formed on the N-type epitaxial layer; A first gate region is formed on the N-type epitaxial layer, and a second gate region is formed on the high-voltage P-type well region. The first gate region includes an integrally formed planar electrode region and a trench electrode region. The second gate region, the planar electrode region, and the trench electrode region are formed simultaneously. A first P-type substrate region and a first source region are formed between the first gate region, and a second drain region and a second source region are formed in the high-voltage P-type well region, with the second drain region and the second source region distributed on both sides of the second gate region; A first drain region is formed beneath the N+ substrate.

13. The manufacturing method according to claim 12, characterized in that, A first gate region is formed in the N-type epitaxial layer, and a second gate region is formed on the high-voltage P-type well region, including: A first deep trench is dug in the N-type epitaxial layer; A first insulating material and a first conductive material are formed within the first deep trench, on the N-type epitaxial layer, and on the high-voltage P-type well region; The first conductive material and the first insulating material formed on the N-type epitaxial layer and the high-voltage P-type well region are etched in segments to form a trench electrode region in the first deep trench, a planar electrode region on the N-type epitaxial layer, and a second gate region on the high-voltage P-type well region.

14. The manufacturing method according to claim 12, characterized in that, A first gate region is formed in the N-type epitaxial layer, and a second gate region is formed on the high-voltage P-type well region, including: A first deep trench is dug in the N-type epitaxial layer; A first insulating material is formed in the first deep trench, on the N-type epitaxial layer and on the high-voltage P-type well region, and the first insulating material located between the first deep trench and on the first insulating material on the high-voltage P-type well region is etched. A second insulating material is formed in the first deep trench, on the N-type epitaxial layer and on the high-voltage P-type well region, so as to form a stepped first oxide layer on the N-type epitaxial layer, wherein the thickness of the first oxide layer away from the first deep trench is less than the thickness of the first oxide layer near the first deep trench. A first conductive material is deposited on the first insulating layer; The first conductive material is etched in segments to form a trench electrode region in the first deep trench, a planar electrode region in the N-type epitaxial layer, and a second gate region on the high-voltage P-type well region.

15. The manufacturing method according to claim 12, characterized in that, A first gate region is formed in the N-type epitaxial layer, and a second gate region is formed on the high-voltage P-type well region, including: A first deep trench is dug in the N-type epitaxial layer; A first insulating material and a first conductive material are formed within the first deep trench, on the N-type epitaxial layer, and on the high-voltage P-type well region; The first conductive material and the first insulating material are etched to form a shielding gate and a field oxide layer in the first deep trench, the field oxide layer being located below and on both sides of the shielding gate; A second insulating material and a second conductive material are formed above the shielding grid, the N-type epitaxial layer, and the high-voltage P-type well region within the first deep trench; The second conductive material is etched to form a trench electrode region in the first deep trench, a planar electrode region on the N-type epitaxial layer, and a second gate region on the high-voltage P-type well region.

16. The manufacturing method according to any one of claims 12 to 15, characterized in that, A first P-type substrate region and a first source region are formed between the first gate regions, and a second drain region and a second source region are formed in the high-voltage P-type well region, including: P-type ions are implanted into the N-type epitaxial layer through the gap between the first gate regions to form the first P-type substrate region between the first gate regions. The overlap region between the first P-type substrate region and the planar electrode region in the vertical direction forms a planar channel. The length of the channel is controlled by the diffusion length of the first P-type substrate region. A first lightly doped region and a second lightly doped region are formed, as well as a first isolation sidewall and a second isolation sidewall. The first isolation sidewall is located above the first lightly doped region and is in contact with the edge of the first gate region. The second isolation sidewall is located above the second lightly doped region and is in contact with the edge of the second gate region. A first source region is formed on the first P-type substrate region, and a second source region and a second drain region are formed on the high-voltage P-type well region and on both sides of the second gate region.

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