A main source co-gate potential adaptive SiC MOSFET device

Abstract

The application relates to a main-source cooperative gate potential adaptive SiC MOSFET device and belongs to the technical field of semiconductor power devices. The device integrates a main gate-controlled trench gate and a source auxiliary trench gate in a cell to build a P-type barrier switch with controllable gate voltage, realizes adaptive dynamic switching of the P-shield region potential, and integrates a low-barrier MOS channel diode in the same cell through the source auxiliary trench gate without additional chip area and process cost. When the device is forwardly turned on, the main gate-controlled trench gate and the source auxiliary trench gate cooperate to deplete the P-ch region of the P-type barrier switch, so that the P-shield region is floating, the JFET effect is effectively inhibited, and the specific on-resistance is reduced; in the blocking state, the P-ch region remains on, the P-shield region is reliably grounded, the gate oxide field concentration is shielded, the negative charge storage effect is inhibited, the device breakdown voltage and long-term reliability are improved; when the reverse current is continued, the low-barrier reverse channel controlled by the source auxiliary trench gate is preferentially turned on, the bipolar degradation effect of the body diode is completely eliminated, and the reverse recovery characteristics are greatly optimized. The application has low on-state loss, high gate oxide reliability, excellent high-frequency switching characteristics and low reverse current loss, and is suitable for high-end power electronic scenes such as new energy vehicles and smart grids.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology and relates to a main source co-gate potential adaptive SiCMOSFET device. Background Technology

[0002] With the transformation of the global energy structure and the rapid development of power electronics technology, power semiconductor devices, as core components of power conversion, directly determine the efficiency, reliability, and integration of energy systems. Especially in fields such as new energy vehicles, smart grids, industrial frequency converters, and renewable energy power generation, more stringent requirements are placed on the high-voltage withstand capability, high-frequency switching characteristics, high-temperature stability, and low-loss characteristics of power devices. Traditional power devices, represented by silicon (Si)-based materials, are gradually facing performance bottlenecks in high-voltage, high-temperature, and high-switching-frequency applications due to their physical properties. Therefore, wide-bandgap semiconductor materials, represented by silicon carbide (SiC), have become the ideal choice for next-generation power devices due to their superior physical properties, namely wider bandgap, higher breakdown voltage, and lower on-resistance.

[0003] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), as a typical representative of SiC power devices, exhibit significant advantages in high-voltage blocking capability, on-resistance, and switching speed by combining gate control with a vertical conduction structure. However, with the increasing complexity of application scenarios and the improvement of performance requirements, existing SiC MOSFET technology still faces four major bottlenecks.

[0004] First, the long-term reliability bottleneck of the trench gate oxide layer. The geometric characteristics of the trench gate structure cause the gate oxide layer to be subjected to an extremely high longitudinal electric field in the off state. In particular, the electric field concentration phenomenon at the bottom corner of the trench makes the local field strength reach 5-6 MV / cm, which far exceeds the safety threshold of 3 MV / cm at the SiC / SiO2 interface. This seriously threatens the long-term reliability of the device and is the core bottleneck restricting the practical application of trench gate SiC MOSFETs.

[0005] Second, there is a trade-off between on-resistance (Ron,sp) and breakdown voltage (BV). To alleviate the aforementioned gate oxide electric field concentration problem, mainstream technologies introduce a P-type shielding region (P-shield) below the gate trench. However, this approach introduces new performance contradictions: while a grounded P-shield can shield the electric field and ensure reliability, it creates a JFET depletion region in the on-state, increasing the specific on-resistance by 15%-20%; while a floating P-shield can reduce on-resistance, it induces a negative charge storage effect, leading to a significant degradation in dynamic on-resistance and a decrease in switching speed. Simultaneously, when the device is forward-biased, current flows through the JFET region between the drift region and the channel region. The doping concentration and geometry of the JFET region directly affect the on-resistance. Increasing the JFET region size or doping concentration to optimize on-resistance leads to a decrease in breakdown voltage, while conversely, a significant increase in on-resistance results in an irreconcilable performance trade-off.

[0006] Third, the bipolar degradation effect of the body diode during reverse freewheeling. In applications such as inverter circuits and motor drives, SiCMOSFETs must withstand reverse freewheeling conditions. Under these conditions, the parasitic body diode (composed of P-base and N-drift regions) inside the device is forced to conduct. The minority carrier injection effect triggers bipolar degradation: on the one hand, the injected carriers recombine in the drift region, generating heat, exacerbating the device temperature rise and reducing reliability; on the other hand, the rapid release of stored charge during reverse recovery causes current spikes and voltage oscillations, increasing switching losses and damaging peripheral circuits. While existing technologies can suppress body diode conduction by introducing Schottky contacts, this sacrifices the device's forward characteristics or significantly increases process complexity and cost.

[0007] Fourth, the process and performance defects of existing potential adaptive technologies. While existing potential adaptive P-shield solutions with embedded vias in the gate can achieve dynamic switching of the P-shield potential, they require the fabrication of high-precision deep vias inside the gate, resulting in high process complexity, low yield, and the lack of integrated low-barrier reverse conduction structures, failing to address the industry pain point of bipolar degradation in body diodes. Existing dual-trench auxiliary gate solutions, while capable of integrating a reverse channel, do not incorporate P-shield potential adaptation as a core optimization, thus failing to completely resolve the trade-off between on-resistance and breakdown voltage. Summary of the Invention

[0008] The purpose of this invention is to provide a main source co-generation gate potential adaptive SiC MOSFET device. By optimizing the device's structural design, it simultaneously achieves P-shield potential adaptive control and low-barrier MOS channel diode integration within the same cell, without additional process overhead and chip area. This further reduces on-resistance, accelerates reverse recovery rate, and improves long-term gate oxide reliability, thereby enhancing the device's performance in high-frequency and high-efficiency applications.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0010] A main-source co-gate potential adaptive SiC MOSFET device includes, from bottom to top, a drain metal contact region, an N+ substrate region, an N- drift region, an N-CSL current extension layer, a P-base region, and a source metal contact region; a main-source co-gate control structure is set at the center of the device cell, a main MOSFET channel structure is set on the left side of the cell, and a low-barrier MOS channel diode structure is integrated within the cell;

[0011] The main-source co-gate control structure includes a left main-gate controlled trench gate, a right source auxiliary trench gate, a trench gate oxide layer surrounding the two trenches, a P-shield region at the bottom of the two trenches, and a P-type barrier switch between the two trenches. The P-type barrier switch includes a P-ch region and a central source P+ region. The P-ch region is formed on the upper surface of the N-drift region between the two trenches, and the central source P+ region is formed on the upper surface of the P-ch region and ohmically connected to the source metal contact region. The main-gate controlled trench gate is connected to the device gate potential, and the source auxiliary trench gate is equipotentially connected to the source metal contact region.

[0012] The low-barrier MOS channel diode structure is composed of a source-assisted trench gate, a trench gate oxide layer that surrounds the trench, a P-base region on the right side of the source-assisted trench gate, and a source N+ region connected to the top of the P-base region and the source metal contact region.

[0013] The main MOSFET channel structure consists of a main gate controlled trench gate, a left P-base region, a left source N+ region, a left source P+ region, an N-CSL current extension layer, an N-drift region, an N+ substrate region, and a drain metal contact region.

[0014] Furthermore, when the device is forward-biased, a 15V positive bias is applied to the main gate controlled trench gate, and the source auxiliary trench gate is connected to the source potential of 0V. The transverse bidirectional electric field formed by the two completely depletes and pinches off the middle P-ch region, breaking the conductive path between the P-shield region and the top source P+ region, making the P-shield region float. The floating P-shield will not produce additional depletion effect on the N-CSL current extension layers on both sides, greatly weakening the JFET effect, widening the current conduction path, and significantly reducing the specific on-resistance of the device.

[0015] Furthermore, in the device's blocking state, a negative bias voltage of 0V or no more than 5V is applied to the main gate-controlled trench gate, and the source auxiliary trench gate is connected to the source at a potential of 0V. The potential difference between the two is insufficient to deplete the P-ch region, allowing the P-ch region to maintain good P-type conductivity. This enables the P-shield region to be reliably grounded through the P-ch region, the central source P+ region, and the source metal. This negative bias voltage amplitude meets the engineering requirements for preventing accidental turn-on of SiC MOSFETs and ensures stable grounding of the P-shield region. The grounded P-shield region forms a reverse-biased PN junction with the N-drift region, bearing the device's blocking voltage. At the same time, it achieves electric field redistribution through the depletion effect, shielding the electric field concentration at the bottom of the trench gate and limiting the maximum electric field of the gate oxide layer to within the safe threshold of 3MV / cm. Simultaneously, it completely suppresses the negative charge storage effect caused by the floating P-shield, avoids dynamic on-resistance degradation, and improves the long-term reliability of the device.

[0016] Furthermore, during reverse freewheeling, the main gate controlled trench is subjected to 0V or a negative bias, the main channel remains off, and the source auxiliary trench is connected to the source potential of 0V. Relative to the negatively biased drain and N-drift region, this is equivalent to a positive bias, forming an N-type inversion channel near the sidewall of the source auxiliary trench in the P-base region, thus constituting a low-barrier MOS channel diode. This channel has a turn-on voltage as low as 1.2V, far lower than the 2.7V on-state voltage drop of a traditional SiC body diode. Reverse current preferentially flows through this unipolar channel, completely suppressing parasitic body diode conduction and eliminating the bipolar degradation effect caused by minority carrier injection at its source, significantly optimizing the device's reverse recovery characteristics.

[0017] Furthermore, both the main gate controlled trench gate and the source auxiliary trench gate are encapsulated by a trench gate oxide layer; the sidewall oxide layer thickness of both the main gate controlled trench gate and the source auxiliary trench gate is 0.05 μm, which is less than the oxide layer thickness of 0.08 μm at the bottom of the trench. This enhances the reverse channel gate control capability and reduces the turn-on voltage while ensuring the electric field shielding capability and gate oxide reliability at the bottom of the trench.

[0018] Furthermore, by adjusting the thickness of the trench gate oxide layer, the size of the gate-source capacitance and gate-drain capacitance of the device can be flexibly controlled, balancing the conduction and switching characteristics of the device, and achieving synergistic optimization of static and dynamic performance.

[0019] Furthermore, the P-ch region uses low-doped P-type SiC, with a doping concentration lower than that of the P-shield region and the central source P+ region. This ensures that during forward conduction, the P-shield region can be completely depleted and pinched off by the main gate-controlled trench gate and the source auxiliary trench gate. In the blocking state, a stable conductive path can be formed, enabling precise switching of the P-shield region potential.

[0020] Furthermore, the source metal contact region simultaneously achieves ohmic contact with the source N+ region, the source P+ region, the central source P+ region, and the source auxiliary trench gate; the drain metal contact region is located on the lower surface of the N+ substrate region and forms ohmic contact with the N+ substrate region.

[0021] The beneficial effects of this invention are as follows:

[0022] Overcoming the inherent trade-off between on-resistance and breakdown voltage: By coordinating the control of the main gate-controlled trench gate and the source-assisted trench gate, the P-shield achieves adaptive potential switching. During forward conduction, the P-shield floats, reducing the JFET region resistance by 20.69% and the specific on-resistance by 12.5% ​​compared to traditional asymmetric trench SiCMOSFETs. In the blocking state, the P-shield is reliably grounded, increasing the device breakdown voltage to 1265V. This breaks through the inherent bottleneck of traditional solutions that "grounding increases resistance and floating decreases reliability," achieving a decoupled design between conduction loss and withstand voltage performance.

[0023] Significantly improves gate oxide reliability: The grounded P-shield in the blocking state limits the maximum electric field of the gate oxide layer to within the safe threshold of 3MV / cm, fundamentally solving the reliability bottleneck of the concentrated electric field of the trench gate.

[0024] Completely eliminates bipolar degradation effect and significantly optimizes reverse freewheeling performance: No additional chip area or process steps are required; a low-barrier MOS channel diode is integrated within the same cell, achieving a reverse turn-on voltage as low as 1.2V, a 55.6% reduction compared to traditional SiC body diodes. During reverse freewheeling, the unipolar channel preferentially conducts, completely suppressing body diode turn-on and eliminating the bipolar degradation effect caused by minority carrier injection. The reverse recovery time is reduced from 13ns in traditional devices to less than 6ns, a reduction of over 53.8%, and the reverse recovery charge is reduced by 65.2%, significantly reducing reverse recovery losses and circuit oscillation risks, making it perfectly suited for high-frequency inverters, motor drives, and other applications.

[0025] High process compatibility and high cell utilization: It abandons the gate-embedded via process of existing potential adaptive devices, and achieves potential control and reverse channel integration through the collaborative structure design of main gate controlled trench gate and source auxiliary trench gate. No additional photolithography, etching and ion implantation steps are required. It is fully compatible with traditional SiC trench MOSFET process and avoids the cost increase and yield reduction caused by additional processes. At the same time, there is no need to sacrifice cell area to set ground via or independent diode structure. The cell area utilization reaches 100%, which further reduces the specific on resistance of the device.

[0026] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0027] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0028] Figure 1 A schematic diagram of the cell cross-sectional structure of the SiC MOSFET device with main source co-gate potential adaptive function provided by the present invention;

[0029] Figure 2 The equivalent circuit schematic diagram of the device provided in the embodiment of the present invention;

[0030] Figure 3 The diagram shows the valence band energy spectrum of the device under different operating states of the present invention. (a) is the valence band energy spectrum under the forward blocking state (Vg=0V, Vs=0V), and (b) is the valence band energy spectrum under the forward conducting state (Vg=15V, Vs=0V).

[0031] Figure 4 This is a comparison curve of the valence band barrier height of the device of the present invention under the on and off conditions;

[0032] Figure 5 This is a diagram showing the internal electric field distribution of the P-shield region of the device of the present invention in a floating state;

[0033] Figure 6 This is a comparison diagram of the current density distribution of the device of the present invention and a conventional trench SiC MOSFET in the forward conduction state;

[0034] Figure 7 This is a comparison diagram of the current density distribution of the device of the present invention and a conventional trench SiC MOSFET under reverse freewheeling state;

[0035] Figure 8 The curves show a comparison of the reverse conduction characteristics of the device of the present invention and a conventional trench SiC MOSFET device.

[0036] Figure 9 The curves show a comparison of the forward conduction output characteristics of the device of the present invention and that of a conventional trench SiC MOSFET device.

[0037] Explanation of reference numerals in the attached figures: 1-Drain metal contact region, 2-N+ substrate region, 3-N-Drift region, 4-P-Shield region, 5-Source auxiliary trench gate, 6-P-base region, 7-Source P+ region, 8-Source N+ region, 9-Trench gate oxide layer, 10-Center source P+ region, 11-Source metal contact region, 12-N-CSL current spread layer, 13-P-ch region, 14-Master gate controlled trench gate. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0039] like Figure 1 As shown, a preferred embodiment of the present invention provides a main-source co-gate potential adaptive SiC MOSFET device. The device is a vertical trench gate structure with a total cell width of 3.5 μm. From bottom to top, it includes a drain metal contact region 1, an N+ substrate region 2, an N- drift region 3, an N-CSL current extension layer 12, a P-base region 6, and a source metal contact region 11. The center of the cell is the main-source co-gate control structure, the left side of the cell is the main MOSFET channel structure, and the right side of the cell integrates a low-barrier MOS channel diode structure.

[0040] The equivalent circuit of the device of the present invention is as follows: Figure 2As shown, the gate of the main MOSFET is electrically connected to the main gate controlled trench gate 14. The source and drain of the main MOSFET correspond to the source metal contact region 11 and the drain metal contact region 1 of the device, respectively. The P-type barrier switch is equivalent to a voltage-controlled switch controlled by the main gate controlled trench gate 14 and the source auxiliary trench gate 5, and is connected in series between the P-shield region 4 and the source to realize adaptive switching of the P-shield region potential. The integrated low barrier MOS channel diode is equivalent to a unipolar diode connected in antiparallel between the drain and source of the main MOSFET. Its gate and source are connected at the same potential and are used to suppress the conduction of the parasitic body diode when reverse freewheeling occurs.

[0041] The drain metal contact region 1 is located on the lower surface of the N+ substrate region 2 and forms an ohmic contact with the N+ substrate region 2;

[0042] The N+ substrate region 2 is located on the lower surface of the N- drift region 3 and the upper surface of the drain metal contact region 1, with a thickness of 3 μm. The SiC material is doped with N-type impurity nitrogen (N) at a doping concentration of 2 × 10¹. 9 cm⁻³;

[0043] The N-drift region 3 is located on the upper surface of the N+ substrate region 2 and the lower surface of the N-CSL current extension layer 12, with a thickness of 12 μm. The SiC material is doped with N-type impurity nitrogen (N) at a doping concentration of 8 × 10¹. 5 cm⁻³;

[0044] The N-CSL current extension layer 12 is located on the upper surface of the N-drift region 3 and the lower surface of the P-base region 6, with a thickness of 1.5 μm. The SiC material is doped with N-type impurity nitrogen (N) at a doping concentration of 2.5 × 10¹. 6 cm⁻³.

[0045] The two P-base regions 6, one on the left and one on the right, are located on the upper surface of the N-CSL current extension layer 12. Each P-base region has a thickness of 0.5 μm and a width of 1 μm. The SiC material is doped with p-type aluminum (Al) impurity at a doping concentration of 2 × 10¹⁰. 7 cm⁻³;

[0046] The source N+ region 8 is located on the upper surface of the P-base region 6, with a thickness of 0.3 μm and a width of 0.4 μm. The SiC material is doped with N-type impurity nitrogen (N) at a doping concentration of 1 × 10¹. 9 cm⁻³, forming an ohmic contact with the source metal contact region 11;

[0047] The source P+ region 7 is located on the upper surface of the P-base region 6, adjacent to the source N+ region 8, with a thickness of 0.3 μm and a width of 0.2 μm. The SiC material is doped with p-type aluminum (Al) impurity at a doping concentration of 1 × 10¹.9 cm⁻³, forming an ohmic contact with the source metal contact region 11, used to suppress the parasitic thyristor effect;

[0048] The main-source co-gate control structure includes a left main-gate control trench gate 14, a right source auxiliary trench gate 5, a trench gate oxide layer 9 enclosing the two trenches, a P-shield region 4 at the bottom of the two trenches, and a P-type barrier switch between the two trenches; the P-type barrier switch includes a P-ch region 13 and a central source P+ region 10.

[0049] The P-ch region 13 is located between the two trenches, with a thickness of 1.8 μm and a width of 0.2 μm. The SiC material is doped with p-type aluminum (Al) impurities at a doping concentration of 2 × 10¹. 7 cm⁻³;

[0050] The P-shield region 4 is located at the bottom of the two trenches, and its lower half is surrounded by the N-drift region 3. It has a thickness of 0.5 μm and a width of 1.5 μm. The SiC material is doped with P-type aluminum (Al) impurity at a doping concentration of 2 × 10¹. 8 cm⁻³;

[0051] The low-barrier MOS channel diode structure is composed of a source-assisted trench gate 5, a trench gate oxide layer 9 that surrounds the trench, a P-base region 6 on the right side of the source-assisted trench gate 5, and a source N+ region 8 on top of the P-base region 6.

[0052] The main gate controlled trench gate 14 is located on the left side of the cell and is wrapped by the trench gate oxide layer 9, which has a thickness of 1.8 μm and a width of 0.5 μm. The material is heavily doped N-type polysilicon. The main gate controlled trench gate 14 is connected to the device gate input potential.

[0053] The trench gate oxide layer 9 covers all trench gates, wherein the thickness of the oxide layer on the trench sidewall is 0.05 μm and the thickness of the oxide layer at the bottom of the trench is 0.08 μm, and the material is silicon dioxide.

[0054] The source metal contact region 11 is located at the top of the device and forms an ohmic contact with the source N+ region 8, the source P+ region 7, the central source P+ region 10, and the source auxiliary trench gate 5.

[0055] The core working mechanism of the device in this embodiment will be explained in detail below with reference to the accompanying drawings:

[0056] Forward guidance mechanism

[0057] When the device is forward biased, a +15V positive bias is applied to the main gate controlled trench gate 14, the source auxiliary trench gate 5 and the source metal contact region 11 are connected to 0V, and a positive bias is applied to the drain. At this time, the positive gate voltage of the main gate controlled trench gate 14 and the 0V potential of the source auxiliary trench gate 5 form a transverse bidirectional electric field, completely depleting and pinching off the middle P-ch region 13, breaking the conductive path between the P-shield region 4 and the top center source P+ region 10, causing the P-shield region 4 to enter a floating state. Figure 3 (b) shows the valence band energy spectrum. A high hole barrier of 3.2 eV is formed in the P-ch region, completely blocking the hole flow path. The P-shield region is completely isolated from the source and enters a floating state. Figure 4 The valence band barrier curve achieves complete isolation between the P-shield and the source. The floating P-shield region 4 does not produce additional depletion effects on the N-CSL current extension layers 12 on both sides, significantly reducing the JFET effect and lowering the JFET region resistance by 20.69%. Figure 6 The comparison diagram of the current density distribution of the device of the present invention and that of a conventional trench SiC MOSFET in the forward conduction state shows that the current conduction path of the device is significantly widened, ultimately achieving a 12.5% ​​reduction in specific on-resistance compared to the conventional trench device; correspondingly Figure 9 The comparison curves of the forward conduction output characteristics of the device of the present invention and the conventional trench SiC MOSFET device show that, under the same drain-source voltage, the drain current density of the device of the present invention is significantly higher than that of the conventional device, and the conduction characteristics are superior. At the same time, the positive bias of the main gate controlled trench gate forms an N-type inversion channel on the sidewall of the left P-base region 6. Electrons flow from the source N+ region 8 through the inversion channel into the N-CSL current extension layer 12 and the N-drift region 3, and finally reach the drain, completing the forward conduction. The floating P-shield region 4 will not have a negative impact on the carrier transport in the main channel.

[0058] Forward blocking mechanism:

[0059] When the device is forward-biased, the main gate controlled trench gate 14 is applied with a negative bias of 0V or no more than 5V, the source auxiliary trench gate 5 is connected to a 0V potential, and the drain is applied with a high positive bias of 600V. At this time, the potential difference between the main gate controlled trench gate and the source auxiliary trench gate is insufficient to deplete the P-ch region 13. The P-ch region 13 is not depleted and maintains good P-type conductivity. The P-shield region 4 is reliably grounded through the P-ch region 13, the central source P+ region 10, and the source metal contact region 11. Figure 3(a) Valence band energy spectrum: There is no hole barrier in the P-ch region, allowing holes to flow freely. The P-shield region forms a stable conductive path with the source through the P-ch region, the central source P+ region, and the source, ensuring reliable grounding. The grounded P-shield region 4 and the N-drift region 3 form a reverse-biased PN junction, bearing the forward blocking voltage of the device. The depletion region extends towards the less doped N-drift region 3, achieving a high breakdown voltage of 1265V. Simultaneously, the electric field redistribution is achieved through the PN junction depletion effect, concentrating the electric field at the bottom of the shielding trench gate and limiting the maximum electric field of the gate oxide layer to a safe threshold of 3MV / cm.

[0060] Reverse freewheeling working mechanism:

[0061] When the device is in reverse freewheeling mode, a negative bias of 0V or no more than 5V is applied to the main gate controlled trench gate 14, keeping the main channel off. The source auxiliary trench gate 5 is connected to a 0V potential, and the drain potential is lower than the source potential. At this time, the 0V potential of the source auxiliary trench gate 5, relative to the negatively biased drain and N-drift region 3, is equivalent to applying a positive bias, forming an N-type inversion channel in the P-base region 6 near the sidewall of the source auxiliary trench gate 5, thus constituting a low-barrier MOS channel diode. Figure 8 The reverse conduction characteristic curve shows that the reverse turn-on voltage of the device of this invention is only 1.2V, which is much lower than the 2.7V forward voltage drop of the traditional SiC body diode; corresponding to Figure 7 The comparison diagram of the current density distribution of the device of the present invention and a conventional trench SiC MOSFET under reverse freewheeling state shows that the reverse current preferentially flows through the unipolar channel of the source auxiliary trench gate sidewall, completely suppressing the conduction of the parasitic body diode formed by the P-base region 6 and the N-drift region 3. This mechanism eliminates the bipolar degradation effect caused by minority carrier injection into the drift region at its source, and at the same time significantly optimizes the reverse recovery characteristics of the device: the reverse recovery time is reduced from 13ns of conventional devices to less than 6ns, a reduction of more than 53.8%; the reverse recovery charge is reduced by 65.2%; and the reverse recovery peak current is reduced by 18.8%, effectively reducing reverse recovery losses and circuit oscillation risk.

Claims

1. A main-source co-current gate potential adaptive SiC MOSFET device, characterized in that, The device, from bottom to top, includes: Drain metal contact area (1); N+ substrate region (2) formed on the upper surface of the drain metal contact region (1); N- drift region (3) formed on the upper surface of the N+ substrate region (2); An N-CSL current extension layer (12) is formed on the upper surface of the N-drift region (3). The main source cooperative gate control structure is located deep inside the N-drift region (3) and between the N-CSL current extension layers (12). The main source cooperative gate control structure includes a left main gate controlled trench gate (14), a right source auxiliary trench gate (5), a trench gate oxide layer (9) that wraps the main gate controlled trench gate (14) and the source auxiliary trench gate (5), a P-shield region (4) located at the bottom of the two trenches, and a P-type barrier switch located between the two trenches. The P-type barrier switch is controlled by the main source cooperative gate control structure and is used to control the floating and grounding states of the P-shield region (4). The P-type barrier switch includes a P-ch region (13) and a central source P+ region (10). The P-ch region (13) is formed on the upper surface of the N-drift region (3) between the two trenches, and the central source P+ region (10) is formed on the upper surface of the P-ch region (13). Two P-base regions (6) are formed on the upper surface of the N-CSL current extension layer (12). The source N+ region (8) and source P+ region (7) are formed on the upper surface of the P-base region (6) on the left side of the main gate control trench gate (14). Source N+ region (8) and source P+ region (7) are formed on the upper surface of the P-base region (6) on the right side of the source auxiliary trench gate (5). The source metal contact area formed at the top of the device (11). The main gate controlled trench gate (14) is connected to the device gate potential, and the source auxiliary trench gate (5) is electrically connected to the source metal contact region (11). The device integrates a low-barrier MOS channel diode structure, which is composed of the source auxiliary trench gate (5), the trench gate oxide layer (9) surrounding the trench, the P-base region (6) on the right side of the source auxiliary trench gate (5), and the source N+ region (8) connected to the source metal contact region (11) at the top of the P-base region (6). The central source P+ region (10) is in ohmic contact with the source metal contact region (11). The main MOSFET channel structure of the device is composed of a main gate controlled trench gate (14), a P-base region (6) on the left side of the main gate controlled trench gate (14), a source N+ region (8) and a source P+ region (7) on the top of the P-base region (6), an N-CSL current extension layer (12), an N-drift region (3), an N+ substrate region (2), and a drain metal contact region (1).

2. The main-source cooperative gate potential adaptive SiC MOSFET device according to claim 1, characterized in that, When the device is forward-biased, the main gate control trench gate (14) applies a positive bias of +15V relative to the source, forming a transverse depletion electric field with the source auxiliary trench gate (5), completely depleting and pinching off the P-ch region (13), breaking the conductive path between the P-shield region (4) and the central source P+ region (10), so that the P-shield region (4) is in a floating state, suppressing the JFET effect and reducing the specific on-resistance of the device.

3. The SiC MOSFET device with main source co-gate potential adaptive characteristics according to claim 1, characterized in that, When the device is forward blocked, the main gate control trench gate (14) is subjected to a negative bias voltage of 0V or not exceeding 5V. The P-ch region (13) is not depleted. The P-shield region (4) is reliably grounded through the P-ch region (13), the central source P+ region (10) and the source metal contact region (11). The electric field at the bottom of the shield trench gate is concentrated, suppressing the negative charge storage effect and improving the breakdown voltage and long-term reliability of the device.

4. The SiC MOSFET device with main source co-gate potential adaptive characteristics according to claim 1, characterized in that, When the device is reverse freewheeling, the main gate control trench gate (14) is given a negative bias of 0V or no more than 5V, the main channel is kept off, and the source potential of the source auxiliary trench gate (5) is positively biased relative to the negative voltage drain. An N-type inverted channel is formed on the sidewall of the source auxiliary trench gate in the right P-base region (6), forming a low barrier MOS channel diode. The reverse current preferentially flows through this unipolar channel, suppressing the conduction of the parasitic diode and eliminating the bipolar degradation effect.

5. The main-source co-current gate potential adaptive SiC MOSFET device according to claim 1, characterized in that, The main gate controlled trench gate (14) and the source auxiliary trench gate (5) are both wrapped by the trench gate oxide layer (9); the sidewall oxide layer thickness of the main gate controlled trench gate (14) and the source auxiliary trench gate (5) is 0.05μm, which is less than the bottom oxide layer thickness of 0.08μm.

6. The main-source cooperative gate potential adaptive SiC MOSFET device according to claim 5, characterized in that, By adjusting the thickness of the trench gate oxide layer, the gate-source capacitance and gate-drain capacitance of the device can be controlled, thereby balancing the conduction and switching characteristics of the device.

7. The main-source cooperative gate potential adaptive SiC MOSFET device according to claim 1, characterized in that, The P-ch region (13) is made of low-doped P-type SiC, and its doping concentration is lower than that of the P-shield region (4) and the central source P+ region (10).

8. The main-source co-gate potential adaptive SiC MOSFET device according to claim 1, characterized in that, The source metal contact region (11) simultaneously achieves ohmic contact with all source N+ regions (8), all source P+ regions (7), the central source P+ region (10), and the source auxiliary trench gate (5); the drain metal contact region (1) is located on the lower surface of the N+ substrate region (2) and forms an ohmic contact with the N+ substrate region (2).

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