A trench silicon carbide mosfet device with integrated lateral channel

Abstract

The application discloses a trench silicon carbide MOSFET device integrated with a lateral channel and belongs to the technical field of semiconductor power devices. The application integrates lateral channels on both sides or in the center below a trench gate; the application comprises the following parts: an N-type substrate, an N-type epitaxial layer, a P body region, a P+ source region, an N+ source region, a first oxide layer medium, a polysilicon gate, a second oxide layer medium, a source metal and a drain metal. The application integrates lateral channels on both sides or in the center below a SiC MOSFET trench gate, eliminates a high-resistance area at the bottom of a trench when a device is turned on, and makes channels exist on the sidewall and the bottom of the trench, so that the device has a longitudinal channel and a lateral channel simultaneously, the device current density can be greatly improved, and the device on-resistance can be reduced. The structure of the application can effectively improve the first and third quadrant static and dynamic performance of the device, and simultaneously improve the reliability problems of the device, such as the gate oxide quality, the bipolar degradation of the body diode, the short-circuit resistance and the surge current resistance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, and relates to a trench silicon carbide MOSFET device with integrated lateral channel, specifically a trench silicon carbide superjunction MOSFET device with integrated lateral channel and Schottky diode. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, is an ideal material for fabricating high-performance power devices due to its larger bandgap, higher critical breakdown field strength, and higher thermal conductivity. Compared with traditional silicon-based devices, SiC power devices have advantages such as lower on-resistance, faster switching speed, and higher temperature stability, making them ideal for extreme applications such as high frequency, high temperature, and high power.

[0003] However, despite the numerous advantages of silicon carbide power devices, their practical applications still face several challenges. Firstly, with the ever-increasing demands for power density and efficiency in power electronic systems, the inherent contradiction between the on-resistance (Rds(on)) and blocking voltage (BV) of traditional silicon carbide devices means their performance can no longer meet current application requirements. This is particularly true in medium- and high-voltage applications such as traction inverters for new energy vehicles, photovoltaics, energy storage, smart grids, and rail transit. How to further reduce device conduction losses while maintaining a high blocking voltage has become a key challenge for technological development. Secondly, there are issues related to gate oxide quality and long-term reliability. The critical breakdown electric field strength of SiC is ten times that of silicon (Si), forcing the gate oxide to withstand a high electric field, which exponentially increases its lifetime stress. Furthermore, the inherent characteristics of SiC materials and processes result in a much higher defect density in its gate oxide layer than traditional silicon (Si) devices, making it more prone to breakdown under long-term high electric fields. This is a key bottleneck determining the device's lifetime and reliability. Therefore, in practical applications, SiC MOSFET drive circuits require more stringent control over gate voltage overshoot, negative voltage turn-off (to prevent false turn-on and release interface trap charges), and carefully designed gate resistors than silicon devices to balance switching losses and gate oxide stress, ensuring reliable lifetime. Secondly, the body diode exhibits bipolar degradation when in forward conduction or freewheeling mode. This is due to the parasitic BJT effect inside the device. When the body diode is in forward conduction or freewheeling mode, the energy released by electron-hole recombination will cause the pre-existing basal plane dislocations (BPDs) in the drift layer to expand into stacking faults (SFs). These stacking faults act as recombination centers, causing the on-resistance of the device to gradually increase, the forward voltage drop of the body diode to rise, and the reverse recovery characteristics to deteriorate. The degree of degradation intensifies with the increase of accumulated current stress and temperature, and it cannot be ignored, especially in high current density switching applications.

[0004] To address these issues, researchers have proposed several improvement schemes. One such scheme uses a trench-type SiC MOSFET, which eliminates the junction field-effect transistor (JFET) region of planar MOSFETs, reducing on-resistance, cell size, and manufacturing costs. However, the gate oxide at the bottom corner of the trench experiences a higher electric field than in planar structures, which reduces the device's breakdown voltage and long-term gate oxide reliability. To address the bipolar degradation of the body diode, a Schottky barrier diode (SBD) is proposed to be connected in anti-parallel within the SiC MOSFET to prevent the body diode from turning on. However, this increases leakage current, and the integrated Schottky diode has weak surge protection. Therefore, effectively addressing reliability issues such as gate oxide degradation, body diode bipolar degradation, and surge protection while improving the superior performance of SiC MOSFET devices has become a key research focus and challenge. Summary of the Invention

[0005] To address the shortcomings of silicon carbide trench MOSFETs in terms of device performance, structural design, and reliability, this invention proposes an innovative trench silicon carbide superjunction MOSFET device with integrated lateral channel and Schottky diode. This solution has several key features. First, it integrates a lateral channel MOSFET beneath the trench gate, giving the device both longitudinal and lateral channels. Channels exist on the trench gate sidewalls and bottom, significantly increasing the on-current density and reducing on-resistance. Second, it introduces a superjunction structure by using alternating N-pillars and P-pillars in the drift region, improving breakdown voltage, reducing on-resistance, and enhancing short-circuit withstand capability. Third, it integrates a hybrid PiN / Schottky diode (MPS) in the source region to address the bipolar degradation effect of the body diode, reducing leakage current and improving surge current withstand capability. Fourth, it cleverly shorts the P-body region, N+ source region, and source of the lateral channel MOSFET at the bottom of the trench using a selective semi-enclosed structure, effectively suppressing the electric field strength at the bottom of the trench, reducing gate-leakage capacitance, increasing switching speed, and improving gate oxide strength and long-term reliability. This invention enables the fabrication of high-performance, high-reliability trench silicon carbide superjunction MOSFETs, providing a feasible technical path for the commercial application of silicon carbide trench devices.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] A trench silicon carbide MOSFET device with integrated lateral channels, comprising: an N-type substrate; an N-type epitaxial layer above the N-type substrate; a P-body region located at the top of the N-type epitaxial layer and the bottom of the trench; P+ source regions located on both sides of the P-body region; N+ source regions located at the top of the N-type epitaxial layer and the bottom of the trench; a first oxide layer dielectric located inside the trench; a polysilicon gate located at the center of the first oxide layer dielectric; a second oxide layer dielectric located above the N-type epitaxial layer; a source metal located above the N-type epitaxial layer and the second oxide layer dielectric; and a drain metal located below the N-type substrate; wherein the P-body region, P+ source region, and N+ source region are shorted by the source metal.

[0008] Furthermore, the selective regions of the P-body region and N+ source region at the bottom of the trench in the direction perpendicular to the device cell are shorted to the P-body region and N+ source region at the top of the N-type epitaxial layer.

[0009] Furthermore, the N-type epitaxial layer contains a P-pillar region, and the device drift region contains alternating P-pillar and N-pillar superjunction structures.

[0010] Furthermore, the P-body region at the top of the N-type epitaxial layer is selectively injected, and the device source region integrates a unipolar junction barrier Schottky diode.

[0011] Furthermore, the P-body region at the top of the N-type epitaxial layer is selectively implanted, the P+ source region is selectively implanted, and the device source region integrates a hybrid PiN / Schottky diode.

[0012] Furthermore, the P-pillar region is formed through multiple epitaxial ion implantations, and a protruding P-pillar region is provided in the center of the P-pillar region.

[0013] Furthermore, the P-pillar region is located at the bottom of the N-type epitaxial layer, and the superjunction P-pillar region is disposed at the bottom of the N-type epitaxial layer.

[0014] Furthermore, the device gate is configured as a split-gate trench structure, with P-type regions on both sides of the center of the split-gate trench, and a hybrid PiN / Schottky diode integrated in the center of the split-gate trench.

[0015] Furthermore, the P-column region is formed through multiple epitaxial ion implantations or trench filling.

[0016] Furthermore, the P-body region, P+ source region, and N+ source region are formed through multiple ion implantations.

[0017] The beneficial effects of this invention are as follows:

[0018] 1. This invention eliminates the high-resistance region at the bottom of the trench when the device is turned on by integrating lateral channels on both sides or in the center below the trench gate of the SiC MOSFET. Channels exist on both the sidewalls and the bottom of the trench, and the device has both longitudinal and lateral channels, which can greatly improve the on-current density of the device and reduce the on-resistance of the device.

[0019] 2. This invention cleverly shorts the P-body region, N+ source region, and source of the transverse channel MOSFET at the bottom of the trench by setting a selective semi-enclosed structure on the three-dimensional structure. This converts most of the gate-drain capacitance of the device into drain-source capacitance, improves the switching speed of the device, reduces the switching loss of the device, and can effectively suppress the electric field strength at the bottom and corners of the device trench, thereby improving the long-term reliability of the gate oxide dielectric and the device.

[0020] 3. This invention further increases the doping concentration in the drift region by setting alternating P-pillar and N-pillar superjunction structures, thereby reducing the on-resistance and optimizing the device performance; improves the short-circuit withstand capability by setting a protruding P-pillar region in the center of the P-pillar region; and optimizes the electric field and improves the device breakdown voltage by setting the superjunction P-pillar region at the bottom of the N-type epitaxial layer and introducing a new electric field peak.

[0021] 4. This invention solves the bipolar degradation problem of the device body diode by integrating a hybrid PiN / Schottky diode (MPS) in the device source region, reduces the reverse leakage current of the integrated Schottky diode, and improves its surge current resistance. Furthermore, the device gate is configured as a gate trench structure, and a hybrid PiN / Schottky diode (MPS) is integrated in the center of the gate trench to further increase the area of ​​the integrated Schottky diode and reduce the forward voltage drop of the Schottky diode.

[0022] 5. This invention addresses the shortcomings of silicon carbide trench MOSFETs in terms of device performance, structural design, and reliability by innovatively proposing a gate-splitting trench silicon carbide superjunction MOSFET device with an integrated lateral channel and a Schottky diode. The new structure integrates a central lateral channel at the bottom of the trench. Existing trench silicon carbide superjunction MOSFETs with integrated lateral channels typically have two side channels, which can lead to current congestion when the device is turned on, negatively impacting thermal stability. The central lateral channel integrated at the bottom of the trench in the new structure improves both device performance and reliability of the trench silicon carbide MOSFET. The current paths of the lateral and longitudinal channels are independent, preventing current congestion and eliminating the high-resistance region at the bottom of the trench when the device is turned on. Compared to existing silicon carbide trench MOSFETs, the new structure can effectively improve the device's static and dynamic performance in the first and third quadrants, while also improving reliability issues such as gate oxide quality, body diode bipolar degradation, short-circuit resistance, and surge current capability. It overcomes the technical bias of existing technologies that make it impossible to achieve both high performance and high reliability, and provides a feasible technical path for the localization and commercial application of silicon carbide trench MOSFET devices. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a trench silicon carbide MOSFET device structure with integrated lateral channels on both sides, as proposed in Example 1, where A is the cell structure and B is the selective semi-enclosed short-circuit region structure.

[0024] Figure 2 This is a schematic diagram of a trench silicon carbide MOSFET device structure with an integrated central lateral channel proposed in Example 2, where A is the cell structure and B is the selective semi-enclosed short-circuit region structure.

[0025] Figure 3 This is a schematic diagram of a trench silicon carbide superjunction MOSFET device with an integrated central lateral channel proposed in Example 3, where A is the cell structure and B is the selective semi-enclosed short-circuit region structure.

[0026] Figure 4 This is a schematic diagram of a trench silicon carbide superjunction MOSFET device structure with an integrated central lateral channel and a Schottky diode, as proposed in Example 4, where A is the cell structure and B is the selective semi-enclosed short-circuit region structure.

[0027] Figure 5 This is a schematic diagram of a trench silicon carbide superjunction MOSFET device structure with an integrated central lateral channel and a hybrid PiN / Schottky diode (MPS) proposed in Example 5, where A is the cell structure and B is the selective half-enclosed short-circuit region structure;

[0028] Figure 6This is a schematic diagram of a trench silicon carbide bumped superjunction MOSFET device structure with an integrated central lateral channel and a hybrid PiN / Schottky diode (MPS) proposed in Example 6, where A is the cell structure and B is the selective half-enclosed short-circuit region structure;

[0029] Figure 7 This is a schematic diagram of a trench silicon carbide bottom superjunction MOSFET device structure with an integrated central lateral channel and a hybrid PiN / Schottky diode (MPS) proposed in Example 7, where A is the cell structure and B is the selective half-enclosed short-circuit region structure;

[0030] Figure 8 This is a schematic diagram of a gated trench silicon carbide bottom superjunction MOSFET device structure with an integrated central lateral channel and a hybrid PiN / Schottky diode (MPS) proposed in Example 8. In the diagram, A is the cell structure, B is the selective half-enclosed short-circuit region structure, the solid lines in the figure represent the MOS current flow, the straight lines on the trench sidewalls represent the longitudinal channel, and the broken lines at the bottom of the trench represent the lateral channel; the dashed lines represent the Schottky diode current flow.

[0031] List of identifiers in attached diagrams:

[0032] 1-N-type substrate, 2-N-type epitaxial layer, 3-P-pillar region, 4-P-body region, 5-P+ source region, 6-N+ source region, 7-first oxide layer dielectric, 8-polysilicon gate, 9-second oxide layer dielectric, 10-source metal, 11-drain metal, 12-P-type region. Detailed Implementation

[0033] The technical solutions provided by the present invention will be described in detail below with reference to specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0034] The following examples all use a single cell as an example to illustrate the trench silicon carbide MOSFET device with integrated lateral channel.

[0035] Example 1:

[0036] like Figure 1 As shown, A is a schematic diagram of the cell structure of a trench silicon carbide MOSFET device with integrated lateral channels on both sides, and B is a schematic diagram of the selective half-enclosed short-circuit region structure of a trench silicon carbide MOSFET device with integrated lateral channels on both sides. The device includes: an N-type substrate 1, an N-type epitaxial layer 2, a P-body region 4, a P+ source region 5, an N+ source region 6, a first oxide dielectric layer 7, a polysilicon gate 8, a second oxide dielectric layer 9, a source metal 10, and a drain metal 11.

[0037] In this structure, the N-type epitaxial layer 2 is located above the N-type substrate 1; the P-body region 4 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench; the P+ source region 5 is located on both sides of the P-body region 4; and the N+ source region 6 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench. The P-body region 4, P+ source region 5, and N+ source region 6 are formed through multiple ion implantations. The first oxide layer dielectric 7 is located inside the trench; the polysilicon gate 8 is located in the center of the first oxide layer dielectric 7; and the second oxide layer dielectric 9 is located above the N-type epitaxial layer 2. The source metal 10 is located above the N-type epitaxial layer 2 and the second oxide layer dielectric 9; and the drain metal 11 is located below the N-type substrate 1. The P-body region 4, P+ source region 5, and N+ source region 6 are shorted by the source metal 10, wherein the selective regions of the P-body region 4 and N+ source region 6 at the bottom of the trench in the direction perpendicular to the device cell are shorted to the P-body region 4 and N+ source region 6 at the top of the N-type epitaxial layer 2. In Embodiment 1 of the present invention, the N-type substrate 1, the N-type epitaxial layer 2, the P-body region 4, the N+ source region 6, the polysilicon gate 8, the source metal 10, and the drain metal 11 are used for conducting electricity.

[0038] This example integrates a lateral channel MOSFET under the trench gate. The device has both longitudinal and lateral channels, with channels present on the sidewalls and bottom of the trench gate. This can greatly increase the device's on-current density and reduce its on-resistance. By setting a selective semi-enclosed structure, the P-body region, N+ source region, and source of the lateral channel MOSFET at the bottom of the trench are cleverly shorted, converting most of the gate-drain capacitance into drain-source capacitance. This reduces the device's Miller capacitance, increases the device's switching speed, reduces the device's switching losses, and can effectively suppress the electric field strength at the bottom of the trench, improving the gate oxide dielectric and the long-term reliability of the device.

[0039] Example 2:

[0040] Example 1 integrates a lateral channel MOSFET below the trench gate, reducing the device's on-resistance. By cleverly shorting the P-body region, N+ source region, and source of the lateral channel MOSFET at the bottom of the trench using a selective semi-enclosed structure, the electric field strength at the bottom of the trench is effectively suppressed. However, when this structure is turned on, the current paths of the lateral and longitudinal channels overlap, causing current congestion, which is detrimental to the device's thermal stability. A high-resistance region exists at the bottom of the trench, and the P-body region of the lateral channel at the bottom of the trench cannot adequately protect the gate oxide layer at the corner of the trench bottom. Therefore, this invention proposes a second trench silicon carbide device structure with an integrated lateral channel.

[0041] like Figure 2As shown, A is a schematic diagram of the cell structure of a trench silicon carbide MOSFET device with an integrated central lateral channel, and B is a schematic diagram of the selective semi-enclosed short-circuit region structure of a trench silicon carbide MOSFET device with an integrated central lateral channel. The device includes: an N-type substrate 1, an N-type epitaxial layer 2, a P-body region 4, a P+ source region 5, an N+ source region 6, a first oxide dielectric layer 7, a polysilicon gate 8, a second oxide dielectric layer 9, a source metal 10, and a drain metal 11.

[0042] The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-body region 4 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench; the P+ source region 5 is located on both sides of the P-body region 4; and the N+ source region 6 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench. The P-body region 4, P+ source region 5, and N+ source region 6 are formed through multiple ion implantations. The first oxide layer dielectric 7 is located inside the trench; the polysilicon gate 8 is located in the center of the first oxide layer dielectric 7; and the second oxide layer dielectric 9 is located above the N-type epitaxial layer 2. The source metal 10 is located above the N-type epitaxial layer 2 and the second oxide layer dielectric 9; and the drain metal 11 is located below the N-type substrate 1. The P-body region 4, P+ source region 5, and N+ source region 6 are shorted through the source metal 10, wherein the selective regions of the P-body region 4 and N+ source region 6 at the bottom of the trench in the direction perpendicular to the device cell are shorted to the P-body region 4 and N+ source region 6 at the top of the N-type epitaxial layer 2. In Embodiment 2 of the present invention, the N-type substrate 1, the N-type epitaxial layer 2, the P-body region 4, the N+ source region 6, the polysilicon gate 8, the source metal 10, and the drain metal 11 are used for conducting electricity.

[0043] This example integrates another type of lateral channel MOSFET under the trench gate. This structure also has the following advantages of Example 1: Firstly, the integration of the lateral channel MOSFET under the trench gate reduces the device's on-resistance. Secondly, by cleverly setting a selective semi-enclosed structure, the P-body region, N+ source region, and source of the lateral channel MOSFET at the bottom of the trench are shorted, converting most of the gate-drain capacitance into drain-source capacitance, reducing Miller capacitance, improving switching speed, and reducing switching losses. Thirdly, the current paths of the lateral and longitudinal channels in Example 2 are independent, preventing current congestion and eliminating the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, further increasing the on-current density and reducing on-resistance. Fourthly, the P-body region of the lateral channel MOSFET at the bottom of the trench can better suppress the electric field strength at the corner of the trench bottom, improving the overall gate oxide and long-term reliability of the device.

[0044] Example 3:

[0045] Example 2 integrates a lateral channel MOSFET below the trench gate, eliminating the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, thus reducing the device's on-resistance. By cleverly using a selective semi-enclosed structure to short-circuit the P-body region, N+ source region, and source of the lateral channel MOSFET at the bottom of the trench, the electric field strength at the corner of the trench bottom is effectively suppressed, improving the gate oxide dielectric and the long-term reliability of the device. To further reduce the device's on-resistance and increase its breakdown voltage, this invention proposes a third lateral channel integrated trench silicon carbide superjunction device structure.

[0046] like Figure 3 As shown, A is a schematic diagram of the cell structure of a trench silicon carbide superjunction MOSFET device with an integrated central lateral channel, and B is a schematic diagram of the selective semi-enclosed short-circuit region structure of a trench silicon carbide superjunction MOSFET device with an integrated central lateral channel, including: N-type substrate 1, N-type epitaxial layer 2, P-pillar region 3, P-body region 4, P+ source region 5, N+ source region 6, first oxide layer dielectric 7, polysilicon gate 8, second oxide layer dielectric 9, source metal 10, and drain metal 11.

[0047] The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-pillar region 3 is located inside the N-type epitaxial layer 2; the P-pillar region 3 can be formed by multiple epitaxial ion implantations or trench filling. The P-body region 4 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench; the P+ source region 5 is located on both sides of the P-body region 4; the N+ source region 6 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench; the P-body region 4, P+ source region 5, and N+ source region 6 are formed by multiple ion implantations. The first oxide layer dielectric 7 is located inside the trench; the polysilicon gate 8 is located in the center of the first oxide layer dielectric 7; the second oxide layer dielectric 9 is located above the N-type epitaxial layer 2. The source metal 10 is located above the N-type epitaxial layer 2 and the second oxide layer dielectric 9; the drain metal 11 is located below the N-type substrate 1. P-body region 4, P+ source region 5, and N+ source region 6 are shorted by source metal 10. Selective regions of P-body region 4 and N+ source region 6 at the bottom of the trench, perpendicular to the device cell direction, are shorted to P-body region 4 and N+ source region 6 at the top of the N-type epitaxial layer 2. In embodiment 3 of the present invention, the N-type substrate 1, N-type epitaxial layer 2, P-body region 4, N+ source region 6, polysilicon gate 8, source metal 10, and drain metal 11 are used for conductivity.

[0048] This example proposes a trench silicon carbide superjunction MOSFET device with an integrated lateral channel. This structure combines the advantages of embodiments 1-2: integrating the lateral channel MOSFET below the trench gate eliminates the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, reducing the device's on-resistance; by cleverly setting a selective half-enclosed structure, the P-body region, N+ source region, and source of the lateral channel MOSFET at the bottom of the trench are shorted, converting most of the gate-drain capacitance into drain-source capacitance, improving the device's switching speed, reducing switching losses, and effectively suppressing the electric field strength at the corner of the trench bottom. Furthermore, embodiment 3 sets an alternating P-pillar and N-pillar superjunction structure in the device's drift region, which can further increase the doping concentration in the drift region, reduce the device's on-resistance, and optimize device performance.

[0049] Example 4:

[0050] Example 3 integrates a lateral channel MOSFET below the trench gate, eliminating the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, thus reducing the on-resistance of the device. Alternating P-pillar and N-pillar superjunction structures are set in the device drift region to further optimize device performance. However, the body diode in the above device structure exhibits bipolar degradation under forward conduction or freewheeling states. To address this issue, this invention proposes a fourth trench silicon carbide superjunction device structure integrating a lateral channel and a Schottky diode.

[0051] like Figure 4 As shown, A is a schematic diagram of the cell structure of a trench silicon carbide superjunction MOSFET device with an integrated central lateral channel and a Schottky diode, and B is a schematic diagram of the selective half-enclosed short-circuit region structure of a trench silicon carbide superjunction MOSFET device with an integrated central lateral channel and a Schottky diode, including: N-type substrate 1, N-type epitaxial layer 2, P-pillar region 3, P-body region 4, P+ source region 5, N+ source region 6, first oxide layer dielectric 7, polysilicon gate 8, second oxide layer dielectric 9, source metal 10, and drain metal 11.

[0052] The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-pillar region 3 is located inside the N-type epitaxial layer 2; the P-pillar region 3 can be formed by multiple epitaxial ion implantations or trench filling. The P-body region 4 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench, with the P-body region 4 at the top of the N-type epitaxial layer 2 being selectively implanted. The P+ source region 5 is located on both sides of the P-body region 4; the N+ source region 6 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench. The P-body region 4, P+ source region 5, and N+ source region 6 are formed by multiple ion implantations. The first oxide layer dielectric 7 is located inside the trench; the polysilicon gate 8 is located in the center of the first oxide layer dielectric 7; the second oxide layer dielectric 9 is located above the N-type epitaxial layer 2. The source metal 10 is located above the N-type epitaxial layer 2 and the second oxide layer dielectric 9; the drain metal 11 is located below the N-type substrate 1. P-body region 4, N-type epitaxial layer 2, P+ source region 5, and N+ source region 6 between P-body regions 4 are shorted by source metal 10. Selective regions of P-body region 4 and N+ source region 6 at the bottom of the trench, perpendicular to the device cell direction, are shorted to P-body region 4 and N+ source region 6 at the top of N-type epitaxial layer 2. In embodiment 4 of the present invention, N-type substrate 1, N-type epitaxial layer 2, P-body region 4, N+ source region 6, polysilicon gate 8, source metal 10, and drain metal 11 are used for conductivity.

[0053] This example presents a trench silicon carbide superjunction MOSFET device with integrated lateral channel and Schottky diode. This structure combines the advantages of embodiments 1-3: integrating the lateral channel MOSFET below the trench gate eliminates the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, reducing the device's on-resistance; cleverly using a selective semi-enclosed structure to short-circuit the P-body region, N+ source region, and source of the lateral channel MOSFET at the bottom of the trench, converting most of the gate-drain capacitance into drain-source capacitance, improving the device's switching speed, reducing switching losses, and effectively suppressing the electric field strength at the bottom and corners of the trench; and employing alternating P-pillar and N-pillar superjunction structures in the device's drift region further increases the doping concentration in the drift region, reduces the device's on-resistance, and optimizes device performance. Secondly, in embodiment 4, a unipolar junction barrier Schottky diode (JBS) is integrated in the source region of the device. Since the turn-on voltage of the Schottky diode is lower than that of the body diode, only the Schottky diode integrated in the source region is turned on when the device is operating in the third quadrant, which can effectively solve the bipolar degradation problem of the body diode.

[0054] Example 5:

[0055] Example 4 integrates a lateral channel MOSFET below the trench gate, eliminating the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, thus reducing the on-resistance of the device. Alternating P-pillar and N-pillar superjunction structures are set in the device drift region to further optimize device performance. A unipolar junction barrier Schottky diode (JBS) is integrated in the device source region, effectively solving the bipolar degradation problem of the device body diode. However, the unipolar junction barrier Schottky diode (JBS) integrated in the source region of the above device structure has a large reverse leakage current and weak surge resistance. To solve the above problems, this invention proposes a fifth trench silicon carbide superjunction device structure integrating a lateral channel and a Schottky diode.

[0056] like Figure 5 As shown, A is a schematic diagram of the cell structure of a trench silicon carbide superjunction MOSFET device with an integrated central lateral channel and a hybrid PiN / Schottky diode MPS, and B is a schematic diagram of the selective half-enclosed short-circuit region structure of a trench silicon carbide superjunction MOSFET device with an integrated central lateral channel and a hybrid PiN / Schottky diode MPS, including: N-type substrate 1, N-type epitaxial layer 2, P-pillar region 3, P-body region 4, P+ source region 5, N+ source region 6, first oxide layer dielectric 7, polysilicon gate 8, second oxide layer dielectric 9, source metal 10, and drain metal 11.

[0057] The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-pillar region 3 is located inside the N-type epitaxial layer 2; the P-pillar region 3 can be formed by multiple epitaxial ion implantations or trench filling. The P-body region 4 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench, with the P-body region 4 at the top of the N-type epitaxial layer 2 being selectively implanted. The P+ source region 5 is located on both sides of the P-body region 4, and the P+ source region 5 is selectively implanted; the N+ source region 6 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench. The P-body region 4, P+ source region 5, and N+ source region 6 are formed by multiple ion implantations. The first oxide layer dielectric 7 is located inside the trench; the polysilicon gate 8 is located in the center of the first oxide layer dielectric 7; the second oxide layer dielectric 9 is located above the N-type epitaxial layer 2. The source metal 10 is located above the N-type epitaxial layer 2 and the second oxide layer dielectric 9; the drain metal 11 is located below the N-type substrate 1. P-body region 4, N-type epitaxial layer 2, P+ source region 5, and N+ source region 6 between P-body regions 4 are shorted by source metal 10. Selective regions of P-body region 4 and N+ source region 6 at the bottom of the trench, perpendicular to the device cell direction, are shorted to P-body region 4 and N+ source region 6 at the top of N-type epitaxial layer 2. In embodiment 5 of the present invention, N-type substrate 1, N-type epitaxial layer 2, P-body region 4, N+ source region 6, polysilicon gate 8, source metal 10, and drain metal 11 are used for conductivity.

[0058] This example presents a trench silicon carbide superjunction MOSFET device with integrated lateral channel and Schottky diode. This structure combines the advantages of embodiments 1-4: integrating the lateral channel MOSFET below the trench gate eliminates the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, reducing the device's on-resistance; cleverly using a selective semi-enclosed structure to short-circuit the P-body region, N+ source region, and source of the lateral channel MOSFET at the bottom of the trench, converting most of the gate-drain capacitance into drain-source capacitance, improving the device's switching speed, reducing switching losses, and effectively suppressing the electric field strength at the bottom and corners of the trench; and employing alternating P-pillar and N-pillar superjunction structures in the device's drift region further increases the doping concentration in the drift region, reduces the device's on-resistance, and optimizes device performance. Secondly, in Example 5, a hybrid PiN / Schottky diode (MPS) is integrated in the source region of the device. On the one hand, this can effectively solve the bipolar degradation problem of the device body diode; on the other hand, it can reduce the reverse leakage current of the unipolar junction barrier Schottky diode (JBS) integrated in the source region of Example 4 and improve its surge current resistance.

[0059] Example 6:

[0060] Example 5 integrates a lateral channel MOSFET below the trench gate, eliminating the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, thus reducing the on-resistance of the device. Alternating P-pillar and N-pillar superjunction structures are set in the device drift region to further optimize device performance. A hybrid PiN / Schottky diode (MPS) is integrated in the device source region, effectively solving the bipolar degradation problem of the device body diode, reducing the reverse leakage current of the integrated Schottky diode, and improving its surge current resistance. However, the above device structure has a large on-state current and is prone to failure under short-circuit conditions. To solve the above problems, this invention proposes a sixth trench silicon carbide superjunction device structure integrating a lateral channel and a Schottky diode.

[0061] like Figure 6 As shown, A is a schematic diagram of the cell structure of a trench silicon carbide bumped superjunction MOSFET device with an integrated central lateral channel and a hybrid PiN / Schottky diode (MPS), and B is a schematic diagram of the selective half-enclosed short-circuit region structure of a trench silicon carbide bumped superjunction MOSFET device with an integrated central lateral channel and a hybrid PiN / Schottky diode (MPS), including: N-type substrate 1, N-type epitaxial layer 2, P-pillar region 3, P-body region 4, P+ source region 5, N+ source region 6, first oxide layer dielectric 7, polysilicon gate 8, second oxide layer dielectric 9, source metal 10, and drain metal 11.

[0062] The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-pillar region 3 is located inside the N-type epitaxial layer 2; the P-pillar region 3 is formed by multiple epitaxial ion implantations, with a protruding P-pillar region implanted in the center of the P-pillar region. The P-body region 4 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench, with the P-body region 4 at the top of the N-type epitaxial layer 2 being selectively implanted. The P+ source region 5 is located on both sides of the P-body region 4, with the P+ source region 5 being selectively implanted; the N+ source region 6 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench. The P-body region 4, P+ source region 5, and N+ source region 6 are formed by multiple ion implantations. The first oxide layer dielectric 7 is located inside the trench; the polysilicon gate 8 is located in the center of the first oxide layer dielectric 7; the second oxide layer dielectric 9 is located above the N-type epitaxial layer 2. The source metal 10 is located above the N-type epitaxial layer 2 and the second oxide layer dielectric 9; the drain metal 11 is located below the N-type substrate 1. P-body region 4, N-type epitaxial layer 2, P+ source region 5, and N+ source region 6 between P-body regions 4 are shorted by source metal 10. Selective regions of P-body region 4 and N+ source region 6 at the bottom of the trench, perpendicular to the device cell direction, are shorted to P-body region 4 and N+ source region 6 at the top of N-type epitaxial layer 2. In embodiment 6 of the present invention, N-type substrate 1, N-type epitaxial layer 2, P-body region 4, N+ source region 6, polysilicon gate 8, source metal 10, and drain metal 11 are used for conductivity.

[0063] This example presents a trench silicon carbide superjunction MOSFET device with integrated lateral channel and Schottky diode. This structure combines the advantages of embodiments 1-5: integrating the lateral channel MOSFET below the trench gate eliminates the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, reducing the device's on-resistance; cleverly using a selective half-enclosed structure to short-circuit the P-body region, N+ source region, and source of the lateral channel MOSFET at the bottom of the trench, converting most of the gate-drain capacitance into drain-source capacitance, improving the device's switching speed, reducing switching losses, and effectively suppressing the electric field strength at the bottom and corners of the trench; the alternating P-pillar and N-pillar superjunction structure in the device's drift region further increases the doping concentration in the drift region, reduces the device's on-resistance, and optimizes device performance; and the integration of a hybrid PiN / Schottky diode (MPS) in the device's source region solves the bipolar degradation problem of the device's body diode, reduces the reverse leakage current of the integrated Schottky diode, and improves its surge current resistance. Secondly, in embodiment 6, a protruding P-pillar region is provided in the center of the superjunction P-pillar region. When the MOS structure of the device is turned on, the saturation current can be reduced, thereby effectively improving the short-circuit withstand capability of the device.

[0064] Example 7:

[0065] The device structures in Examples 1-6 achieve the following optimizations: a lateral channel MOSFET is integrated below the trench gate, eliminating the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, thus reducing the on-resistance of the device; alternating P-pillar and N-pillar superjunction structures are set in the device drift region, further optimizing device performance; a hybrid PiN / Schottky diode (MPS) is integrated in the device source region, effectively solving the bipolar degradation problem of the device body diode, reducing the reverse leakage current of the integrated Schottky diode, and improving its surge current resistance; a protruding P-pillar region is set in the center of the superjunction P-pillar region, improving the device's short-circuit withstand capability. To further improve the device breakdown voltage, this invention proposes a seventh trench silicon carbide bottom superjunction device structure integrating a lateral channel and a Schottky diode.

[0066] like Figure 7 As shown, A is a schematic diagram of the cell structure of a trench silicon carbide bottom superjunction MOSFET device with an integrated central lateral channel and a hybrid PiN / Schottky diode (MPS), and B is a schematic diagram of the selective semi-enclosed short-circuit region structure of a trench silicon carbide bottom superjunction MOSFET device with an integrated central lateral channel and a hybrid PiN / Schottky diode (MPS), including: N-type substrate 1, N-type epitaxial layer 2, P-pillar region 3, P-body region 4, P+ source region 5, N+ source region 6, first oxide layer dielectric 7, polysilicon gate 8, second oxide layer dielectric 9, source metal 10, and drain metal 11.

[0067] The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-pillar region 3 is located at the bottom of the N-type epitaxial layer 2; the P-pillar region 3 can be formed by multiple epitaxial ion implantations or trench filling. The P-body region 4 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench, with the P-body region 4 at the top of the N-type epitaxial layer 2 being selectively implanted. The P+ source region 5 is located on both sides of the P-body region 4, and the P+ source region 5 is selectively implanted; the N+ source region 6 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench; the P-body region 4, P+ source region 5, and N+ source region 6 are formed by multiple ion implantations. The first oxide layer dielectric 7 is located inside the trench; the polysilicon gate 8 is located in the center of the first oxide layer dielectric 7; the second oxide layer dielectric 9 is located above the N-type epitaxial layer 2. The source metal 10 is located above the N-type epitaxial layer 2 and the second oxide layer dielectric 9; the drain metal 11 is located below the N-type substrate 1. The P-body region 4, the N-type epitaxial layer 2, the P+ source region 5, and the N+ source region 6 between the P-body regions 4 are shorted by the source metal 10. Selective regions of the P-body region 4 and the N+ source region 6 at the bottom of the trench, perpendicular to the device cell direction, are shorted to the P-body region 4 and the N+ source region 6 at the top of the N-type epitaxial layer 2. In Embodiment 7 of the present invention, the N-type substrate 1, the N-type epitaxial layer 2, the P-body region 4, the N+ source region 6, the polysilicon gate 8, the source metal 10, and the drain metal 11 are used for conductivity.

[0068] This example presents a trench silicon carbide bottom superjunction MOSFET device with integrated lateral channel and Schottky diode. This structure combines the advantages of embodiments 1-6 as follows: Integrating a lateral channel MOSFET below the trench gate eliminates the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, reducing the device's on-resistance; By cleverly shorting the P-body region, N+ source region, and source of the trench-bottom lateral channel MOSFET using a selective half-enclosed structure, most of the gate-drain capacitance is converted into drain-source capacitance, improving the device's switching speed, reducing switching losses, and effectively suppressing the electric field strength at the bottom and corners of the trench; Alternating P-pillar and N-pillar superjunction structures are set in the device's drift region, further increasing the doping concentration in the drift region, reducing the device's on-resistance, and optimizing device performance; A hybrid PiN / Schottky diode (MPS) is integrated in the device's source region, solving the bipolar degradation problem of the device's body diode, reducing the reverse leakage current of the integrated Schottky diode, and improving its surge current resistance. Secondly, in embodiment 7, the superjunction P-pillar region is placed at the bottom of the N-type epitaxial layer. By introducing a new electric field peak, the electric field is optimized and the device breakdown voltage is improved.

[0069] Example 8:

[0070] The device structures in Examples 1-7 achieve the following optimizations: a lateral channel MOSFET is integrated below the trench gate, eliminating the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, thus reducing the on-resistance of the device; alternating P-pillar and N-pillar superjunction structures are set in the device drift region, further optimizing device performance; a hybrid PiN / Schottky diode (MPS) is integrated in the device source region, effectively solving the bipolar degradation problem of the device body diode, reducing the reverse leakage current of the integrated Schottky diode, and improving its surge current resistance; a protruding P-pillar region is set in the center of the superjunction P-pillar region, improving the device's short-circuit withstand capability; the superjunction P-pillar region is set at the bottom, optimizing the electric field by introducing a new electric field peak, thus improving the device's breakdown voltage. To further reduce the on-state voltage drop of the integrated Schottky diode and increase the device switching frequency, this invention proposes an eighth trench-gate silicon carbide bottom superjunction device structure integrating a lateral channel and a Schottky diode.

[0071] like Figure 8As shown, A is a schematic diagram of the cell structure of a gate trench silicon carbide bottom superjunction MOSFET device with an integrated central lateral channel and a hybrid PiN / Schottky diode (MPS), and B is a schematic diagram of the selective semi-enclosed short-circuit region structure of a gate trench silicon carbide bottom superjunction MOSFET device with an integrated central lateral channel and a hybrid PiN / Schottky diode (MPS), including: N-type substrate 1, N-type epitaxial layer 2, P-pillar region 3, P-body region 4, P+ source region 5, N+ source region 6, P-type region 12, first oxide layer dielectric 7, polysilicon gate 8, second oxide layer dielectric 9, source metal 10, and drain metal 11.

[0072] The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-pillar region 3 is located at the bottom of the N-type epitaxial layer 2, and the P-pillar region 3 can be formed by multiple epitaxial ion implantations or trench filling. The P-body region 4 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench, and the P-body region 4 at the top of the N-type epitaxial layer 2 is selectively implanted. The P+ source region 5 is located on both sides of the P-body region 4; the P+ source region 5 is selectively implanted; the N+ source region 6 is located at the top of the N-type epitaxial layer 2 and the bottom of the trench; the P-type region 12 is located on both sides of the center of the gate trench; the P-body region 4, P+ source region 5, N+ source region 6, and P-type region 12 are formed by multiple ion implantations. The first oxide layer dielectric 7 is located inside the trench; the polysilicon gate 8 is located in the center of the first oxide layer dielectric 7; the second oxide layer dielectric 9 is located above the N-type epitaxial layer 2. The source metal 10 is located above the N-type epitaxial layer 2 and the second oxide layer dielectric 9; the drain metal 11 is located below the N-type substrate 1. P-body region 4, N-type epitaxial layer 2, P+ source region 5, N+ source region 6, and P-type region 12 between P-body regions 4 are shorted by source metal 10. Selective regions of P-body region 4 and N+ source region 6 at the bottom of the trench, perpendicular to the device cell direction, are shorted to P-body region 4 and N+ source region 6 at the top of N-type epitaxial layer 2. In embodiment 8 of the present invention, N-type substrate 1, N-type epitaxial layer 2, P-body region 4, N+ source region 6, polysilicon gate 8, source metal 10, and drain metal 11 are used for conductivity.

[0073] This example presents a gate trench silicon carbide bottom superjunction MOSFET device with integrated lateral channel and Schottky diode. This structure possesses the following advantages of embodiments 1-7: Integrating a lateral channel MOSFET below the trench gate eliminates the high-resistance region at the bottom of the trench when the trench MOSFET is turned on, reducing the device's on-resistance; cleverly shorting the P-body region, N+ source region, and source of the lateral channel MOSFET at the bottom of the trench using a selective semi-enclosed structure converts most of the gate-drain capacitance into drain-source capacitance, improving switching speed, reducing switching losses, and effectively suppressing the electric field strength at the bottom and corners of the trench; setting alternating P-pillar and N-pillar superjunction structures in the device drift region further increases the doping concentration in the drift region, reduces the device's on-resistance, optimizes device performance, and places the superjunction P-pillar region at the bottom of the N-type epitaxial layer, introducing new electric field peaks to optimize the electric field and improve the device's breakdown voltage; integrating a hybrid PiN / Schottky diode (MPS) in the device source region solves the bipolar degradation problem of the device body diode, reduces the reverse leakage current of the integrated Schottky diode, and improves its surge current resistance. Secondly, in embodiment 8, the device gate is configured as a split-gate trench structure, and a hybrid PiN / Schottky diode (MPS) is integrated in the center of the split-gate trench. This can further increase the area of ​​the integrated Schottky diode, reduce the forward voltage drop of the Schottky diode, and improve the switching frequency of the device.

[0074] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A trench silicon carbide MOSFET device with integrated lateral channel, characterized in that, A transverse trench is integrated on both sides or in the center below the trench gate; including: an N-type substrate (1); an N-type epitaxial layer (2) above the N-type substrate (1); a P-body region (4) at the top of the N-type epitaxial layer (2) and the bottom of the trench; a P+ source region (5) on both sides of the P-body region (4); an N+ source region (6) at the top of the N-type epitaxial layer (2) and the bottom of the trench; a first oxide layer dielectric (7) inside the trench; a polysilicon gate (8) in the center of the first oxide layer dielectric (7); a second oxide layer dielectric (9) above the N-type epitaxial layer (2); a source metal (10) above the N-type epitaxial layer (2) and the second oxide layer dielectric (9); and a drain metal (11) below the N-type substrate (1); the P-body region (4), the P+ source region (5), and the N+ source region (6) are shorted by the source metal (10).

2. The trench silicon carbide MOSFET device with integrated lateral channel according to claim 1, characterized in that, The selective regions of the P-body region (4) and N+ source region (6) at the bottom of the trench in the direction perpendicular to the device cell are shorted to the P-body region (4) and N+ source region (6) at the top of the N-type epitaxial layer (2).

3. The trench silicon carbide MOSFET device with integrated lateral channel according to claim 1 or 2, characterized in that, The N-type epitaxial layer (2) has a P-pillar region (3) inside, and the device drift region has an alternating P-pillar and N-pillar superjunction structure.

4. The trench silicon carbide MOSFET device with integrated lateral channel according to claim 3, characterized in that, The P-body region (4) at the top of the N-type epitaxial layer (2) is selectively injected, and the source region of the device integrates a unipolar junction barrier Schottky diode.

5. The trench silicon carbide MOSFET device with integrated lateral channel according to claim 3, characterized in that, The P-body region (4) at the top of the N-type epitaxial layer (2) is selectively injected, and the P+ source region (5) is selectively injected. The device source region integrates a hybrid PiN / Schottky diode.

6. The trench silicon carbide MOSFET device with integrated lateral channel according to claim 5, characterized in that, The P-pillar region (3) is formed by multiple epitaxial ion implantations, and a protruding P-pillar region is provided in the center of the P-pillar region.

7. The trench silicon carbide MOSFET device with integrated lateral channel according to claim 5, characterized in that, The P-pillar region (3) is located at the bottom of the N-type epitaxial layer (2), and the superjunction P-pillar region is set at the bottom of the N-type epitaxial layer.

8. The trench silicon carbide MOSFET device with integrated lateral channel according to claim 7, characterized in that, The device gate is configured as a split-gate trench structure, with P-type regions (12) on both sides of the center of the split-gate trench, and a hybrid PiN / Schottky diode is integrated in the center of the split-gate trench.

9. The trench silicon carbide MOSFET device with integrated lateral channel according to claim 3, characterized in that, The P-column region (3) is formed by multiple epitaxial ion implantations or trench filling.

10. The trench silicon carbide MOSFET device with integrated lateral channel according to claim 1, characterized in that, The P-body region (4), P+ source region (5), and N+ source region (6) are formed through multiple ion implantations.

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