Thin film transistor and method of manufacturing the same

Abstract

The present disclosure provides a thin film transistor. The thin film transistor comprises a substrate, an indium gallium zinc oxide (IGZO) active layer, a gate insulating layer and a gate electrode. Ions are implanted in the source region and the drain region. The source region comprises a first ion concentration region and a second ion concentration region, the second ion concentration region is closer to the channel, and the ion concentration of the first ion concentration region is greater than that of the second ion concentration region. The drain region comprises a third ion concentration region and a fourth ion concentration region, the fourth ion concentration region is closer to the channel, and the ion concentration of the third ion concentration region is greater than that of the fourth ion concentration region. The technical scheme is characterized in that a gradient ion concentration distribution is constructed in the source region and the drain region, specifically, low-concentration ion doping is adopted in the region close to the channel, and high-concentration ion doping is adopted in the region far from the channel. By utilizing the diffusion mechanism of the concentration gradient, the transverse diffusion speed is inhibited, and the loss of the effective channel length is significantly compressed.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to thin-film transistors and methods for their fabrication. Background Technology

[0002] Top-gate IGZO devices are thin-film transistors (TFTs) based on indium gallium zinc oxide (IGZO) material, widely used in modern displays (such as OLEDs and LCDs) and flexible electronic devices. Their core advantage lies in the high electron mobility of IGZO material, enabling higher resolution and lower power consumption compared to traditional amorphous silicon (a-Si) devices.

[0003] As display technology evolves towards miniaturization and high density, the manufacturing process of top-gate IGZO TFTs is also constantly being optimized. Among these processes, ion implantation technology, due to its elimination of complex masking and metal deposition steps, is widely used for source and drain conductor fabrication. This technology selectively alters the electrical properties of localized areas of IGZO through high-energy ion bombardment, directly forming low-resistivity electrode regions. This not only simplifies the manufacturing process but also avoids interface damage that can occur with traditional etching processes, significantly improving device integration and production efficiency. However, with the continuous miniaturization of pixel sizes, the device channel length is also decreasing, posing unprecedented challenges to process accuracy and material stability.

[0004] Research has found that the electrical performance of devices can experience unexpected degradation. Specifically, the gate's control over the conductive channel decreases significantly, and the leakage current between the source and drain gradually increases with prolonged operation, leading to image retention, uneven brightness, and even abnormally high power consumption on the display screen. This reduces the reliability of the display panel. Summary of the Invention

[0005] This disclosure aims to address the problem of reduced effective channel length in devices due to ion diffusion issues.

[0006] In a first aspect, this disclosure provides a thin-film transistor. The thin-film transistor includes a substrate, an indium gallium zinc oxide (IGZO) active layer, a gate insulating layer, and a gate. The IGZO active layer is located on one side of the substrate. The IGZO active layer has a source region, a drain region, and a channel. In a direction parallel to the substrate, the source region is located on one side of the channel, and the drain region is located on the other side of the channel. The gate insulating layer covers the surface of the IGZO active layer on the side away from the substrate. The gate is disposed on the side of the gate insulating layer away from the IGZO active layer, and the orthographic projection of the gate onto the substrate is located inside the orthographic projection of the gate insulating layer onto the substrate. Ions are implanted in the source and drain regions. The source region includes a first ion concentration region and a second ion concentration region, the second ion concentration region being closer to the channel, and the ion concentration in the first ion concentration region being greater than the ion concentration in the second ion concentration region. The drain region includes a third ion concentration region and a fourth ion concentration region, the fourth ion concentration region being closer to the channel, and the ion concentration in the third ion concentration region being greater than the ion concentration in the fourth ion concentration region.

[0007] In top-gate thin-film transistors (IGZO TFTs), the source and drain regions formed by ion implantation often suffer from reduced effective channel length due to lateral diffusion. The core cause of this problem lies in the diffusion dynamics of high-concentration ion implantation regions. When a single high-dose ion implantation is performed on the source and drain regions of the IGZO active layer, the high-concentration ions diffuse laterally (i.e., along the channel direction) during annealing or device operation, invading the predetermined channel region. According to Fick's second law, the diffusion rate is proportional to the concentration gradient. If the implanted region is directly adjacent to the channel, ions from the high-concentration region will preferentially migrate towards the low-concentration channel direction, resulting in a shortened effective channel length between the source and drain. For example, when the designed channel length is 1 μm, a single implantation may shorten the effective channel to 0.7 μm due to lateral diffusion, directly causing a decrease in the gate electric field's control over the channel, an increase in leakage current, a decrease in the on / off ratio, and ultimately leading to image retention or abnormal power consumption in the display.

[0008] To address the aforementioned issues, the technical solution proposed in this disclosure constructs a gradient ion concentration distribution in the source and drain regions. Specifically, low-concentration doping is used in regions near the channel (the second and fourth ion concentration regions), while high-concentration doping is used in regions farther from the channel (the first and third ion concentration regions). The core of this design lies in utilizing the diffusion direction control mechanism of the concentration gradient. According to the principles of diffusion kinetics, ions migrate from high-concentration regions to low-concentration regions during annealing, and the change in the concentration gradient distribution can buffer the ion diffusion process. By suppressing the lateral diffusion rate, the loss of effective channel length is significantly reduced. Taking a designed channel length of 1 μm as an example, if a single implantation results in 0.3 μm of lateral diffusion, while the gradient implantation scheme reduces the lateral diffusion to below 0.1 μm, the effective channel length can be maintained at 0.9 μm.

[0009] In one exemplary embodiment, on the substrate, the orthographic projection of the second ion concentration region lies between the orthographic projection of the first ion concentration region and the orthographic projection of the channel. On the substrate, the orthographic projection of the fourth ion concentration region lies between the orthographic projection of the third ion concentration region and the orthographic projection of the channel.

[0010] In one exemplary embodiment, the ion concentration in the second ion concentration region is the same as that in the fourth ion concentration region. The ion concentration in the first ion concentration region is the same as that in the third ion concentration region.

[0011] In one exemplary embodiment, the projected area of ​​the second ion concentration region on the substrate is the same as the projected area of ​​the fourth ion concentration region on the substrate. The projected area of ​​the first ion concentration region on the substrate is the same as the projected area of ​​the third ion concentration region on the substrate.

[0012] In one exemplary embodiment, the thin-film transistor further includes a water-oxygen isolation layer disposed between the substrate and the IGZO active layer.

[0013] Preferably, the water-oxygen barrier layer is aluminum oxide and / or silicon oxide.

[0014] Preferably, the ions include at least one of Ar ions, B ions, F ions, H ions, and P ions.

[0015] Secondly, this disclosure also provides a method for fabricating a thin-film transistor. The method includes:

[0016] Provide a substrate layer.

[0017] An IGZO active layer is formed on one side of the substrate.

[0018] Ions are implanted into a first region of the IGZO active layer to form a source region, and ions are implanted into a second region of the IGZO active layer to form a drain region. A third region located between the first and second regions forms a channel between the source and drain regions. The source region includes a first ion concentration region and a second ion concentration region. The second ion concentration region is closer to the channel. The ion concentration in the first ion concentration region is greater than that in the second ion concentration region. The drain region includes a third ion concentration region and a fourth ion concentration region. The fourth ion concentration region is closer to the channel. The ion concentration in the third ion concentration region is greater than that in the fourth ion concentration region.

[0019] A gate insulating layer is disposed on the side of the IGZO active layer away from the substrate.

[0020] A gate is disposed on the side of the gate insulating layer away from the IGZO active layer. The orthogonal projection of the gate onto the substrate lies within the orthogonal projection of the gate insulating layer onto the substrate.

[0021] In an exemplary embodiment, implanting ions into a first region of the IGZO active layer to form a source region and implanting ions into a second region of the IGZO active layer to form a drain region includes:

[0022] The first ion implantation process is performed, injecting ions into the first and second regions.

[0023] A second ion implantation process is performed to implant ions again into the first and second regions to form the source and drain regions.

[0024] In an exemplary embodiment, the ion implantation direction of the first ion implantation process has a first angle with the plane of the substrate, and the ion implantation direction of the second ion implantation process has a second angle with the plane of the substrate, wherein one of the first angle and the second angle is less than 90 degrees and the other is greater than 90 degrees.

[0025] In an exemplary embodiment, the angle between the ion implantation direction of the first ion implantation process and the ion implantation direction of the second ion implantation process is greater than or equal to 45 degrees and less than or equal to 135 degrees.

[0026] In an exemplary embodiment, the implantation time of the first ion implantation step is different from that of the second ion implantation step, and / or the implantation power of the first ion implantation step is different from that of the second ion implantation step. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure, and not all of them.

[0028] It should be understood that the same or similar reference numerals are used in the accompanying drawings to denote the same or similar elements (components or components).

[0029] It should be understood that the accompanying drawings are only schematic, and the dimensions and scale of the elements (components or parts) in the drawings are not necessarily precise.

[0030] Figure 1 This is a cross-sectional schematic diagram of a thin-film transistor provided in an embodiment of the present disclosure.

[0031] Figure 2 This is a cross-sectional schematic diagram of a thin-film transistor provided for another embodiment of the present disclosure.

[0032] Figure 3 for Figure 1 The flowchart shown is a method for fabricating thin-film transistors.

[0033] Figure 4 for Figure 3 A further detailed flowchart of the preparation method shown.

[0034] Figure 5 A schematic diagram of the first ion implantation process.

[0035] Figure 6 A schematic diagram of the second ion implantation process. Detailed Implementation

[0036] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0037] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0038] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0039] The features and exemplary embodiments of various aspects of this application will now be described in detail. Furthermore, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.

[0040] This disclosure provides a display panel for use in a display device, which may include, but is not limited to, mobile phones, tablets, laptops, desktops, terminals, interactive displays, digital audio-visual equipment, IoT devices, etc. Interactive displays may include interactive whiteboards, digital advertising interactive screens, and interactive gaming displays, etc., while IoT devices may include smart home devices and smart wearable devices, etc. The display device may include a display panel, which can provide a display interface and touch input to achieve corresponding functions.

[0041] The display device can be a regular mobile phone, a feature phone, or a smartphone. Smartphones can be flat-screen phones, curved-screen phones, or flip phones, etc. The display panel can be located at the top, middle, or bottom of the display device. The display panel can be used for displaying information; for example, it can serve as the visual information display section. The display panel can also serve as a touch input section, allowing users to operate the display device by touching it, for example, for interface navigation and function switching. The display device can also have a housing, in which the display panel is mounted. The housing protects the display panel and reduces the risk of damage from external forces.

[0042] This disclosure aims to address the problem of reduced effective channel length in devices due to ion diffusion issues.

[0043] This disclosure provides a thin-film transistor. The thin-film transistor includes a substrate, an indium gallium zinc oxide (IGZO) active layer, a gate insulating layer, and a gate. The IGZO active layer is located on one side of the substrate. The IGZO active layer has a source region, a drain region, and a channel. In a direction parallel to the substrate (i.e., a horizontal direction), the source region is located on one side of the channel, and the drain region is located on the other side of the channel. The gate insulating layer covers the surface of the IGZO active layer on the side away from the substrate. The gate is disposed on the side of the gate insulating layer away from the IGZO active layer, and the orthographic projection of the gate onto the substrate is located inside the orthographic projection of the gate insulating layer onto the substrate. Ions are implanted in the source and drain regions. The source region includes a first ion concentration region and a second ion concentration region, the second ion concentration region being closer to the channel, and the ion concentration in the first ion concentration region being greater than the ion concentration in the second ion concentration region. The drain region includes a third ion concentration region and a fourth ion concentration region, the fourth ion concentration region being closer to the channel, and the ion concentration in the third ion concentration region being greater than the ion concentration in the fourth ion concentration region.

[0044] To facilitate the description of the hierarchical relationship of the structure, the structural schematic diagram of the thin-film transistor provided in this disclosure will be presented in a cross-sectional view. For example, as shown... Figure 1The figure shows an axial cross-sectional view of a thin-film transistor 10. The thin-film transistor 10 includes, from bottom to top along the vertical direction, a substrate 11, an IGZO active layer 12, a gate insulating layer 13, and a gate 14.

[0045] Substrate 11 also serves as the substrate for the display panel, meaning that each thin-film transistor on the display panel is formed on the same substrate. The substrate is made of inorganic materials, typically glass or flexible plastic (such as polyimide), and its surface is covered with an inorganic insulating layer (such as SiO2 or SiN). x It is used to support the device and isolate it from external interference.

[0046] The IGZO active layer 12 is a light-emitting layer. The IGZO active layer 12 is formed on the substrate 11 by sputtering or solution deposition, with a thickness of approximately 20-100 nm. Adjacent IGZO active layers are physically separated. An amorphous or crystalline oxide composed of indium (In), gallium (Ga), zinc (Zn), and oxygen (O) serves as the channel layer for thin-film transistors (TFTs), controlling the switching and current transmission of the transistors. The IGZO active layer has a source region P1, a drain region P2, and a channel region C located between the source region P1 and the drain region P2. The proportions of the source region P1, the drain region P2, and the channel region C on the IGZO active layer are predetermined, and the proportions of the source region P1 and the drain region P2 on the IGZO active layer 12 are preferably the same. Ions I are implanted into the source region P1 and the drain region P2 to change the conductivity of the IGZO through doping, thereby achieving source-drain conductor formation. The amount of ions I injected into the source region P1 and the drain region P2 is approximately the same. Within the source region P1, there is a first ion concentration region P11 and a second ion concentration region P12, with the second ion concentration region P12 being closer to the channel C in the second direction. The ion concentration in the first ion concentration region P11 is greater than that in the second ion concentration region P12. Within the drain region S, there are a third ion concentration region P21 and a fourth ion concentration region P22, with the fourth ion concentration region P22 being closer to the channel in the second direction. The ion concentration in the third ion concentration region P21 is greater than that in the fourth ion concentration region P22. The term "ion concentration" refers to the number of ions per unit volume; for example, exemplarily, such as... Figure 1 The proportion of the first ion concentration region P11 on the IGZO active layer shown is three times that of the second ion concentration region P12 on the IGZO active layer. Assuming the volume of the second ion concentration region P12 is 1, then the number of ions in the first ion concentration region P11 is more than three times the number of ions in the second ion concentration region P12.

[0047] A gate insulating layer 13 covers the IGZO active layer 12. The gate insulating layer is typically made of a high-dielectric-constant material (such as Al₂O₃ or SiO₂), with a thickness of approximately 100-300 nm. It isolates the gate 14 from the IGZO active layer 12 and modulates the electric field of the IGZO. The gate 14 is disposed on the gate insulating layer 13 and is made of a metal (such as Al, Mo, or Cu) or a transparent conductive oxide (such as ITO). It is patterned using photolithography to control the channel's on / off state. The vertical projection of the gate 14 is covered by the vertical projection of the gate insulating layer. The projection of the gate onto the IGZO active layer 12 lies above the channel C; that is, the channel C and the gate 14 are electrically isolated vertically by the gate insulating layer 13.

[0048] Preferably, the ions can be argon (Ar), boron (B), fluorine (F), hydrogen (H), phosphorus (P), etc.

[0049] In this embodiment, the display panel can be an OLED panel, a Mini-LED panel, a Micro-LED panel, etc.

[0050] In top-gate thin-film transistors (IGZO TFTs), the source and drain regions formed by ion implantation often suffer from reduced effective channel length due to lateral diffusion. The core cause of this problem lies in the diffusion kinetics of high-concentration ion implantation regions. When a single high-dose ion implantation is performed on the source and drain regions of the IGZO active layer, the high-concentration ions diffuse laterally (i.e., along the channel direction) during annealing or device operation, invading the channel region. According to Fick's second law, the diffusion rate is proportional to the concentration gradient. If the implanted region is directly adjacent to the channel, ions from the high-concentration region will preferentially migrate towards the low-concentration channel direction, resulting in a shortened effective channel length between the source and drain. For example, when the designed channel length is 1 μm, a single implantation may shorten the effective channel to 0.7 μm due to lateral diffusion, directly causing a decrease in the gate electric field's control over the channel, an increase in leakage current, a decrease in the on / off ratio, and ultimately leading to image retention or abnormal power consumption in the display.

[0051] To address the aforementioned issues, this disclosure proposes constructing a gradient ion concentration distribution in the source and drain regions. Low-concentration ion doping is used in regions near the channel (the second and fourth ion concentration regions), while high-concentration ion doping is used in regions further away from the channel (the first and third ion concentration regions). Since ions migrate from high-concentration to low-concentration regions during annealing, the gradient distribution provides a buffer for ion diffusion; that is, ions diffuse from the first ion concentration region to the second ion concentration region and stop there, and the same applies to the third and fourth ion concentration regions. By suppressing the lateral diffusion rate, the loss of effective channel length is significantly reduced. Ions located in the second and fourth ion concentration regions are less prone to diffusion due to their lower concentration. For example, with a designed channel length of 1 μm, if a single implantation results in 0.3 μm of lateral diffusion, while the gradient implantation scheme reduces lateral diffusion to below 0.1 μm, the effective channel length can potentially remain above 0.9 μm. Therefore, the channel width can be maintained at the desired level, which is beneficial for unifying the channel width among multiple thin-film transistors on the substrate.

[0052] See also Figure 1 On substrate 11, the orthographic projection of the second ion concentration region P12 lies between the orthographic projection of the first ion concentration region P11 and the orthographic projection of the channel C. On substrate 11, the orthographic projection of the fourth ion concentration region P22 lies between the orthographic projection of the third ion concentration region P21 and the orthographic projection of the channel C.

[0053] In one exemplary embodiment, the ion concentrations in the second and fourth ion concentration regions are the same, and the ion concentrations in the first and third ion concentration regions are the same. That is, the driving forces for lateral ion diffusion in the source and drain on both sides of the channel tend to be consistent. Therefore, the rate of lateral ion diffusion from the first to the second ion concentration region will be balanced with the rate of lateral ion diffusion from the third to the fourth ion concentration region. This makes the channel length variation more controllable, which is beneficial for improving the yield and consistency of thin-film transistors.

[0054] Preferably, the projected area of ​​the second ion concentration region on the substrate is the same as the projected area of ​​the fourth ion concentration region on the substrate. The projected area of ​​the first ion concentration region on the substrate is the same as the projected area of ​​the third ion concentration region on the substrate.

[0055] In one exemplary embodiment, such as Figure 2As shown, between the substrate 11 and the IGZO active layer 12, the thin-film transistor 10 also includes a water-oxygen isolation layer 15. During manufacturing or use, the substrate (such as glass or flexible polyimide) may absorb ambient water and oxygen, especially under high temperature and humidity conditions. Water molecules gradually diffuse into the IGZO active layer through micropores or interface defects on the substrate surface, leading to transistor performance degradation.

[0056] This disclosure proposes to introduce a water-oxygen isolation layer between the substrate and the IGZO active layer, thereby blocking the longitudinal migration of water vapor from the substrate to the IGZO active layer through a dense inorganic thin film.

[0057] Preferably, a dense Al2O3 layer (20-50 nm thick) is formed between the substrate and the IGZO active layer using an ALD process or a SiO2 layer is formed using chemical vapor deposition. The good density of the SiO2 layer is used to block the diffusion of water molecules. The thickness of the Al2O3 layer is usually between 10-50 nm.

[0058] In other embodiments, Al2O3 and SiO2 can be stacked, which may be more effective. The stacking of different materials can fill the micropores or interface defects that may exist in a single material, thereby enhancing the water vapor barrier effect.

[0059] This disclosure also provides a method for fabricating the thin-film transistor as described above. Figure 3 and Figure 1 As shown, the preparation method includes:

[0060] Step S1: Provide a substrate.

[0061] The substrate can be flexible, stretchable, foldable, bendable, or rollable, so that the display panel can be flexible, stretchable, foldable, bendable, or rollable. The substrate can be formed from any suitable insulating material that is flexible.

[0062] Step S2: Deposit an IGZO active layer on one side of the substrate.

[0063] The IGZO active layer is deposited on top of the substrate by sputtering or solution deposition.

[0064] Step S3: Ions are implanted into the first region of the IGZO active layer to form the source region, and ions are implanted into the second region of the IGZO active layer to form the drain region. The third region located between the first and second regions forms a channel between the source and drain regions.

[0065] The source region includes a first ion concentration region and a second ion concentration region, with the second ion concentration region closer to the channel. The ion concentration in the first ion concentration region is greater than that in the second ion concentration region. The drain region includes a third ion concentration region and a fourth ion concentration region, with the fourth ion concentration region closer to the channel. The ion concentration in the third ion concentration region is greater than that in the fourth ion concentration region. Ions can be implanted in sections or in stages. For example, a small number of ions can be implanted in the second and fourth ion concentration regions to maintain a low ion concentration. A large number of ions can be implanted in the first and third ion concentration regions to maintain a high ion concentration. Alternatively, the distribution of ions in adjacent ion concentration regions can be adjusted during a single ion implantation.

[0066] Step S4: Set a gate insulating layer on the side of the IGZO active layer away from the substrate.

[0067] Step S5: A gate is disposed on the side of the gate insulating layer away from the IGZO active layer, wherein the orthogonal projection of the gate on the substrate is located inside the orthogonal projection of the gate insulating layer on the substrate.

[0068] The process includes forming an aluminum layer covering the substrate surface on one side of the substrate after providing the substrate and before forming the IGZO active layer on one side of the substrate, i.e., between steps S1 and S2. After step S2, the aluminum layer undergoes thermal oxidation to form an alumina layer. During the aluminum oxidation process, the oxidation temperature and time can be precisely controlled to form an alumina layer with fewer interface defects, thereby improving production efficiency and reducing production costs. In addition, the alumina formed by aluminum oxidation may have better adhesion, which is beneficial for achieving bonding between the aluminum and the substrate and the IGZO active layer, reducing the risk of film cracking.

[0069] like Figure 1 As shown, the IGZO active layer includes a first region, namely the source region P1, a second region, namely the drain region P2, and a third region, namely the channel region P3, located between the first and second regions. Ions are injected into the source region P1 and the drain region P2 through a high-energy ion beam of a certain width. Furthermore, the ion concentration in the source region P1 is not uniform, with a first ion concentration region P11 and a second ion concentration region P12, wherein the ion concentration in the first ion concentration region P11 is significantly higher than that in the second ion concentration region P12, for example, 3 times, 4 times, or 5 times the ion concentration in the second ion concentration region P12. The ion concentration in the drain region P2 is also not uniform, having a third ion concentration region P21 and a fourth ion concentration region P22, wherein the ion concentration in the third ion concentration region P21 is significantly higher than that in the fourth ion concentration region P22, for example, 3 times, 4 times, or 5 times the ion concentration in the fourth ion concentration region P22.

[0070] like Figures 4-6 As shown, step S3 further includes: step S31: performing the first ion implantation process to implant ions into the first region and the second region.

[0071] Step S32: Perform the second ion implantation process to implant ions into the first and second regions.

[0072] After steps S31 and S32 are completed, the source region and the drain region are formed.

[0073] During the first ion implantation step, a high-energy ion beam of a certain width is implanted into a designated location. For example, Figure 5 As shown, in the first ion implantation process, a first ion beam M1 is implanted into the source region P1 and the drain region P2, wherein the width of the first ion beam M1 covers the second ion concentration region P12 and the fourth ion concentration region P22, and partially covers the first ion concentration region P11 and the third ion concentration region P21.

[0074] Figure 6 As shown, in the second ion implantation process, a second ion beam M2 is implanted into the source region P1 and the drain region P2, wherein the width of the second ion beam M2 only covers the first ion concentration region P11 and the third ion concentration region P21. At this time, the ion concentrations of the second ion concentration region P12 and the fourth ion concentration region P22 are lower than the ion concentrations of the first ion concentration region P11 and the third ion concentration region P21.

[0075] In this embodiment, the gate insulating layer and the gate are formed after the ion implantation process. However, in other embodiments, the gate insulating layer and the gate may be formed before the ion implantation process, and this disclosure does not limit this.

[0076] High-dose ion implantation in a single session can easily induce lateral diffusion, causing dopant elements to invade the channel region and disrupting the uniformity of intrinsic carrier concentration in the IGZO semiconductor, thereby affecting threshold voltage stability and device reliability. Phased implantation, by reducing the energy and time of a single implantation, can effectively constrain the vertical penetration depth of dopant ions, playing a crucial role in suppressing impurity diffusion into the channel region. Simultaneously, by implanting ions at different locations in the source and drain regions in stages, the ion concentration can be adjusted, thereby controlling ion diffusion into the channel, reducing the lateral diffusion range, and preventing the degradation of channel electrical characteristics due to impurity contamination.

[0077] In an exemplary embodiment, the ion implantation direction of the first ion implantation process has a first angle with the plane of the substrate, and the ion implantation direction of the second ion implantation process has a second angle with the plane of the substrate, wherein one of the first angle and the second angle is less than 90 degrees and the other is greater than 90 degrees.

[0078] See you again Figure 5 During the first ion implantation process, a first ion beam M1 with a certain width is implanted into the source region P1 and the drain region P2 along a first direction. The angle between the first direction and the plane where the substrate is located is the first angle α.

[0079] For example, such as Figure 5 As shown, the first included angle α is less than 90 degrees. The first ion beam M1 injects ions into the first ion concentration region P11 in the source region P1 and the third ion concentration region P21 and the fourth ion concentration region P22 in the drain region P2. The width of the first ion beam M1 is preferably equal to the width of the first ion concentration region P11 and the width of the third ion concentration region P21. The first ion beam M1 injects at the first included angle α and completely covers the upper surface of the IGZO active layer in the first ion concentration region P11 and the upper surface of the third ion concentration region P21. At this time, because of the first included angle α, ions can only be injected into the first ion concentration region P11 in the source region P1, while in the drain region P2, ions can be injected into the third ion concentration region P21 and a portion of ions can be injected into the fourth ion concentration region P22.

[0080] like Figure 6 As shown, after the first ion implantation process is completed, the second ion implantation process is performed. A second ion beam M2 with the same width as the first ion beam M1 is implanted into the source region P1 and the drain region P2 along a second direction. The angle between the second direction and the plane of the substrate is the second angle β.

[0081] For example, such as Figure 6 As shown, the second included angle β is greater than 90 degrees. The second ion beam M2 injects ions into the first ion concentration region P11 and the second ion concentration region P12 in the source region P1, and the third ion concentration region P21 in the drain region P2. The width of the second ion beam M2 is preferably equal to the width of the first ion concentration region P11 and the width of the third ion concentration region P21. The second ion beam M2 injects at the second included angle β and completely covers the upper surface of the IGZO active layer in the first ion concentration region P11 and the upper surface of the third ion concentration region P21. At this time, due to the second included angle β, ions in the drain region P2 can only be injected into the third ion concentration region P21, while in the source region P1, ions can be injected into the first ion concentration region P11, and some ions can be injected into the second ion concentration region P12 simultaneously.

[0082] Combination Figure 5 and Figure 6As shown, after the two ion implantation processes, the first ion concentration region P11 and the third ion concentration region P21 are each implanted with ions twice, while the second ion concentration region P12 and the fourth ion concentration region P22 are each implanted with ions only once, so that the ion concentration of the first ion concentration region P11 and the third ion concentration region P21 is higher than that of the second ion concentration region P12 and the fourth ion concentration region P22.

[0083] In this embodiment, the first included angle α is less than 90 degrees. In other embodiments, the first included angle α may also be greater than 90 degrees. Further details will not be provided here.

[0084] In this embodiment, one of the first included angle α and the second included angle β is less than 90 degrees, and the other is greater than 90 degrees. This can be understood as follows: Figure 5 and Figure 6 The direction indicated by the middle arrow is that the angle between the ion beam M1 or M2 and the plane where the substrate is located gradually increases in the counterclockwise direction.

[0085] Preferably, the first ion implantation process and the second ion implantation process can be performed by different ion implantation devices to improve implantation efficiency and accuracy.

[0086] Preferably, the first ion beam M1 and the second ion beam M2 directed towards each thin-film transistor each comprise two ion beams, enabling simultaneous ion implantation into the source region P1 and the drain region P2, respectively. Furthermore, simultaneous ion implantation with two separate ion beams eliminates the need for multiple adjustments to the implantation position, ensuring symmetrical positioning of the source and drain. More importantly, if only one ion beam is used to simultaneously implant ions into the source region P1 and the drain region P2, it is necessary to consider how to shield the predetermined channel region to prevent ions from being implanted into the channel. The present disclosure, by simultaneously implanting ions into the source region P1 and the drain region P2 with two separate ion beams, completely avoids this situation.

[0087] Preferably, the first included angle α is greater than 45 degrees and less than 90 degrees, and the second included angle β is greater than 90 degrees and less than 135 degrees.

[0088] The importance of the tilted injection angle for concentration distribution has been explained above. However, an excessively tilted injection angle will directly affect the width of the channel between the source and drain regions.

[0089] Preferably, the inclination degrees of the first direction and the second direction are the same, that is, the sum of the angles of the first included angle α and the second included angle β is equal to 180 degrees, that is, the angles of the first included angle α and the second included angle β are complementary, that is, the first included angle α and the second included angle β are symmetrical about the normal axis of the plane containing the substrate.

[0090] By setting it up as described above, the ion concentration in the source region P1 and the ion concentration in the drain region P2 can be made the same. Furthermore, the ion concentration in the first ion concentration region P11 and the third ion concentration region P21 are made the same, and the ion concentration in the second ion concentration region P12 and the fourth ion concentration region P22 are made the same.

[0091] Preferably, in an exemplary embodiment, the angle between the ion implantation direction of the first ion implantation process and the ion implantation direction of the second ion implantation process is greater than or equal to 45 degrees and less than or equal to 135 degrees.

[0092] In an exemplary embodiment, the implantation time of the first ion implantation step is different from the implantation time of the second ion implantation step, and / or the implantation power of the first ion implantation step is different from the implantation power of the second ion implantation step.

[0093] Specifically, the first ion implantation uses lower energy and time. A shorter first implantation time (e.g., 10-30 seconds) combined with a lower implantation power (e.g., 50-100W) can form a shallow, low-concentration light doping layer in the source / drain region near the channel, avoiding damage to the IGZO amorphous structure caused by excessive bombardment by high-energy ions. The second implantation uses higher energy and time. A longer second implantation time (e.g., 60-120 seconds) and a higher power (e.g., 200-300W) are used to form a deep, high-concentration heavy doping layer in the region far from the channel.

[0094] Implantation time directly determines the ion dose, while implantation power directly affects the ion penetration depth. This allows for control of ion concentration and the creation of a concentration gradient. The ion diffusion rate is proportional to the concentration gradient, with a stronger driving force for diffusion from high-concentration regions to low-concentration regions. Therefore, during annealing, ions within the source and drain regions preferentially diffuse from the outer regions with high ion concentration to the near-channel regions with low ion concentration. In regions with low ion concentration, ions diffuse less readily or with weaker diffusion capabilities. This compresses the lateral diffusion length, thus preserving a longer effective channel. Two implantation processes can reduce the lateral diffusion length by, for example, approximately 30%-50%, reducing the channel length loss due to diffusion from 0.2 μm to below 0.1 μm.

[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0097] The display panel and display terminal provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A thin-film transistor, characterized in that: include, Substrate; An indium gallium zinc oxide (IGZO) active layer is located on one side of the substrate, wherein the IGZO active layer has a source region, a drain region, and a channel, and in a direction parallel to the substrate, the source region is located on one side of the channel, and the drain region is located on the other side of the channel; A gate insulating layer covering the surface of the IGZO active layer on the side away from the substrate; and A gate electrode is disposed on the side of the gate insulating layer away from the IGZO active layer, and the orthogonal projection of the gate electrode onto the substrate lies within the orthogonal projection of the gate insulating layer onto the substrate. Ions are implanted in the source region and the drain region. The source region includes a first ion concentration region and a second ion concentration region, the second ion concentration region being closer to the channel, and the ion concentration in the first ion concentration region being greater than that in the second ion concentration region. The drain region includes a third ion concentration region and a fourth ion concentration region, the fourth ion concentration region being closer to the channel, and the ion concentration in the third ion concentration region being greater than that in the fourth ion concentration region.

2. The thin-film transistor according to claim 1, characterized in that, On the substrate, the orthographic projection of the second ion concentration region lies between the orthographic projection of the first ion concentration region and the orthographic projection of the channel, and on the substrate, the orthographic projection of the fourth ion concentration region lies between the orthographic projection of the third ion concentration region and the orthographic projection of the channel.

3. The thin-film transistor according to claim 1, characterized in that, The ion concentration in the second ion concentration region is the same as that in the fourth ion concentration region, and the ion concentration in the first ion concentration region is the same as that in the third ion concentration region.

4. The thin-film transistor according to claim 1, characterized in that, The projected area of ​​the second ion concentration region on the substrate is the same as the projected area of ​​the fourth ion concentration region on the substrate, and / or the projected area of ​​the first ion concentration region on the substrate is the same as the projected area of ​​the third ion concentration region on the substrate.

5. The thin-film transistor according to any one of claims 1-4, characterized in that, It also includes a water-oxygen isolation layer disposed between the substrate and the IGZO active layer. Preferably, the water-oxygen barrier layer is aluminum oxide and / or silicon oxide. Preferably, the ions include at least one of Ar ions, B ions, F ions, H ions, and P ions.

6. A preparation method, characterized in that, include: Provide a substrate layer; An IGZO active layer is disposed on one side of the substrate layer; Ions are implanted into a first region of the IGZO active layer to form a source region and ions are implanted into a second region of the IGZO active layer to form a drain region. A third region located between the first and second regions forms a channel between the source and drain regions. The source region includes a first ion concentration region and a second ion concentration region, the second ion concentration region being closer to the channel, and the ion concentration in the first ion concentration region being greater than that in the second ion concentration region. The drain region includes a third ion concentration region and a fourth ion concentration region, the fourth ion concentration region being closer to the channel, and the ion concentration in the third ion concentration region being greater than that in the fourth ion concentration region. A gate insulating layer is disposed on the side of the IGZO active layer away from the substrate; and A gate is disposed on the side of the gate insulating layer away from the IGZO active layer, wherein the orthogonal projection of the gate on the substrate is located inside the orthogonal projection of the gate insulating layer on the substrate.

7. The preparation method according to claim 6, characterized in that, The step of implanting ions into a first region of the IGZO active layer to form a source region and implanting ions into a second region of the IGZO active layer to form a drain region includes: Perform the first ion implantation process, implanting ions into the first region and the second region; and A second ion implantation process is performed to implant ions again into the first region and the second region to form the source region and the drain region.

8. The preparation method according to claim 7, characterized in that, The ion implantation direction of the first ion implantation process has a first angle with the plane where the substrate is located, and the ion implantation direction of the second ion implantation process has a second angle with the plane where the substrate is located, wherein one of the first angle and the second angle is less than 90 degrees, and the other is greater than 90 degrees.

9. The preparation method according to claim 8, characterized in that, The angle between the ion implantation direction of the first ion implantation process and the ion implantation direction of the second ion implantation process is greater than or equal to 45 degrees and less than or equal to 135 degrees.

10. The preparation method according to claim 7, characterized in that, The implantation time of the first ion implantation step is different from that of the second ion implantation step, and / or the implantation power of the first ion implantation step is different from that of the second ion implantation step.

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