Thin film transistor, preparation method thereof, display panel and display device

Abstract

The application discloses a thin film transistor and a preparation method thereof, a display panel and a display device, and relates to the technical field of display. The thin film transistor comprises a buffer layer, a semiconductor layer, a first insulating layer, a gate layer, a second insulating layer and a source-drain layer which are stacked in sequence. The second part of the orthographic projection of the semiconductor layer and the gate layer which are overlapped comprises a plurality of first semiconductor strips. Therefore, under a unit projection area, the width of the channel region formed by the gate layer and the second part can be increased, so that the comprehensive performance of the thin film transistor is improved. Moreover, the control ability of the gate layer to the channel region is improved, the on-state current of the thin film transistor can be significantly increased, the output capacity of the thin film transistor is improved, the saturation point of the thin film transistor is moved forward, the power consumption of the driving device layer in the display panel is reduced, and the display effect of the display device is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a thin-film transistor and its fabrication method, a display panel, and a display device. Background Technology

[0002] Thin film transistors (TFTs) are devices mounted on a substrate in display devices to drive pixels to emit light.

[0003] In related technologies, a TFT generally includes a semiconductor layer, a gate insulating layer, a gate layer, and a source / drain layer connected to the active layer, sequentially disposed on a substrate. The portion of the semiconductor layer overlapping the gate layer forms the channel of the TFT. To ensure the display quality and smoothness of the display device, a high refresh rate is typically required. Generally, the on-state current of the TFT is positively correlated with the refresh rate of the display device; therefore, to achieve a high refresh rate, the on-state current of the TFT needs to be increased.

[0004] However, in related technologies, the gate layer of TFTs has poor control over the semiconductor layer, resulting in poor overall performance of TFTs and poor display effects of display devices. Summary of the Invention

[0005] This application provides a thin-film transistor and its fabrication method, a display panel, and a display device, which can solve the problem of poor display effect in related technologies. The technical solution is as follows: On one hand, a thin-film transistor is provided, the thin-film transistor comprising: A buffer layer, a semiconductor layer, a first insulating layer, a gate layer, a second insulating layer, and a source / drain layer are sequentially stacked on a substrate along a side away from the substrate. The semiconductor layer includes a first portion, a second portion, and a third portion arranged and connected along a first direction. The orthographic projection of the second portion on the substrate overlaps with the orthographic projection of the gate layer on the substrate. The second portion includes a plurality of first semiconductor strips extending along the first direction and arranged along a second direction. The first direction and the second direction are perpendicular. The source-drain layer includes a source and a drain, the source is electrically connected to the first portion, and the drain is electrically connected to the third portion.

[0006] Optionally, the width of the gate layer in the second direction is greater than the distance between the two relatively distant sides of the two first semiconductor strips that are furthest apart in the second direction among the plurality of first semiconductor strips; the gate layer covers the plurality of first semiconductor strips in the second direction.

[0007] Optionally, the plurality of first semiconductor strips are spaced apart; One end of the plurality of first semiconductor strips in the first part and the second part are connected, and the other end of the plurality of first semiconductor strips in the third part and the second part are connected.

[0008] Optionally, the first part includes a plurality of second semiconductor strips extending along a first direction and arranged along a second direction, wherein the plurality of second semiconductor strips and the plurality of first semiconductor strips are connected in a one-to-one correspondence; The third part includes a plurality of third semiconductor strips extending along a first direction and arranged along a second direction, wherein the plurality of third semiconductor strips and the plurality of first semiconductor strips are connected in a one-to-one correspondence.

[0009] Optionally, the source is electrically connected to each of the plurality of second semiconductor strips, and the drain is electrically connected to each of the plurality of third semiconductor strips.

[0010] Optionally, the second semiconductor strip is connected to a corresponding first semiconductor strip, and the third semiconductor strip is connected to a corresponding first semiconductor strip; The source electrode is electrically connected to the end of each of the second semiconductor bars away from the first semiconductor bar, and the drain electrode is electrically connected to the end of each of the third semiconductor bars away from the first semiconductor bar.

[0011] Optionally, the second insulating layer and the first insulating layer include a first via and a second via; The first via exposes one end of each of the second semiconductor strips away from the first semiconductor strip, and the second via exposes one end of each of the third semiconductor strips away from the first semiconductor strip; The source electrode covers the first via, and the source electrode and the end of each of the second semiconductor strips exposed by the first via are electrically connected away from the first semiconductor strip; the drain electrode covers the second via, and the drain electrode and the end of each of the third semiconductor strips exposed by the second via are electrically connected away from the first semiconductor strip.

[0012] Optionally, the distance between the end of the second semiconductor strip away from the first semiconductor strip and the side of the first via closer to the second portion is less than the distance between the end of the second semiconductor strip away from the first semiconductor strip and the side of the first via away from the second portion; The distance between the end of the third semiconductor strip away from the first semiconductor strip and the side of the second via closer to the second portion is less than the distance between the end of the third semiconductor strip away from the first semiconductor strip and the side of the second via away from the second portion.

[0013] Optionally, the buffer layer includes a first target portion and a second target portion; The first via exposes the first target portion, and the orthographic projection of the first target portion on the substrate is located between the end of the second semiconductor strip away from the first semiconductor strip and the side of the first via away from the second portion; the second via exposes the second target portion, and the orthographic projection of the second target portion on the substrate is located between the end of the third semiconductor strip of the first semiconductor strip and the side of the second via away from the second portion; The first target portion includes a plurality of first protruding strips extending along a first direction and arranged along a second direction on the side away from the substrate; the plurality of first protruding strips and the plurality of second semiconductor strips are arranged in a one-to-one correspondence, and the first protruding strips and the corresponding second semiconductor strips are arranged collinearly along the first direction; The second target portion includes a plurality of second protruding strips extending along a first direction and arranged along a second direction on the side away from the substrate; the plurality of second protruding strips and the plurality of third semiconductor strips are arranged in a one-to-one correspondence, and the second protruding strips and the corresponding third semiconductor strips are arranged collinearly along the first direction.

[0014] Optionally, the source electrode and the first portion are electrically connected to the side away from the substrate, and the drain electrode and the third portion are electrically connected to the side away from the substrate.

[0015] Optionally, the second insulating layer and the first insulating layer include a first via and a second via; The first via exposes a portion of the first portion on the side away from the substrate, and the second via exposes a portion of the third portion on the side away from the substrate; The source electrode covers the first via, and the source electrode and the first portion exposed by the first via are electrically connected; the drain electrode covers the second via, and the drain electrode and the second portion exposed by the second via are electrically connected.

[0016] On the other hand, a method for fabricating a thin-film transistor is provided, the method being used to fabricate a thin-film transistor as described above; the method includes: A buffer layer and a semiconductor thin film are formed on a substrate. Nanoimprint adhesive is formed on the side of the semiconductor thin film away from the substrate. The semiconductor thin film is etched and the nanoimprint adhesive is removed to obtain an initial semiconductor layer; The initial semiconductor layer is patterned to obtain a new semiconductor layer. A first insulating layer, a gate layer, a second insulating layer, and source / drain layers are formed; The semiconductor layer includes a first portion, a second portion, and a third portion arranged along a first direction. The orthographic projection of the second portion on the substrate overlaps with the orthographic projection of the gate layer on the substrate. The second portion includes a plurality of first semiconductor strips extending along the first direction and arranged along a second direction. The source-drain layer includes a source and a drain. The source is electrically connected to the first portion, and the drain is electrically connected to the third portion.

[0017] In another aspect, a display panel is provided, the display panel comprising: Substrate; A driving device layer, the driving device layer including a plurality of pixel circuits, the pixel circuit including a plurality of thin film transistors and at least one storage capacitor, wherein at least one of the plurality of thin film transistors included in the pixel circuit is a thin film transistor as described above. And a light-emitting device layer, the light-emitting device layer including a plurality of light-emitting units corresponding to the plurality of pixel circuits, the pixel circuits providing driving signals to the corresponding light-emitting units.

[0018] Optionally, the driving device layer includes a first sub-driving layer and a second sub-driving layer disposed away from the substrate. The pixel circuit includes a portion of thin-film transistors located in the first sub-driving layer and another portion of thin-film transistors located in the second sub-driving layer; Among them, a portion of the thin-film transistors located in the first sub-driving layer are thin-film transistors as described above, and the other portion of the thin-film transistors located in the second sub-driving layer are low-temperature polycrystalline silicon thin-film transistors or oxide thin-film transistors.

[0019] Optionally, the semiconductor layers of the multiple thin-film transistors included in the pixel circuit are disposed on the same layer; Each of the plurality of thin-film transistors included in the pixel circuit is a thin-film transistor as described above; or, a portion of the plurality of thin-film transistors included in the pixel circuit are thin-film transistors as described above.

[0020] Optionally, the light-emitting unit is a liquid crystal light-emitting unit, or the light-emitting unit is an organic light-emitting unit.

[0021] In another aspect, a display device is provided, the display device comprising: a power supply component and a display panel as described above; The power supply component is connected to the display panel, and the power supply component is used to supply power to the display panel.

[0022] The beneficial effects of the technical solution provided in this application include at least the following: This application provides a thin-film transistor (TFT), its fabrication method, a display panel, and a display device. The TFT includes a buffer layer, a semiconductor layer, a first insulating layer, a gate layer, a second insulating layer, and source / drain layers stacked sequentially. The second portion of the overlapping orthographic projections of the semiconductor layer and the gate layer includes multiple first semiconductor strips. Therefore, the width of the channel region formed by the gate layer and the second portion can achieve a certain gain per unit projected area, thereby improving the overall performance of the TFT. Furthermore, the improved control of the channel region by the gate layer can significantly increase the on-state current of the TFT, enhance its output capability, shift the saturation point of the TFT forward, reduce the power consumption of the driving device layer in the display panel, and improve the display effect of the display device. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a top view of a thin-film transistor provided in an embodiment of this application; Figure 2 yes Figure 1 Cross-sectional view along the AA direction; Figure 3 yes Figure 1 Cross-sectional view along the BB direction; Figure 4 yes Figure 1 Cross-sectional view along the CC direction; Figure 5 It is a thin-film transistor in Figure 1 A schematic diagram showing the cross-sections taken along the DD direction, the EE direction, and the FF direction, pieced together. Figure 6 This is a top view of another thin-film transistor provided in an embodiment of this application; Figure 7 yes Figure 6 Cross-sectional view along the HH direction; Figure 8 yes Figure 6 Cross-sectional view along direction II; Figure 9 This is a schematic diagram of an initial second semiconductor strip and an initial third semiconductor strip provided in an embodiment of this application; Figure 10 This is a top view of yet another thin-film transistor provided in an embodiment of this application; Figure 11 This application provides a top view of another thin-film transistor; Figure 12 yes Figure 11 Cross-sectional view along the BB direction; Figure 13 yes Figure 11 Cross-sectional view along the BB direction; Figure 14 This is a schematic diagram of the voltage-current relationship curve of a thin-film transistor provided in an embodiment of this application; Figure 15 yes Figure 14 A partial schematic diagram; Figure 16 This is a flowchart of a method for fabricating a thin-film transistor according to an embodiment of this application; Figure 17 This is a schematic diagram illustrating the formation of a buffer layer and a semiconductor thin film on a substrate according to an embodiment of this application; Figure 18 This is a schematic diagram of forming a nanoimprint adhesive according to an embodiment of this application; Figure 19 This is a schematic diagram illustrating the etching process for forming a polycrystalline silicon strip and the removal of nanoimprint adhesive, as provided in an embodiment of this application. Figure 20 This is a top view of a polycrystalline silicon strip provided in an embodiment of this application; Figure 21 This is a schematic diagram of another etching process for forming polycrystalline silicon strips and removing nanoimprint adhesive provided in an embodiment of this application; Figure 22 This is a top view of another polycrystalline silicon strip provided in an embodiment of this application; Figure 23 This is a schematic diagram of forming a first insulating film provided in an embodiment of this application; Figure 24 This is a schematic diagram of forming a gate thin film provided in an embodiment of this application; Figure 25 This is a schematic diagram of forming a gate layer according to an embodiment of this application; Figure 26 This is a schematic diagram of forming a second insulating film provided in an embodiment of this application; Figure 27 This is a schematic diagram of forming a first via and a second via provided in an embodiment of this application; Figure 28 This is a schematic diagram of forming a source and a drain according to an embodiment of this application; Figure 29 This is a schematic diagram of a display panel provided in an embodiment of this application; Figure 30 This is a schematic diagram of a driving device layer provided in an embodiment of this application; Figure 31 This is a schematic diagram of another driving device layer provided in an embodiment of this application; Figure 32 This is a schematic diagram of yet another driving device layer provided in the embodiments of this application; Figure 33 This is a schematic diagram of another driving device layer provided in the embodiments of this application; Figure 34 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a top view of a thin-film transistor provided in an embodiment of this application. Figure 2 yes Figure 1 Cross-sectional view along the AA direction. Figure 3 yes Figure 1 Cross-sectional view along the BB direction. Figure 4 yes Figure 1 Cross-sectional view along the CC direction. Figure 5 It is a thin-film transistor in Figure 1 A schematic diagram showing the cross-sections taken along the DD direction, the EE direction, and the FF direction, pieced together. (Combined with...) Figures 1 to 5 The thin-film transistor 100 includes: a buffer layer 101, a semiconductor layer 102, a first insulating layer 103, a gate layer 104, a second insulating layer 105, and a source-drain layer 106, which are stacked sequentially on a substrate 200 and along one side of the substrate 200.

[0027] refer to Figure 1 The semiconductor layer 102 includes a first portion 1021, a second portion 1022, and a third portion 1023 arranged and connected along a first direction X. The orthographic projection of the second portion 1022 on the substrate 200 overlaps with the orthographic projection of the gate layer 104 on the substrate 200. The second portion 1022 includes a plurality of first semiconductor strips P1 extending along the first direction X and arranged along a second direction Y. The first direction X and the second direction Y are perpendicular, the first direction X can be the length direction of the channel of the thin-film transistor 100, and the second direction Y can be the width direction of the channel of the thin-film transistor 100.

[0028] Combination Figures 1 to 5The source-drain layer 106 includes a source 1061 and a drain 1062. The source 1061 is electrically connected to the first portion 1021, and the drain 1062 is electrically connected to the third portion 1023. Optionally, the first portion 1021 of the semiconductor layer 102 may include a source region, the third portion 1023 of the semiconductor layer 102 may include a drain region, and the second portion 1022 of the semiconductor layer 102 may include a channel region.

[0029] Since the second portion 1022 includes multiple first semiconductor strips P1, the width of the channel region formed by the gate layer 104 and the second portion 1022 can achieve a certain gain per unit projected area, thereby improving the overall performance of the thin-film transistor. Furthermore, the improved control of the channel region by the gate layer 104 can significantly increase the on-state current of the thin-film transistor 100, enhance its output capability, shift the saturation point of the thin-film transistor 100 forward, and reduce the power consumption of the driving device layer in the display panel.

[0030] In summary, this application provides a thin-film transistor (TFT) comprising a buffer layer, a semiconductor layer, a first insulating layer, a gate layer, a second insulating layer, and source / drain layers stacked sequentially. The second portion of the overlapping orthographic projections of the semiconductor layer and the gate layer includes multiple first semiconductor strips. Therefore, the width of the channel region formed by the gate layer and the second portion can achieve a certain gain per unit projected area, thereby improving the overall performance of the TFT. Furthermore, the improved control of the channel region by the gate layer can significantly increase the on-state current of the TFT, enhance its output capability, shift the saturation point of the TFT forward, reduce the power consumption of the driving device layer in the display panel, and improve the display effect of the display device.

[0031] In the embodiments of this application, reference is made to Figure 1 The width k1 of the gate layer 104 in the second direction Y is greater than the distance k2 in the second direction Y between the two farthest first semiconductor strips P1 in the second direction Y. The gate layer 104 covers the multiple first semiconductor strips P1 in the second direction Y. This ensures that the multiple first semiconductor strips P1 included in the second portion 1022 can all serve as part of the channel of the thin film transistor 100, thereby improving the performance of the thin film transistor 100.

[0032] In this embodiment of the application, the second part 1022 includes n first semiconductor strips P1, where n can be a positive integer greater than or equal to 2. For example... Figure 1 The second part 1022 includes 12 first semiconductor strips P1. This application embodiment does not limit the number of first semiconductor strips P1 included in the second part 1022.

[0033] Optionally, the gate layer 104 includes a first gate edge 104a and a second gate edge 104b arranged along the second direction Y. The plurality of first semiconductor strips P1 include a first first semiconductor strip P1, a second first semiconductor strip P1, ..., an nth first semiconductor strip P1. The first first semiconductor strip P1 includes a first semiconductor edge 101a away from the nth first semiconductor strip P1, and the nth first semiconductor strip P1 includes a second semiconductor edge 102b away from the first first semiconductor strip P1. The distance k1 between the first gate edge 104a and the second gate edge 104b along the second direction Y is greater than the distance k2 between the first semiconductor edge 101a and the second semiconductor edge 102b along the second direction Y.

[0034] In the embodiments of this application, reference is made to Figure 1 Multiple first semiconductor strips P1 are spaced apart. One end of the multiple first semiconductor strips P1 in the first portion 1021 and the second portion 1022 is connected, and the other end of the multiple first semiconductor strips P1 in the third portion 1023 and the second portion 1022 is connected. Optionally, one end of the first portion 1021 is connected to each of the multiple first semiconductor strips P1, and the other end of the third portion 1023 is connected to each of the multiple first semiconductor strips P1.

[0035] Optionally, the multiple first semiconductor strips P1 being spaced apart can mean that there is a gap between any two adjacent first semiconductor strips P1 along the second direction Y. Optionally, the different gaps can be the same or different, and this application embodiment does not limit this.

[0036] In the embodiments of this application, reference is made to Figure 1 The first part 1021 includes a plurality of second semiconductor strips P2 extending along a first direction X and arranged along a second direction Y, wherein the plurality of second semiconductor strips P2 and the plurality of first semiconductor strips P1 are connected in a one-to-one correspondence. The third part 1023 includes a plurality of third semiconductor strips P3 extending along a first direction X and arranged along a second direction Y, wherein the plurality of third semiconductor strips P3 and the plurality of first semiconductor strips P1 are connected in a one-to-one correspondence.

[0037] Optionally, the number of multiple second semiconductor strips P2 is the same as the number of multiple first semiconductor strips P1, and the number of multiple third semiconductor strips P3 is also the same as the number of multiple first semiconductor strips P1.

[0038] Optionally, each second semiconductor strip P2 is connected to a corresponding first semiconductor strip P1, and each third semiconductor strip P3 is connected to a corresponding first semiconductor strip P1. The first semiconductor strip P1, along with the corresponding second semiconductor strip P2 and the corresponding third semiconductor strip P3, can constitute a single semiconductor strip extending along the first direction X. Optionally, the thin-film transistor 100 in this embodiment can be a micrometer-sized thin-film transistor composed of multiple semiconductor strips connected in parallel.

[0039] In the embodiments of this application, combined with Figures 3 to 5 The source 1061 is electrically connected to each of the plurality of second semiconductor strips P2, and the drain 1062 is electrically connected to each of the plurality of third semiconductor strips P3. This ensures that each integral semiconductor strip in the semiconductor layer 102 contributes to the electrical properties of the thin-film transistor 100.

[0040] Optionally, the source 1061 and the end of each second semiconductor strip P2 away from the first semiconductor strip P1 are electrically connected, and the drain 1062 and the end of each third semiconductor strip P3 away from the first semiconductor strip P1 are electrically connected. For example, the end faces of the source 1061 and each second semiconductor strip P2 away from the first semiconductor strip P1 are electrically connected, and the end faces of the drain 1062 and each third semiconductor strip P3 away from the first semiconductor strip P1 are electrically connected.

[0041] In the embodiments of this application, reference is made to Figures 1 to 5 The second insulating layer 105 and the first insulating layer 103 include a first via G1 and a second via G2. The first via G1 exposes one end of each second semiconductor strip P2 away from the first semiconductor strip P1, and the second via G2 exposes one end of each third semiconductor strip P3 away from the first semiconductor strip P1. The source 1061 covers the first via G1, and the source 1061 and the exposed ends of each second semiconductor strip P2 away from the first semiconductor strip P1 are electrically connected. The drain 1062 covers the second via G2, and the drain 1062 and the exposed ends of each third semiconductor strip P3 away from the first semiconductor strip P1 are electrically connected.

[0042] Optionally, the first via G1 can be a via for connecting the source 1061 and each of the second semiconductor strips P2, and the second via G2 can be a via for connecting the drain 1062 and each of the third semiconductor strips P3.

[0043] In this embodiment, the process of forming semiconductor layer 102 includes: forming a semiconductor thin film; processing the semiconductor thin film using nanoimprinting and etching processes to obtain multiple semiconductor strips; and patterning the multiple semiconductor strips (photolithography etching process) to define the channels of the thin-film transistors to obtain semiconductor layer 102. In other words, during the formation of semiconductor layer 102, the photolithography etching process has the first etching effect on the multiple semiconductor strips.

[0044] Furthermore, the first via G1 and the second via G2 in the first insulating layer 103 and the second insulating layer 105 are also formed based on photolithography etching. That is, during the formation of the first via G1 and the second via G2, the second semiconductor strip P2 exposed by the first via G1 and the third semiconductor strip P3 exposed by the second via G2 will be affected by the second etching, while the first semiconductor strip P1 not exposed by the first via G1 and the second via G2 will not be affected by the second etching.

[0045] For the reasons stated above, the second semiconductor strip P2 exposed by the first via G1 and the third semiconductor strip P3 exposed by the second via G2 may only retain a shorter portion. (Reference) Figure 1 The distance k3 between the end of the second semiconductor strip P2 away from the first semiconductor strip P1 and the side of the first via G1 near the second portion 1022 is less than the distance k4 between the end of the second semiconductor strip P2 away from the first semiconductor strip P1 and the side of the first via G1 away from the second portion 1022. The distance k5 between the end of the third semiconductor strip P3 away from the first semiconductor strip P1 and the side of the second via G2 near the second portion 1022 is less than the distance k6 between the end of the third semiconductor strip P3 away from the first semiconductor strip P1 and the side of the second via G2 away from the second portion 1022.

[0046] Optional, see reference Figure 1 The orthographic projections of multiple second semiconductor strips P2 on the substrate 200 can be located in the edge region of the orthographic projection of the first via G1 on the substrate 200, which is close to the edge region of the orthographic projection of the second via G2 on the substrate 200. The orthographic projections of multiple third semiconductor strips P3 on the substrate 200 can be located in the edge region of the orthographic projection of the second via G2 on the substrate 200, which is close to the edge region of the orthographic projection of the first via G1 on the substrate 200.

[0047] Optionally, the lengths of the plurality of second semiconductor strips P2 exposed by the first via G1 along the first direction X may be the same or different, and this embodiment does not limit this. The lengths of the plurality of third semiconductor strips P3 exposed by the second via G2 along the first direction X may be the same or different, and this embodiment does not limit this.

[0048] In this embodiment, the areas of the second semiconductor strip P2 exposed by the first via G1 and the third semiconductor strip P3 exposed by the second via G2 that have been over-etched after being affected by the second etching will be further etched down to the buffer layer 101, thereby referencing Figures 6 to 8 The surface of the buffer layer 101 away from the substrate 200 can be exposed by the first via G1 and the second via G2, that is, the source electrode 1061 can contact the buffer layer 101 exposed by the first via G1, and the drain electrode 1062 can contact the buffer layer 101 exposed by the second via G2.

[0049] Optional, see reference Figure 7 and Figure 8 The buffer layer 101 includes a first target portion 1011 and a second target portion 1012. A first via G1 exposes the first target portion 1011, and the orthographic projection of the first target portion 1011 on the substrate 200 is located between the end of the second semiconductor strip P2 away from the first semiconductor strip P1 and the side of the first via G1 away from the second portion 1022. That is, the first target portion 1011 can be the portion of the buffer layer 101 exposed by the first via G1, and the orthographic projection of the first target portion 1011 on the substrate 200 is located on the side of the second semiconductor strip P2 away from the orthographic projection of the second portion 1022 on the substrate 200. A second via G2 exposes the second target portion 1012, and the orthographic projection of the second target portion 1012 on the substrate 200 is located between the end of the third semiconductor strip P3 away from the first semiconductor strip P1 and the side of the second via G2 away from the second portion 1022. That is, the second target portion 1012 can be the portion of the buffer layer 101 exposed by the second via G2, and the orthographic projection of the second target portion 1012 on the substrate 200 is on the side away from the orthographic projection of the third semiconductor strip P3 on the substrate 200.

[0050] Optional, see reference Figure 6 and Figure 7 The first target portion 1011, on the side away from the substrate 200, includes a plurality of first protrusions Q1 extending along a first direction X and arranged along a second direction Y. The plurality of first protrusions Q1 and the plurality of second semiconductor strips P2 are arranged in a one-to-one correspondence, and the first protrusions Q1 and the corresponding second semiconductor strips P2 are arranged collinearly along the first direction X.

[0051] In the embodiments of this application, reference is made to Figure 9The distance k7 between the ends of the initial second semiconductor strips P2a away from the second portion 1022 and the side of the first via G1 near the second portion 1022 before the multiple second semiconductor strips P2 are etched is greater than the distance k8 between the ends of the multiple initial second semiconductor strips P2a away from the second portion 1022 and the side of the first via G1 away from the second portion 1022. Optionally, the distance between the ends of the multiple initial second semiconductor strips P2a away from the second portion 1022 and the side of the first via G1 near the second portion 1022 can be approximately the same, that is, the ends of the multiple initial second semiconductor strips P2a away from the second portion 1022 can be aligned in the second direction Y.

[0052] Optionally, the plurality of first protrusions Q1 may be formed by etching the second semiconductor strip P2 onto the buffer layer 101 after the second semiconductor strip P2 has been etched. For example, the plurality of first protrusions Q1 may be formed in the region after the initial second semiconductor strip P2a has been etched, and the spacing between two adjacent first protrusions Q1 may be formed by the spacing between two adjacent initial second semiconductor strips P2a.

[0053] refer to Figure 6 and Figure 8 The second target portion 1012, on the side away from the substrate 200, includes a plurality of second protrusions Q2 extending along a first direction X and arranged along a second direction Y. The plurality of second protrusions Q2 and the plurality of third semiconductor strips P3 are arranged in a one-to-one correspondence, and the second protrusions Q2 and the corresponding third semiconductor strips P3 are collinear along the first direction X.

[0054] In this embodiment, the distance k9 between the ends of the multiple initial third semiconductor strips P3a away from the second portion 1022 and the side of the second via G2 close to the second portion 1022 before the multiple third semiconductor strips P3 are over-etched is greater than the distance k10 between the ends of the multiple initial third semiconductor strips P3a away from the second portion 1022 and the side of the second via G2 away from the second portion 1022. Optionally, the distance between the ends of the multiple initial third semiconductor strips P3a away from the second portion 1022 and the side of the second via G2 close to the second portion 1022 can be approximately the same, that is, the ends of the multiple initial third semiconductor strips P3a away from the second portion 1022 can be aligned in the second direction Y.

[0055] Optionally, the plurality of second protrusions Q2 may be formed by etching the third semiconductor strip P3 onto the buffer layer 101 after the third semiconductor strip P3 has been etched. For example, the plurality of second protrusions Q2 may be formed in the region after the initial third semiconductor strip P3a has been etched, and the spacing between two adjacent second protrusions Q2 may be formed by the spacing between two adjacent initial third semiconductor strips P3a.

[0056] In the embodiments of this application, reference is made to Figure 7 and Figure 8 The areas of the buffer layer 101 exposed by the first via G1 and the areas exposed by the second via G2 on the surface away from the substrate 200 can have an uneven morphology. The recessed areas may be formed due to the buffer layer 101 being over-etched to a greater depth between the semiconductor strips, and the protruding areas may be formed due to the buffer layer 101 being over-etched to a shallower depth in the areas where the semiconductor strips are present.

[0057] In the embodiments of this application, reference is made to Figure 1 The orthographic projection of the first via G1 onto the substrate 200 can be rectangular, and the orthographic projection of the second via G2 onto the substrate 200 can also be rectangular. Alternatively, Figure 10 This is a top view of another thin-film transistor provided in an embodiment of this application. (Reference) Figure 10 The orthographic projection of the first via G1 onto the substrate 200 can be elliptical, and the orthographic projection of the second via G2 onto the substrate 200 can also be elliptical. This application embodiment does not limit the shape of the orthographic projections of the first via G1 and the second via G2 onto the substrate 200.

[0058] Optionally, regardless of the shape of the first via G1, the distance between the end of the second semiconductor strip P2 away from the first semiconductor strip P1 and the side of the first via G1 near the second portion 1022 can be the distance in the second direction Y between the end of the second semiconductor strip P2 away from the first semiconductor strip P1 and the side of the first via G1 near the second portion 1022.

[0059] Optionally, regardless of the shape of the second via G2, the distance between the end of the third semiconductor strip P3 away from the first semiconductor strip P1 and the side of the second via G2 near the second portion 1022 can be the distance in the second direction Y between the end of the third semiconductor strip P3 away from the first semiconductor strip P1 and the side of the second via G2 near the second portion 1022.

[0060] In this embodiment, the width of the first via G1 in the second direction Y is greater than the distance in the second direction Y between the two farthest sides of the plurality of second semiconductor strips P2. That is, the first via G1 can expose each of the plurality of second semiconductor strips P2. This ensures that the source 1061 can be connected to each second semiconductor strip P2, improving the performance of the thin-film transistor 100.

[0061] Optionally, the number of second semiconductor strips P2 included in the first part 1021 can be n, where n can be a positive integer greater than or equal to 2. For example... Figure 1 The first part 1021 includes 12 second semiconductor strips P2. This application embodiment does not limit the number of second semiconductor strips P2 included in the first part 1021.

[0062] Optionally, the plurality of second semiconductor strips P2 include a first second semiconductor strip P2, a second second semiconductor strip P2, ..., an nth second semiconductor strip P2. The first second semiconductor strip P2 includes a third semiconductor edge 102c away from the nth second semiconductor strip P2, and the nth second semiconductor strip P2 includes a fourth semiconductor edge 102d away from the first second semiconductor strip P2. The width k11 of the first via G1 in the second direction Y is greater than the distance k12 between the third semiconductor edge 102c and the fourth semiconductor edge 102d along the second direction Y.

[0063] Optionally, the minimum distance between the edge of the first via G1 and the edge of the third semiconductor 102c can be greater than or equal to 1 μm. The minimum distance between the edge of the first via G1 and the edge of the fourth semiconductor 102d can be greater than or equal to 1 μm.

[0064] In this embodiment, the width of the second via G2 in the second direction Y is greater than the distance in the second direction Y between the two most distant third semiconductor strips P3. That is, the second via G2 can expose each of the multiple third semiconductor strips P3. This ensures that the source 1061 can be connected to each third semiconductor strip P3, improving the performance of the thin-film transistor 100.

[0065] Optionally, the third part 1023 may include n third semiconductor strips P3, where n can be a positive integer greater than or equal to 2. For example... Figure 1 The third part 1023 includes 12 third semiconductor strips P3. This application embodiment does not limit the number of third semiconductor strips P3 included in the first part 1021.

[0066] Optionally, the plurality of third semiconductor strips P3 include a first third semiconductor strip P3, a second third semiconductor strip P3, ..., an nth third semiconductor strip P3. The first third semiconductor strip P3 includes a fifth semiconductor edge 102e away from the nth third semiconductor strip P3, and the nth third semiconductor strip P3 includes a sixth semiconductor edge 102f away from the first third semiconductor strip P3. The width k13 of the second via G2 in the second direction Y is greater than the distance k14 between the fifth semiconductor edge 102e and the sixth semiconductor edge 102f along the second direction Y.

[0067] Optionally, the minimum distance between the edge of the second via G2 and the edge of the fifth semiconductor 102e can be greater than or equal to 1 μm.

[0068] Figure 11 This is a top view of another thin-film transistor provided in the embodiments of this application. Figure 12 yes Figure 11 Cross-sectional view along the BB direction. Figure 13 yes Figure 11 Cross-sectional view along the CC direction. (Reference) Figure 11 The first portion 1021 and the third portion 1023 can be planar structures. The source 1061 can be electrically connected to the side of the first portion 1021 away from the substrate 200, and the drain 1062 can be electrically connected to the side of the third portion 1023 away from the substrate 200. Additionally, Figure 11 The cross-sectional view along the AA direction can be referenced above. Figure 2 .

[0069] Optionally, the second insulating layer 105 and the first insulating layer 103 include a first via G1 and a second via G2. The first via G1 exposes a portion of the first portion 1021 away from the substrate 200, and the second via G2 exposes a portion of the third portion 1023 away from the substrate 200. The source electrode 1061 covers the first via G1, and the source electrode 1061 and the first portion 1021 exposed by the first via G1 are electrically connected. The drain electrode 1062 covers the second via G2, and the drain electrode 1062 and the second portion 1022 exposed by the second via G2 are electrically connected.

[0070] Optionally, the width of the first portion 1021 along the second direction Y can be greater than or equal to the distance between the relatively distant sides of the two first semiconductor strips P1 that are furthest apart in the second direction Y. For example, the width of the first portion 1021 along the second direction Y can be greater than or equal to the distance between the first semiconductor edge 101a and the second semiconductor edge 102b along the second direction Y. This ensures that the first portion 1021 can be connected to each of the multiple first semiconductor strips P1, ensuring that each first semiconductor strip P1 can function as a channel of the thin-film transistor 100.

[0071] Optionally, the width of the third portion 1023 along the second direction Y can be greater than or equal to the distance between the two farthest sides of the first semiconductor strips P1 in the second direction Y. For example, the width of the third portion 1023 along the second direction Y can be greater than or equal to the distance between the first semiconductor edge 101a and the second semiconductor edge 102b along the second direction Y. This ensures that the third portion 1023 can be connected to each of the first semiconductor strips P1, ensuring that each first semiconductor strip P1 can function as a channel of the thin-film transistor 100.

[0072] Optionally, when the first portion 1021 has a planar structure, the first via G1 may expose or cover the edge of the first portion 1021; this embodiment does not limit this. Similarly, when the third portion 1023 has a planar structure, the second via G2 may expose or cover the edge of the third portion 1023; this embodiment does not limit this.

[0073] Optional, see reference Figure 1 The distance k15 between the first via G1 and the gate layer 104, and the distance k16 between the second via G2 and the gate layer 104, can be in the range of 1.5μm to 3μm, for example, it can be 2μm or 2.5μm, etc.

[0074] In this application embodiment, performance tests were performed on conventional thin-film transistors and the thin-film transistors of this application embodiment, resulting in Table 1 below. As can be seen from Table 1, the subthreshold swing (SS) of the thin-film transistor of this application embodiment is smaller than that of conventional thin-film transistors, and the on-state current (Ion) of the thin-film transistor of this application embodiment is larger than that of conventional thin-film transistors. Furthermore, the off-state current (Ioff) of the thin-film transistor of this application embodiment is only slightly different from that of conventional thin-film transistors, resulting in a smaller impact. In Table 1 below, the unit of subthreshold swing (SS) can be V / dec (volts per decade), and the units of on-state current (Ion) and off-state current (Ioff) can be A (amperes). E-07 is used to represent 10 to the power of -7. E-11 is used to represent 10 to the power of -11.

[0075] Table 1

[0076] In addition, output capability tests were performed on conventional thin-film transistors and the thin-film transistors of the embodiments of this application, referring to... Figure 14 and Figure 15 It can be seen that the output capability of the thin-film transistor 100 in this embodiment is significantly enhanced, and the saturation point is significantly shifted, indicating that the thin-film transistor in this embodiment has good performance. Figure 14 and Figure 15 The horizontal axis represents the source-drain voltage (Vd), measured in amperes (A), and the vertical axis represents the drain current (Id), measured in volts (V). In the vertical axis, E-06 represents 10 to the power of -6, E-07 represents 10 to the power of -7, and E-08 represents 10 to the power of -8.

[0077] In summary, this application provides a thin-film transistor (TFT) comprising a buffer layer, a semiconductor layer, a first insulating layer, a gate layer, a second insulating layer, and source / drain layers stacked sequentially. The second portion of the overlapping orthographic projections of the semiconductor layer and the gate layer includes multiple first semiconductor strips. Therefore, the width of the channel region formed by the gate layer and the second portion can achieve a certain gain per unit projected area, thereby improving the overall performance of the TFT. Furthermore, the improved control of the channel region by the gate layer can significantly increase the on-state current of the TFT, enhance its output capability, shift the saturation point of the TFT forward, reduce the power consumption of the driving device layer in the display panel, and improve the display effect of the display device.

[0078] Figure 16 This is a flowchart illustrating a method for fabricating a thin-film transistor according to an embodiment of this application. (Reference) Figure 16 The method includes: Step S101: Form a buffer layer and a semiconductor thin film on a substrate.

[0079] Optionally, the substrate 200 can be a glass substrate. The buffer layer 101 can be a stack of silicon nitride (SiN) and silicon oxide (SiO), with the silicon nitride layer having a thickness of approximately 500 Å and the silicon oxide layer having a thickness in the range of 3000 Å to 5000 Å. The semiconductor thin film can be made of amorphous silicon, with a thickness of approximately 500 Å. Subsequently, laser annealing technology can be used for crystallization to form polycrystalline silicon. (Reference) Figure 17 The buffer layer 101 is located on one side of the substrate 200, and the semiconductor thin film 100a is located on the side of the buffer layer 101 away from the substrate 200.

[0080] Step S102: Form nanoimprint adhesive on the side of the semiconductor thin film away from the substrate.

[0081] In this embodiment, a nanoimprint template can be used to define a polycrystalline silicon nanoarray. The template can be adjusted as needed; for example, the size of the template can be the same as the size of the substrate 200, or it can be a defined specific region. Optionally, in this embodiment, a nanoarray with arbitrary repeating periods in any region of the substrate 200 can be achieved by changing the nanoimprint template.

[0082] Optional, see reference Figure 18 The nanoimprinting adhesive may include multiple spaced adhesive strips 100b. Referring to Table 2 below, the thickness H1 of the nanoimprinting adhesive can range from 96 nm to 135 nm, and the width W1 of each adhesive strip can range from 41 nm to 51 nm. The spacing S1 between two adjacent adhesive strips 100b can range from 53 nm to 77 nm. The residual adhesive thickness R can range from 15 nm to 30 nm.

[0083] Table 2

[0084] Step S103: Etch the semiconductor thin film and remove the nanoimprint adhesive to obtain the initial semiconductor layer.

[0085] In the embodiments of this application, reference is made to Figure 19An etching process is used to remove the nanoimprint sizing agent and all the polysilicon not covered by the nanoimprint sizing agent, leaving a polysilicon nanoarray. Optionally, the thickness of the polysilicon strips 100c included in the polysilicon nanoarray is greater than the thickness of the semiconductor film. For example, the thickness of the polysilicon strips 100c can be in the range of 47nm to 400nm, or approximately 60nm. Furthermore, the width of the polysilicon strips 100c is mainly limited by process capabilities, and can be in the range of 30nm to 1μm (micrometer).

[0086] Optionally, the depth-to-width ratio of the polysilicon strip 100c can be in the range of 47 / 1000 to 400 / 300. For example, the width-to-width ratio of the polysilicon strip 100c can be 1:1. The polysilicon strip 100c can be used at least to form the first semiconductor strip P1 of the thin-film transistor 100.

[0087] Optionally, referring to Table 3, the thickness H2 of the polysilicon strip 100c can be in the range of 58nm to 80nm, the width W2 of the polysilicon strip 100c can be in the range of 59nm to 75nm, and the spacing S2 between two adjacent polysilicon strips 100c can be in the range of 50nm to 65nm.

[0088] Table 3

[0089] In this embodiment, the semiconductor thin film is protected and retained in the area where the nanoimprint stencil is coated during the subsequent etching process. The nanoimprint stencil is then simultaneously ashed and carried away during etching, leaving a polycrystalline silicon nanoarray. Optionally, the polycrystalline silicon nanoarray may include polycrystalline silicon strips that are continuous in the first direction X.

[0090] In the embodiments of this application, reference is made to Figure 19 and Figure 20 The size of the nanoimprint template is the same as the size of the substrate 200. The resulting polycrystalline silicon nanoarray includes polycrystalline silicon strips that can be located in various regions of the substrate 200. Figure 19 It can be Figure 20 Cross-sectional view along the JJ direction.

[0091] Or, refer to Figure 21 and Figure 22 The nanoimprint template is selectively set in the channel region or other regions. A polysilicon nanoarray can be formed in the channel region (which will be covered by the gate layer 104 formed later), while other regions (which may include the source and drain regions of thin film transistors) do not need to be defined as nanoarrays. Figure 21 It can be Figure 22Cross-sectional view along the JJ direction.

[0092] Step S104: Pattern the initial semiconductor layer to obtain the semiconductor layer.

[0093] In this embodiment, the patterning process may include photoresist coating, exposure, development, etching, and photoresist removal. After obtaining the polycrystalline silicon nanoarray comprising the initial semiconductor layer 102, a patterning process can be used to obtain the semiconductor layer 102. The semiconductor layer 102 may include a first portion 1021, a second portion 1022, and a third portion 1023 arranged along a first direction X. The second portion 1022 includes a plurality of first semiconductor strips P1 extending along the first direction X and arranged along the second direction Y.

[0094] Optionally, the first part 1021 may include a plurality of initial second semiconductor strips P2a extending along the first direction X and arranged along the second direction Y, with each of the initial second semiconductor strips P2a corresponding to a plurality of first semiconductor strips P1. Furthermore, the third part 1023 may include a plurality of initial third semiconductor strips P3a extending along the first direction X and arranged along the second direction Y, with each of the initial third semiconductor strips P3a corresponding to a plurality of first semiconductor strips P1. This approach is based on the nanoarray definition of the source and drain regions of the thin-film transistor in step S103 described above.

[0095] Alternatively, the first part 1021 can be a planar structure, and the third part 1023 can be a planar structure. This approach is based on the fact that the source and drain regions of the thin-film transistor are not defined as nanoarrays in step S103 above.

[0096] Step S105: Form a first insulating layer, a gate layer, a second insulating layer, and a source / drain layer.

[0097] In the embodiments of this application, reference is made to Figure 23 The first insulating film 100d can be formed using atomic layer deposition (ALD) technology. The first insulating film 100d can cover the first part 1021, the second part 1022, and the third part 1023.

[0098] Optional, see reference Figure 24 and Figure 25The process of forming the gate layer 104 includes: forming a gate thin film 100e, and patterning the gate thin film 100e to obtain the gate layer 104. The orthographic projection of the gate layer 104 on the substrate 200 and the orthographic projection of the second portion 1022 on the substrate 200 overlap. Optionally, the width of the gate layer 104 in the second direction Y is greater than the distance in the second direction Y between the two sides of the two first semiconductor strips P1 that are furthest apart in the second direction Y.

[0099] Optionally, after forming the gate layer 104, refer to Figure 26 A second insulating film 100f can be formed on the side of the gate layer 104 away from the substrate 200. Then refer to Figure 27 An etching process is used to etch the second insulating film 100f and the first insulating film 100d to form the first via G1 and the second via G2. Furthermore, during the formation of the first via G1 and the second via G2, multiple initial second semiconductor strips P2a and multiple initial third semiconductor strips P3a may be etched to obtain multiple second semiconductor strips P2 and multiple third semiconductor strips P3. Figure 27 It can be after forming the first via and the second via. Figure 1 A schematic diagram showing the cross-sections taken along the DD direction, the EE direction, and the FF direction, pieced together.

[0100] Among them, reference Figure 9 The first via G1 exposes each of the plurality of initial second semiconductor strips P2a, and the second via G2 exposes each of the plurality of initial third semiconductor strips P3a. Due to the effects of the two etching steps S104 and S105, refer to Figure 1 The initial second semiconductor strip P2a exposed by the first via G1 may retain only a shorter portion, which can be the second semiconductor strip P2. Similarly, the initial third semiconductor strip P3a exposed by the second via G2 may retain only one shorter end, which can be the third semiconductor strip P3.

[0101] Optional, see reference Figure 1 The orthographic projections of multiple second semiconductor strips P2 on the substrate 200 can be located in the edge region of the orthographic projection of the first via G1 on the substrate 200, which is close to the edge region of the orthographic projection of the second via G2 on the substrate 200. The orthographic projections of multiple third semiconductor strips P3 on the substrate 200 can be located in the edge region of the orthographic projection of the second via G2 on the substrate 200, which is close to the edge region of the orthographic projection of the first via G1 on the substrate 200.

[0102] In the embodiments of this application, reference is made to Figure 28After forming the first via G1 and the second via G2, source and drain films can be formed. These films are then patterned to obtain source 1061 and drain 1062. Source 1061 can cover the first via G1, and each of the plurality of second semiconductor strips P2 exposed by source 1061 and the first via G1 is electrically connected. Drain 1062 can cover the second via G2, and each of the plurality of third semiconductor strips P3 exposed by drain 1062 and the second via G2 is electrically connected.

[0103] Optionally, the thickness of the first insulating layer 103 can be in the range of 10nm to 20nm, for example, 15nm. The material of the gate layer 104 can include a stack of aluminum (Al) and molybdenum (Mo), with the aluminum layer having a thickness of approximately 80nm and the molybdenum layer having a thickness of approximately 40nm. The second insulating layer 105 can be a stack of silicon oxide (SiO) and silicon nitride (SiN), with the silicon oxide layer having a thickness of approximately 300nm and the silicon nitride layer having a thickness of approximately 200nm. The source / drain layer 106 can be a titanium (Ti), aluminum (Al), and titanium (Ti) triple stack structure (denoted as Ti / Al / Ti), with the titanium layer having a thickness of approximately 50nm and the aluminum layer having a thickness of approximately 400nm.

[0104] In summary, this application provides a method for fabricating a thin-film transistor (TFT). The TFT fabricated by this method includes a buffer layer, a semiconductor layer, a first insulating layer, a gate layer, a second insulating layer, and a source / drain layer stacked sequentially. The second portion of the overlapping orthographic projections of the semiconductor layer and the gate layer includes multiple first semiconductor strips. Therefore, the width of the channel region formed by the gate layer and the second portion can achieve a certain gain per unit projected area, thereby improving the overall performance of the TFT. Furthermore, the improved control of the channel region by the gate layer can significantly increase the on-state current of the TFT, enhance its output capability, shift the saturation point of the TFT forward, and reduce the power consumption of the driving device layer in the display panel.

[0105] Figure 29 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. (Reference) Figure 29 The display panel includes: a substrate 200, a driving device layer 300, and a light-emitting device layer 400.

[0106] The driving device layer 300 includes multiple pixel circuits, each pixel circuit comprising multiple thin-film transistors and at least one storage capacitor. At least one of the multiple thin-film transistors included in the pixel circuit can be the thin-film transistor provided in the above embodiments.

[0107] In addition, the light-emitting device layer 400 includes multiple light-emitting units corresponding to multiple pixel circuits, and the pixel circuits provide driving signals to the corresponding light-emitting units.

[0108] Optionally, the light-emitting unit can be a liquid crystal display (LCD) light-emitting unit, and the display panel can be an LCD display panel. Alternatively, the light-emitting unit can be an organic light-emitting diode (OLED), and the display panel can be an OLED display panel. Another option is that the light-emitting unit can be a micro LED, and the display panel can be a Micro LED display panel. Yet another option is that the light-emitting unit can be a quantum dot LED (QD LED), and the display panel can be a QD LED display panel.

[0109] Optionally, if the display panel is a liquid crystal display panel, the light-emitting device layer may include a pixel electrode layer, a liquid crystal layer, and a common electrode layer. The pixel electrode layer may include multiple pixel electrodes corresponding to multiple light-emitting units, the liquid crystal layer may include liquid crystal molecules, and the common electrode layer may include a common electrode.

[0110] Optionally, if the display panel is an organic light-emitting display panel, the light-emitting device layer may include an anode layer, a pixel defining layer, a light-emitting layer, and a cathode layer. The anode layer may include multiple anode patterns corresponding to multiple light-emitting units. The pixel defining layer may include multiple cutouts corresponding to the multiple anode patterns, each cutout exposing at least a portion of a corresponding anode pattern. The light-emitting layer may include multiple light-emitting patterns corresponding to multiple light-emitting units, each light-emitting pattern being connected to an anode pattern through a cutout. The cathode layer may cover multiple light-emitting patterns, and the cathode layer may be a common cathode for multiple light-emitting units.

[0111] In this embodiment, the driving device layer 300 may include a first sub-driving layer 301 and a second sub-driving layer 302 disposed away from the substrate 200. A portion of the thin-film transistors in the pixel circuit are located in the first sub-driving layer 301, and another portion are located in the second sub-driving layer 302.

[0112] Optional, see reference Figure 30 and Figure 31 A portion of the thin-film transistors located in the first sub-driving layer 301 can all be the thin-film transistor 100 provided in the above embodiments. (See reference...) Figure 30 The other portion of the thin-film transistor located in the second sub-driving layer 302 can be a low-temperature polysilicon (LTPS) thin-film transistor. Alternatively, refer to... Figure 31The other part of the thin-film transistor located in the second sub-driving layer 302 can be an oxide thin-film transistor.

[0113] Alternatively, another portion of the thin-film transistors located in the second sub-driving layer 302 can all be the thin-film transistors 100 provided in the above embodiments. A portion of the thin-film transistors located in the first sub-driving layer 301 can be LTPS thin-film transistors or oxide thin-film transistors.

[0114] refer to Figure 30 The driving device layer 300 includes a buffer layer 011, a first semiconductor layer 012, a first insulating layer 013, a first gate layer 014, a second insulating layer 015, a second semiconductor layer 016, a third insulating layer 017, a second gate layer 018, a fourth insulating layer 019, and a source-drain layer 0110. The first semiconductor layer 012 can be the semiconductor layer 102 of the thin-film transistor provided in this embodiment, i.e., the first semiconductor layer 012 includes a polysilicon array. The second semiconductor layer 016 can be the semiconductor layer of the low-temperature polysilicon thin-film transistor in the second sub-driving layer 302. The source-drain layer 0110 may include a first source 1061 and a first drain 1062. The first source 1061 can be connected to the source region of the first semiconductor layer 012, and the first drain 1062 can be connected to the drain region of the first semiconductor layer 012. The source-drain layer 0110 may further include a second source 01101 and a second drain 01102. The second source 01101 can be connected to the source region of the second semiconductor layer 016, and the second drain 01102 can be connected to the drain region of the second semiconductor layer 016. In this case, the driving device layer 300 can be referred to as a low-temperature polysilicon (LTPS) dual-layer driving backplane.

[0115] refer to Figure 31The driving device layer 300 includes a buffer layer 011, a first semiconductor layer 012, a first insulating layer 013, a first gate layer 014, a second insulating layer 014, an oxide layer 016, a third insulating layer 017, a second gate layer 018, a fourth insulating layer 019, and a source / drain layer 0110. The first semiconductor layer 012 can be the semiconductor layer 102 of the thin-film transistor 100 provided in this embodiment, i.e., the first semiconductor layer 012 includes a polysilicon array. The oxide layer 016 can be the oxide layer of the oxide thin-film transistor in the second sub-driving layer 302. The source / drain layer 0110 may include a first source 1061 and a first drain 1062. The first source 1061 can be connected to the source region of the first semiconductor layer 012, and the first drain 1062 can be connected to the drain region of the first semiconductor layer 012. The source-drain layer 0110 may also include a second source 01101 and a second drain 01102. The second source 01101 may be connected to the source region of the oxide layer, and the second drain 01102 may be connected to the drain region of the oxide layer. In this case, the driving device layer 300 may be referred to as a low-temperature polycrystalline oxide (LTPO) driving backplane.

[0116] In this embodiment, the semiconductor layers 102 of the multiple thin-film transistors included in the pixel circuit are disposed on the same layer. Optionally, refer to... Figure 32 The pixel circuit includes multiple thin-film transistors, all of which are the thin-film transistors provided in the above embodiments. Alternatively, refer to... Figure 33 The pixel circuit includes multiple thin-film transistors, some of which are thin-film transistors 100 provided in the above embodiment, and the other part of which are LTPS thin-film transistors.

[0117] refer to Figure 33The driving device layer 300 includes a buffer layer 011, a semiconductor layer 012, a first insulating layer 013, a gate layer 014, a second insulating layer 015, and a source-drain layer 0110. The semiconductor layer 012 may include a first semiconductor portion of the thin-film transistor 100 provided in this embodiment (the first semiconductor portion includes a polysilicon array, and the first semiconductor portion can serve as the semiconductor layer 102 of the thin-film transistor 100) and a second semiconductor portion of a low-temperature polysilicon thin-film transistor (the second semiconductor portion does not include the polysilicon array). The source-drain layer 0110 may include a first source 1061 and a first drain 1062. The first source 1061 can be connected to the source region of the first semiconductor portion, and the first drain 1062 can be connected to the drain region of the first semiconductor portion. The source-drain layer 0110 may also include a second source 01101 and a second drain 01102. The second source 01101 can be connected to the source region of the second semiconductor portion, and the second drain 01102 can be connected to the drain region of the second semiconductor portion. In this case, the driving device layer 300 can be referred to as a low-temperature polysilicon (LTPS) driving backplane.

[0118] Optionally, the driving device layer 300 may include a planarization layer (not shown) located on the side of the source / drain layer 0110 away from the substrate 200. The light-emitting device layer 400 may be located on the side of the planarization layer away from the substrate 200. The planarization layer can be used to provide a relatively flat surface for the fabrication of the light-emitting device layer 400, thereby improving the fabrication yield of the light-emitting device layer.

[0119] Since the display panel can have essentially the same technical effects as the thin-film transistors described in the previous embodiments, for the sake of brevity, the technical effects of the display panel will not be described again here.

[0120] Figure 34 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. (Reference) Figure 34 The display device includes a power supply component 02 and a display panel 01 as provided in the above embodiment. The power supply component 02 is connected to the display panel 01 and is used to supply power to the display panel 01.

[0121] Optionally, the display device can be an LCD display device, an OLED display device, a MicroLED display device, or a Quantum Dot LED display device, etc. The display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, car navigation systems, and e-readers—any product or component with a display function.

[0122] Since the display device can have essentially the same technical effects as the thin-film transistor described in the previous embodiments, the technical effects of the thin-film transistor will not be repeated here for the sake of brevity.

[0123] The terminology used in the embodiments section of this application is for explaining the embodiments of this application only and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0124] The Description of Embodiments section of this application describes several embodiments; however, this description is exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0125] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0126] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0127] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Furthermore, the drawings schematically illustrate ideal examples, and this application is not limited to the shapes or numerical values ​​shown in the drawings.

[0128] The ordinal numbers "first," "second," and "third" used in this specification are for the purpose of avoiding confusion among the constituent elements, not for limiting the quantity. The term "multiple" in this application refers to two or more quantities.

[0129] The thickness range of the film layer in this specification is A to B, which means that the thickness is between A and B, including the two endpoints of A and B.

[0130] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0131] In this specification, unless otherwise expressly specified and limited, the terms "connected" or "linked" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of the above terms in this application according to the specific circumstances.

[0132] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode (drain terminal, drain region, or drain electrode), and a source electrode (source terminal, source region, or source electrode). A transistor has a channel region between the drain and source electrodes, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0133] In this specification, the first terminal of a transistor can be the drain electrode and the second terminal of a transistor can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0134] In this specification, "connection" includes the situation where constituent elements are connected together by a component that has a certain electrical function. There are no particular limitations on the "component that has a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0135] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0136] In this application, "thickness" and "height" refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer closer to the substrate.

[0137] In this application, "approximately" means a value that is not strictly defined and is within the allowable range of process and measurement errors.

[0138] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A thin-film transistor, characterized in that, The thin-film transistor includes: A buffer layer, a semiconductor layer, a first insulating layer, a gate layer, a second insulating layer, and a source / drain layer are sequentially stacked on a substrate along a side away from the substrate. The semiconductor layer includes a first portion, a second portion, and a third portion arranged and connected along a first direction. The orthographic projection of the second portion on the substrate overlaps with the orthographic projection of the gate layer on the substrate. The second portion includes a plurality of first semiconductor strips extending along the first direction and arranged along a second direction. The first direction and the second direction are perpendicular. The source-drain layer includes a source and a drain, the source is electrically connected to the first portion, and the drain is electrically connected to the third portion.

2. The thin-film transistor according to claim 1, characterized in that, The width of the gate layer in the second direction is greater than the distance between the two sides of the two first semiconductor strips that are furthest apart in the second direction; the gate layer covers the plurality of first semiconductor strips in the second direction.

3. The thin-film transistor according to claim 1, characterized in that, The plurality of first semiconductor strips are spaced apart; One end of the plurality of first semiconductor strips in the first part and the second part are connected, and the other end of the plurality of first semiconductor strips in the third part and the second part are connected.

4. The thin-film transistor according to claim 3, characterized in that, The first part includes a plurality of second semiconductor strips extending along a first direction and arranged along a second direction, wherein the plurality of second semiconductor strips and the plurality of first semiconductor strips are connected in a one-to-one correspondence; The third part includes a plurality of third semiconductor strips extending along a first direction and arranged along a second direction, wherein the plurality of third semiconductor strips and the plurality of first semiconductor strips are connected in a one-to-one correspondence.

5. The thin-film transistor according to claim 4, characterized in that, The source is electrically connected to each of the plurality of second semiconductor strips, and the drain is electrically connected to each of the plurality of third semiconductor strips.

6. The thin-film transistor according to claim 5, characterized in that, The second semiconductor strip is connected to a corresponding first semiconductor strip, and the third semiconductor strip is connected to a corresponding first semiconductor strip; The source electrode is electrically connected to the end of each of the second semiconductor bars away from the first semiconductor bar, and the drain electrode is electrically connected to the end of each of the third semiconductor bars away from the first semiconductor bar.

7. The thin-film transistor according to claim 6, characterized in that, The second insulating layer and the first insulating layer include a first via and a second via; The first via exposes one end of each of the second semiconductor strips away from the first semiconductor strip, and the second via exposes one end of each of the third semiconductor strips away from the first semiconductor strip; The source electrode covers the first via, and the source electrode and the end of each of the second semiconductor strips exposed by the first via are electrically connected away from the first semiconductor strip; The drain covers the second via, and the drain and the end of each of the third semiconductor strips exposed by the second via are electrically connected away from the first semiconductor strip.

8. The thin-film transistor according to claim 7, characterized in that, The distance between the end of the second semiconductor strip away from the first semiconductor strip and the side of the first via closer to the second portion is less than the distance between the end of the second semiconductor strip away from the first semiconductor strip and the side of the first via away from the second portion; The distance between the end of the third semiconductor strip away from the first semiconductor strip and the side of the second via closer to the second portion is less than the distance between the end of the third semiconductor strip away from the first semiconductor strip and the side of the second via away from the second portion.

9. The thin-film transistor according to claim 8, characterized in that, The buffer layer includes a first target portion and a second target portion; The first via exposes the first target portion, and the orthographic projection of the first target portion on the substrate is located between the end of the second semiconductor strip away from the first semiconductor strip and the side of the first via away from the second portion; The second via exposes the second target portion, and the orthographic projection of the second target portion on the substrate is located between one end of the first semiconductor strip and the side of the second via away from the second portion. The first target portion includes a plurality of first protruding strips extending along a first direction and arranged along a second direction on the side away from the substrate; the plurality of first protruding strips and the plurality of second semiconductor strips are arranged in a one-to-one correspondence, and the first protruding strips and the corresponding second semiconductor strips are arranged collinearly along the first direction; The second target portion includes a plurality of second protruding strips extending along a first direction and arranged along a second direction on the side away from the substrate; the plurality of second protruding strips and the plurality of third semiconductor strips are arranged in a one-to-one correspondence, and the second protruding strips and the corresponding third semiconductor strips are arranged collinearly along the first direction.

10. The thin-film transistor according to claim 3, characterized in that, The source electrode is electrically connected to the side of the first portion away from the substrate, and the drain electrode is electrically connected to the side of the third portion away from the substrate.

11. The thin-film transistor according to claim 10, characterized in that, The second insulating layer and the first insulating layer include a first via and a second via; The first via exposes a portion of the first portion on the side away from the substrate, and the second via exposes a portion of the third portion on the side away from the substrate; The source electrode covers the first via, and the source electrode and the first portion exposed by the first via are electrically connected; The drain covers the second via, and the drain and the second portion exposed by the second via are electrically connected.

12. A method for fabricating a thin-film transistor, characterized in that, The method is used to prepare a thin-film transistor as described in any one of claims 1 to 11; the method includes: A buffer layer and a semiconductor thin film are formed on a substrate. Nanoimprint adhesive is formed on the side of the semiconductor thin film away from the substrate. The semiconductor thin film is etched and the nanoimprint adhesive is removed to obtain an initial semiconductor layer; The initial semiconductor layer is patterned to obtain a new semiconductor layer. A first insulating layer, a gate layer, a second insulating layer, and source / drain layers are formed; The semiconductor layer includes a first portion, a second portion, and a third portion arranged along a first direction. The orthographic projection of the second portion on the substrate overlaps with the orthographic projection of the gate layer on the substrate. The second portion includes a plurality of first semiconductor strips extending along the first direction and arranged along a second direction. The source-drain layer includes a source and a drain. The source is electrically connected to the first portion, and the drain is electrically connected to the third portion.

13. A display panel, characterized in that, The display panel includes: Substrate; A driving device layer, the driving device layer including a plurality of pixel circuits, the pixel circuit including a plurality of thin film transistors and at least one storage capacitor, wherein at least one of the plurality of thin film transistors included in the pixel circuit is a thin film transistor according to any one of claims 1 to 11. And a light-emitting device layer, the light-emitting device layer including a plurality of light-emitting units corresponding to the plurality of pixel circuits, the pixel circuits providing driving signals to the corresponding light-emitting units.

14. The display panel according to claim 13, characterized in that, The driving device layer includes a first sub-driving layer and a second sub-driving layer disposed away from the substrate. The pixel circuit includes a portion of thin-film transistors located in the first sub-driving layer and another portion of thin-film transistors located in the second sub-driving layer; Among them, a portion of the thin-film transistors located in the first sub-driving layer are thin-film transistors as described in any one of claims 1 to 11, and the other portion of the thin-film transistors located in the second sub-driving layer are low-temperature polycrystalline silicon thin-film transistors or oxide thin-film transistors.

15. The display panel according to claim 13, characterized in that, The pixel circuit includes multiple thin-film transistors whose semiconductor layers are disposed on the same layer; Each of the plurality of thin-film transistors included in the pixel circuit is a thin-film transistor as described in any one of claims 1 to 11; or, a portion of the plurality of thin-film transistors included in the pixel circuit are thin-film transistors as described in any one of claims 1 to 11.

16. The display panel according to any one of claims 13 to 15, characterized in that, The light-emitting unit is a liquid crystal light-emitting unit, or an organic light-emitting unit.

17. A display device, characterized in that, The display device includes: a power supply component and a display panel as described in any one of claims 13 to 16; The power supply component is connected to the display panel, and the power supply component is used to supply power to the display panel.

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