A four-port bidirectional SiC JFET device and its fabrication method

Abstract

The present application relates to the technical field of design and manufacture of silicon carbide power semiconductor devices, and particularly relates to a four-port bidirectional SiC JFET device and a manufacturing method thereof. The device comprises a second-conductivity-type SiC substrate, a first-conductivity-type buffer layer, a plurality of second-conductivity-type conductive channels and a plurality of first-conductivity-type control / voltage-withstanding layers which are alternately stacked, and a first source region and a second source region, a first gate electrode and a second gate electrode which are located on both sides of the alternately stacked structure. The buffer layer has a gradually decreasing doping concentration from the bottom to the top, and the control / voltage-withstanding layer has a gradually decreasing doping concentration from one side adjacent to the respective source region to the opposite side, and the two constitute a RESURF structure. The device is left-right symmetrical, has bidirectional low-resistance conduction and bidirectional high-voltage blocking functions. The manufacturing method adopts a gradually varying doping epitaxial growth buffer layer, multiple epitaxial growth of conductive channels and a gradually varying light transmittance mask ion implantation to form the control / voltage-withstanding layer, so as to realize accurate control of the doping concentration and the thickness.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide power semiconductor device design and manufacturing technology, and in particular to a four-port bidirectional SiC JFET device and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC) devices are suitable for high-voltage, high-current, high-temperature, and high-frequency applications. Replacing silicon-based devices significantly improves power conversion efficiency and reduces power conversion losses, and are currently widely used in high-end switching power supplies, on-board computers (OBCs) for new energy vehicles, and main electric drives for new energy vehicles. To further simplify circuit topologies, increase power density, and expand four-quadrant operation and bidirectional energy flow capabilities, traditional SiC devices (unidirectional switches) require reverse series connection, greatly increasing the complexity of control strategies and doubling conduction losses, potentially leading to circuit burnout. Bidirectional switching devices offer bidirectional low-resistance conduction and bidirectional high-voltage blocking capabilities. The voltage polarity on both sides can be dynamically reversed without the need for additional anti-reverse series transistors, increasing the freedom of topology design. Compared to the reverse series connection of unidirectional switches, bidirectional switching devices can also effectively increase operating frequency, facilitate heat dissipation design, and leverage the advantages of SiC materials and devices. However, existing bidirectional SiC devices struggle to achieve a good balance between on-resistance and withstand voltage, resulting in complex structures and high manufacturing difficulties. Summary of the Invention

[0003] In view of this, the purpose of this invention is to propose a four-port bidirectional SiC JFET device and its manufacturing method, so as to solve the problems of existing silicon carbide bidirectional devices having difficulty in achieving a good balance between on-resistance and withstand voltage, complex structure and high manufacturing difficulty.

[0004] To achieve the above objectives, the present invention provides a four-port bidirectional SiC JFET device, comprising: SiC substrate of the second conductivity type; A first conductivity type buffer layer located above the substrate; The buffer layer has multiple conductive channels of the second conductivity type and multiple control / voltage withstand layers of the first conductivity type. The conductive channels and the control / voltage withstand layers are alternately stacked in the vertical direction, with the bottom layer being the conductive channel and the top layer being the control / voltage withstand layer. The first source region and the second source region are located on opposite sides of the alternating stacked structure along the first direction and are in contact with the conductive channel. The first gate electrode and the second gate electrode are respectively located above the uppermost control / voltage withstand layer and are respectively disposed adjacent to the first source region and the second source region; The doping concentration of the buffer layer gradually decreases from bottom to top, and the doping concentration of the control / voltage withstand layer gradually decreases from one side adjacent to the respective source region to the other side. The buffer layer and the control / voltage withstand layer constitute a RESURF structure.

[0005] Preferably, a pn junction is formed between the conductive channel and the control / voltage withstand layer; the doping concentration and thickness of the conductive channel are configured such that: when the pn junction is zero-biased or forward-biased, the depletion layer thickness in the conductive channel is less than its thickness, so that multiple conductive channels are connected in parallel and conducting; when the pn junction is reverse-biased, the depletion layer thickness in the conductive channel is not less than its thickness, so that multiple conductive channels are completely depleted and turned off.

[0006] Preferably, the doping concentration and thickness of the control / voltage withstand layer are configured such that when the pn junction is reverse biased, the control / voltage withstand layer is not completely depleted, and as the reverse voltage of the device increases, the control / voltage withstand layer is gradually depleted to alleviate electric field accumulation.

[0007] Preferably, the buffer layer, the source region, and the substrate form an NPN or PNP structure; when the depletion region of the RESURF structure extends to the substrate, the NPN or PNP structure undergoes punch-through breakdown to provide voltage clamping.

[0008] Preferably, within a cross-section perpendicular to the first direction, it further includes: Side control / pressure-resistant layers are located on opposite sides of the alternating laminated structure; The gate electrode is located outside the side control / pressure-resistant layer, above the buffer layer, and above the topmost control / pressure-resistant layer. The side control / voltage withstand layer forms a gate bus for transmitting the control signal of the gate electrode to each control / voltage withstand layer.

[0009] Preferably, the first source region and the second source region have the same doping concentration and depth, the first gate electrode and the second gate electrode have the same structure and size, and the plurality of conductive channels and the plurality of control / voltage withstand layers are symmetrically arranged with respect to the middle position of the first source region and the second source region, so that the functions of the first source region and the second source region can be converted to each other to achieve bidirectional conduction and bidirectional blocking.

[0010] The present invention also provides a method for manufacturing the above-mentioned four-port bidirectional SiC JFET device, comprising the following steps: S1. On a SiC substrate of the second conductivity type, a buffer layer of the first conductivity type is epitaxially grown, wherein the doping concentration of the buffer layer gradually decreases from the bottom to the top. S2. On the buffer layer, an epitaxial conductive channel layer of the second conductivity type is grown; S3. An intrinsic epitaxial layer or a lightly doped second conductivity type epitaxial layer is formed on the conductive channel layer. S4. Ion implantation is performed using a mask with gradient transmittance to form control / voltage-resistant layers of the first conductivity type on both sides of the intrinsic epitaxial layer or the low-doped epitaxial layer, wherein the doping concentration of the control / voltage-resistant layers gradually decreases from the source region side to the opposite side. S5. Repeat steps S2 to S4 at least once to form multiple alternating layers of conductive channels and control / voltage withstand layers, with the topmost layer being the control / voltage withstand layer; S6. First trenches and second trenches are etched on both sides of the alternating stacked structure, and first source regions and second source regions are formed at the bottom and sidewalls of the first trenches and second trenches by vertical and inclined ion implantation. S7. In a cross section perpendicular to the first direction, a third trench and a fourth trench are etched to form, and a side control / pressure-resistant layer is formed on the sidewalls of the third trench and the fourth trench by tilted ion implantation. S8. Form an interlayer dielectric layer, and form a gate electrode and a source electrode on the interlayer dielectric layer.

[0011] Preferably, in step S4, after the control / voltage withstand layer is formed, the middle region of the intrinsic epitaxial layer or the low-doped epitaxial layer remains in an intrinsic or low-doped state to isolate the control / voltage withstand layers on both sides.

[0012] Preferably, in step S6, the depth of the first trench and the second trench does not exceed the depth of the first control / voltage withstand layer of the first conductivity type; the doping concentration of the first source region and the second source region is 1e19 cm⁻¹. -3 up to 1e21 cm -3 .

[0013] Preferably, in step S7, the depths of the third and fourth trenches are not less than those of the conductive channels of the second conductivity type in the first layer; the doping concentration of the side control / voltage withstand layer is 1e17 cm⁻¹. -3 Up to 1e19 cm -3 .

[0014] The beneficial effects of this invention are: 1. This invention provides a four-port bidirectional SiC JFET device, comprising multiple alternating conductive channels of a second conductivity type and control / voltage withstand layers of a first conductivity type, forming an alternating multilayer pn junction structure. When the pn junction is zero-biased or slightly forward-biased, the multiple conductive channels simultaneously act as conductive paths. Benefiting from the parallel properties of the multiple conductive channels, the equivalent on-resistance is extremely low. When the pn junction is reverse-biased, the multiple conductive channels are simultaneously depleted, and the first and second sources are completely turned off.

[0015] 2. This invention employs a buffer layer with gradually increasing doping concentration from top to bottom, which, together with a control / breakdown layer with gradually decreasing concentration from the source region side to the opposite side, forms a RESURF structure. As the source voltage on one side gradually increases, the buffer layer and the control / breakdown layer on the opposite side are gradually depleted, effectively suppressing the electric field strength inside the device and enabling the device to withstand high blocking voltages. The buffer layer forms an npn or pnp structure with the source region and the substrate. When the depleted region touches the substrate, punch-through breakdown occurs, performing a voltage clamping function and providing a path for dissipating avalanche or voltage overshoot energy.

[0016] 3. The definitions of the first and second source regions of the device described in this invention are interchangeable. Correspondingly, the definitions of the first and second source electrodes, and the first and second gate electrodes, are synchronously interchangeable, providing bidirectional low-resistance conduction and bidirectional high-voltage blocking functions. This invention also provides a method for manufacturing a four-port bidirectional SiC JFET device. By using a gradient doping method on a SiC single-crystal substrate to fabricate a buffer layer with a gradually varying concentration distribution, and by precisely controlling the doping concentration and thickness of each conductive channel through multiple epitaxial growths, a gradient transmittance mask combined with ion implantation is used to fabricate a concentration-gradient control / voltage-resistant layer. This fully matches the device's design requirements for high-precision doping concentration and thickness, resulting in a simple structure and easy implementation, thus improving the conduction and high-voltage resistance characteristics of the bidirectional device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the three-dimensional structure of the device of the present invention (excluding the substrate and buffer layer), where xx' is the first cross-section and yy' is the second cross-section; Figure 2 This is a schematic diagram of the first cross-section of the device structure of the present invention; Figure 3 This is a schematic diagram of the second cross-section of the device structure of the present invention; Figure 4 This is a schematic diagram of a first conductivity type buffer layer, a second conductivity type conductive channel, and an intrinsic or low second conductivity type doped epitaxial layer formed on a second conductivity type substrate in a specific embodiment of the present invention. Figure 5 This is a schematic diagram of the structure of the mask with gradient transmittance used in a specific embodiment of the present invention; Figure 6This is a schematic diagram illustrating the formation of a control / voltage-resistant layer with a gradient doping concentration distribution in a specific embodiment of the present invention; Figure 7 This is a schematic diagram illustrating the formation of multiple alternating conductive channels and control / voltage withstand layers in a specific embodiment of the present invention; Figure 8 This is a schematic diagram of a first trench and a second trench formed in a first cross section in a specific embodiment of the present invention, and a high-concentration doped source region formed by vertical and inclined ion implantation. Figure 9 This is a schematic diagram of a second cross section in a specific embodiment of the present invention, in which a third and fourth trench are formed, and a side control / pressure-resistant layer is formed by tilted ion implantation; Figure 10 This is a schematic diagram showing the formation of an interlayer dielectric layer and a first gate electrode, a second gate electrode, a first source electrode, and a second source electrode within a first cross section in a specific embodiment of the present invention. Figure 11 This is a schematic diagram showing a continuous gate electrode including a top, side, and bottom section within the second cross section in a specific embodiment of the present invention.

[0019] The diagram is marked as follows: 100. Silicon carbide substrate of second conductivity type; 200. Buffer layer of first conductivity type; 301. Conductive channel of second conductivity type; 302. Conductive channel of second conductivity type; 303. Conductive channel of second conductivity type; 304. Conductive channel of second conductivity type; 401-a. Control / voltage withstand layer of first conductivity type; 402-a. Control / voltage withstand layer of first conductivity type; 403-a. Control / voltage withstand layer of first conductivity type; 404-a. Control / voltage withstand layer of first conductivity type; 401-b. Control / voltage withstand layer of first conductivity type; 402-b. Control / voltage withstand layer of first conductivity type; 403-b. Control / voltage withstand layer of first conductivity type. Layer; 404-b, Control / voltage withstand layer of first conductivity type; 501, First trench; 502, Second trench; 503, Third trench; 504, Fourth trench; 601, First source region of second conductivity type; 602, Second source region of second conductivity type; 701, Side control / voltage withstand layer of first conductivity type; 702, Side control / voltage withstand layer of first conductivity type; 800, Interlayer dielectric layer; 901-a, First gate electrode; 902-a, First gate electrode; 903-a, First gate electrode; 901-b, Second gate electrode; 902-b, Second gate electrode; 903-b, Second gate electrode; 1001, First source electrode; 1002, Second source electrode. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. Example 1:

[0022] like Figure 1 As shown, this embodiment provides a four-port bidirectional SiC JFET device, whose three-dimensional structure includes a silicon carbide substrate 100 of a second conductivity type and a buffer layer 200 of a first conductivity type located above the substrate 100. Above the buffer layer 200, a plurality of conductive channels 301, 302, 303, 304 of the second conductivity type and a plurality of control / voltage withstand layers 401, 402, 403, 404 of the first conductivity type are alternately stacked, with the conductive channel 301 being the bottom layer and the control / voltage withstand layer 404 being the top layer. The control / voltage withstand layers are divided into a first group of control / voltage withstand layers 401-a, 402-a, 403-a, 404-a on the left and a second group of control / voltage withstand layers 401-b, 402-b, 403-b, 404-b on the right.

[0023] like Figure 2 As shown, in the first section (i.e. Figure 1 Within the cross-section (xx'), a first source region 601 and a second source region 602 of a second conductivity type are respectively disposed on both sides of the alternating layered structure. The first source region 601 and the second source region 602 are located on the left and right sides of the conductive channels 301 to 304 and the control / voltage withstand layers 401 to 404. A first trench 501 is disposed on the outer side of the first source region 601, and a second trench 502 is disposed on the outer side of the second source region 602. The depth of the first trench 501 and the second trench 502 does not exceed the depth of the first layer of the first conductivity type control / voltage withstand layer 401, and a portion of the source region is disposed between the bottom of the trench and the buffer layer 200. The first trench 501 and the second trench 502 are respectively filled with a first source electrode 1001 and a second source electrode 1002.

[0024] Above the uppermost control / voltage withstand layers 404-a and 404-b, a first gate electrode 901-a and a second gate electrode 901-b are respectively disposed. The first gate electrode 901-a is located on the side closer to the first source region 601, and the second gate electrode 901-b is located on the side closer to the second source region 602. An interlayer dielectric layer 800 is disposed between the first gate electrode 901-a, the second gate electrode 901-b, the first source electrode 1001, and the second source electrode 1002 to achieve electrical isolation between the electrodes.

[0025] like Figure 3 As shown, in the second section perpendicular to the first direction (i.e. Figure 1 Within the yy' section, side control / voltage-resistant layers 701 and 702 are respectively provided on both sides of the alternating layered structure. Side control / voltage-resistant layers 701 and 702 are located on the left and right sides of conductive channels 301 to 304 and control / voltage-resistant layers 401 to 404, respectively. A third trench 503 is provided on the outer side of side control / voltage-resistant layer 701, and a fourth trench 504 is provided on the outer side of side control / voltage-resistant layer 702. The bottoms of the third trench 503 and the fourth trench 504 touch the buffer layer 200, and their depth is not less than that of the first layer of conductive channel 301 of the second conductivity type. Within the second cross-section, gate electrodes 901-a and 901-b are located above the uppermost control / voltage withstand layers 404-a and 404-b, gate electrodes 902-a and 902-b are located outside the side control / voltage withstand layers 701 and 702, and gate electrodes 903-a and 903-b are located above the exposed buffer layer 200. The first gate electrode includes 901-a, 902-a, and 903-a, and the second gate electrode includes 901-b, 902-b, and 903-b, forming a continuous structure. The side control / voltage withstand layers 701 and 702 serve as the gate bus, transmitting the control signals of the gate electrode to each control / voltage withstand layer.

[0026] The doping concentration of the buffer layer 200 gradually decreases from bottom to top, that is, from the side closer to the substrate 100 to the side farther away from the substrate 100, with the highest doping concentration at the bottom and the lowest at the top. The doping concentration of the control / breakdown layers 401-a to 404-a and 401-b to 404-b gradually decreases from the side adjacent to their respective source regions to the opposite side. That is, the doping concentration of the first group of control / breakdown layers 401-a to 404-a on the left gradually decreases from left to right, and the doping concentration of the second group of control / breakdown layers 401-b to 404-b on the right gradually decreases from right to left. The gradually varying doping concentration distribution of the buffer layer 200 and the gradually varying doping concentration distribution of the control / breakdown layers together form a RESURF structure. As the source voltage on one side gradually increases, the depletion region extends from the control / breakdown layer into the interior of the buffer layer 200, and the electric field strength is effectively suppressed, thereby enhancing the high voltage withstand capability of the device.

[0027] The doping concentration and thickness of conductive channels 301 to 304 satisfy the following conditions: when the above pn junction is zero biased or slightly forward biased, the depletion layer thickness in the conductive channel is much smaller than the conductive channel thickness, and multiple conductive channels simultaneously serve as conductive channels, achieving extremely low parallel equivalent on-resistance; when the above pn junction is reverse biased, the depletion layer thickness in the conductive channel is not less than the conductive channel thickness, multiple conductive channels are completely depleted, and the first source region 601 and the second source region 602 are completely turned off.

[0028] The doping concentration and thickness of the control / voltage withstand layers 401-a to 404-a and 401-b to 404-b simultaneously satisfy the following conditions: when the above pn junction is reverse biased, the depletion layer thickness in the control / voltage withstand layer is less than the control / voltage withstand layer thickness, and the control / voltage withstand layer is not completely depleted; as the source voltage on the opposite side gradually increases, the control / voltage withstand layer is gradually depleted, effectively alleviating the electric field accumulation inside the device and further enhancing the high voltage withstand capability of the device.

[0029] The buffer layer 200 forms an npn or pnp structure with the source regions 601, 602 and the substrate 100. When the depletion region of the RESURF structure touches the substrate 100, the npn or pnp structure undergoes punch-through breakdown, assumes voltage clamping function, and provides a path for dissipating avalanche or voltage overshoot energy.

[0030] The first source region 601 and the second source region 602 have the same doping concentration and depth. The first gate electrodes 901-a, 902-a, and 903-a have the same structure and size as the second gate electrodes 901-b, 902-b, and 903-b. Multiple conductive channels 301 to 304 and multiple control / voltage withstand layers 401-a to 404-a and 401-b to 404-b are symmetrically arranged relative to the intermediate positions of the first source region 601 and the second source region 602. Therefore, the definitions of the first source region 601 and the second source region 602 can be interchanged. Correspondingly, the definitions of the first source electrode 1001 and the second source electrode 1002, and the definitions of the first gate electrode and the second gate electrode are synchronously interchanged, achieving bidirectional low-resistance conduction and bidirectional high-voltage blocking functions.

[0031] The contact properties of the source electrode 1001 with the source region 601, the source electrode 1002 with the source region 602, the gate electrode with the control / voltage withstand layer, and the gate electrode with the buffer layer 200 are all ohmic contacts. Example 2:

[0032] This embodiment provides a method for manufacturing a four-port bidirectional SiC JFET device, including the following steps.

[0033] like Figure 4As shown, a gradually doped buffer layer 200 of the first conductivity type is epitaxially grown on a silicon carbide substrate 100 of the second conductivity type. The doping concentration of the buffer layer 200 gradually decreases from bottom to top, and this gradually doped distribution is achieved by gradually changing the doping source flux during the epitaxial growth process.

[0034] On top of the buffer layer 200, a conductive channel 301 of a second conductivity type with a specific doping concentration and thickness is epitaxially grown. The conductive channel 301 should have a low to medium doping concentration, with a reference value of 1e15 cm⁻¹. -3 up to 1e17 cm -3 The thickness reference value is 0.2 μm to 1.0 μm.

[0035] On the upper part of the conductive channel 301, an intrinsic epitaxial layer with a specific thickness or an epitaxial layer with a lower doping concentration of the second conductivity type is epitaxially grown, which is used for subsequent formation of a control / breakdown layer.

[0036] like Figure 5 and Figure 6 As shown, a mask structure with a gradient exposure rate is formed through thin film deposition, photolithography, and etching. Then, ion implantation is used to perform first conductivity type doping. Control / breakdown layers 401-a and 401-b with gradient doping concentrations of the first conductivity type are formed on the left and right sides of this intrinsic epitaxial layer or low-doped epitaxial layer, respectively. The control / breakdown layers 401-a and 401-b should have medium to high doping concentrations, with a maximum doping concentration reference value of 1e17 cm⁻¹. -3 Up to 1e19 cm -3 The thickness reference value is 0.2 μm to 1.0 μm. The doping concentration of the control / voltage withstand layers 401-a and 401-b gradually decreases from their respective source regions towards the opposite side; that is, the doping concentration of the control / voltage withstand layer 401-a on the left gradually decreases from left to right, and the doping concentration of the control / voltage withstand layer 401-b on the right gradually decreases from right to left. After the control / voltage withstand layers 401-a and 401-b are formed, the middle region of the intrinsic epitaxial layer or the low-doped epitaxial layer remains intrinsic or low-doped to isolate the control / voltage withstand layers on both sides.

[0037] like Figure 7As shown, the steps of epitaxially growing conductive channels, epitaxially growing intrinsic layers or lightly doped layers, and graded mask ion implantation are repeated until the required number of alternating conductive channels 301, 302, 303, 304 of the second conductivity type and control / voltage withstand layers 401-a to 404-a, 401-b to 404-b of the first conductivity type are obtained. The bottom layer is conductive channel 301, and the top layers are control / voltage withstand layers 404-a and 404-b. All conductive channels 301 to 304 have the same doping concentration and thickness, and all control / voltage withstand layers 401-a to 404-a and 401-b to 404-b have the same doping concentration distribution and thickness. The alternating conductive channels of the second conductivity type and the control / voltage withstand layers of the first conductivity type form alternating pn junction structures. There should be at least one alternating conductive channel of the second conductivity type and one control / voltage withstand layer of the first conductivity type. In this embodiment, four layers are used as an example for illustration, but the present invention is not limited thereto.

[0038] like Figure 8 As shown, a first trench 501 and a second trench 502 of specific width and depth are formed by thin film deposition, photolithography, and etching. The first trench 501 and the second trench 502 are located outside the first source region and the second source region to be formed subsequently, respectively. The depth of the first trench 501 and the second trench 502 should not exceed the first layer of the first conductivity type control / voltage withstand layer 401. Then, a first source region 601 and a second source region 602 of the second conductivity type are formed by vertical and tilted ion implantation. Source regions 601 and 602 are highly doped regions; high-concentration doping is applied to the bottom and inner sides of the first trench 501 and the second trench 502 by vertical and tilted ion implantation, with a doping concentration reference value of 1e19 cm⁻¹. -3 up to 1e21 cm -3 The first trench 501 and the second trench 502 are respectively filled with the first source electrode and the second source electrode formed subsequently, and a portion of the source region is disposed between the bottom of the trench and the buffer layer 200.

[0039] like Figure 9 As shown, in a second cross-section perpendicular to the first direction, a third trench 503 and a fourth trench 504 of specific width and depth are formed by thin film deposition, photolithography, and etching. The depth of the third trench 503 and the fourth trench 504 should not be less than the conductive channel 301 of the second conductivity type in the first layer. Then, side control / voltage withstand layers 701 and 702 of the first conductivity type are formed by tilted ion implantation. The side control / voltage withstand layers 701 and 702 have a medium to high doping concentration, with a reference doping concentration value of 1e17 cm⁻¹. -3 Up to 1e19 cm -3The side control / voltage withstand layers 701 and 702 are located on the left and right sides of the conductive channels 301 to 304 and the control / voltage withstand layers 401-a to 404-a and 401-b to 404-b, respectively, and serve as the gate bus function.

[0040] like Figure 10 As shown, an interlayer dielectric layer 800 is formed above the uppermost control / pressure-resistant layers 404-a and 404-b.

[0041] Then, a first source electrode 1001, a second source electrode 1002, a first gate electrode, and a second gate electrode are formed. For example... Figure 10 As shown, in the first cross-section, the first gate electrode 901-a and the second gate electrode 901-b are located above the uppermost control / voltage withstand layers 404-a and 404-b, respectively, and are located on the side closest to the first source region 601 and the second source region 602, respectively. The first source electrode 1001 and the second source electrode 1002 are respectively filled in the first trench 501 and the second trench 502. Figure 11 As shown, in the second cross-section, gate electrodes 901-a and 901-b are located above the uppermost control / voltage withstand layers 404-a and 404-b, gate electrodes 902-a and 902-b are located outside the side control / voltage withstand layers 701 and 702, and gate electrodes 903-a and 903-b are located above the exposed buffer layer 200. The first gate electrode includes 901-a, 902-a, and 903-a, and the second gate electrode includes 901-b, 902-b, and 903-b, forming a continuous structure. The contact properties of the source electrode 1001 with the source region 601, the source electrode 1002 with the source region 602, the gate electrode with the control / voltage withstand layer, and the gate electrode with the buffer layer 200 are all ohmic contacts.

[0042] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0043] In the embodiments provided in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0044] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0045] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on a terminal device, the terminal device can implement the steps in the various method embodiments described above.

[0046] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A four-port bidirectional SiC JFET device, characterized in that, include: SiC substrate of the second conductivity type; A first conductivity type buffer layer located above the substrate; The buffer layer has multiple conductive channels of the second conductivity type and multiple control / voltage withstand layers of the first conductivity type. The conductive channels and the control / voltage withstand layers are alternately stacked in the vertical direction, with the bottom layer being the conductive channel and the top layer being the control / voltage withstand layer. The first source region and the second source region are located on opposite sides of the alternating stacked structure along the first direction and are in contact with the conductive channel. The first gate electrode and the second gate electrode are respectively located above the uppermost control / voltage withstand layer and are respectively disposed adjacent to the first source region and the second source region; The doping concentration of the buffer layer gradually decreases from bottom to top, and the doping concentration of the control / voltage withstand layer gradually decreases from one side adjacent to the respective source region to the other side. The buffer layer and the control / voltage withstand layer constitute a RESURF structure.

2. The four-port bidirectional SiC JFET device according to claim 1, characterized in that, A pn junction is formed between the conductive channel and the control / voltage withstand layer; the doping concentration and thickness of the conductive channel are configured such that when the pn junction is zero-biased or forward-biased, the depletion layer thickness in the conductive channel is less than its thickness, so that multiple conductive channels are connected in parallel and conducting; when the pn junction is reverse-biased, the depletion layer thickness in the conductive channel is not less than its thickness, so that multiple conductive channels are completely depleted and turned off.

3. The four-port bidirectional SiC JFET device according to claim 1, characterized in that, The doping concentration and thickness of the control / voltage withstand layer are configured such that when the pn junction is reverse biased, the control / voltage withstand layer is not completely depleted, and as the reverse voltage of the device increases, the control / voltage withstand layer is gradually depleted to alleviate electric field accumulation.

4. The four-port bidirectional SiC JFET device according to claim 1, characterized in that, The buffer layer, the source region, and the substrate form an NPN or PNP structure; when the depletion region of the RESURF structure extends to the substrate, the NPN or PNP structure undergoes punch-through breakdown to provide voltage clamping.

5. The four-port bidirectional SiC JFET device according to claim 1, characterized in that, Within the cross-section perpendicular to the first direction, it further includes: Side control / pressure-resistant layers are located on opposite sides of the alternating laminated structure; The gate electrode is located outside the side control / pressure-resistant layer, above the buffer layer, and above the topmost control / pressure-resistant layer. The side control / voltage withstand layer forms a gate bus for transmitting the control signal of the gate electrode to each control / voltage withstand layer.

6. The four-port bidirectional SiC JFET device according to claim 1, characterized in that, The first source region and the second source region have the same doping concentration and depth, and the first gate electrode and the second gate electrode have the same structure and size. The plurality of conductive channels and the plurality of control / voltage withstand layers are symmetrically arranged with respect to the middle position of the first source region and the second source region, so that the functions of the first source region and the second source region can be converted to each other to achieve bidirectional conduction and bidirectional blocking.

7. A method for manufacturing a four-port bidirectional SiC JFET device as described in any one of claims 1 to 6, characterized in that, Includes the following steps: S1. On a SiC substrate of the second conductivity type, a buffer layer of the first conductivity type is epitaxially grown, wherein the doping concentration of the buffer layer gradually decreases from the bottom to the top. S2. On the buffer layer, an epitaxial conductive channel layer of the second conductivity type is grown; S3. An intrinsic epitaxial layer or a lightly doped second conductivity type epitaxial layer is formed on the conductive channel layer. S4. Ion implantation is performed using a mask with gradient transmittance to form control / voltage-resistant layers of the first conductivity type on both sides of the intrinsic epitaxial layer or the low-doped epitaxial layer, wherein the doping concentration of the control / voltage-resistant layers gradually decreases from the source region side to the opposite side. S5. Repeat steps S2 to S4 at least once to form multiple alternating layers of conductive channels and control / voltage withstand layers, with the topmost layer being the control / voltage withstand layer; S6. First trenches and second trenches are etched on both sides of the alternating stacked structure, and first source regions and second source regions are formed at the bottom and sidewalls of the first trenches and second trenches by vertical and inclined ion implantation. S7. In a cross section perpendicular to the first direction, a third trench and a fourth trench are etched to form, and a side control / pressure-resistant layer is formed on the sidewalls of the third trench and the fourth trench by tilted ion implantation. S8. Form an interlayer dielectric layer, and form a gate electrode and a source electrode on the interlayer dielectric layer.

8. The manufacturing method according to claim 7, characterized in that, In step S4, after the control / voltage withstand layer is formed, the middle region of the intrinsic epitaxial layer or the low-doped epitaxial layer remains in an intrinsic or low-doped state to isolate the control / voltage withstand layers on both sides.

9. The manufacturing method according to claim 7, characterized in that, In step S6, the depth of the first trench and the second trench does not exceed the depth of the first control / voltage withstand layer of the first conductivity type; the doping concentration of the first source region and the second source region is 1e19 cm⁻¹. -3 up to 1e21 cm -3 .

10. The manufacturing method according to claim 7, characterized in that, In step S7, the depths of the third and fourth trenches are not less than those of the conductive channels of the second conductivity type in the first layer; the doping concentration of the side control / voltage withstand layer is 1e17 cm⁻¹. -3 Up to 1e19 cm -3 .

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