A semiconductor device

Abstract

The application discloses a semiconductor device and belongs to the technical field of semiconductor. The semiconductor device at least comprises a substrate, a channel layer arranged on the substrate, a first barrier layer arranged on the channel layer and covering the channel layer, a P-type semiconductor layer arranged on the first barrier layer, a gate arranged on the semiconductor layer, a source arranged on the first barrier layer, and a drain arranged on the first barrier layer. The first barrier layer has a columnar crystal structure. The semiconductor device can improve the average electric field and the breakdown voltage.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a semiconductor device. Background Technology

[0002] With the rapid development of power electronics technology, the demand for high-efficiency, high-power-density, and high-operating-temperature power devices is becoming increasingly urgent. Third-generation semiconductor materials possess advantages such as large bandgap, high breakdown electric field, fast electron saturation drift velocity, and high thermal conductivity, making them ideal materials for next-generation high-performance power devices. However, when using third-generation semiconductor materials as the material for semiconductor devices, the devices may suffer from uneven electric field, making them susceptible to breakdown. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device that can solve the problem of uneven electric field in semiconductor devices, which makes semiconductor devices prone to breakdown.

[0004] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: This invention provides a semiconductor device comprising at least: Substrate; A channel layer is disposed on the substrate; A first barrier layer is disposed on the channel layer, and the first barrier layer covers the channel layer; A P-type semiconductor layer is disposed on the first barrier layer; A gate is disposed on the semiconductor layer; The source electrode is disposed on the first barrier layer; The drain is disposed on the first barrier layer; The first barrier layer has a columnar crystal structure.

[0005] In one embodiment, the semiconductor device further includes a second barrier layer formed on the first barrier layer.

[0006] In one embodiment, a portion of the second barrier layer extends between the P-type semiconductor layer and the gate.

[0007] In one embodiment, a portion of the second barrier layer is formed between the P-type semiconductor layer and the gate.

[0008] In one embodiment, the semiconductor device further includes at least one dielectric layer formed between the second barrier layer and the gate.

[0009] In one embodiment, a portion of the second barrier layer is formed on the P-type semiconductor layer and the gate.

[0010] In one embodiment, the semiconductor device further includes: A regenerated semiconductor layer is formed between the source and the first barrier layer; Another regenerated semiconductor layer is formed between the drain and the first barrier layer.

[0011] In one embodiment, the regrown semiconductor layer is embedded in the first barrier layer.

[0012] In one embodiment, a multilayer gate dielectric layer is further included between the gate and the P-type semiconductor layer.

[0013] In one embodiment, the gate dielectric layer includes one or more of the following: a first titanium nitride layer, a first silicon nitride layer, a high dielectric constant layer, a second titanium nitride layer, an oxide layer, and a second silicon nitride layer.

[0014] In one embodiment of the present invention, the channel layer is a gallium nitride layer, and the first barrier layer and the second barrier layer are aluminum gallium nitride layers.

[0015] In one embodiment of the present invention, the materials of the first barrier layer and the second barrier layer are Al. 0.2 Ga 0.8 N.

[0016] In one embodiment of the present invention, the thickness of the second barrier layer is greater than the thickness of the first barrier layer.

[0017] In one embodiment of the present invention, the semiconductor device further includes an N-type gallium nitride layer disposed between the source and the first barrier layer, and between the drain and the first barrier layer.

[0018] In one embodiment of the present invention, the N-type gallium nitride layer is a heavily doped gallium nitride layer.

[0019] In one embodiment of the present invention, a multilayer gate dielectric layer is further included between the gate and the P-type gallium nitride layer.

[0020] In one embodiment of the present invention, the gate dielectric layer includes one or more of the following: a first titanium nitride layer, a first silicon nitride layer, a high dielectric constant layer, a second titanium nitride layer, an oxide layer, and a second silicon nitride layer.

[0021] The present invention also provides an electronic device comprising the semiconductor device described in any of the above claims.

[0022] The present invention also provides a radio frequency device, including the semiconductor device described in any of the above claims.

[0023] In summary, the semiconductor device provided by this invention can make the electric field distribution smoother and improve the breakdown voltage. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of a semiconductor substrate in one embodiment of the present invention.

[0026] Figure 2 This is a flowchart illustrating the fabrication process of a semiconductor substrate according to one embodiment of the present invention.

[0027] Figure 3 This is a schematic diagram of a semiconductor substrate with a transition layer in one embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram of a semiconductor epitaxial structure in one embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram of the structure of a semiconductor substrate having a first single crystal layer in one embodiment of the present invention.

[0030] Figure 6 This is a schematic diagram of a semiconductor epitaxial structure having a second single crystal layer in one embodiment of the present invention.

[0031] Figure 7 This is a schematic diagram of a semiconductor substrate having a sealing layer and a planarization layer in one embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram of the structure of a semiconductor substrate with a protective layer in one embodiment of the present invention.

[0033] Figure 9 This is a schematic diagram of the structure of a semiconductor substrate with a stress relief layer in one embodiment of the present invention.

[0034] Figure 10 This is a schematic diagram of a semiconductor epitaxial structure with a stress relief structure in one embodiment of the present invention.

[0035] Figure 11 This is a schematic diagram of the structure of a semiconductor device in one embodiment of the present invention.

[0036] Figure 12 This is a schematic diagram of the structure of a multilayer gate dielectric layer in one embodiment of the present invention.

[0037] Figure 13 This is a schematic diagram of a semiconductor device with a dielectric layer according to an embodiment of the present invention.

[0038] Figure 14 This is a schematic diagram of a semiconductor device with a dielectric layer in another embodiment of the present invention.

[0039] Figure 15 This is a schematic diagram of a semiconductor device with a regenerated semiconductor layer having an embedded barrier layer in one embodiment of the present invention.

[0040] Figure 16 This is a schematic diagram of the structure of a vertical power device in one embodiment of the present invention.

[0041] Figure 17 This is a schematic diagram of the structure of a radio frequency device in one embodiment of the present invention. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0044] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0045] With the rapid development of power electronics technology, the demand for power devices with high efficiency, high power density, and high operating temperature is becoming increasingly urgent. Third-generation semiconductor materials, with their advantages of large bandgap, high breakdown electric field, fast electron saturation drift velocity, and high thermal conductivity, are considered ideal materials for next-generation high-performance power devices. Gallium nitride (GaN), as the core material of third-generation semiconductors, has wide applications in high-frequency, high-power electronic devices and short-wavelength optoelectronic devices. The growth of high-quality gallium nitride epitaxial layers typically requires heterogeneous substrates with matching lattice constants and coefficients of thermal expansion. Among these, aluminum nitride (AlN), with its high thermal conductivity (theoretically up to 320 W / m·K) and good lattice matching (mismatch of approximately 2.4%) and thermal expansion matching with gallium nitride, is considered an ideal material for gallium nitride epitaxial substrates.

[0046] Please see Figure 1 As shown, the present invention provides a semiconductor substrate and its manufacturing method, which can solve the problems of rough surface and many defects in aluminum nitride ceramic substrates. Moreover, the semiconductor substrate can achieve both high thermal conductivity and atomically flat surface, and can replace the more expensive single-crystal silicon substrate, making it suitable for mass production.

[0047] Please see Figure 1 As shown, in one embodiment of the present invention, the semiconductor substrate includes a ceramic powder sintered layer 1001 and an aluminum nitride sputtered layer 1002, wherein the aluminum nitride sputtered layer 1002 is disposed on the ceramic powder sintered layer 1001. The ceramic powder sintered layer 1001 serves as the mechanical support and main heat dissipation channel of the substrate, and the aluminum nitride sputtered layer 1002 disposed on the ceramic powder sintered layer 1001 forms a template layer for epitaxial growth.

[0048] Please see Figure 1 As shown, in one embodiment of the present invention, the thickness of the ceramic powder sintered layer 1001 is, for example, 100 μm to 1000 μm, and the thermal conductivity of the ceramic powder sintered layer 1001 is greater than or equal to 150 W / m·K. The thickness of the aluminum nitride sputtered layer 1002 is, for example, 0.5 μm to 10 μm.

[0049] Please see Figure 1 As shown, in one embodiment of the present invention, the ceramic powder sintered layer 1001 is, for example, at least one polycrystalline ceramic selected from aluminum nitride, gallium nitride, silicon nitride, boron nitride, alumina, and silicon carbide, or a composite ceramic thereof. In the embodiments shown in this application, an aluminum nitride powder sintered ceramic layer is used as an example for illustration.

[0050] Please see Figure 1 and Figure 2 As shown, the present invention also provides a method for manufacturing a semiconductor substrate, and the semiconductor manufacturing method includes at least steps S101 to S103.

[0051] Step S101: Provide ceramic powder to form a green body, and sinter the green body at high temperature to obtain a ceramic powder sintered layer.

[0052] In one embodiment of the present invention, the purity of the high-purity aluminum nitride powder is ≥99.99%, and the particle size range of the high-purity aluminum nitride powder is, for example, 0.5 μm to 2 μm. In some embodiments, a sintering aid may be added to the high-purity aluminum nitride powder to promote sintering densification and improve thermal conductivity. The sintering aid may be, for example, yttrium oxide (Y₂O₃), and the amount added may be, for example, 0.3 wt% to 1.0 wt%. When the sintering aid is added to the high-purity aluminum nitride powder, the high-purity aluminum nitride powder and the sintering aid can be placed in a planetary ball mill, using anhydrous ethanol as the milling medium, to ensure that the high-purity aluminum nitride powder and the sintering aid powder are mixed uniformly without agglomeration. After mixing the high-purity aluminum nitride powder and the sintering aid, vacuum drying is performed to obtain a uniformly mixed powder.

[0053] In one embodiment of the present invention, after forming a green blank by dry pressing, cold isostatic pressing, or tape casting, the green blank is sintered at, for example, 1700°C to 2000°C under a reducing or inert gas atmosphere to obtain a ceramic powder sintered layer 1001. Specifically, during the high-temperature sintering of the green blank, it is first placed in a sintering furnace. The furnace lining material is graphite or a tungsten-molybdenum alloy. Next, high-purity nitrogen or argon is introduced into the furnace lining as a protective gas. Finally, the furnace temperature is raised to 1700°C to 2000°C and sintered at this temperature. The sintering time is, for example, 2 hours to 6 hours. Afterward, the sintering furnace is cooled to room temperature to obtain the ceramic powder sintered layer 1001.

[0054] Step S102: Mechanically grind and polish the ceramic powder sintered layer to make the surface roughness of the ceramic powder sintered layer less than or equal to the preset roughness.

[0055] In one embodiment of the present invention, the preset roughness is, for example, 1 nm. After forming the ceramic powder sintered layer 1001, the upper surface of the ceramic powder sintered layer 1001 can be ground and polished so that the surface roughness Ra of the ceramic powder sintered layer 1001 is ≤ 1 nm. Specifically, the surface roughness Ra of the ceramic powder sintered layer 1001 is, for example, equal to 0.8, 0.7, or 0.6, or equal to 0.65, 0.55, or 0.45, etc.

[0056] Step S103: Using a sputtering method, an aluminum nitride sputtered layer is sputtered and grown on the surface of the ceramic powder sintered layer.

[0057] In one embodiment of the present invention, an aluminum nitride sputtered layer 1002 is formed using physical vapor deposition (PVD) and magnetron sputtering. During the sputtering growth of the aluminum nitride sputtered layer 1002, high-purity aluminum nitride or aluminum metal is used as the target material, and the aluminum nitride sputtered layer 1002 is sputtered in a nitrogen-containing atmosphere at a substrate temperature, for example, 400°C to 800°C.

[0058] In one embodiment of the present invention, after forming the aluminum nitride sputtered layer 1002, the aluminum nitride sputtered layer 1002 is subjected to high-temperature annealing. The high-temperature annealing temperature is, for example, 1000°C to 1500°C, and the annealing time is 10 minutes to 2 hours. Specifically, during the high-temperature annealing of the aluminum nitride sputtered layer 1002, the substrate on which the aluminum nitride sputtered layer 1002 is disposed is placed in an atmosphere filled with nitrogen or ammonia at a temperature of, for example, 1000°C to 1500°C, for annealing, for example, 10 minutes to 2 hours, to improve the crystal quality of the aluminum nitride sputtered layer 1002 and reduce stress.

[0059] Please see Figure 1 As shown in this application, the aluminum nitride sputtered layer grown by sputtering has a columnar crystal structure with grains arranged perpendicularly along the thickness direction, clear grain boundaries, and small grain size. Under high-temperature annealing, the columnar aluminum nitride grains undergo solid-phase growth and grain boundary migration, with small grains continuously merging into larger grains. The grain orientation becomes more uniform, the arrangement more regular, the defect density is significantly reduced, and the lattice distortion is effectively released. After high-temperature annealing, the aluminum nitride sputtered layer 1002 transforms from the original fine columnar crystals into a large-size, highly oriented, low-defect near-single-crystal structure. The lattice integrity is greatly improved, the surface is more flat and dense, and it is closer to the crystal characteristics of single-crystal aluminum nitride. This provides a near-single-crystal growth template with high crystal quality, low defects, and high flatness for subsequent gallium nitride epitaxial layers, significantly improving the crystal quality and device performance of subsequent epitaxial layers.

[0060] Please see Figure 3 As shown, in one embodiment of the present invention, a transition layer 1003 may be provided between the ceramic powder sintered layer 1001 and the aluminum nitride sputtered layer 1002. In this case, the semiconductor substrate includes the ceramic powder sintered layer 1001, the transition layer 1003, and the aluminum nitride sputtered layer 1002, with the transition layer 1003 disposed on the ceramic powder sintered layer 1001 and the aluminum nitride sputtered layer 1002 disposed on the transition layer 1003. The transition layer 1003 may be at least one of a gallium nitride powder ceramic sintered layer and a boron nitride ceramic powder sintered layer. That is, the transition layer 1003 is a gallium nitride powder ceramic sintered layer, a boron nitride ceramic powder sintered layer, or a sintered layer consisting of a mixture of gallium nitride powder and boron nitride ceramic powder.

[0061] Please see Figure 3 As shown, in one embodiment of the present invention, a gallium nitride powder ceramic sintered layer is formed as a transition layer 1003. Specifically, gallium nitride powder with a purity greater than or equal to, for example, 99.99%, is selected, and yttrium oxide is added as a sintering aid. This mixture is then mixed with an organic solvent and a binder to prepare a gallium nitride ceramic slurry. Next, the gallium nitride ceramic slurry is uniformly coated onto the surface of the ceramic powder sintered layer 1001 using screen printing, spin coating, or spraying. The coating thickness of the gallium nitride ceramic slurry is, for example, 2 μm to 5 μm. Then, after drying the gallium nitride ceramic slurry at, for example, 120°C to 150°C, it is held at, for example, 400°C to 600°C in a nitrogen atmosphere for, for example, 30 min to 60 min to complete the binder removal. Afterwards, high-temperature sintering is performed at, for example, 1500°C to 1700°C in a nitrogen or ammonia atmosphere for, for example, 1 h to 3 h, to obtain the gallium nitride powder ceramic sintered layer. Finally, the surface roughness Ra of the gallium nitride powder ceramic sintered layer is reduced to ≤1 nm by slight chemical mechanical polishing. The thickness of the gallium nitride powder ceramic sintered layer is, for example, 1 μm to 3 μm.

[0062] Please see Figure 3 As shown, in another embodiment of the present invention, a boron nitride ceramic powder sintered layer is formed as a transition layer 1003. Specifically, boron nitride powder with a purity greater than or equal to, for example, 99.9%, is selected, and boron oxide or yttrium oxide is added as a sintering aid to prepare a boron nitride ceramic slurry. Then, the boron nitride ceramic slurry is coated onto the surface of the ceramic powder sintered layer 1001 by screen printing, spraying, or spin coating, with a coating thickness of, for example, 2 μm to 5 μm. Next, after drying at, for example, 120°C and removing the binder under a nitrogen atmosphere at, for example, 500°C, the layer is sintered at, for example, 1800°C to 1950°C under an inert or nitrogen atmosphere for, for example, 2 to 4 hours, to obtain the boron nitride ceramic powder sintered layer. Finally, the boron nitride ceramic powder sintered layer is polished to achieve a surface roughness Ra ≤ 1 nm. The thickness of the boron nitride ceramic powder sintered layer is, for example, 1 μm to 3 μm.

[0063] Please see Figures 1 to 3 As shown, the semiconductor substrate provided in this application can achieve both high thermal conductivity and high-quality epitaxial surface. Specifically, the semiconductor substrate provided in this application creatively combines a high thermal conductivity aluminum nitride ceramic layer with a high crystallinity aluminum nitride sputtering template layer. The bottom aluminum nitride ceramic layer provides excellent mechanical strength and heat dissipation capabilities, solving the heat dissipation bottleneck of traditional thin template layers. The top sputtered aluminum nitride layer is optimized to provide an atomically flat surface with highly consistent crystal orientation, laying an ideal foundation for subsequent gallium nitride epitaxial growth.

[0064] Please see Figures 1 to 3As shown, the semiconductor substrate provided in this application can effectively reduce the epitaxial defect density. Specifically, the sputtered aluminum nitride layer, as a single-crystal or highly oriented buffer layer, can effectively block the influence of the random lattice orientation of the underlying polycrystalline aluminum nitride ceramic layer on the epitaxial layer, guide the gallium nitride epitaxial layer to grow in a single direction, thereby significantly reducing the density of crystal defects such as dislocations and improving device performance and reliability.

[0065] Please see Figures 1 to 3 As shown, the semiconductor substrate provided in this application incorporates an optional transition layer 1003 to enhance adhesion and stress regulation. Specifically, introducing a GaN or BN transition layer 1003 between the ceramic layer and the sputtered layer can further improve interfacial bonding and serve as a stress buffer layer to alleviate thermal stress that may be caused by slight differences in the coefficient of thermal expansion, preventing film cracking or warping.

[0066] Please see Figures 1 to 3 As shown, the semiconductor substrate formation method provided in this application is simple and cost-controllable. Specifically, the manufacturing method of this application combines mature ceramic sintering technology and standard semiconductor sputtering technology, avoiding the extreme conditions of bulk single-crystal aluminum nitride growth, which is conducive to large-scale production and achieves an excellent balance between performance and cost.

[0067] Please combine Figure 1 , Figure 3 and Figure 4 As shown, the present invention also provides a semiconductor epitaxial structure, the semiconductor structure comprising as follows Figure 1 or Figure 3 The semiconductor substrate and the gallium nitride epitaxial layer 1004 disposed on the semiconductor substrate are described above. The gallium nitride epitaxial layer 1004 is disposed on the semiconductor substrate and also on the aluminum nitride sputtered layer 1002. In this application, the thickness of the gallium nitride epitaxial layer 1004 is, for example, 1 μm to 10 μm, and the dislocation density of the gallium nitride epitaxial layer 1004 is less than 1 × 10⁻⁶. 8  cm 21 .

[0068] Please see Figure 4As shown, in one embodiment of the present invention, a gallium nitride epitaxial layer 1004 is deposited on a semiconductor substrate using a metal-organic chemical vapor deposition (MOCVD) method. Specifically, the semiconductor substrate with the aluminum nitride sputtered layer 1002 is placed in an MOCVD reaction chamber and subjected to evacuation. Next, ammonia and hydrogen are introduced into the reaction chamber, and the chamber temperature is raised to, for example, 1000°C to 1050°C under an ammonia and hydrogen atmosphere to perform a nitriding activation treatment on the surface of the aluminum nitride sputtered layer 1002 for, for example, 10 min to 15 min, to passivate the aluminum nitride sputtered layer 1002. Then, the chamber temperature is lowered to, for example, 520°C to 600°C, and the chamber pressure is controlled to, for example, 400 mbar to 600 mbar. Trimethylgallium and ammonia are introduced to grow a low-temperature gallium nitride nucleation layer of, for example, 20 nm to 50 nm. The temperature is then increased to, for example, 1020℃~1080℃, and the pressure is adjusted to, for example, 200mbar~400mbar. The flow rates of ammonia and trimethylgallium are increased to epitaxially grow a high-temperature gallium nitride layer with a thickness of, for example, 1μm~10μm, on the nucleation layer. After growth, the gallium nitride epitaxial layer 1004 is subjected to in-situ high-temperature annealing and slowly cooled to room temperature under ammonia protection. Finally, a gallium nitride epitaxial layer 1004 with low defects and high flatness is obtained on the aluminum nitride sputtered layer 1002.

[0069] Please see Figure 5 As shown, in one embodiment of the present invention, the present invention also provides a semiconductor substrate, which includes at least a ceramic powder sintered layer 1001, an aluminum nitride sputtered layer 1002, and a first single crystal layer 1005. The aluminum nitride sputtered layer 1002 is disposed on the ceramic powder sintered layer 1001, and the first single crystal layer 1005 is disposed on the aluminum nitride sputtered layer 1002. Furthermore, the semiconductor substrate may also include a transition layer 1003, which is disposed on the ceramic powder sintered layer 1001, the aluminum nitride sputtered layer 1002 is disposed on the transition layer 1003, and the first single crystal layer 1005 is disposed on the aluminum nitride sputtered layer 1002.

[0070] Please see Figure 5 As shown, in one embodiment of the present invention, the thickness of the first single-crystal layer 1005 is, for example, 0.05 μm to 0.09 μm, and specifically, for example, 0.05 μm, 0.06 μm, or 0.07 μm, or 0.08 μm or 0.09 μm. The material of the first single-crystal layer 1005 can be formed from single-crystal materials such as sapphire, aluminum nitride, gallium nitride, silicon, or silicon carbide.

[0071] Please see Figure 5As shown, in one embodiment of the present invention, the first single-crystal layer 1005 is, for example, a single-crystal silicon layer, and the material of the single-crystal silicon layer is single-crystal silicon with a crystal orientation of

[111] . When fabricating the first single-crystal layer 1005, a composite substrate comprising a ceramic powder sintered layer 1001 and an aluminum nitride sputtered layer 1002 is used as the substrate. A single-crystal silicon substrate is then selected, and hydrogen ions or helium ions are implanted into the single-crystal silicon substrate to form a release point inside the single-crystal silicon substrate. Then, the ion-implanted surface of the single-crystal silicon substrate is low-temperature bonded to the surface of the aluminum nitride sputtered layer 1002 of the substrate. The single-crystal silicon substrate is then separated along the release point, allowing a portion of the thickness of the single-crystal silicon substrate to be transferred onto the aluminum nitride sputtered layer 1002. Next, chemical mechanical polishing, wet etching, or plasma-assisted chemical etching (PACE) can be used to completely remove the stripped areas, thus eliminating the damage caused by ion implantation, and forming a thinner first single-crystal layer 1005 on the aluminum nitride sputtered layer 1002. This first single-crystal layer 1005 serves as a high-quality epitaxial template, guiding the subsequent gallium nitride epitaxial layer 1004 to grow uniformly along a single crystal direction, significantly reducing dislocation density and interface stress, and improving the crystal quality of the gallium nitride epitaxial layer 1004. Furthermore, the thinner first single-crystal layer 1005 can completely eliminate ion implantation damage, reduce interlayer thermal stress, and suppress substrate warping and cracking, while relaxing the quality requirements for seed materials and reducing manufacturing costs.

[0072] Please see Figure 6 As shown, the present invention also provides a semiconductor epitaxial structure, which includes any of the semiconductor substrates provided in this application, a gallium nitride epitaxial layer 1004 disposed on the semiconductor substrate, and a second single-crystal layer 1006 disposed on the gallium nitride epitaxial layer 1004. The thickness of the second single-crystal layer 1006 is, for example, 0.05 μm to 0.09 μm, specifically, for example, 0.05 μm, 0.06 μm, or 0.07 μm, or possibly 0.08 μm or 0.09 μm. The material of the second single-crystal layer 1006 can be a single-crystal material such as sapphire, aluminum nitride, gallium nitride, silicon, or silicon carbide.

[0073] Please see Figure 6As shown, in one embodiment of the present invention, the second single-crystal layer 1006 is, for example, a single-crystal silicon layer, and the material of the single-crystal silicon layer is single-crystal silicon with a crystal orientation of

[111] . At this time, a single-crystal silicon substrate is selected, and hydrogen ions or helium ions are implanted into the single-crystal silicon substrate to form a peeling position inside the single-crystal silicon substrate. Then, the ion implantation surface of the single-crystal silicon substrate is bonded to the surface of the gallium nitride epitaxial layer 1004 at a low temperature. Then, the single-crystal silicon substrate is separated along the peeling position, so that a portion of the thickness of the single-crystal silicon substrate is transferred onto the gallium nitride epitaxial layer 1004. Then, chemical mechanical polishing, wet etching, or plasma-assisted chemical etching are used to completely remove the peeling position to remove the damage caused by ion implantation, thereby forming a thinner second single-crystal layer 1006 on the gallium nitride epitaxial layer 1004. A second single crystal layer 1006 is formed on the gallium nitride epitaxial layer 1004. The second single crystal layer 1006 can be used in multilayer epitaxial structures such as deep ultraviolet LEDs, high-frequency HEMTs, and power devices as a high-quality nucleation interface for the top or middle layer, suppressing defect proliferation, improving interface flatness, and enhancing device breakdown voltage and high-temperature reliability.

[0074] Please see Figure 7 As shown, the present invention also provides a semiconductor substrate, which includes at least a ceramic powder sintered layer 1001, an aluminum nitride sputtered layer 1002, a first single crystal layer 1005, a sealing layer 1007, and a planarization layer 1008. The aluminum nitride sputtered layer 1002 is disposed on the ceramic powder sintered layer 1001, the sealing layer 1007 encapsulates both the ceramic powder sintered layer 1001 and the aluminum nitride sputtered layer 1002, the planarization layer 1008 is disposed on the sealing layer 1007 or encapsulates the sealing layer 1007, and the first single crystal layer 1005 is disposed on the planarization layer 1008. Furthermore, a transition layer 1003 may also be disposed in the semiconductor substrate. At this point, the transition layer 1003 is disposed on the ceramic powder sintered layer 1001, the aluminum nitride sputtered layer 1002 is disposed on the transition layer 1003, and the sealing layer 1007 encapsulates the ceramic powder sintered layer 1001, the transition layer 1003, and the aluminum nitride sputtered layer 1002. The planarization layer 1008 is disposed on the sealing layer 1007 or the planarization layer 1008 encapsulates the sealing layer 1007, and the first single crystal layer 1005 is disposed on the planarization layer 1008.

[0075] Please see Figure 7 As shown, in one embodiment of the present invention, the sealing layer 1007 can be a single-layer silicon nitride thin film or a multilayer composite thin film of gallium nitride silicon and silicon oxynitride. The sealing layer 1007, composed of a single-layer thin film or a multilayer composite thin film, can prevent impurities in the ceramic powder sintered layer 1001, the transition layer 1003, and the aluminum nitride sputtered layer 1002 from diffusing outward, improve the uniformity of the surface of the aluminum nitride sputtered layer 1002, reduce interfacial stress, and also provide a stable interface for the planarization layer 1008.

[0076] Please see Figure 7 As shown, in one embodiment of the present invention, the thickness of the sealing layer 1007 is, for example, 500 nm to 1000 nm. Setting the thickness of the sealing layer 1007 prevents insufficient sealing performance from a thinner layer, which could lead to impurities penetrating the sealing layer 1007 and affecting the quality of the formed first single-crystal layer 1005. Furthermore, it prevents the formation of a thicker sealing layer 1007 from causing increased thermal stress and resulting in the delamination of the sealing layer 1007.

[0077] Please see Figure 7 As shown, in one embodiment of the present invention, after forming the aluminum nitride sputtered layer 1002, a sealing layer 1007 with the best coverage, density, and impurity blocking ability is formed using a low-pressure chemical vapor deposition (LPCVD) method. Specifically, when forming the sealing layer 1007 using the LPCVD method, silicon nitride or silicon oxynitride is used as the main component. The semiconductor substrate on which the ceramic powder sintered layer 1001 and the aluminum nitride sputtered layer 1002 are disposed is placed in a LPCVD apparatus and deposited under low-pressure and high-temperature conditions, so that the sealing layer 1007 completely encapsulates the ceramic powder sintered layer 1001 and the aluminum nitride sputtered layer 1002, forming a dense sealing structure with excellent impurity blocking ability.

[0078] Please see Figure 7 As shown, in one embodiment of the present invention, a planarization layer 1008 encapsulates a sealing layer 1007. The planarization layer 1008 is, for example, one of a silicon oxide layer (SiO2), a silicon oxynitride layer (SiON), or an aluminum arsenide layer (AlAs). The planarization layer 1008 is a single-layer dense dielectric film that can provide an atomically flat surface for the first single-crystal layer 1005 and facilitate the formation of the first single-crystal layer 1005. The thickness of the planarization layer 1008 is, for example, 1 μm to 3 μm, specifically 1 μm, 2 μm, or 3 μm, or it can be 1.5 μm or 2.5 μm. Setting the thickness of the planarization layer 1008 prevents a thinner planarization layer 1008 from failing to fill unevenness. Furthermore, it prevents the formation of a thicker planarization layer 1008 from causing warping, excessive stress, and easy cracking.

[0079] Please see Figure 7As shown, in one embodiment of the present invention, a planarization layer 1008 can be formed using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or metal-organic chemical vapor deposition (MOCVD). The specific deposition method of the planarization layer 1008 is determined based on the material of the planarization layer 1008. A silicon oxide layer or a silicon oxynitride layer can be deposited as the planarization layer 1008 using plasma-enhanced chemical vapor deposition, or an aluminum arsenide layer can be deposited as the planarization layer 1008 using MOCVD. After the planarization layer 1008 is formed, it can be subjected to high-temperature densification treatment and chemical mechanical polishing to obtain an atomically flat surface for subsequent bonding and transfer of the first single-crystal layer 1005.

[0080] Please combine Figure 5 and Figure 8 As shown, the present invention also provides a semiconductor substrate, which includes a ceramic powder sintered layer 1001, an aluminum nitride sputtered layer 1002, a first single crystal layer 1005, and a protective layer 1009. The aluminum nitride sputtered layer 1002 is disposed on the ceramic powder sintered layer 1001, the first single crystal layer 1005 is disposed on the aluminum nitride sputtered layer 1002, and the protective layer 1009 is disposed on the first single crystal layer 1005. Furthermore, the semiconductor substrate may also include a transition layer 1003, a sealing layer 1007, and a planarization layer 1008. In this case, the transition layer 1003 is disposed on the ceramic powder sintered layer 1001, the aluminum nitride sputtered layer 1002 is disposed on the transition layer 1003, and the sealing layer 1007 encapsulates the ceramic powder sintered layer 1001, the transition layer 1003, and the aluminum nitride sputtered layer 1002. The planarization layer 1008 is disposed on the sealing layer 1007 or the planarization layer 1008 wraps the sealing layer 1007, the first single crystal layer 1005 is disposed on the planarization layer 1008, and the protective layer 1009 is disposed on the first single crystal layer 1005.

[0081] Please combine Figure 5 and Figure 8As shown, in one embodiment of the present invention, a protective layer 1009 is disposed on the first single crystal layer 1005, and the protective layer 1009 covers the surface and sidewalls of the first single crystal layer 1005, and the protective layer 1009 covers a portion of the contact surface where the semiconductor layer at the bottom of the first single crystal layer 1005 connects to the sidewall of the first single crystal layer 1005. In some embodiments, the bottom of the first single crystal layer 1005 is a planarization layer 1008, then the protective layer 1009 covers a portion of the contact surface where the planarization layer 1008 connects to the sidewall of the first single crystal layer 1005. In other embodiments, the bottom of the first single crystal layer 1005 is an aluminum nitride sputtered layer 1002, then the protective layer 1009 covers a portion of the contact surface where the aluminum nitride sputtered layer 1002 connects to the sidewall of the first single crystal layer 1005.

[0082] Please see Figure 8 As shown, in one embodiment of the present invention, the protective layer 1009 is, for example, an aluminum nitride layer, and is formed by sputtering or atomic layer deposition (ALD) to form a dense protective layer 1009 with good coverage. The thickness of the protective layer 1009 is, for example, 50 nm to 100 nm, specifically 60 nm, 70 nm, 80 nm, or 90 nm, or even 50 nm or 100 nm. Setting the protective layer 1009 to 50 nm to 100 nm prevents the formed protective layer 1009 from being too thin and discontinuous, avoiding high-temperature melting and failure of the protective layer 1009. It also prevents the formation of a thicker protective layer 1009 from causing high stress, which would result in poor crystallinity of the gallium nitride epitaxial layer 1004.

[0083] Please see Figure 8 As shown, in some embodiments of the present invention, the protective layer 1009 is formed, for example, by sputtering. Specifically, when the protective layer 1009 is formed by sputtering, aluminum is used as the target material, and the temperature of the substrate on which the first single crystal layer 1005 is disposed is raised to, for example, 500°C to 800°C in a mixed atmosphere of argon and nitrogen, so that plasma reaction deposition is performed to form an aluminum nitride layer as the protective layer 1009.

[0084] Please see Figure 8 As shown, in some other embodiments of the present invention, the protective layer 1009 can also be formed by atomic layer deposition. Specifically, when forming the protective layer 1009 by atomic layer deposition, aluminum nitride is deposited at a temperature of, for example, 300°C to 400°C, using trimethylaluminum and ammonia as precursors.

[0085] Please see Figure 8As shown, the protective layer 1009 formed by the present invention covers the surface and sidewalls of the first single crystal layer 1005, and the protective layer 1009 covers the partial contact surface where the semiconductor layer at the bottom of the first single crystal layer 1005 connects to the sidewalls of the first single crystal layer 1005, forming a seamless, dead-angle-free, and continuous full coverage of the first single crystal layer 1005. On the one hand, the protective layer 1009 can prevent the first single crystal layer 1005 from oxidizing. On the other hand, as a dense barrier layer, the protective layer 1009 can completely isolate the gallium in the gallium nitride epitaxial layer 1004 from contacting the first single crystal layer 1005, avoiding the gallium element in the gallium nitride epitaxial layer 1004 from corroding the first single crystal layer 1005 during high-temperature annealing, causing the gallium nitride epitaxial layer 1004 to fall off, thereby leading to device failure.

[0086] Please see Figure 9 As shown, the present invention also provides a semiconductor substrate, which includes at least a ceramic powder sintered layer 1001, an aluminum nitride sputtered layer 1002, and a stress relief layer 1010. The aluminum nitride sputtered layer 1002 is disposed on the ceramic powder sintered layer 1001, and the stress relief layer 1010 is disposed on the bottom surface of the ceramic powder sintered layer 1001, i.e., the stress relief layer 1010 is disposed on the side of the ceramic powder sintered layer 1001 opposite to the aluminum nitride sputtered layer 1002. Furthermore, the semiconductor substrate may also include one or more of the following: a transition layer 1003, a sealing layer 1007, a planarization layer 1008, and a first single crystal layer 1005. The transition layer 1003 is disposed on the ceramic powder sintered layer 1001, and the aluminum nitride sputtered layer 1002 is disposed on the transition layer 1003. The sealing layer 1007 encapsulates the ceramic powder sintered layer 1001, the transition layer 1003, and the aluminum nitride sputtered layer 1002. A planarization layer 1008 is disposed on the sealing layer 1007 or the planarization layer 1008 wraps around the sealing layer 1007, and a first single crystal layer 1005 is disposed on the planarization layer 1008. A stress relief layer 1010 is disposed on the bottom surface of the ceramic powder sintered layer 1001, that is, the stress relief layer 1010 is disposed on the side of the ceramic powder sintered layer 1001 opposite to the aluminum nitride sputtered layer 1002, and the stress relief layer 1010 covers the planarization layer 1008 on the side of the ceramic powder sintered layer 1001 opposite to the first single crystal layer 1005.

[0087] Please see Figure 9 As shown, in one embodiment of the present invention, the stress relief layer 1010 is formed of, for example, silicon, polycrystalline silicon, or amorphous silicon material, and can be configured as a single layer or multiple layers according to the warpage compensation requirements. The thickness of the formed stress relief layer 1010 is, for example, 50 nm to 1000 nm. The specific thickness of the relief layer 1010 can be set according to the required warpage adjustment.

[0088] Please see Figure 9As shown, in one embodiment of the present invention, when forming the stress relief layer 1010, plasma chemical vapor deposition is used, for example, to deposit the stress relief layer 1010. Furthermore, when forming the stress relief layer 1010, silicon dioxide or silicon oxynitride can be deposited first as a buffer layer between the stress relief layer 1010 and the planarization layer 1008, and then a polycrystalline silicon or amorphous silicon film is deposited to form the stress relief layer 1010. After forming the stress relief layer 1010, it can be subjected to high-temperature annealing to stabilize the stress, ultimately achieving low warpage and low stress on the substrate. By forming a silicon-based stress relief layer 1010 on the back side, reverse stress can be introduced to counteract the warpage caused by the front planarization layer 1008, resulting in overall low stress, low warpage, and stable process performance of the substrate.

[0089] Please see Figure 10 As shown, the present invention also provides a semiconductor epitaxial structure, which includes any of the semiconductor substrates provided in this application and a gallium nitride epitaxial layer 1004 disposed on the semiconductor substrate. The gallium nitride epitaxial layer 1004 is provided with a stress relief structure 1011. The stress relief structure 1011 is disposed in the gallium nitride epitaxial layer 1004 and is located at the bottom of the gallium nitride epitaxial layer 1004. The stress relief structure 1011 is a stress relief gap disposed in the gallium nitride epitaxial layer 1004.

[0090] Please see Figure 10 As shown, in one embodiment of the present invention, when forming a gallium nitride epitaxial layer 1004 with stress-relieving gaps, a gallium nitride layer is first deposited at a relatively low temperature using MOCVD. The deposition temperature of the gallium nitride layer is, for example, 500°C to 550°C. Next, the gallium nitride layer is subjected to high-temperature treatment, causing internal decomposition and forming stress-relieving gaps within the gallium nitride layer. Then, a gallium nitride layer is grown vertically, causing stress-relieving gaps to also form within the subsequently deposited gallium nitride layer, and the size of the stress-relieving gaps increases with the increase in growth thickness. Next, when the size of the stress-relieving gaps in the gallium nitride layer reaches a preset size, a gallium nitride layer is grown horizontally, keeping the stress-relieving gaps in the horizontally grown gallium nitride layer constant. In some embodiments, gallium nitride layers can also be grown cyclically in both the vertical and horizontal directions as needed, causing the size of the stress-relieving gaps in the gallium nitride layer to gradually increase.

[0091] Please see Figure 10As shown, in one embodiment of the present invention, after forming stress-relief gaps in the gallium nitride epitaxial layer 1004, a gallium nitride layer with stress-relief structure 1011 is grown on the gallium nitride layer using hydride vapor phase epitaxy (HVPE). During the deposition of the gallium nitride layer using hydride vapor phase epitaxy, the gaps in the bottom gallium nitride layer merge and annihilate, gradually forming a seamless gallium nitride layer. At this point, the gallium nitride epitaxial layer 1004 with stress-relief structure 1011 formed in this application can reduce dislocation defects and intergranular stress, thereby improving the quality of the gallium nitride epitaxial film.

[0092] Please see Figures 1 to 10 As shown, the present invention also provides a semiconductor device, which includes at least one of the above-described semiconductor epitaxial structures. Furthermore, the semiconductor device includes, but is not limited to, high electron mobility transistors, light-emitting diodes, laser diodes, or power diodes.

[0093] Please see Figure 11 As shown, the present invention provides a semiconductor device including a substrate 101, a buffer layer 102, a channel layer 103, a first barrier layer 1041, a second barrier layer 1042, a P-type semiconductor layer 105, a source 1081, a drain 1082, and a gate 107. The buffer layer 102 is disposed on the substrate 101, the channel layer 103 is disposed on the buffer layer 102, and the first barrier layer 1041 is disposed on the channel layer 103. The P-type semiconductor layer 105, the source 1081, the drain 1082, and the gate 107 can be contacted with the first barrier layer 1041 through gallium nitride layers of different doping types. The second barrier layer 1042 is disposed on the first barrier layer 1041 and extends below the gate 107.

[0094] For details, please refer to Figure 11 As shown, in one embodiment of the present invention, the substrate 101 can be made of semiconductor materials such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), and lithium aluminate (LiAlO2). When the substrate 101 is a silicon (Si) based material, it can be, for example, silicon (Si) or silicon carbide (SiC).

[0095] Please see Figure 11As shown, in one embodiment of the present invention, the buffer layer 102 is on the substrate 101, that is, the buffer layer 102 is located between the substrate 101 and the channel layer 103. It can buffer lattice mismatch and thermal mismatch between the substrate 101 and the channel layer 103, and is also beneficial for the subsequent growth of epitaxial structures, improving the quality of the semiconductor device. In this embodiment, the buffer layer 102 is a gallium nitride (GaN) layer. The GaN buffer layer 102 can be a doped GaN buffer layer 102 or an undoped GaN buffer layer. In other embodiments, the buffer layer 102 may also include a stacked aluminum nitride layer and a GaN layer. In this embodiment, when forming the GaN buffer layer 102, a high-quality GaN buffer layer 102 can be grown on the substrate 101 using a physical vapor deposition (PVD) method. Furthermore, when forming the GaN buffer layer 102, the material properties of the buffer layer 102 can be adjusted by optimizing growth parameters and controlling the doping concentration. In other embodiments, the gallium nitride buffer layer 102 may also be formed using any other suitable method such as metal-organic chemical vapor deposition (MOCVD).

[0096] Please see Figure 11 As shown, in one embodiment of the present invention, a channel layer 103 is disposed on a buffer layer 102, serving as a conductive channel for a semiconductor device. When gallium nitride (GaN) is used as the channel layer 103, the GaN device exhibits a higher breakdown voltage due to its high breakdown electric field. Furthermore, GaN possesses a wide bandgap, high saturation electron velocity, and high thermal conductivity. The wide bandgap allows GaN devices to operate stably at higher temperatures, while also exhibiting lower leakage current and better radiation resistance. The high saturation electron velocity enables the formed semiconductor power devices to be used in high-frequency and radio-frequency applications, and the high thermal conductivity helps the device dissipate heat better during high-power operation, improving reliability and lifespan. In this embodiment, after forming the GaN buffer, a GaN channel layer 103 can be formed on the GaN buffer layer 102 using metal-organic chemical vapor deposition (MOCVD) or physical vapor deposition (PVD). In other embodiments, the GaN buffer layer 102 can be formed using any other suitable method.

[0097] Please see Figure 11As shown, in one embodiment of the present invention, one or more barrier layers are disposed on the channel layer 103, and the barrier layer is, for example, an aluminum gallium nitride (GaN) layer. The heterojunction formed by the GaN channel layer 103 and the GaN barrier layer can generate a high concentration of two-dimensional electron gas (2DEG) at the interface, achieving high conductivity even without doping, thus simplifying the fabrication of semiconductor devices while improving device performance and reliability. In this embodiment, the barrier layer includes a first barrier layer 1041 and a second barrier layer 1042. The first barrier layer 1041 is disposed on the channel layer 103, and the second barrier layer 1042 is disposed on the first barrier layer 1041. The second barrier layer 1042 extends from the sidewall of the P-type semiconductor layer 105 at the bottom of the gate 107 to the bottom of the gate 107, and covers a portion of the P-type semiconductor layer 105 at the bottom of the gate 107. This improves the breakdown voltage of the semiconductor device while averaging the electric field of the semiconductor device.

[0098] For details, please refer to Figure 11 As shown, in one embodiment of the present invention, a first barrier layer 1041 is disposed on the channel layer 103. The material of the first barrier layer 1041 is Al. x1 Ga y1 N. Where x1 is, for example, 0.2, and y1 is, for example, 0.8. Wherein, the thickness of the first barrier layer 1041 is, for example, 8nm~12nm, specifically, 10nm.

[0099] Please see Figure 11 As shown, in one embodiment of the present invention, after forming the channel layer 103, a first barrier layer 1041 can be formed, for example, using physical vapor deposition. Specifically, high-purity aluminum (Al), gallium (Ga), and aluminum nitride (AlN) or gallium nitride (GaN) targets can be selected, and high-purity nitrogen gas is introduced as the reaction gas, while a small amount of argon (Ar) gas can be added as the sputtering gas. When the sputtering process is started, aluminum (Al), gallium (Ga), and nitrogen (N) atoms are sputtered from the target and react on the surface of the channel layer 103 to form an aluminum gallium nitride (AlGaN) thin film. When forming the aluminum gallium nitride layer using physical vapor deposition, the composition of aluminum and gallium in the AlGaN thin film can be precisely controlled by adjusting the sputtering power ratio of the aluminum target and the gallium target.

[0100] Please see Figure 11As shown, in one embodiment of the present invention, after forming the first barrier layer 1041, a P-type semiconductor layer 105, a regrown semiconductor layer 1061, and a regrown semiconductor layer 1062 can be formed on the first barrier layer 1041. The P-type semiconductor layer 105 is located between the gate 107 and the first barrier layer 1041, the regrown semiconductor layer 1061 is located between the source 1081 and the first barrier layer 1041, and the regrown semiconductor layer 1062 is located between the drain 1082 and the first barrier layer 1041. That is, the P-type semiconductor layer 105 is located at the bottom of the gate 107, the regrown semiconductor layer 1061 is located at the bottom of the source 1081, and the regrown semiconductor layer 1062 is located at the bottom of the drain 1082. In this embodiment, the regrown semiconductor layers 1061 and 1062 are, for example, ohmic contact layers, such as N-type gallium nitride layers, and may be heavily doped gallium nitride layers. The P-type semiconductor layer 105 is, for example, a P-type gallium nitride layer, and may be a lightly doped gallium nitride layer. That is, the ion doping concentration in the regrown semiconductor layers 1061 and 1062 may be greater than the ion doping concentration in the P-type semiconductor layer 105. Furthermore, in this embodiment, the thickness of the regrown semiconductor layers 1061 and 1062 may be greater than the thickness of the P-type semiconductor layer 105.

[0101] Please see Figure 11 As shown, in one embodiment of the present invention, when forming the P-type semiconductor layer 105, the regrown semiconductor layer 1061, and the regrown semiconductor layer 1062, any suitable method such as physical vapor deposition, metal chemical vapor deposition, or atomic layer deposition (ALD) can be used to deposit a gallium nitride layer on the first barrier layer 1041. Next, at the locations of the source 1081 and drain 1082, N-type ions such as silicon ions are doped into the gallium nitride layer to form the regrown semiconductor layer 1061 and regrown semiconductor layer 1062. At the location of the gate 107, P-type ions such as magnesium ions are doped into the gallium nitride layer to form the P-type semiconductor layer 105. Finally, the gallium nitride layers between the source 1081 and the gate 107, and between the drain 1082 and the gate 107, are removed by an etching process. In other embodiments, the regrown semiconductor layer 1061, the regrown semiconductor layer 1062, and the P-type semiconductor layer 105 can also be formed stepwise.

[0102] Please see Figure 11 As shown, in one embodiment of the present invention, the formed P-type semiconductor layer 105 is located between the regenerated semiconductor layer 1061 and the regenerated semiconductor layer 1062, and there is a preset distance between the P-type semiconductor layer 105 and the regenerated semiconductor layer 1061 and the regenerated semiconductor layer 1062.

[0103] Please see Figure 11As shown, in this invention, a regrown semiconductor layer 1061 and a regrown semiconductor layer 1062 are formed under the source 1081 and drain 1082. First, since the regrown semiconductor layer 1061 and the regrown semiconductor layer 1062 can have a high electron concentration (e.g., 1 × 10⁻⁶), 19 cm 3 ~9×10 20 cm 3 First, the regrown semiconductor layers 1061 and 1062 form a good ohmic contact between the source 1081 and drain 1082 and the channel, thereby significantly reducing the contact resistance of the source 1081 and drain 1082, thus reducing the on-resistance of the device and improving the device efficiency. Second, the regrown semiconductor layers 1061 and 1062 provide a high-concentration electron source for the source 1081 and drain 1082, which can effectively inject charge carriers into the channel and improve the current drive capability of the device. Finally, the regrown semiconductor layers 1061 and 1062 formed under the source 1081 and drain 1082 can optimize the electric field distribution inside the device, reduce electric field concentration, and thus improve the breakdown voltage and reliability of the device.

[0104] Please see Figure 11 As shown, the presence of the P-type semiconductor layer 105 can raise the threshold voltage of the device, allowing it to conduct at a higher positive gate voltage, thereby improving the device's noise immunity and reliability. Secondly, the P-type semiconductor layer 105 can enhance the gate 107's control over the 2DEG in the channel, increasing the device's transconductance and switching speed. Furthermore, the P-type semiconductor layer 105 can form a PN junction, effectively suppressing gate 107 leakage current and improving the device's static performance and reliability.

[0105] Please see Figure 11 As shown, in one embodiment of the present invention, after forming the P-type semiconductor layer 105, the regrown semiconductor layer 1061, and the regrown semiconductor layer 1062, a second barrier layer 1042 is formed on the first barrier layer 1041. The second barrier layer 1042 is disposed on the first barrier layer 1041 and covers a portion of the P-type semiconductor layer 105. Specifically, the thickness of the second barrier layer 1042 may be less than the thickness of the P-type semiconductor layer 105, the regrown semiconductor layer 1061, and the regrown semiconductor layer 1062. The formed second barrier layer 1042 fills the gap between the regrown semiconductor layer 1061, the regrown semiconductor layer 1062, and the P-type semiconductor layer 105, and the second gallium nitride layer covers the sidewalls of the P-type semiconductor layer 105 and the edge portion of the upper surface of the P-type semiconductor layer 105, forming an opening on the upper surface of the P-type semiconductor layer 105. The opening enables the connection between the P-type semiconductor layer 105 and the gate 107.

[0106] Please see Figure 11 As shown, in one embodiment of the present invention, the material of the second barrier layer 1042 is Al. x2 Ga y2 N. Where x2 is, for example, 0.2, and y2 is, for example, 0.8. Wherein, the thickness of the second barrier layer 1042 can be greater than the thickness of the first barrier layer 1041, and the thickness of the second barrier layer 1042 is, for example, 13nm~20nm, specifically, for example, 15nm.

[0107] Please see Figure 11 As shown, in one embodiment of the present invention, a second barrier layer 1042 can be formed using physical vapor deposition, thereby thickening the barrier layer. Specifically, high-purity aluminum (Al), gallium (Ga), and aluminum nitride (AlN) or gallium nitride (GaN) targets can be selected, and high-purity nitrogen gas is introduced as the reaction gas, while a small amount of argon (Ar) gas can be added as the sputtering gas. When the sputtering process is started, aluminum (Al), gallium (Ga), and nitrogen (N) atoms are sputtered from the target and react on the surface of the first barrier layer 1041 to form an aluminum gallium nitride (AlGaN) thin film. When forming the aluminum gallium nitride layer using physical vapor deposition, the composition of aluminum and gallium in the AlGaN thin film can be precisely controlled by adjusting the sputtering power ratio of the aluminum target and the gallium target.

[0108] Please see Figure 11 As shown, in one embodiment of the present invention, a gate 107 can be formed on a P-type semiconductor layer 105, a source 1081 can be formed on a regrown semiconductor layer 1061, and a drain 1082 can be formed on a regrown semiconductor layer 1062. The source 1081 covers the surface of the regrown semiconductor layer 1061, and the drain 1082 covers the surface of the regrown semiconductor layer 1062. The gate 107 covers the opening of the P-type semiconductor layer 105 exposed by the second barrier layer 1042, and the second barrier layer 1042 adjacent to the opening.

[0109] Please see Figure 11As shown, in one embodiment of the present invention, ohmic contact materials can be deposited on the regenerated semiconductor layer 1061 and the regenerated semiconductor layer 1062 using electron beam evaporation or sputtering to form source 1081 and drain 1082. The ohmic contact materials forming source 1081 and drain 1082 can be, for example, titanium / aluminum / nickel / gold (Ti / Al / Ni / Au), titanium / aluminum / molybdenum / gold (Ti / Al / Mo / Au), or titanium / aluminum / titanium / gold (Ti / Al / Ti / Au). Titanium (Ti) can form good interfacial contact with gallium nitride, aluminum (Al) has low resistance, and nickel (Ni) and gold (Au) can serve as protective and bonding layers. Molybdenum (Mo) can replace nickel (Ni) to provide better thermal stability and anti-diffusion properties, while the double titanium layer structure can further optimize contact resistance.

[0110] Please see Figure 11 As shown, in one embodiment of the present invention, a Schottky material can be deposited on the P-type semiconductor layer 105 using electron beam evaporation or sputtering to form a gate 107. The Schottky material forming the gate 107 can be, for example, nickel / gold (Ni / Au) or platinum / gold (Pt / Au). Nickel (Ni) and platinum (Pt) can form a Schottky barrier with gallium nitride, and gold (Au) can serve as a protective layer and a bonding layer.

[0111] Please see Figure 11 As shown, in one embodiment of the present invention, the formed gate 107 covers the opening of the exposed P-type semiconductor layer 105 of the second barrier layer 1042, as well as the second barrier layer 1042 near the opening. The width of the gate 107 is smaller than the width of the P-type gallium nitride. At this time, the second barrier layer 1042 covers the sidewalls and top edge of the P-type gallium nitride, and extends to the bottom of the gate 107. The second barrier layer 1042 can then act as a dielectric field plate, extending the depletion region below the gate 107. In the off state, the depletion region extends laterally towards the AlGaN / GaN interface, making the electric field distribution flatter and preventing premature breakdown at the edge of the gate 107 due to electric field concentration. Simultaneously, because the bandgap of the aluminum gallium nitride layer is larger than that of the gallium nitride layer, the critical breakdown electric field strength of both the aluminum gallium nitride and gallium nitride layers is higher. When subjected to a high electric field, this layer can delay avalanche breakdown, thereby improving the overall breakdown voltage capability of the semiconductor device. Furthermore, the second barrier layer 1042 and the P-type semiconductor layer 105 can form a heterostructure, which can further regulate the vertical and lateral expansion of the depletion region, reduce the non-uniformity of the field below the gate 107, make the electric field distribution smoother, and improve the breakdown voltage.

[0112] Please see Figure 11As shown, in one embodiment of the present invention, the highly doped regrown semiconductor layers 1061 and 1062 significantly reduce the contact resistance of the source 1081 and drain 1082, ensuring uniform current flow into and out of the channel during conduction. This reduces current congestion, avoids Joule heating and electric field distortion caused by excessively high local current density, and indirectly improves the uniformity of the electric field distribution. Simultaneously, the highly doped nature of the regrown semiconductor layers 1061 and 1062 makes them difficult to deplete under reverse bias (resulting in a narrow depletion region), forcing the depletion region to extend laterally towards the less doped GaN channel layer 103 or GaN buffer layer 102. This makes the electric field more uniformly distributed in the drift region (low-doped region), avoiding electric field spikes at the source / drain edges. The regrown semiconductor layers 1061 and 1062 form a doping concentration gradient with the underlying buffer layer 102 (low-doped). In the off state, the buffer layer 102 bears the main electric field, while the high doping characteristics of the regenerated semiconductor layer 1061 and the regenerated semiconductor layer 1062 can smooth the electric field gradient, prevent sudden changes in the electric field at the interface, and further improve the breakdown voltage.

[0113] Please see Figures 11 to 12 As shown, in one embodiment of the present invention, a multilayer gate dielectric layer may be disposed between the P-type semiconductor layer 105 and the gate 107. The gate dielectric layer may include one or more of the following: a first titanium nitride layer 111, a first silicon nitride layer 112, a high dielectric constant layer 113, a second titanium nitride layer 114, an oxide layer 115, and a second silicon nitride layer 116.

[0114] Please see Figure 12 As shown, in one embodiment of the present invention, a first titanium nitride layer 111 is located on the P-type semiconductor layer 105 and covers a portion of the P-type semiconductor layer 105. The material of the first titanium nitride layer 111 is titanium nitride (TiN). TiN is conductive and can serve as a transition layer between the gate 107 and the P-type gallium nitride, improving electrical contact. Furthermore, TiN forms a good interface contact with the P-type gallium nitride, reducing the interface state density. Moreover, TiN can prevent metal atoms from diffusing into the P-type gallium nitride, avoiding contamination and performance degradation. In this embodiment, the first titanium nitride layer 111 can be formed on the P-type semiconductor layer 105 by sputtering or atomic deposition.

[0115] Please see Figure 12As shown, in one embodiment of the present invention, a first silicon nitride layer 112 is located on a first titanium nitride layer 111, and the first silicon nitride layer 112 covers the first titanium nitride layer 111, the P-type semiconductor layer 105, and a first barrier layer 1041 adjacent to the P-type semiconductor layer 105. The material of the first silicon nitride layer 112 is silicon nitride (SiN). SiN can passivate the surface of P-type gallium nitride, reduce the interface state density, and reduce leakage current. At the same time, SiN can prevent direct electrical contact between the gate 107 and P-type gallium nitride, thereby improving the reliability of the device. In this embodiment, the first silicon nitride layer 112 can be formed by sputtering, PVD, plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD).

[0116] Please see Figure 12 As shown, in one embodiment of the present invention, the first titanium nitride layer 111 and the first silicon nitride layer 112 may be located at the bottom of the second barrier layer 1042, while the high dielectric constant layer 113 is disposed on the surface of the second barrier layer 1042. The high dielectric constant layer 113 is metal-silicon oxide-silicon nitride (MOSiN). MOSiN can increase the capacitance of the gate 107 and improve the driving capability of the device. Simultaneously, MOSiN can further optimize the interface characteristics between the gate 107 and P-type gallium nitride, reducing the interface state density. In this embodiment, a layer of MOSiN can be formed as the high dielectric constant layer 113 by atomic deposition or sputtering.

[0117] Please see Figure 12 As shown, in one embodiment of the present invention, the second titanium nitride layer 114 is located on the high dielectric constant layer 113, and the second titanium nitride layer covers the high dielectric constant layer 113. The material of the second titanium nitride layer 114 is titanium nitride (TiN). The second titanium nitride layer 114 can improve the electrical contact between the gate 107 and the upper layer material, and at the same time prevent the upper metal atoms from diffusing downwards, avoiding contamination. In this embodiment, the second titanium nitride layer 114 can be formed on the P-type semiconductor layer 105 by sputtering or atomic deposition.

[0118] Please see Figure 12 As shown, in one embodiment of the present invention, a silicon oxide layer is located on and covers the second titanium nitride layer 114. The silicon oxide layer is made of silicon oxide (SiO), and SiO can alleviate stress between multilayer structures and improve device reliability. In this embodiment, a silicon oxide layer can be formed on the second titanium nitride layer 114 by thermal oxidation or chemical vapor deposition.

[0119] Please see Figure 12As shown, in one embodiment of the present invention, the second silicon nitride layer 116 is located on the silicon oxide layer and covers the silicon oxide layer. The material of the second silicon nitride layer 116 is silicon nitride (SiN). Silicon nitride can passivate the surface of p-type gallium nitride, reduce the interface state density, and reduce leakage current. At the same time, silicon nitride can serve as a protective layer to prevent the device from being contaminated or damaged in subsequent processes. Silicon nitride can also further isolate the gate 107 from other structures, improving the reliability of the device. In this embodiment, the second silicon nitride layer 116 can be formed by plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD).

[0120] Please see Figures 13 to 14 As shown, in another embodiment of the present invention, a dielectric layer 1071 is further disposed between the second barrier layer 1042 and the gate 107. The dielectric layer 1071 can be formed of a wide bandgap material, which can deplete the holes in the p-type gallium nitride. The dielectric layer 1071 separates the second barrier layer 1042 and the gate 107, which can block direct leakage current from the gate and improve the static stability of the device. Moreover, the dielectric layer 1071 can serve as a field plate dielectric, spreading the high electric field from the edge of the gate, allowing the depletion region to expand more uniformly laterally and avoiding local breakdown.

[0121] Please see Figure 13 As shown, in some embodiments of the present invention, a dielectric layer 1071 is disposed on the surface of the gate 107, and the dielectric layer 1071 covers the top and sidewalls of the gate 107. A second barrier layer 1024 extends from the sidewall of the P-type semiconductor layer 105 at the bottom of the gate 107 to the sidewall of the dielectric layer 1071, and covers the dielectric layer 1071. In this case, the dielectric layer 1071 covers the top and sidewalls of the gate 107, which can completely shield the gate edge electric field, suppress gate edge tip breakdown, enhance the field plate effect, make the electric field more uniformly distributed, and also protect the gate metal from diffusion and damage.

[0122] Please see Figure 14 As shown, in some embodiments of the present invention, the second barrier layer 1042 extends from the sidewall of the P-type semiconductor layer 105 at the bottom of the gate 107 to the bottom of the gate 107 and covers the P-type semiconductor layer 105 at the bottom of the gate 107. A dielectric layer 1071 is disposed on the surface of the second barrier layer 1042, and the dielectric layer 1071 is located above the P-type semiconductor layer 105, with the gate 107 disposed on the dielectric layer 1071. In this case, the dielectric layer is located directly above the second barrier layer 1042 on the surface of the P-type semiconductor layer 105 and directly below the gate 107, enabling a pure dielectric gate with lower leakage current and higher withstand voltage. Furthermore, by setting the dielectric layer 1071, the depletion region under the gate can be precisely controlled, optimizing switching characteristics and isolating the gate from the P-type gallium nitride, reducing interface states and leakage current.

[0123] Please see Figure 15 As shown, in some embodiments of the present invention, the regrown semiconductor layer 1061 and the regrown semiconductor layer 1062 can be embedded in the first barrier layer 1041 and extend into the first barrier layer 1041, and are close to the two-dimensional electron gas between the channel layer 103. This allows the regrown semiconductor layer 1061 and the regrown semiconductor layer 1062 to be close to or in contact with the two-dimensional electron gas layer between the first barrier layer 1041 and the channel layer 103.

[0124] Please see Figure 15 As shown, in some embodiments, the regenerated semiconductor layer 1061 and the regenerated semiconductor layer 1062 are embedded in a barrier layer, and the thickness of the first barrier layer 1041 and / or the second barrier layer may be less than 30 nm, for example, 1 nm to 20 nm, or 5 nm to 20 nm.

[0125] Please see Figure 15 As shown, in this application, the regrown semiconductor layers 1061 and 1062 are embedded in the barrier layer, making them close to the two-dimensional electron gas layer. This shortens the carrier transport path, reduces the resistance caused by the AlGaN barrier, and consequently significantly reduces the on-resistance of the semiconductor device, resulting in higher efficiency and less heat generation. Furthermore, after embedding the regrown semiconductor layers 1061 and 1062 in the barrier layer, the current is injected vertically and directly into the two-dimensional electron gas layer, resulting in a more uniform lateral current distribution. This avoids the source / drain current having to pass through the entire barrier layer, which can easily concentrate at the edges and cause localized large currents. Moreover, embedding the regrown semiconductor layers 1061 and 1062 in the barrier layer forces the depletion region to extend laterally towards the GaN channel or buffer layer, rather than being squeezed at the source / drain edges. This results in a smoother electric field distribution, eliminates electric field spikes, and improves the breakdown voltage of the semiconductor device.

[0126] Please see Figure 16 As shown, in one embodiment of the present invention, the semiconductor device of this application may be, for example, a vertical power device, wherein the drift region 121 and the regrown semiconductor layer 123 may be N-type semiconductor layers, and the base region 122 may be a P-type semiconductor layer. In one embodiment, the aforementioned regrown semiconductor layer may be formed in the vertical power device, and the thickness of the regrown semiconductor layer may be 90 nm to 1500 nm.

[0127] Please see Figure 16 As shown, in one embodiment of the present invention, the substrate 101 is, for example, a highly doped N-type gallium nitride single crystal substrate. The substrate 101 serves as the current output terminal, discharging the current conducted down from the drift region into the device. Simultaneously, the substrate 101 also provides a lattice-matched growth platform for all the epitaxial layers above it.

[0128] Please see Figure 16As shown, in one embodiment of the present invention, the drain 1082 is disposed on one side of the substrate 101, serving as the current output terminal of the semiconductor device and forming an ohmic contact with the substrate 101. The entire drain 1082 provides a low-resistance current outgoing path, completing the entire current path from the source 1081 to the drain 1082.

[0129] Please see Figure 16 As shown, in one embodiment of the present invention, a drift region 121 is disposed on a substrate 101. The drift region 121 is an N-type semiconductor layer, specifically a lightly doped N-type gallium nitride layer. The drift region 121 serves as a high-voltage withstand core, capable of withstanding most of the reverse voltage when the device is turned off. Furthermore, the drift region 121 also functions as the main current channel; when the device is turned on, current flows vertically downwards from the channel region, through the drift region 121, to the bottom substrate 101.

[0130] Please see Figure 16 As shown, in one embodiment of the present invention, the thickness of the drift region 121 is set according to the breakdown voltage level of the semiconductor device to be formed. Through reasonable doping and thickness design, the electric field distribution during turn-off can be made uniform, avoiding premature breakdown caused by localized electric field concentration. In some embodiments, if the breakdown voltage level of the semiconductor device is, for example, 650V, the thickness of the drift region 121 can be set to, for example, 5μm~8μm. In other embodiments, if the breakdown voltage level of the semiconductor device is, for example, 1200V, the thickness of the drift region 121 can be set to, for example, 8μm~12μm. If the breakdown voltage level of the semiconductor device is greater than 2000V, the thickness of the drift region 121 is set to, for example, 12μm~20μm. The doping concentration of the drift region 121 is, for example, 1×10⁻⁶. 15 ~5×10 15 cm -3 .

[0131] Please see Figure 16 As shown, in one embodiment of the present invention, two base regions 122 are disposed in the drift region 121, and the two base regions 122 are, for example, P-type semiconductor layers, and for example, P-type gallium nitride layers. The two base regions 122 have a predetermined spacing, and the width between the two base regions 122 is the width of the PN junction depletion region, which is also the lateral dimension of the JFET channel region. In some embodiments, the thickness of the base region 122 is, for example, 500 nm to 2 μm. The width between the two base regions 122 is, for example, 0.5 μm to 2 μm. The width between the two base regions 122 directly determines the on-resistance, turn-off voltage, and threshold voltage of the semiconductor device. The smaller the width between the two base regions 122, the higher the turn-off voltage, the higher the on-resistance, and the higher the threshold voltage. The width between the two base regions 122 can be set according to design requirements.

[0132] Please see Figure 16As shown, in one embodiment of the present invention, a regrown semiconductor layer 123 is disposed in two base regions 122. The regrown semiconductor layer 123 is an N-type heavily doped region and is an N-type gallium nitride layer. The thickness of the regrown semiconductor layer 123 can be 90 nm to 1500 nm.

[0133] Please see Figure 16 As shown, in one embodiment of the present invention, the source 1081 is disposed above the two base regions 122, and the source 1081 forms an ohmic contact with the regrown semiconductor layer 123. The gate 107 is located directly above the two base regions 122 and directly opposite the JFET channel region. An isolation region 124 is disposed between the source 1081 and the gate 107. The isolation region 124 is, for example, a P-type gallium nitride layer. The isolation region 124 is disposed around the gate 107, electrically isolating the source 1081 and the gate 107, and participating in the formation of the gate-controlled PN junction to realize the turn-on and turn-off of the channel.

[0134] Please see Figure 17 As shown, in one embodiment, the semiconductor device of this application is, for example, a radio frequency device, wherein a regrown semiconductor layer 1061 and a regrown semiconductor layer 1062 can be formed in the radio frequency device, and the thickness of the regrown semiconductor layer can be 40nm~120nm.

[0135] Please see Figure 17 As shown, in one embodiment of the present invention, substrate 101 is a high-resistivity silicon substrate. The high resistivity substrate significantly reduces substrate leakage current and parasitic capacitance of the device, ensuring the performance of the RF device. A nucleation layer 131 is disposed on substrate 101, and nucleation layer 131 is, for example, an aluminum nitride nucleation layer. Nucleation layer 131 can alleviate the significant lattice mismatch and thermal mismatch problems between the subsequently formed gallium nitride and silicon substrate, improve the crystal quality of the gallium nitride epitaxial layer, and reduce dislocation and defect density. A buffer layer 102 is disposed on nucleation layer 13, and buffer layer 102 is, for example, an AlGaN buffer layer. Buffer layer 102 can further alleviate stress, suppress crack formation, and improve the overall quality of the epitaxial wafer. Furthermore, due to the high resistivity characteristics of aluminum gallium nitride, buffer layer 102 can block vertical leakage current, increasing the breakdown voltage when the device is turned off.

[0136] Please see Figure 17 As shown, in one embodiment of the present invention, a channel layer 103 is disposed on a buffer layer 102. The channel layer 103 is an unintentionally doped gallium nitride layer. Unintentionally doped gallium nitride ensures high purity and high electron mobility, which is crucial for achieving low on-resistance in semiconductor devices. The thickness of the channel layer 103, for example, is greater than or equal to 1000 nm, providing sufficient space to ensure that the two-dimensional electron gas formed on the top of the channel layer 103 is not affected by defects in the buffer layer 102.

[0137] Please see Figure 17As shown, in one embodiment of the present invention, an insertion layer 132, which is an aluminum nitride layer, is disposed on the channel layer 103. The insertion layer 132 is disposed between the channel layer 103 and the barrier layer 104, which can suppress the disordered scattering of the InAlN / GaN interface, improve the performance of the semiconductor device, and simultaneously prevent In atoms in the barrier layer 104 from diffusing into the GaN channel, ensuring the stability of the two-dimensional electron gas. The thickness of the insertion layer 132 is less than or equal to 1 nm. The ultrathin insertion layer 132 can significantly reduce the interface state density and significantly improve the mobility of the two-dimensional electron gas.

[0138] Please see Figure 17 As shown, in one embodiment of the present invention, a barrier layer 104 is disposed on the insertion layer 132, and the barrier layer 104 is, for example, InAlN. A high-density two-dimensional electron gas is generated by utilizing the strong polarization effect between the InAlN in the barrier layer 104 and the GaN in the channel layer 103. The thickness of the barrier layer 104 is, for example, 8nm to 12nm, such as 9nm, 10nm, or 11nm. An 8nm to 12nm barrier layer 104 can balance the ability to generate a high-density two-dimensional electron gas and control the gate.

[0139] Please see Figure 17 As shown, in one embodiment of the present invention, the regenerated semiconductor layer 1061 and the regenerated semiconductor layer 1062 are respectively disposed at the bottom of the source 1081 and the drain 1082, and extend into the channel layer 103 and are close to the two-dimensional electron gas layer.

[0140] Please see Figure 17 As shown, in one embodiment of the present invention, the gate 107 is disposed on the barrier layer, and the gate 107 includes a neck 1071 and a gate cap 1072 disposed on the neck 1071, and the central axis of the neck 1071 coincides with the central axis of the gate cap 1072.

[0141] Please see Figure 17As shown, in one embodiment of the present invention, the width of the gate cap 1072 is greater than the width of the neck 1071, and the cross-section of the gate cap 1072 is an isosceles trapezoid. The width of the neck 1071 is, for example, 50nm to 80nm, specifically 50nm, 60nm, or 80nm. The height of the neck 1071 is, for example, 140nm to 160nm, specifically 145nm, 150nm, or 155nm. The top width of the gate cap 1072 is, for example, 200nm to 260nm, specifically 220nm, 240nm, 250nm, or 260nm. The bottom width of the gate cap 1072 is, for example, 280nm to 320nm, specifically 290nm, 300nm, 310nm, or 320nm. The height of the gate cap 1072 is, for example, 270nm~300nm, specifically 270nm, 280nm, 285nm or 290nm, etc.

[0142] Please see Figure 17 As shown, in one embodiment of the present invention, the width of the gate cap 1072 is greater than the width of the neck 1071, so that the gate 107 as a whole forms a large hat structure, which is equivalent to increasing the lateral cross-sectional area of ​​the gate 107, which can significantly reduce the gate series resistance and improve radio frequency performance.

[0143] Please see Figure 17 As shown, in one embodiment of the present invention, the gate cap 1072 extends toward the source 1081 and drain 1082, equivalent to a gate field plate, which can weaken the electric field peaks at the gate edge, avoid local breakdown, and flatten the electric field distribution in the off state, significantly improving the breakdown voltage of the semiconductor device. The neck 1071 has a relatively high height, which allows the field plate to maintain a suitable distance from the channel, achieving electric field optimization without affecting gate control capability.

[0144] Please see Figure 17 As shown, in one embodiment of the present invention, the cross-section of the gate cap 1072 is arranged in an isosceles trapezoid, which makes the contact area between the gate metal and the barrier layer more reasonable, while the field plate effect reduces the impact of the high electric field on the gate dielectric. This achieves the technical effects of suppressing gate leakage, improving the stability of the device during turn-off, reducing hot electron injection, and extending the lifespan of the semiconductor device.

[0145] Please see Figure 17 As shown, in one embodiment of the present invention, setting the width of the neck 1071 to be relatively small can maintain the strong control capability of the neck 1071 over the channel, ensuring the switching characteristics of the device. Meanwhile, the larger width of the gate cap 1072 ensures that the low resistance of the gate cap 1072 does not increase additional conduction losses, maintaining the low on-resistance of the semiconductor device.

[0146] In one embodiment, the semiconductor device of this application may further include a surface treatment layer, which may be formed on the substrate 101 and may have a two-dimensional structure, such as a nanostructure with uneven surface, to alleviate stress in subsequent stacking of semiconductor layers. The surface treatment layer may be formed, for example, by sputtering, PVD, or MOCVD.

[0147] In one embodiment, the semiconductor device of this application may further include a field plate to improve the electric field distribution.

[0148] In some embodiments of the present invention, one or more barrier layers, regrown semiconductor layers, buffer layers, channel layers, dielectric layers, nucleation layers, surface treatment layers, field plates, or other semiconductor layers in the semiconductor device provided by the present invention can be formed or grown by sputtering, PVD, ALD, or other suitable methods, and can have columnar crystal structures or columnar crystal characteristics. When the relative temperature for crystal growth is relatively high (e.g., greater than 0.5), the intracrystalline defect density can be low, the thin film crystallization is very complete, and the strength is high. The relative temperature is the ratio of the substrate temperature to the thin film melting temperature; if the substrate temperature is low, the relative temperature is low, and if the substrate temperature is high, the relative temperature is high.

[0149] When the relative temperature for crystal growth is relatively stable and high, i.e., 0.3-0.7, sputtered ions can undergo sufficient surface diffusion after incident on the substrate surface. The migration distance of the sputtered ions increases, and the microfiber structure forms columnar crystals due to surface diffusion. These columnar crystals then undergo bulk diffusion and grain boundary movement to form coarse equiaxed crystals, reducing defects between grain boundaries. Therefore, deposition at a uniform high temperature results in a fast film formation rate, and the lattice arrangement of the thin film (e.g., aluminum nitride) exhibits columnar crystal growth, leading to good crystallinity and improved film uniformity.

[0150] In one embodiment, after sputtering or PVD growing a thin film or semiconductor layer, the surface of the grown film may be post-treated, for example by plasma, to improve the surface quality or uniformity of the thin film or semiconductor layer.

[0151] In some embodiments of the present invention, the semiconductor device provided by the present invention can be used in power conversion devices, specifically, for example, in electronic devices such as AC-DC or DC-DC converters. In some embodiments of the present invention, the semiconductor device can be used in consumer electronic devices, specifically, for example, in electronic devices such as fast chargers or wireless chargers. In some embodiments, the semiconductor device can be used in radio frequency (RF) devices, specifically, for example, in devices such as 5G communication base stations or radar systems. In some embodiments, the semiconductor device can be used in electric vehicles, specifically, for example, in devices such as on-board chargers and motor drives.

[0152] The semiconductor device provided by this invention can improve the average electric field and increase the breakdown voltage.

[0153] In some embodiments of the present invention, the second barrier layer can serve as a dielectric field plate, extending the depletion region below the gate. In the off state, the depletion region extends laterally towards the AlGaN / GaN interface, making the electric field distribution flatter and preventing premature breakdown at the gate edge due to electric field concentration. Simultaneously, because the bandgap of the aluminum gallium nitride layer is larger than that of the gallium nitride layer, the critical breakdown electric field strength of both the aluminum gallium nitride and gallium nitride layers is higher. This layer can delay avalanche breakdown when subjected to high electric fields, thereby improving the overall breakdown voltage capability of the semiconductor device. Furthermore, the second barrier layer and the p-type gallium nitride layer can form a heterostructure, further modulating the longitudinal and lateral expansion of the depletion region, reducing the non-uniformity of the field below the gate, making the electric field distribution smoother, and improving the breakdown voltage.

[0154] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized in that, At least including: Substrate; A channel layer is disposed on the substrate; A first barrier layer is disposed on the channel layer, and the first barrier layer covers the channel layer; A P-type semiconductor layer is disposed on the first barrier layer; A gate is disposed on the semiconductor layer; The source electrode is disposed on the first barrier layer; The drain is disposed on the first barrier layer; The first barrier layer has a columnar crystal structure.

2. The semiconductor device according to claim 1, characterized in that, It also includes a second barrier layer, which is formed on the first barrier layer.

3. The semiconductor device according to claim 2, characterized in that, A portion of the second barrier layer extends between the P-type semiconductor layer and the gate.

4. The semiconductor device according to claim 2, characterized in that, A portion of the second barrier layer is formed between the P-type semiconductor layer and the gate.

5. The semiconductor device according to claim 2, characterized in that, It also includes at least one dielectric layer formed between the second barrier layer and the gate.

6. The semiconductor device according to claim 2, characterized in that, A portion of the second barrier layer is formed on the P-type semiconductor layer and the gate.

7. The semiconductor device according to claim 1, characterized in that, Also includes: A regenerated semiconductor layer is formed between the source and the first barrier layer; Another regenerated semiconductor layer is formed between the drain and the first barrier layer.

8. The semiconductor device according to claim 7, characterized in that, The regenerated semiconductor layer is embedded in the first barrier layer.

9. The semiconductor device according to claim 1, characterized in that, Between the gate and the P-type semiconductor layer, there is also a multilayer gate dielectric layer.

10. The semiconductor device according to claim 1, characterized in that, The semiconductor device is a power device or a radio frequency device.

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