Low-power-consumption GaN bidirectional switch device and preparation method thereof

Abstract

The application discloses a low-power-consumption GaN bidirectional switch device and a preparation method thereof. The device comprises a substrate (1), a buffer layer (2), a GaN layer 1 (3), an AlGaN barrier layer (4), a GaN layer 2 (5), a source electrode 1 (6) and a source electrode 2 (7) arranged on the surfaces of the AlGaN barrier layer (4) at two ends of the device respectively, two p-GaN layers (8) arranged on the GaN layer 2 (5) at intervals, two GaN layers (9) arranged on the two p-GaN layers (8) respectively, a gate electrode 1 (10) and a gate electrode 2 (11) arranged on the two GaN layers (9) respectively. + The application can realize an enhanced working mode, reduce the device size and parasitic parameters, reduce the conduction loss under the same voltage resistance specification, and realize low power consumption. + The application can realize an enhanced working mode, reduce the device size and parasitic parameters, reduce the conduction loss under the same voltage resistance specification, and realize low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a low-power GaN bidirectional switching device and its fabrication method. Background Technology

[0002] With the continuous development of new power conversion system applications, the topologies and performance of matrix converters (AC / AC), solid-state relays (SSRs), and inverters (DC-AC) are mainly constrained by the performance of bidirectional switching devices. Traditional bidirectional switches are mainly composed of two Si MOSFETs or IGBTs connected back to back, which are large in size and have high losses.

[0003] Compared to traditional Si power device topologies, GaN bidirectional switches can monolithically integrate a dual-gate structure, significantly improving integration density while substantially reducing conduction losses and parasitic inductance. However, improving the breakdown voltage of dual-gate GaN bidirectional switches requires increasing the spacing between the two gates, leading to a substantial increase in the nonlinearity of the device's on-resistance. Furthermore, existing GaN bidirectional switches often employ field-plate structures to achieve electric field modulation and reduce the peak electric field at the gate side. GaN bidirectional switches require multiple layers of gate and source field plates, making their field plate structures more complex than those of conventional GaN devices. The introduction of dual-gate field plates also introduces more complex parasitic capacitance effects, severely impacting the reliability of AC power conversion topologies in high-frequency, high-power applications. Summary of the Invention

[0004] To address the aforementioned issues, this invention provides a low-power GaN bidirectional switching device and its fabrication method, which balances enhancement-mode operation, low conduction loss, small chip area, and small parasitic parameters.

[0005] To achieve the above objectives, such as Figure 1 As shown, the bidirectional switching device provided by the present invention is provided with a substrate (1), a buffer layer (2), a GaN layer 1 (3), an AlGaN barrier layer (4), and a GaN layer 2 (5) arranged sequentially from bottom to top. Source 1 (6) and source 2 (7) are respectively disposed on the surface of the AlGaN barrier layer (4) at both ends of the device. Two p-GaN layers (8) are disposed on the GaN layer 2 (5) at intervals. + -GaN layers (9) are respectively disposed on the two p-GaN layers (8), and gate 1 (10) and gate 2 (11) are respectively disposed on the two p-GaN layers (8). + -GaN layer (9) on.

[0006] In this invention, the substrate (1) can be made of one of sapphire, SiC, Si, or GaN;

[0007] In this invention, the thickness of the GaN layer 1 (3) is 300-500 nm;

[0008] In this invention, the AlGaN barrier layer (4) has a thickness of 10–20 nm and an Al composition of 0.20–0.25.

[0009] In this invention, the thickness of the GaN layer 2 (5) is 30-40 nm;

[0010] In this invention, the thickness of the p-GaN layer (8) is 50–70 nm;

[0011] In this invention, p + - The GaN layer (9) has a thickness of 2–4 nm;

[0012] In this invention, the Mg doping concentration in the p-GaN layer (8) is 1×10⁻⁶. 17 ~1×10 19 cm -3 ;

[0013] In this invention, p + The Mg doping concentration in the GaN layer (9) is 1×10⁻⁶. 19 ~3×10 20 cm -3 ;

[0014] In this invention, source 1 (6) and source 2 (7) both form ohmic contacts with the AlGaN barrier layer (4); gate 1 (10) and gate 2 (11) respectively form ohmic contacts with p + - The GaN layer (9) forms an ohmic contact.

[0015] The GaN layer 2 (5), AlGaN barrier layer (4), and GaN layer 1 (3) between the two gates constitute a shared polarization superjunction drift region. The shared polarization superjunction drift region utilizes the charge compensation effect between the positive and negative polarization charges at the heterojunction interface of GaN layer 2 (5) / AlGaN barrier layer (4) / GaN layer 1 (3) to modulate the lateral electric field distribution between the two gates.

[0016] This invention also provides a method for fabricating a low-power GaN bidirectional switching device, the method comprising:

[0017] S1: Buffer layer (2), GaN layer 1 (3), AlGaN barrier layer (4), GaN layer 2 (5), p-GaN layer (8), and p-GaN layer (9) are sequentially grown on substrate (1). + -GaN layer (9) forms an epitaxial structure.

[0018] S2: Using photolithography and inductively coupled plasma etching processes, the portion above the preset horizontal plane of the GaN layer 1 (3) in the epitaxial structure is etched to form a mesa structure with a lower projected area larger than the upper projected area in order to achieve device isolation.

[0019] S3: In the obtained mesa structure, photolithography and inductively coupled plasma etching processes are used to remove the p-GaN layer (8) and p-GaN layer in the non-gate region. + -GaN layer (9), and stop etching when the upper surface of GaN layer 2 (5) is exposed.

[0020] S4: Using photolithography and inductively coupled plasma etching processes, the GaN layer 2 (5) is etched on both sides, and the etching is stopped when the upper surface of the AlGaN barrier layer (4) is exposed, thereby forming the GaN layer 2 (5) mesa and the source contact areas located on both sides of the mesa.

[0021] S5: Source 1 (6) and source 2 (7) are formed on the AlGaN barrier layer (4) exposed at both ends of the device by photolithography, metal deposition and lift-off processes; then rapid thermal annealing is performed to form n-type ohmic contacts.

[0022] S6: Through photolithography, metal deposition, and lift-off processes, in p + - A GaN layer (9) is formed to form gate 1 (10) and gate 2 (11), respectively; then rapid thermal annealing is performed to form a p-type ohmic contact.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] GaN superjunction bidirectional switches utilize the superjunction structure between the two gates to improve the electric field distribution between the gates, resulting in an approximately rectangular electric field distribution. Therefore, the breakdown voltage and on-resistance of the device increase approximately linearly with the increase in the spacing between the two gates. Compared to GaN bidirectional switching devices with field-plate structures, GaN superjunction bidirectional switches exhibit smaller size, lower parasitic parameters, and lower conduction losses at the same voltage rating. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present invention and form part of this application, are not intended to limit the embodiments of the present invention.

[0026] Figure 1 A schematic diagram of the cross-sectional structure of the low-power GaN bidirectional switching device provided by the present invention.

[0027] Figure 2 This is a schematic diagram of the cross-sectional structure of a low-power GaN bidirectional switching device provided in Embodiment 1 of the present invention.

[0028] Figure 3 This is a schematic diagram of the fabrication process of the low-power GaN bidirectional switching device provided in Embodiment 1 of the present invention.

[0029] Figure 4 This is a schematic diagram of the cross-sectional structure of a device using a SiC substrate and an AlN nucleation layer, provided in Embodiment 2 of the present invention.

[0030] Figure 5 This is a schematic diagram of the cross-sectional structure of a device with a SiO2 passivation layer provided in Embodiment 3 of the present invention. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0032] Example 1:

[0033] like Figure 2 As shown, this embodiment provides a low-power GaN bidirectional switching device. The device includes, from bottom to top, a sapphire substrate (12), a buffer layer (13), a GaN layer 1 (14), an AlGaN barrier layer (15), and a GaN layer 2 (16). Source 1 (17) and source 2 (18) are respectively disposed on the surface of the AlGaN barrier layer (15) at both ends of the device. Two p-GaN layers (19) are disposed at intervals on the GaN layer 2 (16). + -GaN layers (20) are respectively disposed on the two p-GaN layers (19), and gate 1 (21) and gate 2 (22) are respectively disposed on the two p-GaN layers (19). + -On the GaN layer (20).

[0034] In this embodiment, the buffer layer (13), GaN layer 1 (14), AlGaN barrier layer (15), GaN layer 2 (16), p-GaN layer (19) and p + The thicknesses of the GaN layers (20) are 1 μm, 400 nm, 15 nm, 35 nm, 68 nm and 3 nm, respectively. The Al composition of the AlGaN barrier layer (15) is 0.21, and the Mg doping concentration in the p-GaN layer (19) is 5 × 10⁻⁶. 18 cm -3 p + The Mg doping concentration in the GaN layer (20) is 2×10⁻⁶. 20 cm -3 The width of both gates is 3 μm, the length of the shared polarized superjunction drift region between them is 10 μm, and the spacing between source 1 (17) to gate 1 (21) and between gate 2 (22) and source 2 (18) is 1 μm.

[0035] like Figure 3 As shown, the device described in this embodiment can be fabricated using the following method:

[0036] S1: Using metal-organic chemical vapor deposition (MOCVD), a buffer layer (13) with a thickness of 1 μm, a GaN layer 1 (14) with a thickness of 400 nm, an AlGaN barrier layer (15) with a thickness of 15 nm and an Al composition of 0.21, a GaN layer 2 (16) with a thickness of 35 nm, and a GaN layer 38 nm with a Mg doping concentration of 5 × 10⁻⁶ were sequentially grown on a sapphire substrate (12). 18 cm -3 The p-GaN layer (19) with a thickness of 3 nm and a Mg doping concentration of 2 × 10⁻⁶ 20 cm -3 p + -GaN layer (20) forms an epitaxial structure.

[0037] S2: Using photolithography and inductively coupled plasma etching processes, the portion above the preset horizontal plane of the GaN layer 1 (14) in the epitaxial structure is etched to form a mesa structure with a lower projected area larger than the upper projected area in order to achieve device isolation.

[0038] S3: In the obtained mesa structure, photolithography and inductively coupled plasma etching (ICP-C) processes are used. ICP-C uses BCl3 and Cl2 as etching gases for selective etching to remove p-type non-gate regions. + -GaN layer (20) and p-GaN layer (19), and stop etching when the upper surface of GaN layer 2 (16) is exposed.

[0039] S4: Using photolithography and inductively coupled plasma etching processes, the GaN layer 2 (16) at both ends of the device is removed, and etching is stopped when the upper surface of the AlGaN barrier layer (15) is exposed, thereby forming the mesa of the GaN layer 2 (16) and the source contact regions located on both sides of the mesa.

[0040] S5: A patterned photoresist layer with source 1 (17) patterned openings and source 2 (18) patterned openings is formed on the device surface, the two source patterned openings being located on the AlGaN barrier layer (15) surfaces at both ends of the device, respectively. Subsequently, Ti / Al / Ni / Au (20 / 140 / 55 / 45 nm) is sequentially deposited using an electron beam evaporation process to form source 1 (17) and source 2 (18). Then, rapid thermal annealing is performed for 35 s at 870 °C in a N2 atmosphere to form an n-type ohmic contact.

[0041] S6: Electron beam evaporation process is used to evaporate two p +Ni / Au (20 / 35 nm) was sequentially deposited on the GaN layer, and gate 1 (21) and gate 2 (22) were formed by stripping. Subsequently, the device was annealed at 560 °C for 5 min in a N2 / O2 mixed atmosphere to form a p-type ohmic contact. The fabrication of the device in this embodiment is now complete.

[0042] Example 2:

[0043] This embodiment is basically the same as embodiment 1, except that: a SiC substrate (23) is used, and an AlN nucleation layer (24) is provided between the SiC substrate (23) and the buffer layer (25).

[0044] like Figure 4 As shown, this embodiment provides a low-power GaN bidirectional switching device. The device includes, from bottom to top, a SiC substrate (23), an AlN nucleation layer (24), a buffer layer (25), a GaN layer 1 (26), an AlGaN barrier layer (27), and a GaN layer 2 (28). Source 1 (29) and source 2 (30) are respectively disposed on the surface of the AlGaN barrier layer (27) at both ends of the device. Two p-GaN layers (31) are disposed at intervals on the GaN layer 2 (28). + -GaN layers (32) are respectively disposed on the two p-GaN layers (31), and gate 1 (33) and gate 2 (34) are respectively disposed on the two p-GaN layers (31). + -GaN layer (32) on.

[0045] In this embodiment, the AlN nucleation layer (24), buffer layer (25), GaN layer 1 (26), AlGaN barrier layer (27), GaN layer 2 (28), p-GaN layer (31), and p + The thicknesses of the GaN layers (32) are 100 nm, 1 μm, 400 nm, 15 nm, 35 nm, 68 nm and 3 nm, respectively. The Al composition of the AlGaN barrier layer (27) is 0.21, and the Mg doping concentration in the p-GaN layer (31) is 5 × 10⁻⁶. 18 cm -3 p + The Mg doping concentration in the GaN layer (32) is 2×10⁻⁶. 20 cm -3 The width of both gates is 3 μm, the length of the shared polarized superjunction drift region between them is 10 μm, and the spacing between source 1 (29) to gate 1 (33) and between gate 2 (34) and source 2 (30) is 1 μm.

[0046] The device described in this embodiment can be fabricated using the following method:

[0047] S1: Using metal-organic chemical vapor deposition (MOCVD), a 100 nm thick AlN nucleation layer (24), a 1 μm buffer layer (25), a 400 nm thick GaN layer 1 (26), a 15 nm thick AlGaN barrier layer (27) with an Al composition of 0.21, a 35 nm thick GaN layer 2 (28), and a 68 nm thick Mg doping concentration of 5 × 10⁻⁶ were sequentially grown on a SiC substrate (23). 18 cm -3 The p-GaN layer (31) with a thickness of 3 nm and a Mg doping concentration of 2 × 10⁻⁶ 20 cm -3 p + -GaN layer (32) forms an epitaxial structure.

[0048] S2: Using photolithography and inductively coupled plasma etching processes, the portion above the preset horizontal plane of the GaN layer 1 (26) in the epitaxial structure is etched to form a mesa structure with a lower projected area larger than the upper projected area to achieve device isolation.

[0049] S3: In the obtained mesa structure, photolithography and inductively coupled plasma etching (ICP-C) processes are used. ICP-C uses BCl3 and Cl2 as etching gases for selective etching to remove p-type non-gate regions. + -GaN layer (32) and p-GaN layer (31), and stop etching when the upper surface of GaN layer 2 (28) is exposed.

[0050] S4: Using photolithography and inductively coupled plasma etching processes, the GaN layer 2 (28) at both ends of the device is removed, and etching is stopped when the upper surface of the AlGaN barrier layer (27) is exposed, thereby forming the mesa of the GaN layer 2 (28) and the source contact regions located on both sides of the mesa.

[0051] S5: A patterned photoresist layer with source 1 (29) patterned openings and source 2 (30) patterned openings is formed on the device surface, the two source patterned openings being located on the AlGaN barrier layer (27) surfaces at both ends of the device, respectively. Subsequently, Ti / Al / Ni / Au (20 / 140 / 55 / 45 nm) is sequentially deposited using an electron beam evaporation process to form source 1 (29) and source 2 (30). Then, rapid thermal annealing is performed for 35 s at 870 °C in a N2 atmosphere to form an n-type ohmic contact.

[0052] S6: Electron beam evaporation process is used to evaporate two p +Ni / Au (20 / 35 nm) was sequentially deposited on the GaN layer, and gate 1 (33) and gate 2 (34) were formed by stripping. Subsequently, the device was annealed at 560 °C for 5 min in a N2 / O2 mixed atmosphere to form a p-type ohmic contact. The fabrication of the device in this embodiment is now complete.

[0053] Example 3:

[0054] This embodiment is basically the same as embodiment 1, except that a SiO2 passivation layer (46) is further provided on the surface of the device.

[0055] like Figure 5 As shown, this embodiment provides a low-power GaN bidirectional switching device. The device includes, from bottom to top, a sapphire substrate (35), a buffer layer (36), a GaN layer 1 (37), an AlGaN barrier layer (38), and a GaN layer 2 (39). Source 1 (40) and source 2 (41) are respectively disposed on the surface of the AlGaN barrier layer (38) at both ends of the device. Two p-GaN layers (42) are disposed at intervals on the GaN layer 2 (39). + -GaN layers (43) are respectively disposed on the two p-GaN layers (42), and gate 1 (44) and gate 2 (45) are respectively disposed on the two p-GaN layers (42). + - On the GaN layer (43), the SiO2 passivation layer (46) covers the device surface and forms corresponding contact holes on the four electrode surfaces.

[0056] In this embodiment, the buffer layer (36), GaN layer 1 (37), AlGaN barrier layer (38), GaN layer 2 (39), p-GaN layer (42), p + The thicknesses of the GaN layer (43) and the SiO2 passivation layer (46) are 1 μm, 400 nm, 15 nm, 35 nm, 68 nm, 3 nm and 20 nm, respectively. The Al composition of the AlGaN barrier layer (38) is 0.21, and the Mg doping concentration in the p-GaN layer (42) is 5 × 10⁻⁶. 18 cm -3 p + The Mg doping concentration in the GaN layer (43) is 2×10⁻⁶. 20 cm -3 The width of both gates is 3 μm, the length of the shared polarized superjunction drift region between them is 10 μm, and the spacing between source 1 (40) to gate 1 (44) and between gate 2 (45) and source 2 (41) is 1 μm.

[0057] The device described in this embodiment can be fabricated using the following method:

[0058] S1: Using metal-organic chemical vapor deposition (MOCVD), a buffer layer (36) with a thickness of 1 μm, a GaN layer 1 (37) with a thickness of 400 nm, an AlGaN barrier layer (38) with a thickness of 15 nm and an Al composition of 0.21, a GaN layer 2 (39) with a thickness of 35 nm, and a GaN layer 2 (39) with a thickness of 68 nm and an Mg doping concentration of 5 × 10⁻⁶ were sequentially grown on a sapphire substrate (35). 18 cm -3 The p-GaN layer (42) with a thickness of 3 nm and a Mg doping concentration of 2 × 10⁻⁶ 20 cm -3 p + -GaN layer (43) forms an epitaxial structure.

[0059] S2: Using photolithography and inductively coupled plasma etching processes, the portion above the preset horizontal plane of the GaN layer 1 (37) in the epitaxial structure is etched to form a mesa structure with a lower projected area larger than the upper projected area in order to achieve device isolation.

[0060] S3: In the obtained mesa structure, photolithography and inductively coupled plasma etching (ICP-C) processes are used. ICP-C uses BCl3 and Cl2 as etching gases for selective etching to remove p-type non-gate regions. + -GaN layer (43) and p-GaN layer (42), and stop etching when the upper surface of GaN layer 2 (39) is exposed.

[0061] S4: Using photolithography and inductively coupled plasma etching processes, the GaN layer 2 (39) at both ends of the device is removed, and etching is stopped when the upper surface of the AlGaN barrier layer (38) is exposed, thereby forming the GaN layer 2 (39) mesa and the source contact regions located on both sides of the mesa.

[0062] S5: A patterned photoresist layer with source 1 (40) patterned opening and source 2 (41) patterned opening is formed on the device surface, the two source patterned openings being located on the AlGaN barrier layer (38) surfaces at both ends of the device, respectively. Subsequently, Ti / Al / Ni / Au (20 / 140 / 55 / 45 nm) is sequentially deposited using an electron beam evaporation process to form source 1 (40) and source 2 (41). Then, rapid thermal annealing is performed for 35 s at 870 °C in a N2 atmosphere to form an n-type ohmic contact.

[0063] S6: Electron beam evaporation process is used to evaporate two p + Ni / Au (20 / 35 nm) was deposited sequentially on the GaN layer, and gate 1 (44) and gate 2 (45) were formed by stripping. Then, the p-type ohmic contact was formed by annealing at 560 °C for 5 min in a N2 / O2 mixed atmosphere.

[0064] S7: The obtained device is placed in the plasma-enhanced chemical vapor deposition (PECVD) reaction chamber, and a 20 nm thick SiO2 passivation layer (46) is deposited on the device surface at 400 °C using the PECVD process. Finally, the passivation layer covering source 1 (40), source 2 (41), gate 1 (44) and gate 2 (45) is selectively etched to form corresponding contact holes.

[0065] The SiO2 passivation layer (46) is used to protect the exposed semiconductor surface and electrode edges, and helps to reduce the influence of surface states and surface leakage current on the static and dynamic characteristics of the device. The passivation structure can also be used in combination with the SiC substrate and AlN nucleation layer described in Example 2.

[0066] Those skilled in the art can make equivalent substitutions for the epitaxial growth method, etching mask material, metal formation method, and passivation layer formation method without departing from the concept of the present invention; such substitutions do not change the basic technical concept of p-GaN enhanced gate control and shared polarization superjunction drift region.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. All modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-power GaN bidirectional switching device, characterized in that, include: From bottom to top, the following layers are arranged sequentially: substrate (1), buffer layer (2), GaN layer 1 (3), AlGaN barrier layer (4), and GaN layer 2 (5). Source 1 (6) and source 2 (7) are respectively disposed on the surfaces of the AlGaN barrier layer (4) at both ends of the device. Two p-GaN layers (8) are disposed on the GaN layer 2 (5) at intervals. + -GaN layers (9) are respectively disposed on the two p-GaN layers (8), and gate 1 (10) and gate 2 (11) are respectively disposed on the two p-GaN layers (8). + -On the GaN layer (9); The GaN layer 2 (5), AlGaN barrier layer (4), and GaN layer 1 (3) between gate 1 (10) and gate 2 (11) constitute a shared polarization superjunction drift region.

2. The bidirectional switch according to claim 1, characterized in that, The thickness of GaN layer 1 (3) is 300-500 nm.

3. The bidirectional switch according to claim 1, characterized in that, The AlGaN barrier layer (4) has a thickness of 10–20 nm and an Al composition of 0.20–0.

25.

4. The bidirectional switch according to claim 1, characterized in that, The thickness of GaN layer 2 (5) is 30–40 nm.

5. The bidirectional switch according to claim 1, characterized in that, The p-GaN layer (8) has a thickness of 50–70 nm and a Mg doping concentration of 1 × 10⁻⁶. 17 ~1×10 19 cm -3 .

6. The bidirectional switch according to claim 1, characterized in that, p + - The GaN layer (9) has a thickness of 2–4 nm, and the Mg doping concentration is 1 × 10⁻⁶. 19 ~3×10 20 cm -3 .

7. A method for fabricating a low-power GaN bidirectional switching device, characterized in that, The method for fabricating the low-power GaN bidirectional switching device according to any one of claims 1 to 6 includes the following steps: A buffer layer (2), GaN layer 1 (3), AlGaN barrier layer (4), GaN layer 2 (5), p-GaN layer (8), and p-GaN layer (9) are sequentially formed on a substrate (1). + -GaN layer (9) forms an epitaxial structure; Mesa etching is performed on the epitaxial structure to form the active region of the device and achieve device isolation; Selective etching of non-gate regions p + -GaN layer and p-GaN layer, and stop etching when GaN layer 2 (5) is exposed; The GaN layer 2 (5) at both ends of the device is etched, and the etching is stopped when the AlGaN barrier layer (4) is exposed to form the source contact region at both ends of the device. Source 1 (6) and source 2 (7) are formed in the source contact region respectively, and annealing is performed to form an n-type ohmic contact; In the two p + Gate 1 (10) and gate 2 (11) are formed on the GaN layer (9) respectively, and annealing is performed to form a p-type ohmic contact.

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