Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate structure including a semiconductor substrate and a trench isolation structure in the semiconductor substrate, the semiconductor substrate including a first region and a second region separated by the trench isolation structure; one or more sub-structures on the substrate structure, the one or more sub-structures including a first sub-structure on the first region and a second sub-structure on the second region, each sub-structure including a substrate layer and a sacrificial layer on the substrate structure and a channel structure on the substrate layer, the sacrificial layer being on the trench isolation structure, the sacrificial layer in the first sub-structure being between the channel structure in the first sub-structure and the channel structure in the second sub-structure, the channel structure including a channel layer; an electrode connected to the channel layer; a gate structure on the channel layer; and a contact component connected to the electrode.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the development of semiconductor devices, the reduction in the critical dimension (CD) of the source and drain contact components leads to an increase in the contact resistance of the source and drain. Related technologies employ various contact techniques to reduce this contact resistance. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate structure including a semiconductor substrate and a trench isolation structure in the semiconductor substrate, wherein the semiconductor substrate includes a first region and a second region separated by the trench isolation structure; one or more substructures on the substrate structure, the one or more substructures including a first substructure and a second substructure, the first substructure being located on the first region and the second substructure being located on the second region, each substructure including a substrate layer and a sacrificial layer on the substrate structure and a channel structure on the substrate layer, the sacrificial layer being located on the trench isolation structure, the sacrificial layer in the first substructure and the sacrificial layer in the second substructure being located between the channel structure in the first substructure and the channel structure in the second substructure, the channel structure including a channel layer; an electrode connected to the channel layer; a gate structure on the channel layer; and a contact member connected to the electrode.

[0004] According to another aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: providing a semiconductor structure including a substrate structure and one or more substructures on the substrate structure, the substructures including a substrate layer and a first sacrificial layer on the substrate structure and a channel structure on the substrate layer, wherein the first sacrificial layer includes a first portion on a first side of the substrate layer and a second portion on a second side of the substrate layer, the first side being opposite to the second side, the substrate layer including a first substrate layer portion covered by the channel structure and a second substrate layer portion not covered by the channel structure, the channel structure including a channel layer; performing a doping process on the second substrate layer portion; forming an electrode connected to the channel layer on the doped second substrate layer portion, the electrode being located between the first and second portions of the first sacrificial layer; forming a gate structure on the channel layer after forming the electrode; performing an etching process on the semiconductor structure after forming the gate structure to form an opening exposing the first and second portions of the first sacrificial layer and the electrode; removing the first and second portions of the first sacrificial layer and the second substrate layer portion through the opening to form a first void; and forming a contact member surrounding the electrode in the first void.

[0005] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0006] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0007] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0008] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0009] Figure 2A and Figure 2B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating a stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 3A and Figure 3B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0011] Figure 4A and Figure 4BThese are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 5A and Figure 5B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0013] Figure 6A and Figure 6B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0014] Figure 7A and Figure 7B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0015] Figure 8 This is a schematic cross-sectional view showing the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure, taken along a first direction.

[0016] Figure 9A and Figure 9B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0017] Figure 10A and Figure 10B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0018] Figure 11 This is a schematic cross-sectional view showing the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure, taken along a first direction.

[0019] Figure 12 This is a schematic cross-sectional view showing the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure, taken along a first direction.

[0020] Figure 13A and Figure 13B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0021] Figure 14Aand Figure 14B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0022] Figure 15 This is a schematic cross-sectional view showing the structure of another stage in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure, taken along a first direction.

[0023] Figure 16A and Figure 16B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0024] Figure 17A and Figure 17B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0025] Figure 18A and Figure 18B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0026] Figure 19A and Figure 19B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0027] Figure 20A and Figure 20B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure.

[0028] Figure 21A and Figure 21B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating a stage of the manufacturing process of a semiconductor device according to other embodiments of the present disclosure.

[0029] Figure 22A and Figure 22B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0030] Figure 23A and Figure 23BThese are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0031] Figure 24A and Figure 24B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0032] Figure 25A and Figure 25B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0033] Figure 26A and Figure 26B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0034] Figure 27A and Figure 27B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0035] Figure 28A and Figure 28B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0036] Figure 29 This is a schematic cross-sectional view taken along a first direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0037] Figure 30A and Figure 30B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0038] Figure 31A and Figure 31B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0039] Figure 32A and Figure 32BThese are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0040] Figure 33A and Figure 33B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0041] Figure 34A and Figure 34B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0042] Figure 35A and Figure 35B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0043] Figure 36A and Figure 36B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0044] Figure 37A and Figure 37B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0045] Figure 38A and Figure 38B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0046] Figure 39A and Figure 39B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating the structure of another stage in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure;

[0047] Figure 40A and Figure 40B These are schematic cross-sectional views taken along a first direction and a second direction, illustrating another stage of the manufacturing process of a semiconductor device according to other embodiments of the present disclosure.

[0048] It should be understood that the dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale. Furthermore, the same or similar reference numerals denote the same or similar components. Detailed Implementation

[0049] In related technologies, wrap-around contact (WAC) is a method used to reduce the contact resistance of the source / drain. However, due to the characteristics of epitaxial phase growth of the source and drain, achieving a wrap-around contact may lead to an increase in the critical dimensions of the contact components, which contradicts the miniaturization of device dimensions. Furthermore, the wrap-around contact in related technologies does not actually achieve a complete wrap around the source / drain, therefore, the reduction in contact resistance is limited.

[0050] In view of this, embodiments of the present disclosure provide a method for manufacturing a semiconductor device to reduce the size of contact components while also reducing contact resistance.

[0051] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 1 As shown, the manufacturing method includes steps S102 to S114.

[0052] In step S102, a semiconductor structure is provided. The semiconductor structure includes a substrate structure and one or more substructures on the substrate structure. The substructures include a substrate layer and a first sacrificial layer on the substrate structure, and a channel structure on the substrate layer. The first sacrificial layer includes a first portion on a first side of the substrate layer and a second portion on a second side of the substrate layer, with the first side opposite to the second side. The substrate layer includes a first substrate layer portion covered by the channel structure and a second substrate layer portion not covered by the channel structure. The channel structure includes a channel layer.

[0053] In step S104, a doping process is performed on the second substrate layer.

[0054] For example, at least one impurity atom (or ion) selected from argon, oxygen, hydrogen, helium, germanium, boron, phosphorus, carbon, and nitrogen is incorporated into the second substrate layer portion.

[0055] In some embodiments, performing a doping process on a portion of the second substrate layer includes implanting impurity atoms (or impurity ions) into the portion of the second substrate layer. Here, the impurity atoms (or impurity ions) include at least one atom (or ion) selected from argon, oxygen, hydrogen, helium, germanium, boron, phosphorus, carbon, and nitrogen.

[0056] Here, by performing doping on the second substrate layer portion but not on the first substrate layer portion, the etching selectivity ratio of the second substrate layer portion and the first substrate layer portion can be changed, which facilitates the subsequent removal of at least a portion of the second substrate layer portion by etching process while retaining the first substrate layer portion.

[0057] In step S106, an electrode connected to the channel layer is formed on the doped second substrate layer portion, with the electrode located between the first and second portions of the first sacrificial layer.

[0058] In some embodiments, the electrode includes a source and / or a drain. For example, at least one of the source and drain is located between a first portion and a second portion of the first sacrificial layer. That is, the source or drain is located between a first portion and a second portion of the first sacrificial layer, or the source and drain are located between a first portion and a second portion of the first sacrificial layer, respectively.

[0059] In step S108, after the electrode is formed, a gate structure is formed on the channel layer.

[0060] In some embodiments, forming a gate structure on the channel layer includes forming a gate structure surrounding the channel layer. For example, the gate structure includes a gate insulating layer surrounding the channel layer and a gate layer surrounding the gate insulating layer. This can improve gate control capability.

[0061] In step S110, an etching process is performed on the semiconductor structure after the gate structure is formed to form a first portion and a second portion exposing the first sacrificial layer and an opening for the electrode.

[0062] In step S112, the first and second portions of the first sacrificial layer and the second substrate layer portion are removed through the opening to form a first void.

[0063] In other words, by forming an opening that exposes the first and second portions of the first sacrificial layer and the electrode, the first and second portions of the first sacrificial layer and the second substrate layer portion can be easily removed, thus forming a first void.

[0064] It should be noted that removing the second substrate layer portion through the opening here refers to removing the exposed second substrate layer portion after removing the first and second portions of the first sacrificial layer; that is, removing at least a portion of the entire second substrate layer portion. In step S114, a contact component surrounding the electrode is formed in the first gap.

[0065] In the preceding steps, since the first and second portions of the first sacrificial layer around the electrode and the second substrate layer portion are all removed, the surface of the electrode is exposed by the first void, so that a contact component that fully surrounds the electrode can be formed in the first void.

[0066] Thus, a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is provided. The method includes: providing a semiconductor structure, the semiconductor structure including a substrate structure and one or more substructures on the substrate structure, the substructures including a substrate layer and a first sacrificial layer on the substrate structure and a channel structure on the substrate layer, wherein the first sacrificial layer includes a first portion on a first side of the substrate layer and a second portion on a second side of the substrate layer, the first side opposite to the second side, the substrate layer including a first substrate layer portion covered by the channel structure and a second substrate layer portion not covered by the channel structure, the channel structure including a channel layer; performing a doping process on the second substrate layer portion; forming an electrode connected to the channel layer on the doped second substrate layer portion, the electrode being located between the first and second portions of the first sacrificial layer; after forming the electrode, forming a gate structure on the channel layer; performing an etching process on the semiconductor structure after forming the gate structure to form an opening exposing the first and second portions of the first sacrificial layer and the electrode; removing the first and second portions of the first sacrificial layer and the second substrate layer portion through the opening to form a first void; and forming a contact member surrounding the electrode in the first void. In this manufacturing method, by providing a first sacrificial layer, an electrode can be grown within a confined space between a first portion and a second portion of the first sacrificial layer. This allows for a smaller contact component size during the formation of the contact component surrounding the electrode. Furthermore, after removing the first and second portions of the first sacrificial layer and the second substrate layer portion, the electrode surface is exposed by a first gap, allowing the formation of a contact component that fully surrounds the electrode within this gap. In other words, the contact component completely surrounds (or completely encircles) the electrode. Therefore, the above manufacturing method achieves the goal of reducing both the size of the contact component and the contact resistance between the electrode and the contact component, thereby improving the device performance of the semiconductor device.

[0067] It should be noted that the above electrodes include source and / or drain electrodes. That is, in the above manufacturing method, a contact component that completely surrounds the source electrode can be formed, or a contact component that completely surrounds the drain electrode can be formed, or a contact component that completely surrounds both the source and drain electrodes can be formed.

[0068] In some embodiments, the width of the opening in one direction is greater than the sum of the widths of the first and second portions of the first sacrificial layer and the electrode in that direction, wherein the direction is either from the first portion of the first sacrificial layer to the second portion of the first sacrificial layer or from the second portion of the first sacrificial layer to the first portion of the first sacrificial layer. In this embodiment, by making the width of the opening greater than the sum of the widths of the first and second portions of the first sacrificial layer and the electrode, it is convenient to sufficiently remove the first and second portions of the first sacrificial layer and the second substrate layer portion around the electrode, thereby fully exposing the surface of the electrode, which facilitates the formation of a contact component that fully surrounds the electrode.

[0069] In some embodiments, the first sacrificial layer further includes a third portion on a third side of the substrate layer, wherein the third side is adjacent to the first side and the second side, respectively. The one or more substructures include a first substructure and a second substructure, wherein the third portions of the first sacrificial layer in the first substructure and the third portions of the first sacrificial layer in the second substructure are located between the channel structure in the first substructure and the channel structure in the second substructure, and the third portions of the first sacrificial layer in the first substructure are spaced apart from the channel structure in the first substructure to form a second gap, and the third portions of the first sacrificial layer in the second substructure are spaced apart from the channel structure in the second substructure to form a third gap.

[0070] Based on this, forming an electrode connected to the channel layer may include: forming a first electrode in the second gap and on the second substrate layer portion of the substrate layer in the first substructure, and forming a second electrode in the third gap and on the second substrate layer portion of the substrate layer in the second substructure, wherein the first electrode is connected to the channel layer in the first substructure, and the second electrode is connected to the channel layer in the second substructure.

[0071] In the above embodiment, a first electrode is formed in a second gap in the first substructure, and a second electrode is formed in a third gap in the second substructure. Therefore, the growth of the first electrode is restricted by the third part of the first sacrificial layer in the first substructure, and the growth of the second electrode is restricted by the third part of the first sacrificial layer in the second substructure. This can reduce the risk of the first electrode and the second electrode merging.

[0072] In some embodiments, the substrate structure includes a semiconductor substrate and a trench isolation structure within the semiconductor substrate. The semiconductor substrate includes a first region and a second region separated by the trench isolation structure. For example, the conductivity type of the first region is different from that of the second region. For example, an NMOS (N-channel Metal-Oxide-Semiconductor) transistor can be formed on the first region, and a PMOS (P-channel Metal-Oxide-Semiconductor) transistor can be formed on the second region. The first substructure is located on the first region, and the second substructure is located on the second region. That is, the two substructures are located in different regions. Therefore, by using the third portion of the first sacrificial layer in the two substructures to restrict the growth of the electrodes, the risk of merging of the two electrodes formed in different regions can be reduced.

[0073] Figures 2A to 20B This is a schematic cross-sectional view showing the structure of several stages in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure, taken along a first or second direction.

[0074] It should be noted that, in this disclosure, the first direction is the extension direction of the channel formed by the semiconductor device, that is, the direction from the source to the drain or from the drain to the source of the semiconductor device; the second direction is the direction perpendicular to the first direction, that is, the direction perpendicular to the extension direction of the channel. Furthermore, it should be noted that the cross-sectional schematic diagram of the structure taken along the second direction in the accompanying drawings is a cross-sectional schematic diagram taken at the source and / or drain positions along the second direction.

[0075] The following is combined with Figures 2A to 20B The manufacturing process of a semiconductor device according to some embodiments of the present disclosure is described in detail.

[0076] First, we provide the semiconductor structure. The following section combines... Figures 2A to 9B Describe in detail the process of forming a semiconductor structure.

[0077] like Figure 2A and Figure 2B As shown, a substrate layer 112 is formed on a semiconductor substrate 111. For example, the substrate layer 112 can be formed on the semiconductor substrate 111 by processes such as epitaxial growth or deposition. For example, the material of the semiconductor substrate 111 includes semiconductor materials such as silicon. For example, the material of the substrate layer 112 may include semiconductor materials such as GeSi (germanium silicon). Of course, those skilled in the art will understand that the scope of the embodiments of this disclosure is not limited to the semiconductor substrates and substrate layer materials disclosed herein.

[0078] For example, in the germanium-silicon substrate, the germanium content can be 50% to 60%. Of course, the germanium content in the substrate is merely exemplary, and the scope of this disclosure is not limited thereto.

[0079] In some embodiments, such as Figure 2A and Figure 2B As shown, the semiconductor substrate 111 includes a first region 111a and a second region 111b. For example, the conductivity type of the first region 111a is different from that of the second region 111b. For example, an NMOS transistor can be formed on the first region 111a, and a PMOS transistor can be formed on the second region 111b.

[0080] Next, one or more stacked structures 120 are formed on the substrate 112, each stacked structure 120 including a second sacrificial layer 121 and a channel layer 122 on the second sacrificial layer 121.

[0081] For example, the second sacrificial layer 121 and the channel layer 122 can be alternately formed on the substrate layer 112 using an epitaxial process. That is, the second sacrificial layer 121 is first formed on the substrate layer 112, then the channel layer 122 is formed on the second sacrificial layer 121, and then the second sacrificial layer 121 is formed on the channel layer 122, and so on. For example, Figure 2A and Figure 2B Three stacked structures 120 are shown. Of course, those skilled in the art will understand that more or fewer stacked structures can be formed. In some embodiments, the material of the second sacrificial layer 121 comprises germanium-silicon, and the material of the channel layer 122 comprises silicon. Of course, those skilled in the art will understand that the scope of the embodiments disclosed herein is not limited to the materials of the second sacrificial layer and the channel layer disclosed herein.

[0082] For example, the germanium content in the second sacrificial layer 121 differs from the germanium content in the substrate layer 112, allowing the second sacrificial layer and the substrate layer to have different etching selectivity ratios. Specifically, the germanium content in the second sacrificial layer 121 is 30%. Of course, the germanium content in the second sacrificial layer is merely exemplary, and the scope of this disclosure is not limited thereto.

[0083] Next, as Figure 3A and Figure 3B As shown, for example, etching can be performed on the one or more stacked structures 120 and the semiconductor substrate 111 to form one or more fins by patterning processes such as SADP (Self-aligned Double Exposure), SAQP (Self-aligned Quadruple Exposure), or LELE (Lens-Etching-Lens-Etching), etc., with trenches 201 formed around each fin.

[0084] Next, as Figure 4A and Figure 4BAs shown, a trench isolation structure 200 is formed in the trench 201. For example, the trench isolation structure 200 includes a second insulating layer 202 on the side of the trench 201 and a third insulating layer 203 filled in the trench 201. For example, the material of the second insulating layer 202 includes silicon nitride, and the material of the third insulating layer 203 includes silicon oxide, etc.

[0085] Next, a first insulating layer 205 is formed on the surface (i.e., the upper surface and the side surface) of the one or more stacked structures 120. For example, the material of the first insulating layer 205 includes silicon oxide, etc.

[0086] Next, a first sacrificial layer 210 is formed on the surface of the first insulating layer 205 using a deposition process. Optionally, the first sacrificial layer 210 can also be formed on the trench isolation structure 200.

[0087] In some embodiments, the material of the first sacrificial layer 210 includes one or more of the following: tungsten nitride, tungsten carbide, titanium nitride, titanium oxide, aluminum oxide, tungsten oxide, silicon carbide, tantalum nitride, tantalum oxide, carbon-containing silicon nitride, carbon-containing silicon oxide, oxygen-containing silicon nitride, and doped silicon oxide. For example, doped silicon oxide includes: boron phosphorus silicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), or borosilicate glass (BSG), etc. Of course, those skilled in the art will understand that the material of the first sacrificial layer is merely exemplary, and the scope of this disclosure is not limited thereto.

[0088] As an example, the thickness of the first sacrificial layer 210 ranges from 1 nanometer to 10 nanometers. This disclosure is not limited thereto.

[0089] Next, as Figure 5A and Figure 5B As shown, for example, using an ICP (Inductively Coupled Plasma) process, the first sacrificial layer 210 is etched to remove a portion of the first sacrificial layer 210, leaving another portion of the first sacrificial layer 210 on the side surface of the first insulating layer 205. Here, this other portion of the first sacrificial layer 210 is vertically positioned on the trench isolation structure. That is, in this step, the remaining portion of the first sacrificial layer 210, excluding the portion on the side surface of the first insulating layer 205, is removed, thereby forming a structure as shown in the diagram. Figure 5A and Figure 5B The structure shown.

[0090] like Figure 5B As shown, the first sacrificial layer 210 includes a first portion 211 on a first side of the substrate layer 112 and a second portion 212 on a second side of the substrate layer 112, with the first side and the second side opposite to each other. Optionally, as... Figure 5A As shown, the first sacrificial layer 210 may further include a third portion 213 on the third side of the substrate layer 112, wherein the third side is adjacent to the first side and the second side, respectively.

[0091] Next, a dummy gate structure is formed on the first insulating layer 205. For example, as... Figure 6A and Figure 6B As shown, in Figure 5A and Figure 5B The structure shown sequentially forms a dummy gate layer (which may be called the first dummy gate layer) 311, a fourth insulating layer 312, a fifth insulating layer 313, a sixth insulating layer 314, a dummy gate layer (which may be called the second dummy gate layer) 315, and a seventh insulating layer 316. For example, the materials of the fourth insulating layer 312, the sixth insulating layer 314, and the seventh insulating layer 316 include silicon oxide, etc.; the materials of the dummy gate layers 311 and 315 include amorphous silicon, etc.; and the material of the fifth insulating layer 313 includes silicon nitride, etc. Then, as... Figure 7A and Figure 7B As shown, the first dummy gate layer 311, the fourth insulating layer 312, the fifth insulating layer 313, the sixth insulating layer 314, the second dummy gate layer 315, and the seventh insulating layer 316 are patterned using photolithography and etching processes, and then the second dummy gate layer 315 and the seventh insulating layer 316 are removed. Next, as... Figure 8 As shown, a hard mask layer 321 is formed by a deposition process. For example, the material of the hard mask layer 321 includes silicon nitride. Thus, dummy gate structures 310a and / or 310b are formed on the first insulating layer 205. The dummy gate structure includes a dummy gate layer 311. This dummy gate structure may also include a fourth insulating layer 312, a fifth insulating layer 313, a sixth insulating layer 314, and the hard mask layer 321.

[0092] Next, as Figure 9A and Figure 9B As shown, using dummy gate structures 310a and / or 310b as masks, one or more stacked structures 120 are etched to form a channel structure 710. The channel structure 710 includes a channel layer 122 and a second sacrificial layer 121.

[0093] This forms a semiconductor structure. The semiconductor structure includes a substrate structure and one or more substructures on the substrate structure. The substrate structure includes a semiconductor substrate 111 and a trench isolation structure 200 in the semiconductor substrate 111, wherein the semiconductor substrate 111 includes a first region 111a and a second region 111b separated by the trench isolation structure 200. Each substructure includes a substrate layer 112 and a first sacrificial layer 210 on the substrate structure, and a channel structure 710 on the substrate layer. Figure 9B As shown, the first sacrificial layer 210 includes a first portion 211 on a first side of the substrate layer 112 and a second portion 212 on a second side of the substrate layer 112, with the first side opposite to the second side. The substrate layer 112 includes a first substrate layer portion 112a covered by the channel structure and a second substrate layer portion 112b not covered by the channel structure.

[0094] Optionally, the first sacrificial layer 210 may further include a third portion 213 on a third side of the substrate layer 112, wherein the third side is adjacent to both the first side and the second side. The one or more substructures include a first substructure 410a and a second substructure 410b, the first substructure 410a being located on a first region 111a and the second substructure 410b being located on a second region 111b. The third portion 213 of the first sacrificial layer 210 in the first substructure 410a and the third portion 213 of the first sacrificial layer 210 in the second substructure 410b are located between the channel structure in the first substructure 410a and the channel structure in the second substructure 410b. The third portion 213 of the first sacrificial layer 210 in the first substructure 410a is spaced apart from the channel structure in the first substructure 410a to form a second void 412, and the third portion 213 of the first sacrificial layer 210 in the second substructure 410b is spaced apart from the channel structure in the second substructure 410b to form a third void 413.

[0095] In some embodiments, the channel layer on different regions of the semiconductor substrate may be doped with corresponding conductivity types as needed.

[0096] Next, as Figure 10A and Figure 10B As shown, a doping process is performed on the second substrate layer portion 112b. For example, impurity atoms (or impurity ions) may be implanted into the second substrate layer portion to perform the doping process, wherein the impurity atoms (or impurity ions) include at least one atom (or ion) selected from argon, oxygen, hydrogen, helium, germanium, boron, phosphorus, carbon, and nitrogen.

[0097] Here, by performing doping treatment on the second substrate layer portion but not on the first substrate layer portion, the etching selectivity ratio of the second substrate layer portion and the first substrate layer portion can be changed, making it easier to remove the second substrate layer portion while retaining the first substrate layer portion through subsequent etching processes.

[0098] Next, optionally, such as Figure 11 As shown, for example, the second sacrificial layer 121 is etched by an etching process to cause the second sacrificial layer 121 to retract, thereby forming a recess 421.

[0099] Next, optionally, such as Figure 12 As shown, for example, a spacer layer 422 filling the depression 421 can be formed by deposition and etching processes. For example, the material of the spacer layer 422 includes a low-k material (a material with a low dielectric constant).

[0100] Next, as Figure 13A and Figure 13B As shown, electrodes connected to the channel layer 122 are formed on the doped second substrate layer portion 112b using an epitaxial process. Figure 13A As shown, the electrodes include a first electrode 510 and a second electrode 520. The first electrode 510 includes a first sub-electrode 511 and a second sub-electrode 512. The first sub-electrode 511 is the source, and the second sub-electrode 512 is the drain; or, the first sub-electrode 511 is the drain, and the second sub-electrode 512 is the source. The second electrode 520 includes a third sub-electrode 521 and a fourth sub-electrode 522. The third sub-electrode 521 is the source, and the fourth sub-electrode 522 is the drain; or, the third sub-electrode 521 is the drain, and the fourth sub-electrode 522 is the source.

[0101] For example, a structure covering the second region 111b with a first mask layer can be used to form a first sub-electrode 511 and a second sub-electrode 512 connected to the channel layer 122 in the first substructure 410a through an epitaxial growth process. For example, the material of the first mask layer may include a photoresist, etc. Then, the first mask layer is removed. Next, a structure covering the first region 111a with a second mask layer can be used to form a third sub-electrode 521 and a fourth sub-electrode 522 connected to the channel layer 122 in the second substructure 410b through an epitaxial growth process. For example, the material of the second mask layer may include a photoresist, etc. Then, the second mask layer is removed. In this way, a structure is formed as shown... Figure 13A and Figure 13B The structure shown.

[0102] like Figure 13BAs shown, the first electrode 510 is located between a first portion 211 and a second portion 212 of the first sacrificial layer 210, and the second electrode 520 is located between another first portion 211 and another second portion 212 of the first sacrificial layer 210. This achieves constrained growth of the electrode in a direction perpendicular to the extension direction of the channel, i.e., constrained growth in the second direction, to facilitate a reduction in the size of the contact components of the subsequently formed fully enclosed electrode.

[0103] Furthermore, such as Figure 13A As shown, a first electrode 510 (e.g., a first sub-electrode 511) is formed in the second gap 412 and on the second substrate layer portion 112b of the substrate layer in the first substructure 410a, and a second electrode 520 (e.g., a third sub-electrode 521) is formed in the third gap 413 and on the second substrate layer portion 112b of the substrate layer in the second substructure 410b. The first electrode 510 is connected to the channel layer 122 in the first substructure 410a, and the second electrode 520 is connected to the channel layer 122 in the second substructure 410b. Thus, the growth of the first electrode 510 (e.g., the first sub-electrode 511) is limited by the third portion 213 of the first sacrificial layer in the first substructure 410a, and the growth of the second electrode 520 (e.g., the third sub-electrode 521) is limited by the third portion 213 of the first sacrificial layer in the second substructure 410b. This reduces the risk of merging of the first and second electrodes, thereby preventing electrode merging of transistors formed in different regions.

[0104] Next, after forming the electrodes, a gate structure is formed on the channel layer. The following section combines... Figures 14A to 15 Describe the process of forming the gate structure.

[0105] like Figure 14A and Figure 14B As shown, a first dielectric layer 440 is formed on the semiconductor structure after the electrodes are formed. This first dielectric layer 440 is an interlayer dielectric layer. For example, this interlayer dielectric layer is formed by a deposition process.

[0106] Then, a portion of the first dielectric layer 440 and a portion of the dummy gate structure are removed to expose the dummy gate layer. For example, chemical mechanical polishing is performed on the first dielectric layer 440 and the dummy gate structures 310a and 310b to expose the dummy gate layer 311.

[0107] Next, for example, the dummy gate layer 311 and the second sacrificial layer 121 are removed by an etching process to expose the channel layer 122.

[0108] Next, as Figure 15As shown, for example, a gate insulating layer 611 surrounding the channel layer 122 and a gate layer 612 on the gate insulating layer 611 are formed by deposition and chemical mechanical polishing processes. For example, the gate layer 612 surrounds the gate insulating layer 611. For example, the gate insulating layer 611 includes silicon oxide and / or a high dielectric constant dielectric layer. For example, the gate layer 612 includes a work function layer and a metal layer. For example, the material of the work function layer includes titanium nitride, tantalum nitride, etc., and the material of the metal layer includes tungsten, etc. Of course, the configuration of the gate layer is not limited to the above description based on the transistor type and electrical threshold requirements, and this disclosure does not limit it. In this way, a gate structure is formed, which includes a gate insulating layer 611 and a gate layer 612.

[0109] Next, an etching process is performed on the semiconductor structure after the gate structure is formed to form a first portion and a second portion exposing the first sacrificial layer, as well as openings for the electrodes. The following section combines... Figures 16A to 17B Describe in detail the process by which the opening is formed.

[0110] like Figure 16A and Figure 16B As shown, for example, a second dielectric layer 620 is formed on the semiconductor structure after the gate structure is formed by a deposition process. For example, the second dielectric layer 620 includes at least one of an eighth insulating layer 621 and a ninth insulating layer 622. For example, the material of the eighth insulating layer 621 includes silicon nitride, and the material of the ninth insulating layer 622 includes silicon oxide, etc.

[0111] Then, as Figure 17A and Figure 17B As shown, for example, the second dielectric layer 620 and the first dielectric layer 440 are etched by processes such as photolithography and etching to form an opening 630 that exposes the first portion 211 and the second portion 212 of the first sacrificial layer 210 and exposes the electrodes 510 and 520.

[0112] In some embodiments, such as Figure 17B As shown, the width W1 of the opening 630 in one direction is greater than the sum of the widths of the first portion 211 and the second portion 212 of the first sacrificial layer 210 and the electrode 510 (or 520) in that direction. Here, the aforementioned direction is either from the first portion 211 of the first sacrificial layer to the second portion 212 of the first sacrificial layer or from the second portion 212 of the first sacrificial layer to the first portion 211 of the first sacrificial layer, which is also the second direction mentioned above.

[0113] In the above embodiments, by making the width of the opening greater than the sum of the width of the first and second portions of the first sacrificial layer and the electrode, it is convenient to fully remove the first and second portions of the first sacrificial layer and the second substrate layer portion around the electrode, thereby fully exposing the surface of the electrode, which facilitates the subsequent formation of a contact component that fully surrounds the electrode.

[0114] Next, as Figure 18A and Figure 18B As shown, for example, by using an etching process, the first portion 211 and the second portion 212 of the first sacrificial layer 210 and the second substrate layer portion 112b are removed through the opening 630 to form the first void 635.

[0115] Next, a contact component surrounding the electrode is formed in the first gap 635. (The following is in conjunction with...) Figures 19A to 20B Describe in detail the process of forming the contact components.

[0116] Alternatively, for example, such as Figure 19A and Figure 19B As shown, a first conductive layer 641 surrounding the electrode can be formed on the surface of the electrode via the first void 635 through a deposition process (e.g., chemical vapor deposition, CVD, etc.). For example, the first conductive layer 641 may include a metal such as titanium (Ti). Optionally, after forming the first conductive layer 641, an annealing process can be performed. Annealing the first conductive layer can reduce the contact resistance.

[0117] Then, as Figure 20A and Figure 20B As shown, for example, a second conductive layer 642 is formed in the first void 635 by a deposition process to fill the first void. For example, the material of the second conductive layer includes metals such as tungsten, cobalt, copper, ruthenium, or molybdenum. This second conductive layer 642 surrounds the surface of the first conductive layer 641. This forms a contact member 640 surrounding electrodes 510 and 520. The contact member 640 includes the first conductive layer 641 and the second conductive layer 642.

[0118] In other embodiments, instead of forming the first conductive layer 641, a second conductive layer 642 surrounding the electrode may be formed directly on the surface of the electrode. In this case, the contact component includes the second conductive layer 642.

[0119] In other embodiments, the first conductive layer 641 can be used to fill the gap below the electrode, and then a second conductive layer 642 connected to the first conductive layer 641 can be formed, which can fill the remaining gap portion of the first gap 635.

[0120] Therefore, a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is provided. In this manufacturing method, by providing a first sacrificial layer, an electrode can be grown between a first portion and a second portion of the first sacrificial layer, thus allowing for a relatively small size of the contact component during the formation of the contact component surrounding the electrode. Furthermore, in this manufacturing method, after removing the first and second portions of the first sacrificial layer and the second substrate layer portion, the surface of the electrode is exposed by a first gap, allowing the formation of a contact component that fully surrounds the electrode within the first gap. That is, the contact component fully surrounds the electrode. Therefore, the above manufacturing method can reduce both the size of the contact component and the contact resistance between the electrode and the contact component, thereby improving the device performance of the semiconductor device. The above manufacturing method has a simple process flow, is compatible with the process flow of multi-channel field-effect transistors, and has relatively low technical difficulty in implementation.

[0121] Furthermore, in the above manufacturing method, the first sacrificial layer also includes a third portion on the third side of the substrate layer. In this way, during the growth of electrodes in different regions of the transistor, the growth of electrodes in different regions is restricted by the third portion of the first sacrificial layer in the first direction, which can reduce the risk of electrodes in different regions merging.

[0122] It should be noted that the third part 213 of the first sacrificial layer mentioned above was not removed, but retained as shown in the figure. Figure 20A In the semiconductor device shown.

[0123] Additionally, it should be noted that, Figures 2A to 20B The process of forming contact components that fully surround electrodes 512 and 522 is shown; however, in practice, contact components that fully surround other electrodes (e.g., electrodes 511 and 521, etc.) can also be formed according to the manufacturing method described above. Therefore, the scope of this disclosure is not limited. Figures 2A to 20B The manufacturing process is shown in the figure.

[0124] Figures 21A to 25B This is a schematic cross-sectional view showing the structure of several stages in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure, taken along a first or second direction. Figures 21A to 25B Describes the formation of gate structures (such as Figure 15 The manufacturing process of the semiconductor device (as shown in the figure).

[0125] like Figure 21A and Figure 21B As shown, the semiconductor structure after the gate structure is formed (e.g.) Figure 15 An interconnect layer 625 is formed on the semiconductor structure shown. For example, it can be formed by a deposition process, such as... Figure 15An eighth insulating layer 621 is formed on the semiconductor structure shown; then, an interconnect layer 625 is formed on the eighth insulating layer 621. This interconnect layer 625 includes multiple interconnected metal layers, etc. Here, this interconnect layer can be formed using a back-end-of-line (BEOL) process.

[0126] Next, an etching process is performed on the semiconductor structure after the gate structure is formed to form a first portion and a second portion exposing the first sacrificial layer, as well as openings for the electrodes. The following section combines... Figures 22A to 23B Describe in detail the process of opening formation.

[0127] For example, such as Figure 22A and Figure 22B As shown, the substrate structure is thinned on the back side of the semiconductor structure. For example, using a wafer flipping process, the substrate structure is thinned as follows: Figure 21A and Figure 21B The semiconductor structure shown is flipped; then the semiconductor substrate 111 is thinned from the back side of the semiconductor substrate 111 in the substrate structure.

[0128] Then, an etching process is performed on the thinned substrate structure to form an opening 630' on the back side of the semiconductor structure, exposing the first portion 211 and the second portion 212 of the first sacrificial layer 210 and the electrode 510 (or 520).

[0129] For example, such as Figure 23A and Figure 23B As shown, a third dielectric layer 700 is formed on the back side of the semiconductor structure and on the thinned substrate structure. For example, the third dielectric layer 700 includes at least one of a tenth insulating layer 701 and an eleventh insulating layer 702. For example, the material of the tenth insulating layer 701 includes silicon nitride, and the material of the eleventh insulating layer 702 includes silicon oxide, etc. Then, using photolithography and etching processes, etching is performed on the third dielectric layer 700 and the substrate structure to form an opening 630'. This opening 630' exposes a first portion 211 and a second portion 212 of the first sacrificial layer 210 and an electrode 510 (or 520).

[0130] Next, as Figure 24A and Figure 24B As shown, for example, by using an etching process, the first portion 211 and the second portion 212 of the first sacrificial layer 210 and the second substrate layer portion 112b are removed through the opening 630' to form the first void 635'.

[0131] Next, a contact component surrounding the electrode is formed in the first gap.

[0132] Alternatively, for example, such as Figure 25A and Figure 25B As shown, a first conductive layer 641 surrounding the electrode can be formed on the surface of the electrode via a deposition process (e.g., atomic layer deposition (ALD)). For example, the first conductive layer 641 may include a metal such as titanium (Ti). Optionally, an annealing process can be performed after the first conductive layer 641 is formed. Annealing the first conductive layer can reduce the contact resistance.

[0133] Then, a second conductive layer 642 is formed in the first void 635' by a deposition process to fill the first void. For example, the material of the second conductive layer includes metals such as tungsten, cobalt, copper, ruthenium, or molybdenum. The second conductive layer 642 surrounds the surface of the first conductive layer 641. This forms a contact member 640 surrounding electrodes 510 and 520. The contact member 640 includes the first conductive layer 641 and the second conductive layer 642.

[0134] In other embodiments, instead of forming the first conductive layer 641, a second conductive layer 642 surrounding the electrode may be formed directly on the surface of the electrode. In this case, the contact component includes the second conductive layer 642.

[0135] In other embodiments, the first conductive layer 641 can also be used to cover the gap below the electrode (e.g. Figure 24A and Figure 24B (as shown) is filled, and then a second conductive layer 642 connected to the first conductive layer 641 is formed. The second conductive layer 642 can fill the remaining gap portion of the first gap.

[0136] Thus, a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is provided. This manufacturing method employs Back Side AllAround Contact (BSAAC) technology.

[0137] The aforementioned manufacturing method can form a contact component that fully surrounds the electrode, and the size of this contact component can be relatively small. Therefore, it is possible to reduce the size of the contact component while simultaneously reducing the contact resistance between the electrode and the contact component, thereby improving the device performance of the semiconductor device. Furthermore, the aforementioned manufacturing method can reduce the risk of electrode merging in different regions. The process flow of the aforementioned manufacturing method is simple, compatible with the process flow of multi-channel field-effect transistors, and has relatively low technical difficulty.

[0138] It should be noted that the third part 213 of the first sacrificial layer mentioned above was not removed, but retained as shown in the figure. Figure 25A In the semiconductor device shown.

[0139] Additionally, it should be noted that, Figures 2A to 15 as well as Figures 21A to 25B The process of forming contact components that fully surround electrodes 512 and 522 is shown; however, in practice, contact components that fully surround other electrodes (e.g., electrodes 511 and 521, etc.) can also be formed according to the manufacturing method described above. Therefore, the scope of this disclosure is not limited. Figures 2A to 15 as well as Figures 21A to 25B The manufacturing process is shown in the figure.

[0140] In summary, the embodiments of this disclosure employ a strategy of reserving a sacrificial layer at the epitaxial location of the source / drain, thereby limiting the growth space of the source / drain in multiple directions. This not only achieves isolation between electrodes in different regions in the first direction, preventing the risk of electrode merging, but also allows the source / drain to grow in a limited manner in the second direction, realizing a small-sized, four-sided surrounding contact component for the source / drain, resulting in lower contact resistance than contact components in related technologies. Furthermore, this disclosure can also achieve a fully surrounding contact technology on the back side. The process flow of this disclosure is simple, compatible with the process flow of multi-channel field-effect transistors, and has relatively low technical difficulty.

[0141] Based on the above manufacturing method, a semiconductor device has been developed. The following section combines... Figure 20A and Figure 20B (or Figure 25A and Figure 25B The structure of this semiconductor device will be described in detail here. Figure 20A and Figure 20B This illustrates the structure of the contact components on the front side of the semiconductor device, namely the contact components and the interconnect layer ( Figure 20A and Figure 20B (Not shown) On the same side of the source / drain; Figure 25A and Figure 25B The structure of the contact components on the back side of the semiconductor device (using BSAAC technology) is shown, where the contact components and the interconnect layer are located on different sides of the source / drain.

[0142] like Figure 20A and Figure 20B (or Figure 25A and Figure 25B As shown, the semiconductor device includes a substrate structure. The substrate structure includes a semiconductor substrate 111 and a trench isolation structure 200 within the semiconductor substrate. The semiconductor substrate 111 includes a first region 111a and a second region 111b separated by the trench isolation structure 200. For example, the conductivity type of the first region 111a is different from that of the second region 111b.

[0143] like Figure 20A and Figure 20B (or Figure 25A and Figure 25BAs shown, the semiconductor device also includes one or more substructures on a substrate structure. The one or more substructures include a first substructure 410a and a second substructure 410b. The first substructure 410a is located on a first region 111a, and the second substructure 410b is located on a second region 111b. Each substructure includes a substrate layer 112 and a sacrificial layer (i.e., the previously described first sacrificial layer) 210 on the substrate structure, and a channel structure 710 on the substrate layer 112. The sacrificial layer 210 is located on a trench isolation structure 200. The sacrificial layer 210 in the first substructure 410a (i.e., the third portion 213 of the previously described sacrificial layer) and the sacrificial layer 210 in the second substructure 410b (i.e., the third portion 213 of the previously described sacrificial layer) are located between the channel structure in the first substructure 410a and the channel structure in the second substructure 410b. The channel structure 710 includes a channel layer 122.

[0144] like Figure 20A and Figure 20B (or Figure 25A and Figure 25B As shown, the semiconductor device also includes electrodes connected to the channel layer 122. For example, the electrode may be a source and / or a drain. As another example, the electrodes include a first electrode 510 and a second electrode 520. The first electrode 510 includes a first sub-electrode 511 and a second sub-electrode 512. The first sub-electrode 511 is the source, and the second sub-electrode 512 is the drain; or, the first sub-electrode 511 is the drain, and the second sub-electrode 512 is the source. The second electrode 520 includes a third sub-electrode 521 and a fourth sub-electrode 522. The third sub-electrode 521 is the source, and the fourth sub-electrode 522 is the drain; or, the third sub-electrode 521 is the drain, and the fourth sub-electrode 522 is the source.

[0145] like Figure 20A and Figure 20B (or Figure 25A and Figure 25B As shown, the semiconductor device also includes a gate structure on the channel layer 122. For example, the gate structure includes a gate insulating layer 611 surrounding the channel layer 122 and a gate layer 612 on the gate insulating layer 611. For example, the gate layer 612 surrounds the gate insulating layer 611.

[0146] like Figure 20A and Figure 20B (or Figure 25A and Figure 25BAs shown, the semiconductor device also includes a contact member 640 connected to the electrode. For example, the contact member 640 is a fully enclosed contact member, that is, the contact member surrounds the electrode. For example, the contact member 640 includes a first conductive layer 641 surrounding the electrode and a second conductive layer 642 surrounding the surface of the first conductive layer 641. As another example, the contact member 640 includes a second conductive layer 642 that directly surrounds the electrode.

[0147] Thus, a semiconductor device according to some embodiments of the present disclosure is provided. This semiconductor device can reduce the size of the contact components while also reducing the contact resistance between the electrodes and the contact components, thereby improving the device performance of the semiconductor device and reducing the risk of electrode merging in different regions.

[0148] In some embodiments, the thickness of the sacrificial layer 210 ranges from 1 nanometer to 10 nanometers.

[0149] In some embodiments, the material of the sacrificial layer 210 includes one or more of the following: tungsten nitride, tungsten carbide, titanium nitride, titanium oxide, aluminum oxide, tungsten oxide, silicon carbide, tantalum nitride, tantalum oxide, carbon-containing silicon nitride, carbon-containing silicon oxide, oxygen-containing silicon nitride, and doped silicon oxide. For example, doped silicon oxide includes borosilicate glass, fluorine-doped silicate glass, phosphosilicate glass, or boron-doped silicate glass.

[0150] Figures 26A to 35B This is a cross-sectional schematic diagram showing the structure of several stages in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure, taken along a first or second direction. The following is in conjunction with... Figures 26A to 35B The manufacturing process of a semiconductor device according to some embodiments of the present disclosure is described in detail.

[0151] First, such as Figure 26A and Figure 26B As shown, a substrate layer 112 is formed on a semiconductor substrate 111. For example, the material of the semiconductor substrate 111 includes semiconductor materials such as silicon. For example, the material of the substrate layer 112 may include semiconductor materials such as GeSi (germanium silicon). For example, in the germanium silicon material of the substrate layer, the germanium content may be 30%. Of course, the germanium content in the substrate layer is merely exemplary, and the scope of this disclosure is not limited thereto.

[0152] In some embodiments, such as Figure 26A and Figure 26B As shown, the semiconductor substrate 111 includes a first region 111a and a second region 111b. For example, the conductivity type of the first region 111a is different from that of the second region 111b.

[0153] Next, for example, a channel layer 122 is formed on the substrate layer 112 by an epitaxial process. For example, the material of the channel layer 122 includes semiconductor materials such as silicon.

[0154] Next, as Figure 27A and Figure 27B As shown, etching is performed on the channel layer 122 and the semiconductor substrate 111 to form one or more fins, with a trench 201 formed around each fin.

[0155] Next, as Figure 28A and Figure 28B As shown, a trench isolation structure 200 is formed in the trench 201. The structure of the trench isolation structure 200 can be referred to the previous description.

[0156] Next, a first insulating layer 205 is formed on the surface (i.e., the upper surface and the side surface) of the channel layer 122. For example, the material of the first insulating layer 205 includes silicon oxide, etc.

[0157] Next, a sacrificial layer (i.e., the first sacrificial layer) 210 is formed on the side surface of the first insulating layer 205 using processes such as deposition and ICP. The material and thickness of the sacrificial layer 210 can be referred to the preceding description.

[0158] like Figure 28B As shown, the sacrificial layer 210 includes a first portion 211 on a first side of the substrate layer 112 and a second portion 212 on a second side of the substrate layer 112, with the first side opposite to the second side. Optionally, as... Figure 28A As shown, the sacrificial layer 210 may further include a third portion 213 on a third side of the substrate layer 112, wherein the third side is adjacent to the first side and the second side, respectively.

[0159] Next, as Figure 29 As shown, dummy gate structures 310a and / or 310b are formed on the first insulating layer 205. The dummy gate structure includes a dummy gate layer 311. The dummy gate structure may also include a fourth insulating layer 312, a fifth insulating layer 313, a sixth insulating layer 314, and a hard mask layer 321, etc.

[0160] Next, as Figure 30A and Figure 30B As shown, using dummy gate structures 310a and / or 310b as a mask, the channel layer 122 is etched to form a channel structure. Here, this channel structure is the channel layer 122. This forms one or more substructures. Each substructure includes a substrate layer 112 and a sacrificial layer 210 on the substrate structure, and a channel structure on the substrate layer, which includes the channel layer 122. Figure 30A and Figure 30BAs shown, the sacrificial layer 210 includes a first part 211, a second part 212, and a third part 213.

[0161] For example, the above-mentioned one or more substructures include a first substructure 410a and a second substructure 410b, wherein the first substructure 410a is located on a first region 111a and the second substructure 410b is located on a second region 111b. A third portion 213 of the sacrificial layer 210 in the first substructure 410a is spaced apart from the channel layer 122 in the first substructure 410a to form a second void 412, and a third portion 213 of the sacrificial layer 210 in the second substructure 410b is spaced apart from the channel layer 122 in the second substructure 410b to form a third void 413.

[0162] Similarly, substrate 112 may include a first substrate portion 112a covered by the channel structure and a second substrate portion 112b not covered by the channel structure.

[0163] Next, as Figure 31A and Figure 31B As shown, a doping process is performed on the second substrate layer portion 112b. This doping process is performed, for example, by implanting impurity atoms (or impurity ions) into the second substrate layer portion. The impurity atoms (or impurity ions) may include at least one atom (or ion) selected from argon, oxygen, hydrogen, helium, germanium, boron, phosphorus, carbon, and nitrogen.

[0164] Next, as Figure 32A and Figure 32B As shown, electrodes connected to the channel layer 122 are formed on the doped second substrate layer portion 112b by an epitaxial process. Similar to the previous description, for example, the electrodes include a first electrode 510 and a second electrode 520. The first electrode 510 includes a first sub-electrode 511 and a second sub-electrode 512. The second electrode 520 includes a third sub-electrode 521 and a fourth sub-electrode 522.

[0165] Next, after forming the electrodes, the gate structure is formed on the channel layer.

[0166] like Figure 33A and Figure 33B As shown, a first dielectric layer 440 is formed on the semiconductor structure after the electrodes are formed.

[0167] Then, for example, chemical mechanical polishing is performed on the first dielectric layer 440 and the dummy gate structures 310a and 310b to expose the dummy gate layer 311.

[0168] Next, structural layers such as the dummy gate layer 311 and a portion of the first insulating layer 205 are removed to expose the channel layer 122.

[0169] Next, a gate insulating layer 611 and a gate layer 612 are formed on the channel layer 122. For example, the gate insulating layer 611 includes silicon oxide and / or a high-dielectric-constant dielectric layer. For example, the gate layer 612 includes a work function layer and a metal layer, etc. In this way, a gate structure is formed, which includes the gate insulating layer 611 and the gate layer 612.

[0170] Next, as Figure 34A and Figure 34B As shown, a second dielectric layer 620 is formed on the semiconductor structure after the gate structure is formed. For example, the second dielectric layer 620 includes at least one of an eighth insulating layer 621 and a ninth insulating layer 622.

[0171] Next, as Figure 35A and Figure 35B As shown, the second dielectric layer 620 and the first dielectric layer 440 are etched to form an opening 630, which exposes the first portion 211 and the second portion 212 of the sacrificial layer 210 and exposes the electrodes 510 and 520.

[0172] Next, through the opening 630, the first portion 211 and the second portion 212 of the sacrificial layer 210 and the second substrate portion 112b are removed to form the first void 635.

[0173] Next, for example, a first conductive layer 641 surrounding the electrode can be formed on the surface of the electrode via the first void 635 using an ALD process. Optionally, an annealing process can also be performed after the first conductive layer 641 is formed.

[0174] Next, a second conductive layer 642 is formed to fill the first void 635. This forms a contact member 640 surrounding electrodes 510 and 520. The contact member 640 includes a first conductive layer 641 and a second conductive layer 642. Here, the materials of the first conductive layer 641 and the second conductive layer 642 can be referred to the previous description.

[0175] In other embodiments, instead of forming the first conductive layer 641, a second conductive layer 642 surrounding the electrode may be formed directly on the surface of the electrode. In this case, the contact component includes the second conductive layer 642.

[0176] In other embodiments, the first conductive layer 641 can be used to fill the gap below the electrode, and then a second conductive layer 642 connected to the first conductive layer 641 can be formed, which can fill the remaining gap portion of the first gap 635.

[0177] Thus, a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is provided. The above-described manufacturing method can reduce the size of the contact components while also reducing the contact resistance between the electrodes and the contact components, thereby improving the device performance of the semiconductor device. Furthermore, the above-described manufacturing method can reduce the risk of electrode merging in different regions.

[0178] It should be noted that the third part 213 of the aforementioned sacrificial layer was not removed, but rather retained as shown in the diagram. Figure 35A In the semiconductor device shown.

[0179] It should also be noted that the above combination Figures 26A to 35B The described manufacturing method has steps that are combined with Figures 2A to 20B The same or similar steps in the described manufacturing method are described in detail in the preceding description and will not be repeated here.

[0180] Figures 36A to 40B This is a schematic cross-sectional view showing the structure of several stages in the manufacturing process of a semiconductor device according to other embodiments of the present disclosure, taken along a first or second direction. Figures 36A to 40B Describes the formation of gate structures (such as Figure 33A and Figure 33B The manufacturing process of the semiconductor device (as shown in the figure).

[0181] like Figure 36A and Figure 36B As shown, the semiconductor structure after the gate structure is formed (e.g.) Figure 33A and Figure 33B An interconnect layer 625 is formed on the semiconductor structure shown. For example, it can be formed by a deposition process, such as... Figure 33A and Figure 33B An eighth insulating layer 621 is formed on the semiconductor structure shown; then, an interconnect layer 625 is formed on the eighth insulating layer 621.

[0182] Next, as Figure 37A and Figure 37B As shown, it will be as follows Figure 36A and Figure 36B The semiconductor structure shown is flipped, and then the semiconductor substrate 111 is thinned from the back side of the semiconductor substrate 111.

[0183] Next, as Figure 38A and Figure 38BAs shown, a third dielectric layer 700 is formed on the back side of the semiconductor structure and on a thinned substrate structure. For example, the third dielectric layer 700 includes at least one of a tenth insulating layer 701 and an eleventh insulating layer 702. Then, using photolithography and etching processes, the third dielectric layer 700 and the substrate structure are etched to form an opening 630'. The opening 630' exposes a first portion 211 and a second portion 212 of the sacrificial layer 210 and an electrode 510 (or 520).

[0184] Next, as Figure 39A and Figure 39B As shown, the first portion 211 and the second portion 212 of the sacrificial layer 210, as well as the second substrate portion 112b, are removed through the opening 630' to form the first void 635'.

[0185] Next, as Figure 40A and Figure 40B As shown, a contact member 640 surrounding the electrode is formed in the first gap 635'. Optionally, for example, a first conductive layer 641 surrounding the electrode can be formed on the surface of the electrode via the first gap 635'. Optionally, an annealing process can also be performed after the first conductive layer 641 is formed.

[0186] Then, a second conductive layer 642 is formed in the first void 635' by a deposition process to fill the first void. This forms a contact component 640 surrounding electrodes 510 and 520. The contact component 640 includes a first conductive layer 641 and a second conductive layer 642.

[0187] In other embodiments, instead of forming the first conductive layer 641, a second conductive layer 642 surrounding the electrode may be formed directly on the surface of the electrode. In this case, the contact component includes the second conductive layer 642.

[0188] In other embodiments, the first conductive layer 641 can be used to fill the gap below the electrode, and then a second conductive layer 642 connected to the first conductive layer 641 can be formed, which can fill the remaining gap of the first gap.

[0189] Thus, a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is provided. This manufacturing method employs a back-side full-surround contact technology. The above-described manufacturing method can reduce the size of the contact components while also reducing the contact resistance between the electrodes and the contact components, thereby improving the device performance of the semiconductor device. Furthermore, the above-described manufacturing method can reduce the risk of electrode merging in different regions.

[0190] It should be noted that the third part 213 of the aforementioned sacrificial layer was not removed, but rather retained as shown in the diagram. Figure 40AIn the semiconductor device shown.

[0191] It should also be noted that the above combination Figures 36A to 40B The described manufacturing method has steps that are combined with Figures 21A to 25B The same or similar steps in the described manufacturing method are described in detail in the preceding description and will not be repeated here.

[0192] in addition, Figures 26A to 35B as well as Figures 36A to 40B The process of forming contact components that fully surround electrodes 512 and 522 is shown respectively. However, in practice, contact components that fully surround other electrodes (e.g., electrodes 511 and 521, etc.) can also be formed according to the manufacturing method described above. Therefore, the scope of this disclosure is not limited. Figures 26A to 35B as well as Figures 36A to 40B The manufacturing process is shown in the figure.

[0193] Based on the above manufacturing method, a semiconductor device is formed. The structure of this semiconductor device differs from the structure of the semiconductor device described previously in that, as in... Figure 35A and Figure 35B As shown (or as Figure 40A and Figure 40B In the semiconductor device shown, the channel layer employs a non-nanostructure fin-like structure. And as... Figure 35A and Figure 35B As shown (or as Figure 40A and Figure 40B Other structural parts of the semiconductor device (as shown) are similar to those shown in the figure. Figure 20A and Figure 20B (or Figure 25A and Figure 25B The semiconductor devices shown in the diagram have the same or similar structures; therefore, other structural parts can be referenced from the previous sections on... Figure 20A and Figure 20B (or Figure 25A and Figure 25B The description of the semiconductor device shown is omitted here.

Claims

1. A semiconductor device, comprising: A substrate structure comprising a semiconductor substrate and a trench isolation structure therein, wherein the semiconductor substrate includes a first region and a second region separated by the trench isolation structure; One or more substructures on the substrate structure, the one or more substructures including a first substructure and a second substructure, the first substructure being located on a first region, the second substructure being located on a second region, each substructure including a substrate layer and a sacrificial layer on the substrate structure and a channel structure on the substrate layer, the sacrificial layer being located on the trench isolation structure, the sacrificial layer in the first substructure and the sacrificial layer in the second substructure being located between the channel structure in the first substructure and the channel structure in the second substructure, the channel structure including a channel layer; Electrodes connected to the channel layer; Gate structure on the channel layer; and Contact components connected to the electrodes.

2. The semiconductor device according to claim 1, wherein, The contact component is a fully enclosed contact component.

3. The semiconductor device according to claim 1, wherein, The thickness of the sacrificial layer ranges from 1 nanometer to 10 nanometers.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The material of the sacrificial layer includes one or more of the following: tungsten nitride, tungsten carbide, titanium nitride, titanium oxide, aluminum oxide, tungsten oxide, silicon carbide, tantalum nitride, tantalum oxide, carbon-containing silicon nitride, carbon-containing silicon oxide, oxygen-containing silicon nitride, and doped silicon oxide.

5. A method for manufacturing a semiconductor device, comprising: A semiconductor structure is provided, the semiconductor structure including a substrate structure and one or more substructures on the substrate structure, the substructure including a substrate layer and a first sacrificial layer on the substrate structure and a channel structure on the substrate layer, wherein the first sacrificial layer includes a first portion on a first side of the substrate layer and a second portion on a second side of the substrate layer, the first side being opposite to the second side, the substrate layer including a first substrate layer portion covered by the channel structure and a second substrate layer portion not covered by the channel structure, the channel structure including a channel layer; Doping is performed on a portion of the second substrate layer; An electrode connected to the channel layer is formed on the doped portion of the second substrate layer, the electrode being located between a first portion and a second portion of the first sacrificial layer; After the electrode is formed, a gate structure is formed on the channel layer; An etching process is performed on the semiconductor structure after the gate structure is formed to form an opening that exposes a first portion and a second portion of the first sacrificial layer and the electrode; Through the opening, a first portion and a second portion of the first sacrificial layer, as well as a portion of the second substrate layer, are removed to form a first void; and A contact element is formed in the first gap to surround the electrode.

6. The manufacturing method according to claim 5, wherein, The width of the opening in one direction is greater than the sum of the widths of the first and second portions of the first sacrificial layer and the electrode in that direction, wherein the one direction is either from the first portion to the second portion or from the second portion to the first portion.

7. The manufacturing method according to claim 5, wherein: The first sacrificial layer further includes a third portion on a third side of the substrate layer, wherein the third side is adjacent to the first side and the second side, respectively; The one or more substructures include a first substructure and a second substructure, wherein the third portion of the first sacrificial layer in the first substructure and the third portion of the first sacrificial layer in the second substructure are located between the channel structure in the first substructure and the channel structure in the second substructure, and the third portion of the first sacrificial layer in the first substructure is spaced apart from the channel structure in the first substructure to form a second gap, and the third portion of the first sacrificial layer in the second substructure is spaced apart from the channel structure in the second substructure to form a third gap; The electrodes formed to connect with the channel layer include: A first electrode is formed in the second gap and on the second substrate layer portion of the substrate layer in the first substructure, and a second electrode is formed in the third gap and on the second substrate layer portion of the substrate layer in the second substructure, wherein the first electrode is connected to the channel layer in the first substructure, and the second electrode is connected to the channel layer in the second substructure.

8. The manufacturing method according to claim 7, wherein: The substrate structure includes a semiconductor substrate and a trench isolation structure in the semiconductor substrate, wherein the semiconductor substrate includes a first region and a second region separated by the trench isolation structure; The first substructure is located on the first region, and the second substructure is located on the second region.

9. The manufacturing method according to claim 5, wherein, The semiconductor structure provided includes: A substrate layer is formed on a semiconductor substrate; One or more stacked structures are formed on the substrate layer, each stacked structure including a second sacrificial layer and a channel layer on the second sacrificial layer; Etching is performed on the one or more stacked structures and the semiconductor substrate to form one or more fins, each fin having a trench formed around it; A trench isolation structure is formed in the trench; A first insulating layer is formed on the surface of the one or more stacked structures; A first sacrificial layer is formed on the surface of the first insulating layer; An etching process is performed on the first sacrificial layer to remove a portion of the first sacrificial layer, leaving another portion of the first sacrificial layer on the side of the first insulating layer; A dummy gate structure is formed on the first insulating layer; and Using the pseudo-gate structure as a mask, one or more stacked structures are etched to form a channel structure.

10. The manufacturing method according to claim 5, wherein, Performing a doping process on a portion of the second substrate layer includes: Impurity atoms are implanted into a portion of the second substrate layer, wherein the impurity atoms include at least one atom selected from argon, oxygen, hydrogen, helium, germanium, boron, phosphorus, carbon, and nitrogen.

11. The manufacturing method according to claim 9, wherein: The pseudo-gate structure includes a pseudo-gate layer; Forming a gate structure on the channel layer includes: forming a first dielectric layer on a semiconductor structure after forming the electrode; removing a portion of the first dielectric layer and a portion of the dummy gate structure to expose the dummy gate layer; removing the dummy gate layer, a second sacrificial layer, and a portion of the first insulating layer to expose the channel layer; and forming a gate insulating layer surrounding the channel layer and a gate layer on the gate insulating layer. Performing an etching process on the semiconductor structure after the gate structure is formed to form an opening exposing a first portion and a second portion of the first sacrificial layer and the electrode includes: forming a second dielectric layer on the semiconductor structure after the gate structure is formed; and etching the second dielectric layer and the first dielectric layer to form an opening exposing a first portion and a second portion of the first sacrificial layer and the electrode.

12. The manufacturing method according to claim 5, wherein, Etching is performed on the semiconductor structure after the gate structure is formed to form an opening exposing a first portion and a second portion of the first sacrificial layer and the electrode, including: On the back side of the semiconductor structure, the substrate structure is thinned; and An etching process is performed on the thinned substrate structure to form an opening on the back side of the semiconductor structure that exposes a first portion and a second portion of the first sacrificial layer and the electrode.

13. The manufacturing method according to claim 12, wherein, Etching of the thinned substrate structure includes: A third dielectric layer is formed on the back side of the semiconductor structure and on the thinned substrate structure; and Etching is performed on the third dielectric layer and the substrate structure to form the opening.

14. The manufacturing method according to claim 12 or 13, further comprising: Before the substrate structure is thinned, an interconnect layer is formed on the semiconductor structure after the gate structure is formed.

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