Aluminum tantalum competitive dipole compensated high-k metal gate semiconductor device and multi-threshold control method thereof

Abstract

The application discloses an aluminum-tantalum competitive dipole compensation high dielectric constant metal gate semiconductor device and a multi-threshold regulation method thereof, and comprises the following steps: S1, sequentially forming an interface dielectric layer and a high dielectric constant dielectric layer on a semiconductor substrate surface; S2, preparing a composite dipole source layer on the high dielectric constant dielectric layer, and determining a composition control parameter; S3, performing drive-in annealing treatment on the composite dipole source layer to form a competitive dipole regulation region in which Al-related species and Ta-related species coexist and are distributed; and S4, sequentially depositing a work function metal layer and a gate electrode layer on the residual source layer. The application utilizes the coexistence and competition mechanism of the two types of dipole species, Al and Ta, in the adjacent region of the high dielectric constant dielectric layer and the interface dielectric layer, and through changing the Al / Ta atomic surface density ratio of the composite dipole source layer, the flat-band voltage regulation in the three directions of negative, near-zero compensation and positive can be realized in the same material system, and the integration difficulty of the multi-threshold process is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a high dielectric constant metal gate semiconductor device with aluminum-tantalum competitive dipole compensation and a multi-threshold control method thereof. Background Technology

[0002] Gate stacks consisting of high-k dielectric (K) dielectrics and metal gates are now widely used in advanced logic devices to meet the comprehensive requirements of device operating speed, static power consumption, and circuit operating margin. Fabricating devices with different threshold voltages on the same manufacturing platform is a core technology for realizing multi-power domain chip design and achieving both high performance and low power consumption.

[0003] Currently, the main technical approaches to achieving multi-threshold modulation of high-k metal gate devices include the following three categories: The first type of method is channel doping control, which changes the threshold voltage by adjusting the doping type and concentration in the channel region. However, this method tends to exacerbate short-channel effects and impurity dispersion, and the control space is limited in deep nano-nodes.

[0004] The second type of method is work function metal control, which achieves threshold adjustment by using metal materials with different work functions or changing the thickness of the work function metal layer. However, this method requires the introduction of multiple metal materials and multiple patterning processes, which significantly increases the process complexity and cost.

[0005] The third type of method is dipole layer modulation. This involves introducing dipole modulation materials near a high-dielectric-constant dielectric layer. After heat treatment, dipole-related species migrate into the interior of the high-dielectric-constant dielectric and the region adjacent to the dielectric interface, altering the local potential distribution within the gate stack and thus regulating the flat-band voltage and threshold voltage of the device. This method does not require changes to the channel doping and metal gate material system, exhibits good process compatibility, and has become an important research direction in the field of multi-threshold modulation.

[0006] In existing dipole modulation techniques, single-component oxides, such as aluminum-based oxides or tantalum-based oxides, are typically used as the dipole source material. The voltage offset is adjusted by changing the thickness or amount of material introduced into the dipole source layer. However, single-component dipole materials can usually only adjust the flat-band voltage offset in one direction: for example, aluminum-based dipole layers typically shift the flat-band voltage negatively, while tantalum-based dipole layers typically shift it positively. If voltage settings in both positive and negative directions are required relative to the same reference device, it is often necessary to switch the type of dipole material, change the work function metal system, or adjust the heat treatment process. It is difficult to establish a unified composition-voltage calibration relationship within the same composite material system, increasing the difficulty of process integration and the risk of batch-to-batch fluctuations.

[0007] Furthermore, dipole source layers are mostly prepared using atomic layer deposition (ALD) processes, and the ALD processes of different metal oxides exhibit different initial nucleation behaviors, effective growth increments per cycle, and metal atomic surface densities. Existing techniques typically use AlO₂... x Deposition cycle number and TaO x Using the same total number of deposition cycles as the basis for thickness consistency control, this method cannot guarantee that composite source layers with different compositions have the same physical thickness or consistent total metal areal density. It is easy to confuse the composition effect and thickness effect of the material, resulting in a decrease in threshold voltage regulation accuracy. At the same time, it causes differences in equivalent oxide thickness (EOT) between different device regions, affecting the consistency of device electrical performance.

[0008] Furthermore, the flat-band voltage variation of the gate stack is simultaneously influenced by multiple factors, including fixed charges within the high-dielectric-constant dielectric, interface trapped states, the physical thickness of the dielectric layer, and oxygen migration effects. Existing dipole modulation processes generally lack a reference structure without a dipole source layer, and also lack a joint calibration process for the actual composition and thickness of the composite source layer. Consequently, it is difficult to stably determine the dipole compensation composition point of the composite system, and it is also impossible to accurately quantify the voltage offset characteristics of different formulations on both sides of the compensation composition. This results in insufficient repeatability and stability of multi-threshold modulation, making it difficult to meet the process requirements of large-scale mass production. Summary of the Invention

[0009] The purpose of this invention is to address the shortcomings of the prior art by providing an aluminum-tantalum competitive dipole compensated high-k metal gate semiconductor device and its multi-threshold control method.

[0010] The objective of this invention is achieved through the following technical solution: a multi-threshold control method for a high-dielectric-constant metal gate semiconductor device with aluminum-tantalum competitive dipole compensation, comprising the following steps: S1: An interface dielectric layer and a high dielectric constant dielectric layer are sequentially formed on the surface of a semiconductor substrate; S2: A composite dipole source layer containing both Al and Ta is prepared on the high dielectric constant dielectric layer; the composition control parameters are determined based on the surface density of metal atoms of Al and Ta in the composite dipole source layer; different voltage regulation regions on the device to be prepared are configured with composite dipole source layers with different composition control parameters to configure multiple different threshold voltages. S3: The composite dipole source layer is subjected to driving annealing to cause Al-related species and Ta-related species to migrate to the region near the interface between the high dielectric constant dielectric layer and the interface dielectric layer, forming a competitive dipole control region in which Al-related species and Ta-related species coexist; the composite dipole source layer forms a residual source layer after driving annealing. S4: Sequentially deposit the work function metal layer and the gate electrode layer on the residual source layer.

[0011] Preferably, the composition control parameter x of the composite dipole source layer is defined by the following formula: x = DAl / (DAl+DTa); Where DAl is the surface density of Al atoms in the composite dipole source layer, and DTa is the surface density of Ta atoms in the composite dipole source layer.

[0012] Preferably, in step S2, the composite dipole source layer is prepared using an atomic layer deposition process, by alternately performing AlO₂ deposition. x Complete atomic layer deposition cycle and TaO x AlO was obtained through a complete atomic layer deposition cycle; AlO was calibrated according to the preset target composition control parameters and target thickness. x Complete atomic layer deposition cycle and TaO x The effective growth increment of a complete atomic layer deposition cycle is adjusted based on the measured composition control parameters and measured physical thickness of the composite dipole source layer in AlO. x Complete atomic layer deposition cycle and TaO x The number and arrangement of complete atomic layer deposition cycles.

[0013] Preferably, the actual physical thickness difference of composite dipole source layers with different composition control parameters does not exceed 10% of their target thickness.

[0014] Preferably, the target thickness of the composite dipole source layer is 0.3–1.2 nm.

[0015] Preferably, in step S3, the driving annealing treatment is carried out in an inert atmosphere, with a peak temperature of 700–950°C and a peak holding time of 0.5–5 s.

[0016] Preferably, in step S2, the threshold voltage is configured as follows: The flat-band voltage of the reference device without a composite dipole source layer is used as the reference flat-band voltage, and a voltage discrimination tolerance not less than the measurement uncertainty is set. The difference between the flat-band voltage of the device to which the composite dipole source layer with different composition control parameters belongs and the reference flat-band voltage is calculated as the flat-band voltage offset. The composition control parameters corresponding to composite dipole source layers with flat-band voltage offset greater than the voltage discrimination tolerance are determined as positive offset composition control parameters, and the composition control parameters corresponding to composite dipole source layers with flat-band voltage offset less than the negative value of the voltage discrimination tolerance are determined as negative offset composition control parameters. The composition control parameters corresponding to the composite dipole source layer whose absolute value of flat band voltage offset is not greater than the voltage discrimination tolerance are determined as the compensation composition control parameters. Based on the first or second combination of control parameters, a composite dipole source layer is prepared in multiple different voltage regulation regions on the device to be prepared to form a corresponding number of threshold voltage levels. The first set of control parameters includes positive offset control parameters and negative offset control parameters; the second set of control parameters includes positive offset control parameters, negative offset control parameters, and compensation control parameters.

[0017] Preferably, it is used in the fabrication of planar MOS devices, FinFET devices, or all-around gate devices.

[0018] A high-k metal gate semiconductor device with aluminum-tantalum competitive dipole compensation includes: a semiconductor substrate, an interface dielectric layer, a high dielectric constant dielectric layer, a competitive dipole control layer, a work function metal layer, and a gate electrode layer sequentially formed on the semiconductor substrate; the competitive dipole control layer is a region where Al-related species and Ta-related species coexist, and is formed by driving-in annealing migration of a composite dipole source layer containing both Al and Ta; the device includes at least two voltage control regions with different threshold voltages, each voltage control region corresponding to a composite dipole source layer with different composition control parameters.

[0019] Preferably, the interface dielectric layer is made of any one or a combination of silicon oxynitride and silicon dioxide, and its thickness is 0.5 to 3 nm; the high dielectric constant dielectric layer is made of hafnium dioxide and its thickness is 1 to 5 nm; the work function metal layer is made of titanium nitride or tantalum nitride, and the gate electrode layer is made of tungsten.

[0020] The beneficial effects of this invention are: 1. This invention overcomes the limitation of traditional single-component dipole materials that can only shift the flat band voltage in one direction. By utilizing the coexistence and competition mechanism of Al and Ta dipole species in the vicinity of the high dielectric constant dielectric layer and the interface dielectric layer, the flat band voltage can be controlled in three directions (negative, near-zero compensation, and positive) within the same material system by changing the Al / Ta atomic surface density ratio of the composite dipole source layer. This eliminates the need to switch dipole materials, change the work function metal system, or adjust the heat treatment process, thus reducing the integration difficulty and design complexity of multi-threshold processes.

[0021] 2. This invention defines the composition parameters based on the measured atomic surface density of metals and uses the measured physical thickness as an independent constraint, completely decoupling the composition effect and thickness effect of the dipole, thus avoiding threshold voltage regulation errors caused by the confusion between the two; at the same time, by strictly controlling the thickness difference of the composite dipole source layer in different regulation regions, the fluctuation of the equivalent oxide layer thickness (EOT) between different device regions is effectively reduced, ensuring the uniformity of the electrical performance of the device.

[0022] 3. In the process of this invention, all voltage regulation regions share the same complete set of fabrication processes, including the interface dielectric layer, the high dielectric constant dielectric layer, the drive-in annealing process, the work function metal layer, and the gate electrode layer. There is no need to introduce multiple work function metal materials, nor is there a need for multiple patterning deposition and etching processes. Compared with traditional channel doping regulation and multi-metal work function regulation schemes, the process steps are simplified, the process cost is reduced, and it is compatible with the manufacturing processes of existing advanced logic devices. Attached Figure Description

[0023] Figure 1 Figure 1(a) shows a schematic diagram before and after the composite dipole source layer is driven in; Figure 1(b) shows a schematic diagram after the composite dipole source layer is driven in.

[0024] Figure 2 This diagram illustrates the deposition sequence, thickness calibration, and common post-processing for different voltage-controlled regions.

[0025] Figure 3 This is a schematic diagram showing the compensation relationship between the actual composition of the composite dipole source layer and the flat-band voltage offset.

[0026] In the figure: 101, semiconductor substrate; 102, interface dielectric layer; 103, high dielectric constant dielectric layer; 104, composite dipole source layer; 105, competing dipole control region; 106, work function metal layer; 107, gate electrode layer; 108, residual source layer; 201, first voltage control region; 202, second voltage control region; 203, third voltage control region; 301, negative offset region; 302, near-compensation region; 303, positive offset region. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0028] Those skilled in the art should understand that, in the disclosure of this invention, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0029] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0030] like Figures 1 to 3 As shown, a multi-threshold modulation method for a high-dielectric-constant metal-gate semiconductor device with aluminum-tantalum competitive dipole compensation includes the following steps: S1: An interface dielectric layer 102 and a high dielectric constant dielectric layer 103 are sequentially formed on the surface of a semiconductor substrate 101.

[0031] The interface dielectric layer 102 is made of any one or a combination of silicon oxynitride and silicon dioxide, and its thickness is 0.5 to 3 nm; the high dielectric constant dielectric layer 103 is made of hafnium dioxide and its thickness is 1 to 5 nm.

[0032] S2: A composite dipole source layer 104 containing both Al and Ta is prepared on the high dielectric constant dielectric layer 103; the composition control parameters are determined based on the surface density of metal atoms of Al and Ta in the composite dipole source layer 104; different voltage regulation regions on the device to be prepared are configured with composite dipole source layers 104 with different composition control parameters to configure multiple different threshold voltages.

[0033] The composition control parameter x of the composite dipole source layer is defined by the following formula: x = DAl / (DAl+DTa); Where DAl is the surface area density of Al atoms in the composite dipole source layer, and DTa is the surface area density of Ta atoms in the composite dipole source layer. 0 < x < 1 indicates that the composite dipole source layer contains both Al (aluminum) and Ta (tantalum).

[0034] Specifically, the composite dipole source layer 104 was prepared using an atomic layer deposition process, by alternately performing AlO₂ deposition. x Complete atomic layer deposition cycle and TaO x AlO was obtained through a complete atomic layer deposition cycle; AlO was calibrated according to the preset target composition control parameters and target thickness. x Complete atomic layer deposition cycle and TaO x The effective growth increment of a complete atomic layer deposition cycle is adjusted based on the measured composition control parameters and measured physical thickness of the composite dipole source layer in AlO. x Complete atomic layer deposition cycle and TaO x The number and arrangement of complete atomic layer deposition cycles. AlO x TaO represents aluminum oxide. x It represents tantalum oxide.

[0035] The measured composition control parameters were obtained through detection methods such as X-ray photoelectron spectroscopy, X-ray fluorescence analysis, and secondary ion mass spectrometry.

[0036] Based on preset target composition control parameters and target thickness, this invention first calibrates AlO₂. x TaO x The effective growth increment of each complete deposition cycle (including the physical thickness increment and the metal atomic surface density increment of a single cycle) is used to calculate the quantity ratio and arrangement of the two types of cycles, and the process parameters are corrected in reverse by using the measured results.

[0037] Due to AlO x with TaO x The atomic layer deposition process exhibits inherent differences in nucleation behavior, single-cycle metal deposition amount, and surface adsorption efficiency; therefore, the number of deposition cycles does not equate to the actual elemental composition ratio. Using measured composition control parameters as adjustment feedback can directly reflect the chemical nature of the composite dipole source layer, ensuring that the correspondence between compositional variables and flat-band voltage offset is not affected by differences in deposition processes. This provides an accurate independent variable benchmark for establishing a unified and reproducible composition-voltage calibration system.

[0038] Furthermore, by alternately executing AlO x with TaO x The complete atomic layer deposition cycle for preparing the composite dipole source layer can, on the one hand, ensure the film quality of the two oxides, reduce interface defects, impurity contamination and non-stoichiometric defects, and avoid interference from additional fixed charges or interface traps with the dipole control effect; on the other hand, the longitudinal distribution uniformity of Al and Ta atoms can be controlled by the flexible design of the cyclic arrangement (such as uniform interleaving and super-periodic arrangement), avoiding component agglomeration and ensuring that the dipole species form a stable and uniform competitive control distribution in the interface region after subsequent driving annealing.

[0039] Among them, the actual physical thickness difference of the composite dipole source layer with different composition control parameters does not exceed 10% of its target thickness.

[0040] The target thickness of the composite dipole source layer 104 is 0.3–1.2 nm. In some embodiments of this application, the target thickness of the composite dipole source layer is 0.6 nm.

[0041] AlO x Trimethylaluminum can be used as a metal precursor in a complete atomic layer deposition cycle; TaO x A complete atomic layer deposition cycle can use pentapentan(dimethylamino)tantalum as a metal precursor; the oxidation reactants can be remote oxygen plasma, ozone, or water vapor. The deposition temperature is 200–350 °C, preferably 250 °C.

[0042] Furthermore, the specific configuration method for the threshold voltage is as follows: First, multiple calibration structures are fabricated on the interface dielectric layer and the high dielectric constant dielectric layer under the same conditions. The calibration structures include a reference device without a composite dipole source layer and multiple devices with composite dipole source layers with different composition control parameters. Each calibration structure is subjected to the same drive-in annealing, and the same metal gate is fabricated on each calibration structure under the same heat treatment conditions.

[0043] The flat-band voltage VFB is taken as the reference flat-band voltage, which is the reference device without a composite dipole source layer (i.e., the reference device without a composite dipole source layer). ref Set a voltage discrimination tolerance δV that is not less than the measurement uncertainty; The difference between the flat-band voltage VFB(x) of the device with different composite dipole source layer control parameters and the reference flat-band voltage is calculated as the flat-band voltage offset ΔVFB(x), where ΔVFB(x) = VFB(x). VFB ref ; The composition control parameters corresponding to the composite dipole source layer with a flat band voltage offset greater than the voltage discrimination tolerance are determined as positive offset composition control parameters, and the composition control parameters corresponding to the composite dipole source layer with a flat band voltage offset less than the negative value (-δV) of the voltage discrimination tolerance are determined as negative offset composition control parameters. The composition control parameters corresponding to the composite dipole source layer whose absolute value of flat band voltage offset is not greater than the voltage discrimination tolerance (|ΔVFB(x)|≤δV) are determined as the compensation composition control parameters. Based on the first or second combination of control parameters, a composite dipole source layer is prepared in multiple different voltage regulation regions on the device to be prepared to form a corresponding number of threshold voltage levels. The first set of control parameters includes positive offset control parameters and negative offset control parameters; the second set of control parameters includes positive offset control parameters, negative offset control parameters, and compensation control parameters.

[0044] This invention uses the flat-band voltage of a reference device without a composite dipole source layer as the reference flat-band voltage. By automatically deducting all common system offsets through difference calculation, the flat-band voltage offset purely reflects the modulation contribution of the composite dipole source layer, thus improving the accuracy of dipole effect quantification.

[0045] Because the CV test of flat band voltage inherently involves measurement uncertainty (including instrument accuracy, probe contact resistance, frequency dispersion, and process fluctuations between samples), typically on the order of tens of millivolts, without setting a tolerance, random fluctuations within the measurement noise range can be misjudged as genuine dipole shifts. This can lead to drift in the positioning of compensation component points across different batches, and even incorrectly classify formulations that should belong to the compensation range as positive or negative shift formulations. This invention uses measurement uncertainty as the lower limit of tolerance, ensuring that only when the shift significantly exceeds the measurement noise envelope is it considered an effective positive or negative control. Formulations with shifts within the tolerance range are uniformly classified as compensation components, thereby avoiding interference from measurement noise on formulation classification and significantly improving the robustness and batch-to-batch consistency of compensation component point positioning.

[0046] By using tolerance discrimination, the composition control parameters of the composite dipole source layer are clearly divided into three categories: positive offset composition control parameters, negative offset composition control parameters, and compensation composition control parameters, which correspond to the three states of positive offset, negative offset, and near-zero offset of the flat-band voltage, respectively. This classification system discretizes the continuous composition space of the Al-Ta competing dipole into three functional regions with clear electrical meanings. In actual production, the corresponding composition region can be directly selected according to the directional requirements of the target threshold voltage.

[0047] See Figure 3 , Figure 3 This figure illustrates the compensation relationship between the actual composition of the composite dipole source layer and the flat-band voltage offset. In this figure, 301 represents the negative offset region, 302 represents the near-compensation region, and 303 represents the positive offset region.

[0048] S3: The composite dipole source layer 104 is subjected to a driving annealing process, which causes Al-related species and Ta-related species to migrate to the adjacent region at the junction of the high dielectric constant dielectric layer 103 and the interface dielectric layer 102, forming a competitive dipole control region 105 in which Al-related species and Ta-related species coexist and are distributed. After the composite dipole source layer 104 is subjected to the driving annealing process, a residual source layer 108 is formed.

[0049] In this step, the drive-in annealing process is carried out in an inert atmosphere, with a peak temperature of 700–950°C and a peak holding time of 0.5–5 seconds.

[0050] After being jointly introduced, Al-related and Ta-related species coexist in the vicinity of the high-dielectric-constant dielectric layer 103 / interface dielectric layer 102, and competitively regulate the local potential. When the composition control parameters (i.e., the aluminum / tantalum ratio) change, the net contribution of the two types of related species to the gate stack interface potential changes accordingly.

[0051] S4: Sequentially deposit a work function metal layer 106 and a gate electrode layer 107 on the residual source layer 108.

[0052] The work function metal layer 106 is made of titanium nitride (TiN), and the gate electrode layer 107 is made of tungsten (W). After depositing the work function metal layer 106 and the gate electrode layer 107, both layers undergo metal annealing. The metal annealing process can be carried out at 400°C in a nitrogen-hydrogen mixed atmosphere for 20 minutes.

[0053] This method can be applied to the fabrication of planar MOS devices, FinFET devices, or all-around gate devices.

[0054] The present invention also provides an aluminum-tantalum competitive dipole compensated high dielectric constant metal gate semiconductor device, comprising: a semiconductor substrate 101, an interface dielectric layer 102, a high dielectric constant dielectric layer 103, a competitive dipole control layer, a work function metal layer 106, and a gate electrode layer 107 sequentially formed on the semiconductor substrate 101; the competitive dipole control layer is a region where Al-related species and Ta-related species coexist, and is formed by a composite dipole source layer 104 containing both Al and Ta through drive-in annealing migration; the device includes at least two voltage control regions with different threshold voltages, each voltage control region corresponding to a composite dipole source layer 104 with different composition control parameters.

[0055] The interface dielectric layer 102 is made of any one or a combination of silicon oxynitride and silicon dioxide, and its thickness is 0.5 to 3 nm; the high dielectric constant dielectric layer 103 is made of hafnium dioxide and its thickness is 1 to 5 nm; the work function metal layer 106 is made of titanium nitride or tantalum nitride, and the gate electrode layer 107 is made of tungsten.

[0056] Example 1: Calibration of control parameters for positive offset, negative offset, and compensation components: Provide p-type semiconductor substrates from the same batch, form a 2nm SiO2 interface dielectric layer on the surface of the semiconductor substrate, and then use atomic layer deposition process to form a 2nm HfO2 high dielectric constant dielectric layer to form the basic device structure.

[0057] Multiple composite dipole source layers with composition control parameters x of 0, 0.25, 0.50, 0.75 and 1 were fabricated on the basic device structure to obtain multiple devices with composite dipole source layers with different composition control parameters, and the basic device structure without composite dipole source layer was retained as a reference device.

[0058] With a target thickness of 0.6 nm, the measured thickness difference between different composite dipole source layers is no greater than 0.06 nm.

[0059] The aforementioned calibration devices (a reference device without a composite dipole source layer and multiple devices with composite dipole source layers of different composition control parameters) were driven into the atmosphere for 1.5 seconds in a nitrogen atmosphere and at 800°C. Subsequently, a 5 nm titanium nitride work function metal layer and a 50 nm tungsten gate electrode layer were deposited on top, followed by metal annealing. The metal annealing conditions were as follows: 20 min in a nitrogen-hydrogen mixed atmosphere at 400°C.

[0060] The C–V characteristics were measured at the same frequency, AC amplitude, scan rate and scan direction. The flat band voltage (VFB) was extracted, and the correspondence between the component control parameter x and the flat band voltage offset (ΔVFB) was obtained.

[0061] The composition points are densified between a positive offset composition control parameter and a negative offset composition control parameter to determine the compensation composition control parameter that satisfies |ΔVFB|≤δV.

[0062] Example 2: Preparation of three voltage threshold levels on the same chip: like Figure 2 As shown, a basic device structure is obtained by sequentially forming a SiO2 interface dielectric layer and a HfO2 high dielectric constant dielectric layer on the surface of a semiconductor substrate. A first voltage control region 201, a second voltage control region 202, and a third voltage control region 203 are defined on the basic device structure. The three voltage control regions share the SiO2 interface dielectric layer and the HfO2 high dielectric constant dielectric layer formed in the same manner.

[0063] Negative offset composition control parameter x1, compensation composition control parameter xc, and positive offset composition control parameter x2 that satisfy thickness constraints are selected. Composite dipole source layers with parameters x1, xc, and x2 are formed in three voltage-controlled regions using sequential deposition and patterned selective removal, or regional selective deposition methods matched with corresponding deposition chemistry.

[0064] After the composite dipole source layers in all regions have been fabricated, the actual thickness t of the composite dipole source layer is... i With target thickness t The thickness difference between them does not exceed the target thickness t 10%.

[0065] The layers are jointly subjected to nitrogen atmosphere annealing at 800℃ for 1.5s, followed by co-deposition of a work function metal layer (TiN) and a gate electrode layer (W) of the same thickness, and then subjected to metal annealing. The first, second, and third voltage regulation regions form gate voltage levels with negative offset, near compensation, and positive offset, respectively.

[0066] This invention is not limited to the preferred embodiments described above. Anyone can derive other products in various forms under the guidance of this invention. However, regardless of any changes in shape or structure, any technical solution that is the same as or similar to this application falls within the protection scope of this invention.

Claims

1. A multi-threshold control method for a high-dielectric-constant metal-gate semiconductor device with aluminum-tantalum competitive dipole compensation, characterized in that, Includes the following steps: S1: An interface dielectric layer and a high dielectric constant dielectric layer are sequentially formed on the surface of a semiconductor substrate; S2: A composite dipole source layer containing both Al and Ta is prepared on a high dielectric constant dielectric layer; the composition control parameters are determined based on the surface density of metal atoms of Al and Ta in the composite dipole source layer; different voltage regulation regions on the device to be prepared are configured with composite dipole source layers with different composition control parameters to configure multiple different threshold voltages. S3: The composite dipole source layer is subjected to driving annealing to cause Al-related species and Ta-related species to migrate to the region near the interface between the high dielectric constant dielectric layer and the interface dielectric layer, forming a competitive dipole control region in which Al-related species and Ta-related species coexist; the composite dipole source layer forms a residual source layer after driving annealing. S4: Sequentially deposit the work function metal layer and the gate electrode layer on the residual source layer.

2. The multi-threshold control method for a high-dielectric-constant metal gate semiconductor device with aluminum-tantalum competitive dipole compensation according to claim 1, characterized in that, The composition control parameter x of the composite dipole source layer is defined by the following formula: x = DAl / (DAl+DTa); Where DAl is the surface density of Al atoms in the composite dipole source layer, and DTa is the surface density of Ta atoms in the composite dipole source layer.

3. The multi-threshold control method for a high-dielectric-constant metal gate semiconductor device with aluminum-tantalum competitive dipole compensation according to claim 1, characterized in that, In step S2, the composite dipole source layer is prepared using an atomic layer deposition process, by alternately performing AlO₂ deposition. x Complete atomic layer deposition cycle and TaO x Obtained by complete atomic layer deposition cycle; AlO was calibrated according to the preset target composition control parameters and target thickness. x Complete atomic layer deposition cycle and TaO x The effective growth increment of a complete atomic layer deposition cycle is adjusted based on the measured composition control parameters and measured physical thickness of the composite dipole source layer in AlO. x Complete atomic layer deposition cycle and TaO x The number and arrangement of complete atomic layer deposition cycles.

4. The multi-threshold control method for a high-dielectric-constant metal gate semiconductor device with aluminum-tantalum competitive dipole compensation according to claim 3, characterized in that, The actual physical thickness difference of composite dipole source layers with different composition control parameters does not exceed 10% of their target thickness.

5. The multi-threshold control method for a high-dielectric-constant metal gate semiconductor device with aluminum-tantalum competitive dipole compensation according to claim 3, characterized in that, The target thickness of the composite dipole source layer is 0.3–1.2 nm.

6. The multi-threshold control method for a high-dielectric-constant metal gate semiconductor device with aluminum-tantalum competitive dipole compensation according to claim 2, characterized in that, In step S3, the drive-in annealing process is carried out in an inert atmosphere, with a peak temperature of 700–950°C and a peak holding time of 0.5–5 s.

7. The multi-threshold control method for a high-dielectric-constant metal gate semiconductor device with aluminum-tantalum competitive dipole compensation according to claim 1, characterized in that, In step S2, the threshold voltage is configured as follows: The flat-band voltage of the reference device without a composite dipole source layer is used as the reference flat-band voltage, and a voltage discrimination tolerance not less than the measurement uncertainty is set. The difference between the flat-band voltage of the device to which the composite dipole source layer with different composition control parameters belongs and the reference flat-band voltage is calculated as the flat-band voltage offset. The composition control parameters corresponding to the composite dipole source layer with a flat band voltage offset greater than the voltage discrimination tolerance are determined as positive offset composition control parameters, and the composition control parameters corresponding to the composite dipole source layer with a flat band voltage offset less than the negative value of the voltage discrimination tolerance are determined as negative offset composition control parameters. The composition control parameters corresponding to the composite dipole source layer whose absolute value of flat band voltage offset is not greater than the voltage discrimination tolerance are determined as the compensation composition control parameters. Based on the first or second combination of control parameters, a composite dipole source layer is prepared in multiple different voltage regulation regions on the device to be prepared to form a corresponding number of threshold voltage levels. The first set of control parameters includes positive offset control parameters and negative offset control parameters; the second set of control parameters includes positive offset control parameters, negative offset control parameters, and compensation control parameters.

8. The multi-threshold control method for a high-dielectric-constant metal gate semiconductor device with aluminum-tantalum competitive dipole compensation according to claim 1, characterized in that, It is used in the fabrication of planar MOS devices, FinFET devices, or all-around gate devices.

9. A high-dielectric-constant metal-gate semiconductor device with aluminum-tantalum competitive dipole compensation, prepared by the multi-threshold modulation method of the high-dielectric-constant metal-gate semiconductor device with aluminum-tantalum competitive dipole compensation according to any one of claims 1-8, characterized in that, include: A semiconductor substrate, an interface dielectric layer, a high dielectric constant dielectric layer, a competing dipole modulation layer, a work function metal layer, and a gate electrode layer are sequentially formed on the semiconductor substrate; The competitive dipole control layer is a region where Al-related species and Ta-related species coexist and are formed by driving-in annealing migration of a composite dipole source layer containing both Al and Ta. The device includes at least two voltage control regions with different threshold voltages, each voltage control region corresponding to a composite dipole source layer with different composition control parameters.

10. The high-dielectric-constant metal-gate semiconductor device with aluminum-tantalum competing dipole compensation according to claim 9, characterized in that, The interface dielectric layer is made of any one or a combination of silicon oxynitride and silicon dioxide, and its thickness is 0.5 to 3 nm; the high dielectric constant dielectric layer is made of hafnium dioxide and its thickness is 1 to 5 nm; the work function metal layer is made of titanium nitride or tantalum nitride, and the gate electrode layer is made of tungsten.

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