Semiconductor package with integrated passive electrical components

Abstract

This application relates to a semiconductor package with integrated passive electrical components. A semiconductor package (100) includes a leadframe (104) comprising input / output pins accessible outside the semiconductor package, and a semiconductor die (102) electrically connected to the leadframe (104). The semiconductor package (100) also includes a passive electrical component (120, 116, 110) mounted on a side of the semiconductor die (102) opposite the leadframe (104). A molding compound (115) encapsulates the passive electrical component (120, 116, 110), semiconductor die (102), and leadframe (104) to form the semiconductor package (110). Related methods are also disclosed.

Description

[0001] Divisional application

[0002] This application is a divisional application of the invention patent application filed on November 16, 2018, with application number 201811364218.X and title "Semiconductor Package with Integrated Passive Electrical Components". Technical Field

[0003] This application relates to the field of semiconductor technology, and more specifically, to semiconductor packaging and methods thereof. Background Technology

[0004] Many types of integrated circuits (ICs) have input / output (I / O) pins for connecting external passive or active components. The IC (also called a semiconductor die) is typically attached to a leadframe and then surrounded by a molding compound to form a semiconductor package. This package is then attached to a printed circuit board (PCB). Capacitors, inductors, or other types of passive electrical components may be attached to the same PCB. The passive electrical components are electrically connected to one or more I / O pins of the leadframe via traces on the PCB, and are electrically connected to the IC through the leadframe. Semiconductor packages and external passive components occupy a considerable amount of space. Space is valuable in many applications, such as smartphones or other types of mobile consumer electronics. Furthermore, interconnect parasitic effects resulting from long interconnect paths can adversely affect performance. Summary of the Invention

[0005] In one example, a semiconductor package includes: a lead frame including input / output pins accessible from the outside of the semiconductor package; and a semiconductor die electrically connected to the lead frame. The semiconductor package further includes a passive electrical component mounted on the side of the semiconductor die opposite the lead frame to clamp the semiconductor die between the passive electrical component and the lead frame. A molding compound encapsulates the passive electrical component, the semiconductor die, and the lead frame to form the semiconductor package.

[0006] Another example is a method comprising: forming a first magnetic material on a first surface of a conductive ring; and forming a second magnetic material on a second surface of the conductive ring opposite to the first surface to form an inductor. The method further comprises: attaching a semiconductor die to a lead frame using solder balls, and attaching the inductor to the lead frame. The semiconductor die is sandwiched between the inductor and the lead frame.

[0007] In yet another example, a semiconductor package includes a lead frame with input / output pins accessible from the outside of the semiconductor package. It also includes a semiconductor die electrically connected to the lead frame. An inductor includes a conductive element sandwiched between a pair of magnetic elements and attached to the lead frame with solder balls, such that the inductor is located on the side of the semiconductor die opposite the lead frame. A molding compound encapsulates the inductor, semiconductor die, and lead frame to form the semiconductor package. Attached Figure Description

[0008] To describe the various examples in detail, reference will now be made to the accompanying drawings, in which:

[0009] Figure 1A Description of a semiconductor package according to one embodiment;

[0010] Figure 1B Examples of switch-mode voltage converters that can be used with semiconductor packages are shown;

[0011] Figures 2A to 2D This illustrates the assembly process of the semiconductor package shown in Figure 1.

[0012] Figure 3 A perspective view of a semiconductor package according to an embodiment of FIG1 is shown;

[0013] Figure 4 A side view of a semiconductor package according to an embodiment of FIG1 is shown;

[0014] Figure 5 Description of a semiconductor package according to another embodiment;

[0015] Figures 6A to 6D illustrate Figure 5 The assembly process of semiconductor packaging; and

[0016] Figure 7 illustrate Figure 5 A perspective view of a semiconductor package. Detailed Implementation

[0017] The disclosed embodiments are for semiconductor packages with integrated passive electrical devices. That is, the passive electrical devices are contained within the package but outside the semiconductor die. In one embodiment, the lead frame, semiconductor die, and passive electrical components are stacked, with the passive electrical components mounted on the side of the semiconductor die opposite the lead frame. Therefore, instead of placing the passive electrical components on a PCB outside the semiconductor package, the passive electrical components are integrated into the semiconductor package, which is stacked vertically relative to the semiconductor die and its lead frame. The passive electrical components may include one or more of inductors, capacitors, resistors, or other types of passive components. The techniques described herein are applicable to any semiconductor package type. Examples of such packages include Quadrature Flat Lead-Free (QFN) packages, Small Outline Integrated Circuit (SOIC) packages, Thin Small Outline Packages (TSOPs), etc.

[0018] The resulting product has a smaller footprint (i.e., cross-sectional area) compared to passive electrical components that are mounted outside the semiconductor package. Furthermore, the closer proximity of the passive electrical components to the semiconductor die offers beneficial electrical characteristics, such as reduced toroidal inductance and resistance.

[0019] Figure 1A This illustration shows a cross-sectional side view of a semiconductor package 100 according to one embodiment. The semiconductor package includes a semiconductor die 102 mounted to a leadframe 104 (e.g., copper) and a passive electrical component 130 also attached to the leadframe. The semiconductor die 102 is attached to the leadframe, for example, using copper pillars 106. The semiconductor die 102 contains any type of integrated circuit. In one example, the integrated circuit is a power circuit, such as a switch-mode voltage converter. In this example, the integrated circuit may include one or more power transistors, lower-power transistor switches, gate drivers, control circuitry, etc.

[0020] Figure 1A In one example, the passive electrical component 130 includes a conductive element 116 (e.g., copper) that spans parallel to the lead frame 104 and is electrically connected to the lead frame via one or more solder balls 125. Figure 1A In the figure, the height H1 of the solder ball is greater than the height H2 of the semiconductor die 102. A conductive element 116 of the passive electrical assembly 130 is sandwiched between a pair of magnetic elements 110 and 120. The conductive element 116 may have a non-linear shape (e.g., a bend, a coil, etc.). In the example of FIG1, the combination of the conductive element 116 with the magnetic elements 110 and 120 forms a passive electrical assembly including an inductor.

[0021] As an inductor, the passive electrical component 130 has two electrical contacts connected to individual solder balls 125 and connected via solder balls 125 to contacts on a leadframe 104. The conductive portion of the leadframe 104 provides electrical connectivity between the solder balls 125 and the I / O pins of the semiconductor die 102. Therefore, the passive electrical component 130 is connected to the semiconductor die via the solder balls 125 and the leadframe 104. As described above, the semiconductor die may include a voltage converter. In one example, the voltage regulator may include a Booker voltage converter comprising one or more pairs of power transistors (e.g., each pair includes a high-side transistor connected to a supply voltage node and a low-side transistor connected to a ground node). Each pair of power transistors is connected together at a switching node. As an inductor, the passive electrical component 130 is connected to the switching node. The footprint occupied by the voltage converter and the passive electrical component is smaller than the footprint would result from the passive electrical component being located outside the semiconductor package.

[0022] Figure 1B An example of an electrical schematic of a switch-mode voltage converter is shown, in which semiconductor package 100 (and package 200 described below) may be used. In this example, the voltage converter includes a controller and gate driver 103, a high-side power transistor (HS), a low-side power transistor (LS), an inductor L, and an output capacitor Cout. The controller and gate driver 103 asserts a gate signal to selectively turn the power transistors HS and LS on and off. The inductor L is connected to a switching node (SW) formed between the source of HS and the drain of LS. The output capacitor Cout is connected to the opposite terminals of the inductor L and provides the output voltage Vout from the converter. The inductor L includes a passive electrical component 130. The aforementioned semiconductor die 102 includes the controller and gate driver 103 and the power transistors HS and LS. Semiconductor package 100 integrates both semiconductor die 102 and inductor L.

[0023] Figures 2A to 2D An example of the semiconductor package 100 assembled in Figure 1 is shown. Figure 2A Describe conductive element 116. The conductive element may be made of copper or other suitable metal. Conductive element 116 is formed in a non-linear shape (e.g., a ring) suitable for forming an inductor. Figure 2B The magnetic elements 110 and 120 are described as being formed on opposite surfaces of the conductive element 116. In one embodiment, the magnetic element comprises a magnetic molding compound applied to the opposite surface of the conductive element 116. In another embodiment, the magnetic element comprises a magnetic sheet adhered to the conductive element by means of, for example, a non-conductive epoxy resin. Such epoxy resin should not be applied to the area where the solder balls of the conductive element 116 contact.

[0024] Figure 2CThe description describes the placement of an inductor (including magnetic elements 110, 120 and conductive element 116) on the semiconductor die 102, attached to the lead frame 106 via copper pillars 106 and electrically connected to the lead frame 104 by means of solder balls 125. The solder balls may be processed and attached to the conductive element 116 and the lead frame 104 by means of a reflow step. In some embodiments, the lower magnetic element 110 may be in contact with the semiconductor die 102. In other embodiments, a dielectric or other type of protective layer may be disposed between the magnetic element 110 and the semiconductor die 102. Figure 2D This describes a molding compound 115 used to encapsulate the components to form a semiconductor package. Figures 2A to 2D The components can be executed on the wafer to create multiple such integrated structures. The wafer is then individually diced using laser or mechanical dicing processes.

[0025] Figure 3 A perspective view of a semiconductor package 100 is shown. In this example, conductive element 116 is shown with a curved shape to form a local loop. The conductive element is sandwiched between magnetic elements 110 and 120. Leadframe 104 is also shown with multiple individual conductive parts to provide externally accessible connections to semiconductor die 102. Figure 4 This view shows another side view of the semiconductor package. It also shows layer 117 between the lower magnetic element 110 of the inductor and the top surface of the semiconductor die 102. Layer 117 may include a protective layer, such as a molding compound or a non-conductive epoxy resin.

[0026] Figure 5 Another embodiment of the semiconductor package 200 is shown. Similar to the embodiment of FIG. 1, the semiconductor package 200 of FIG. 2 includes a semiconductor die 102 mounted to a leadframe 104 by means of copper pillars 106. Conductive elements 216 (e.g., copper alloy) extend along a plane generally parallel to the leadframe and rest on or attach to the semiconductor die 102, and are electrically connected to the leadframe by means of one or more solder balls 125. As described above, the height of the solder balls 125 is greater than the height of the semiconductor die 102. Passive electrical components 220 are mounted to the conductive elements 216. The number of solder balls 125 may correspond to the number of terminals (not shown) of the passive electrical components 220. In some embodiments, the passive components include at least one of an inductor, a capacitor, and a resistor. Figure 5 The components shown are encapsulated in molding compound 115 to form a semiconductor package.

[0027] Figures 6A to 6D Assembly shown Figure 5 An example of a semiconductor package 200. Figure 6A The conductive element 116 provides a connection between the passive electrical component 220 and the solder ball 125. Figure 2B In the partial assembly, the passive electrical component 220 has been installed onto the conductive element 116. Figure 2C The diagram illustrates a semiconductor die 102 attached to a lead frame 106 via copper pillars 106, and passive electrical components and conductive elements 216 placed on the semiconductor die 102 and electrically connected to the lead frame 104 by means of solder balls 125. In some embodiments, the conductive elements 216 may contact the semiconductor die 102. In other embodiments, a dielectric or other type of protective layer may be disposed between the conductive elements 216 and the semiconductor die 102. Figure 6D This describes the molding compound 115 used to encapsulate the components to form a semiconductor package 200.

[0028] Figure 7 This is a perspective view of a semiconductor package 200 with a stacked arrangement of leadframes. In this example, a smaller leadframe 216 is shown, which electrically connects a passive electrical component 220 to a larger leadframe 104 via solder balls 125. Passive electrical components (e.g., inductors) are mounted on the side of a semiconductor die 102 opposite to the leadframes in the sandwich arrangement. The leadframe 104 is also shown having multiple individual conductive elements to provide externally accessible connections to the semiconductor die 102. In this example, the leadframe 104 can be formed, and components such as semiconductor dies are placed on the leadframe 104 and attached to the leadframe by means of solder. The components are then reflowed and subsequently overmolded. Solder balls 125 can then be attached to the larger leadframe 104. A smaller leadframe 216 attached to the passive electrical component 220 can be attached to a solder ball to form a stacked arrangement (passive electrical component 220 on top of semiconductor die 102, semiconductor die on top of leadframe 104). Another molding compound encapsulates the passive electrical component 220, semiconductor die 102, and leadframe 104 to form a final semiconductor package.

[0029] In this specification, the term "coupled" refers to an indirect or direct wired or wireless connection. Therefore, if a first device is coupled to a second device, the connection may be a direct connection or an indirect connection via other devices and connections.

[0030] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A packaged integrated circuit, comprising: A lead frame, which includes conductive leads; A semiconductor die having opposing first and second sides, the first side of the semiconductor die having contacts connected to the lead frame; Solder balls, which are connected to the lead frame; A first magnetic element and a second magnetic element, wherein the first magnetic element is on the second side of the semiconductor die, and the first magnetic element and the semiconductor die are on the same side of the solder ball; A conductive element, at least a portion of which is located between the first magnetic element and the second magnetic element, the conductive element extending beyond the first magnetic element and connected to the lead frame via the solder ball; as well as A molding compound that encapsulates the conductive element, the first magnetic element and the second magnetic element, the solder ball, the semiconductor die, and a lead frame excluding at least a portion of the conductive pins. The conductive element includes a first end and a second end opposite to the first end, the first end being coupled to and supported by the solder ball, and the second end being supported by the semiconductor die via the first magnetic element.

2. The packaged integrated circuit of claim 1, wherein the lead frame includes a conductive path between the solder ball and the contact of the semiconductor die.

3. The packaged integrated circuit according to claim 1, wherein the height of the solder ball is greater than the height of the semiconductor die.

4. The packaged integrated circuit of claim 1, wherein the conductive element comprises at least one of an inductor, a capacitor, and a resistor.

5. The packaged integrated circuit according to claim 1, wherein the conductive element has a non-linear shape.

6. The packaged integrated circuit according to claim 1, wherein the semiconductor die includes a voltage converter circuit.

7. The packaged integrated circuit of claim 1, wherein the conductive element is parallel to the second side of the semiconductor die.

8. A packaged integrated circuit, comprising: A lead frame, which includes conductive leads; A semiconductor die having opposing first and second sides, the first side of the semiconductor die having contacts connected to the lead frame; Solder balls connected to the lead frame; A first magnetic element and a second magnetic element, wherein the first magnetic element is on the second side of the semiconductor die, and the first magnetic element and the semiconductor die are on the same side of the solder ball; An inductor comprising a conductive element, at least a portion of which is located between a first magnetic element and a second magnetic element, and the inductor extending beyond the first magnetic element and connected to the lead frame via the solder ball; as well as A molding compound that encapsulates the conductive element, the first magnetic element and the second magnetic element, the solder ball, the semiconductor die, and the lead frame, excluding at least a portion of the conductive pins. The conductive element includes a first end and a second end opposite to the first end, the first end being coupled to and supported by the solder ball, and the second end being supported by the semiconductor die via the first magnetic element.

9. The packaged integrated circuit of claim 8, wherein the height of the solder ball is greater than the height of the semiconductor die.

10. The packaged integrated circuit of claim 8, wherein the first side of the semiconductor die has a first contact and a second contact, and the lead frame includes: a first conductive path between a first solder ball and the first contact; and a second conductive path between a second solder ball and the second contact.

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