A high-integration ultra-thin active circuit

Abstract

The application relates to the field of electronic circuits and semiconductor technology, in particular to a high-integration ultra-thin active circuit; the active circuit comprises a circuit structure layer, a support substrate and a functional structure layer, the support substrate has a front surface and a back surface arranged oppositely in a thickness direction, and the functional structure layer is arranged on the front surface of the support substrate; a power supply layer is used for providing working power supply to the functional structure layer; a connecting conductor is used for electrical connection between the power supply layer and the functional structure layer; the surface of the power supply layer away from the support substrate is further sequentially provided with a dense packaging layer and a reinforced packaging layer; the power supply layer in the active circuit is directly formed on the support substrate in a 'in-situ growth' mode, the power supply layer and the functional structure layer are integrated in a common substrate, the power supply layer can directly provide power supply for the functional structure layer, an additional external power supply is not needed, and the active circuit plays an important role in miniaturization and microminiaturization development of the integrated functional structure layer.

Description

Technical Field

[0001] This invention relates to the fields of electronic circuits and semiconductor technology, and specifically to a highly integrated ultra-thin active circuit. Background Technology

[0002] As integrated circuits and electronic circuit technologies continue to evolve towards higher performance and smaller sizes, the need for external power supply has become one of the key bottlenecks restricting their development. In the traditional technological approach, chips or electronic circuits rely on external, separate power modules for power, a method with significant limitations.

[0003] Firstly, external power supplies and their power connections require a large amount of space inside the electronic product, which severely limits the further improvement of the overall integration of the electronic product.

[0004] Secondly, the lengthy external power supply loop introduces parasitic parameters that cannot be ignored, leading to increased power supply noise, decreased power integrity, and slow dynamic response, making it difficult to meet the stringent requirements of advanced chips and electronic circuits for ultra-thin, miniaturized, efficient, and stable power supply.

[0005] In recent years, some technical solutions have emerged that attempt to integrate power supply and circuitry within the same substrate or package. For example, CN102744970A discloses a high-speed ink cartridge chip that requires no external power supply. It achieves self-powering by drawing power from communication signals and storing electrical energy. However, this solution relies on specific communication protocols and signal waveforms, limiting its applicability and making it unable to provide a continuous and stable power supply for general-purpose circuits. Furthermore, KR101832057B1 proposes a battery integration packaging solution based on a multi-layer circuit board. This solution forms the battery structure within the substrate through printing and stacking processes. However, its process is complex, and the battery thickness and capacity are limited, making efficient integration in ultra-thin chips or high-density PCBs difficult.

[0006] Therefore, how to provide ultra-thin, miniature, efficient, and reliable power to chips or electronic circuits within a limited space, thereby eliminating dependence on external power supply, has become a core problem that urgently needs to be solved to promote the development of chips and electronic circuits towards higher integration and higher performance. A brand-new integrated power supply solution is urgently needed. Summary of the Invention

[0007] In view of the above-mentioned shortcomings in the prior art, the purpose of this invention is to provide a highly integrated, ultra-thin active circuit that can effectively provide power to the functional structure layers in chips, circuit boards, etc., without the need for an external power supply.

[0008] To achieve the above objectives, the present invention employs the following technical solution: This invention provides a highly integrated, ultra-thin active circuit, which includes: The circuit structure layer includes a supporting substrate and a functional structure layer. The supporting substrate has a front side and a back side disposed opposite to each other in the thickness direction. The functional structure layer is disposed on the front side of the supporting substrate. The circuit structure layer is a chip or a PCB board. The power layer is a thin-film solid-state battery used to provide operating power for the functional structure layer. The thickness of the thin-film solid-state battery is 7.2μm~12.2μm. The power layer includes a positive electrode current collector layer, a positive electrode material layer, a solid electrolyte layer, a negative electrode material layer, and a negative electrode current collector layer stacked sequentially. A connecting conductor is used to electrically connect the power layer and the functional structure layer; the positive current collector layer of the power layer is connected to the positive input terminal of the functional structure layer through the connecting conductor, and the negative current collector layer of the power layer is connected to the negative input terminal of the functional structure layer through the connecting conductor. The surface of the power layer away from the supporting substrate is further provided with a sealing layer and an enhancement encapsulation layer in sequence; the sealing layer is an alumina film deposited by atomic vapor deposition with a thickness of 50nm~200nm; the enhancement encapsulation layer is a polymer sealant with a thickness of 0.1mm~0.3mm. The location of the power layer and the arrangement of the connecting conductors satisfy any of the following configurations: Configuration A: The power layer is disposed on the back side of the support substrate, and the connecting conductor passes through the support substrate to realize the electrical connection between the power layer and the functional structure layer; Configuration B: The power layer is disposed on the side of the functional structure layer away from the supporting substrate, and one end of the connecting conductor is connected to the power layer and the other end is connected to the functional structure layer on the front side of the supporting substrate. Configuration C: The power layer and the functional structure layer are disposed on the front side of the support substrate at intervals, and the connecting conductor is connected between the two; Furthermore, when the power layer is configured, it is formed directly on the back side of the support substrate, the side of the functional structure layer away from the support substrate, or the front side of the support substrate where the functional structure layer is not provided, depending on configuration A, B, or C. In one embodiment of the present invention, when the circuit structure layer is a chip, the location of the power supply layer and the arrangement of the connecting conductors satisfy any one of configuration A, configuration B and configuration C; When the circuit structure layer is a PCB board, the location of the power layer and the arrangement of the connecting conductors satisfy either configuration A or configuration C.

[0009] In one embodiment of the present invention, the thickness of the positive electrode current collector layer is 10nm~100nm; the thickness of the positive electrode material layer is 300nm~6000nm; the thickness of the solid electrolyte layer is 200nm~3000nm; the thickness of the negative electrode material layer is 200nm~3000nm; the thickness of the negative electrode current collector layer is 10nm~100nm; the thickness of the sealing encapsulation layer is 50nm~200nm; the thickness of the reinforcing encapsulation layer is 0.1mm~0.3mm; and the material of the reinforcing encapsulation layer is butyl rubber, silicone, epoxy resin, or polypropylene sealant.

[0010] In one embodiment of the present invention, forming the power supply layer includes forming a positive current collector layer, a positive electrode material layer, a solid electrolyte layer, a negative electrode material layer, and a negative current collector layer; wherein, the step of forming the positive electrode material layer includes: preparing a lithium-ion battery positive electrode material into a slurry, applying the slurry onto the positive current collector layer by 3D printing or screen printing, and obtaining the positive electrode material layer by drying.

[0011] In one embodiment of the present invention, the positive electrode material is selected from at least one of lithium cobalt oxide, NMC ternary material, lithium manganese oxide, lithium iron phosphate, or lithium-rich manganese; the material of the positive electrode current collector layer is selected from nickel, aluminum, gold, silver, or platinum; and the material of the negative electrode current collector layer is selected from nickel, copper, gold, silver, or platinum.

[0012] In one embodiment of the present invention, the step of forming the solid electrolyte layer includes: covering the positive electrode material layer with a battery separator, applying an uncured organic electrolyte precursor onto the separator by printing or printing method, and then performing a curing treatment to form an organic solid electrolyte layer; the raw materials for preparing the organic electrolyte precursor include a monomer, a lithium salt, a plasticizer, and an initiator, wherein the monomer is N,N-dimethylacrylamide, the lithium salt is lithium bis(trifluoromethanesulfonyl)imide, the plasticizer is a mixture of succinic anionyl nitrile and fluoroethylene carbonate, and the initiator is azobisisobutyronitrile. In one embodiment of the present invention, when forming the organic solid electrolyte layer, the mass ratio of the monomer to the initiator is 100:1, the mass ratio of the lithium salt to the plasticizer is 1:2, and the mass ratio of the succinic anionyl ester to the fluoroethylene carbonate is 1:1.

[0013] In one embodiment of the present invention, the step of forming the negative electrode material layer includes: co-sputtering with a silicon target, a lithium target, a graphite target and a boron phosphide target to deposit a silicon-based composite negative electrode material layer on the solid electrolyte layer.

[0014] In one embodiment of the present invention, when forming the silicon-based composite anode material layer, based on the total mass of the silicon-based composite anode material as 100%, the mass content of silicon is 10% to 50%, the mass content of lithium is 5% to 20%, the mass content of carbon is 5% to 20%, the mass content of phosphorus is 0.1% to 5%, and the mass content of boron is 0.1% to 5%.

[0015] In one embodiment of the present invention, when forming the silicon-based composite anode material layer, the sputtering power of the silicon target is 200W, the sputtering power of the lithium target is 50W, the sputtering power of the graphite target is 60W, the sputtering power of the boron phosphide target is 30W, and the total sputtering time is 120min.

[0016] The beneficial effects of adopting the above technical solution are as follows: the chip or electronic circuit is directly integrated with the battery through the silicon substrate of the chip or the PCB board of the electronic circuit, providing an ultra-thin, miniature, efficient and reliable power supply for the chip or electronic circuit in a limited space, thereby getting rid of the dependence on external power supply. This new integrated power supply solution enables the chip or electronic circuit to achieve higher integration and higher stability. Attached Figure Description

[0017] Figure 1 This is a longitudinal cross-sectional view of an active circuit with configuration A provided in one embodiment of this application.

[0018] Figure 2 This is a longitudinal cross-sectional view of an active circuit with configuration B provided in one embodiment of this application.

[0019] Figure 3 This is a longitudinal cross-sectional view of an active circuit with configuration C provided in one embodiment of this application.

[0020] Figure 4 This is a schematic diagram of the power supply layer structure in an active circuit provided in one embodiment of this application.

[0021] Figure 5 This is a schematic diagram of the power supply layer structure in an active circuit provided in another embodiment of this application.

[0022] Figure label: 1. Supporting substrate; 2. Functional structure layer; 3. Power layer; 4. Connecting conductor; 5. Sealing packaging layer; 6. Reinforcing packaging layer; 11. Front side of the supporting substrate; 12. Back side of the supporting substrate; 31. Positive current collector layer; 32. Positive electrode material layer; 33. Solid electrolyte layer; 34. Negative electrode material layer; 35. Negative current collector layer; F1. Direction away from the supporting substrate; F2. Direction towards the supporting substrate. Detailed Implementation

[0023] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0024] See Figures 1-3 One embodiment of this application provides an active circuit, including: The circuit structure layer includes a support substrate 1 and a functional structure layer 2. The support substrate 1 has a front side 11 and a back side 12 disposed opposite to each other in the thickness direction. The functional structure layer 2 is disposed on the front side 11 of the support substrate 1. Power layer 3 is used to provide operating power to functional structure layer 2; Connecting conductor 4 is used for electrical connection between power layer 3 and functional structure layer 2; On the surface of the power layer 3 away from the supporting substrate 1, a sealing layer 5 and an enhanced encapsulation layer 6 are sequentially disposed. The power layer 3 is a thin-film solid-state battery with a thickness of 7.2 μm-12.2 μm.

[0025] The location of the power layer 3 and the arrangement of the connecting conductors 4 satisfy any of the following configurations of AC.

[0026] See Figure 1 Configuration A: The power layer 3 is disposed on the back side 12 of the support substrate 1, and the connecting conductor 4 passes through the support substrate 1 to realize the electrical connection between the power layer 3 and the functional structure layer 2.

[0027] See Figure 2 Configuration B: The power layer 3 is located on the side of the functional structure layer 2 away from the support substrate 1. One end of the connecting conductor 4 is connected to the power layer 3, and the other end is connected to the functional structure layer 2 on the front side 11 of the support substrate 1.

[0028] See Figure 3 Configuration C: The power layer 3 and the functional structure layer 2 are disposed on the front side 11 of the support substrate 1 at intervals, and the connecting conductor 4 is connected between the power layer 3 and the functional structure layer 2 to achieve electrical connection.

[0029] In the direction away from or close to the supporting substrate 1, the power layer is provided with the following structural layers in sequence: Positive electrode current collector layer 31, which is connected to the positive electrode input terminal of the functional structure layer through a through hole or a connecting conductor; positive electrode material layer 32; solid electrolyte layer 33; negative electrode material layer 34; negative electrode current collector layer 35, which is connected to the negative electrode input terminal of the functional structure layer through a connecting conductor.

[0030] See Figure 4 In one embodiment, in the direction away from the supporting substrate 1 (i.e., the F1 direction), the power layer is provided with the following structural layers in sequence: positive current collector layer 31, positive electrode material layer 32, solid electrolyte layer 33, negative electrode material layer 34, and negative electrode current collector layer 35; and a sealing layer 5 and an enhanced encapsulation layer 6 are provided in sequence on the surface of the power layer 3 away from the supporting substrate 1.

[0031] See Figure 5 In one embodiment, in the direction close to the support substrate 1 (i.e., the F2 direction), the power layer is provided with the following structural layers in sequence: positive current collector layer 31, positive electrode material layer 32, solid electrolyte layer 33, negative electrode material layer 34, and negative electrode current collector layer 35; and a sealing layer 5 and an enhanced encapsulation layer 6 are provided in sequence on the surface of the power layer 3 away from the support substrate 1.

[0032] It can be understood that the thickness of a thin-film solid-state battery refers to the sum of the thicknesses of the positive electrode current collector layer 31, the positive electrode material layer 32, the solid electrolyte layer 33, the negative electrode material layer 34, and the negative electrode current collector layer 35.

[0033] In some embodiments, the circuit structure layer is a chip or a PCB board. This allows for the implementation of both active chips and active PCB boards. As an example, the functional layer in the circuit structure layer refers to the key components that enable the corresponding circuit functions of the circuit structure layer. For instance, in a chip, the supporting substrate is a silicon wafer, and the functional structure layer includes integrated circuits capable of signal processing, signal storage, or computation, including but not limited to transistors and metal wires integrated into the chip. In electronic circuits, the supporting substrate is the bottom PCB board, and the functional structure layer refers to the circuit composed of components fixed to the PCB board that enable circuit functions, including but not limited to electronic components, conductive lines, vias, and pads.

[0034] In some embodiments, when the circuit structure layer is a chip, the location of the power layer and the arrangement of the connecting conductors satisfy any one of configuration A, configuration B, and configuration C.

[0035] In some embodiments, when the circuit structure layer is a PCB board, the location of the power layer and the arrangement of the connecting conductors satisfy either configuration A or configuration C.

[0036] In some embodiments, the material of the connecting conductor is selected from copper, nickel, silver, gold, or platinum.

[0037] In one embodiment of this application, a method for fabricating an active circuit is provided, comprising the following steps S1-S4.

[0038] S1. Provide a circuit structure layer; wherein the circuit structure layer includes a support substrate and a functional structure layer, the support substrate has a front side and a back side disposed opposite to each other in the thickness direction, and the functional structure layer is disposed on the front side of the support substrate.

[0039] S2. A power layer is formed on the back side of the support substrate, the surface of the functional structure layer away from the support substrate, or the front side of the support substrate where no functional structure layer is provided; wherein, the power layer is a thin-film solid-state battery. It can be understood that the power layer is formed at different locations depending on its placement.

[0040] In some embodiments, the thin-film solid-state battery is a lithium-ion thin-film solid-state battery.

[0041] In some embodiments, the fabrication of a thin-film solid-state battery includes the following step ae.

[0042] a. Forming a positive current collector layer: A positive current collector layer is formed on the back of the supporting substrate, the surface of the functional structure layer away from the supporting substrate, or the front surface of the supporting substrate where the functional structure layer is not located. This current collector layer has a positive lead-out terminal, which is connected to the positive input terminal of the functional structure layer via a connecting conductor. Under certain conditions, if the positive lead-out terminal is long enough, it can serve as a connecting conductor.

[0043] In some embodiments, the positive current collector layer is formed by magnetron sputtering or vacuum deposition.

[0044] In some embodiments, the material of the positive electrode negative fluid layer is selected from nickel, aluminum, gold, silver or platinum.

[0045] In some embodiments, the thickness of the positive current collector is 10nm-100nm.

[0046] b. Forming a positive electrode material layer: A positive electrode material layer is formed on the positive electrode current collector layer.

[0047] In some embodiments, the cathode material includes a cathode active material and carbon nanotubes, carbon fibers, carbon black, graphite, and an adhesive, wherein the adhesive is polyvinylidene fluoride, acrylic adhesive, or an adhesive conventionally used in the art.

[0048] In some embodiments, the positive electrode active material includes at least one of lithium cobalt oxide, NMC ternary, lithium manganese oxide, lithium iron phosphate, and lithium-rich manganese, or it may be a positive electrode material conventionally used in the art.

[0049] In some embodiments, the method of forming a positive electrode material layer includes: configuring positive electrode material powder of a lithium-ion battery into a second slurry, printing or printing the second slurry onto a positive electrode current collector layer by 3D printing or screen printing, and drying to obtain a positive electrode material layer.

[0050] In some embodiments, the thickness of the cathode material layer is 300nm-6000nm.

[0051] c. Formation of a solid electrolyte layer: A solid electrolyte layer covering the positive electrode material layer is formed on the positive electrode material layer.

[0052] In some embodiments, the solid electrolyte layer is selected from inorganic solid electrolyte layers or organic solid electrolyte layers.

[0053] In some embodiments, the step of forming an inorganic solid electrolyte layer includes: using magnetron sputtering to sputter lithium phosphate, lithium lanthanum zirconium oxide, lithium aluminum titanium phosphorus, or lithium germanium sulfur phosphorus as the target material to form a solid electrolyte layer. The target material can also be other solid electrolytes commonly used in the art.

[0054] In some embodiments, when forming an inorganic solid electrolyte layer, a magnetron sputtering method is used to form a lithium phosphorus oxygen nitrogen solid electrolyte layer by magnetron sputtering with lithium phosphate as the target material in an atmosphere containing nitrogen and argon.

[0055] In some embodiments, when lithium phosphate is used as the target material to form an inorganic solid electrolyte layer by magnetron sputtering, the conditions include: a vacuum degree of 0.1 Pa to 1.0 Pa, a volume ratio of argon to nitrogen of 9:1, and a total flow rate of argon and nitrogen of 30 sccm.

[0056] In some embodiments, when forming an inorganic solid electrolyte layer, a magnetron sputtering method is used to form a LiPON solid electrolyte layer by magnetron sputtering with lithium phosphate as the target material in an argon atmosphere containing nitrogen.

[0057] In some embodiments, the thickness of the inorganic solid electrolyte layer is 200nm-3000nm.

[0058] In some embodiments, the step of forming an organic solid electrolyte layer includes: c1. Cover the positive electrode material layer with a battery separator; c2. The uncured organic electrolyte is coated onto the diaphragm by printing or printing. The raw materials for preparing the uncured organic electrolyte include monomers, lithium salts, plasticizers, and initiators. Among them, the monomer is N,N,-dimethylacrylamide, the lithium salt is lithium bis(trifluoromethanesulfonyl)imide, the plasticizer is a mixture of succinic anionyl nitrile and fluoroethylene carbonate, and the initiator is azobisisobutyronitrile.

[0059] c3. The organic solid electrolyte precursor slurry is solidified to form an organic solid electrolyte layer.

[0060] In some embodiments, the method for preparing the uncured organic electrolyte includes: In a chamber isolated from moisture and oxygen, 10g of N,N,-dimethylacrylamide and 0.1g of azobisisobutyronitrile were stirred and mixed for 2h to obtain slurry A; 3.2g of succinic anionyl nitrile and 2.87g of lithium bis(trifluoromethanesulfonyl)imide were mixed, stirred at 70℃ for 30min, heated for 30min, and then 3.2g of fluoroethylene carbonate was added and stirred for 4h to obtain slurry B; slurry A and slurry B were mixed at a mass ratio of 1:10 and stirred for 2h to obtain an uncured organic solid electrolyte.

[0061] In some embodiments, the mass ratio of monomer to initiator is 100:1.

[0062] In some embodiments, the mass ratio of lithium salt to plasticizer is 1:2.

[0063] In some embodiments, the mass ratio of succinic acid to fluoroethylene carbonate is 1:1.

[0064] In some embodiments, the thickness of the organic solid electrolyte layer is 500 nm-6000 nm.

[0065] In some embodiments, the battery separator is a conventionally used fiber membrane with a thickness of 8-50 μm.

[0066] d. Formation of negative electrode material layer: A negative electrode material layer is formed on the solid electrolyte layer.

[0067] In some embodiments, when the solid electrolyte layer is an inorganic solid electrolyte layer, the step of forming the negative electrode material layer includes: using a silicon target, a lithium target, a graphite target and a boron phosphide target for magnetron co-sputtering to deposit a silicon-based composite negative electrode material layer on the solid electrolyte layer.

[0068] Preferably, under conditions of vacuum of 0.1-1.0 Pa, argon to nitrogen volume ratio of 9:1, and total gas flow of 30 sccm, a magnetron sputtering device is used with lithium phosphate as the target material, power of 200 W, and deposition time of 180 min to form an LPON solid electrolyte layer with a thickness of 550 nm.

[0069] In some embodiments, in the silicon-based composite anode material layer, based on the total mass of the silicon-based composite anode material (100%), the mass content of silicon is 10%-50%, the mass content of lithium is 5%-20%, the mass content of carbon is 5%-20%, the mass content of phosphorus is 0.1%-5%, and the mass content of boron is 0.1%-5%. By using magnetron co-sputtering to dope lithium, carbon, phosphorus, and boron into the silicon-based anode material layer, the volume expansion can be less than 20% while ensuring good electrical performance of the anode material layer.

[0070] In some embodiments, the thickness of the silicon-based composite anode material layer is 200nm-3000nm.

[0071] In some embodiments, when the solid electrolyte layer is an organic solid electrolyte layer, the step of forming the negative electrode material layer includes: preparing a lithium-ion battery negative electrode material into a first slurry, printing or screen printing the first slurry onto the positive electrode current collector layer using 3D printing or screen printing, and drying to obtain the negative electrode material layer. The lithium-ion battery negative electrode material includes graphite negative electrode material, silicon-carbon negative electrode material, carbon black, and a negative electrode lithium replenishing agent.

[0072] In some embodiments, the silicon-carbon anode material may be a silicon-carbon anode material conventionally used in the art, including but not limited to nano-silicon powder, and silicon-carbon anode materials composed of porous carbon and silicon.

[0073] In some embodiments, the negative electrode lithium replenishing agent can be a lithium replenishing agent conventionally used in the art, including but not limited to lithium and lithium-aluminum alloys.

[0074] In some embodiments, the negative electrode material layer can be a negative electrode material conventionally used in the art, including but not limited to graphite, mesophase carbon microspheres, and lithium titanate.

[0075] In some embodiments, when the solid electrolyte layer is an organic solid electrolyte layer, the thickness of the negative electrode material layer is 200 nm-3000 nm. By controlling the thickness of the negative electrode material, the ratio of the negative electrode capacity to the positive electrode capacity can be maintained in the range of 1.05-1.1, which is beneficial to improving the first charge and discharge efficiency of the battery and thus increasing the battery capacity.

[0076] e. Forming a negative electrode current collector layer: A patterned negative electrode current collector layer is formed on the negative electrode material layer, and it has a negative electrode lead-out end. The negative electrode lead-out end is spatially offset from the positive electrode lead-out end, and the negative electrode lead-out end is connected to the negative electrode input end of the functional structure layer through a connecting conductor. It can be understood that, under certain conditions, if the negative electrode lead-out end is long enough, it can serve as a connecting conductor.

[0077] In some embodiments, the material of the negative electrode current collector layer is selected from nickel, copper, gold, silver or platinum.

[0078] In some embodiments, the positive current collector layer is formed by magnetron sputtering or vacuum deposition.

[0079] In some embodiments, the thickness of the positive electrode current collector layer is 10nm-100nm.

[0080] In some embodiments, the fabrication of a thin-film solid-state battery includes the following steps a'-e': a' Forming a negative current collector layer: A negative current collector layer is formed on the back of the support substrate, on the side of the functional structure layer away from the support substrate, or on the front of the support substrate where the functional structure layer is not provided, and it has a negative lead-out end, and the negative lead-out end is connected to the negative input end of the functional structure layer through the connecting conductor. b' Forming a negative electrode material layer: A negative electrode material layer is formed on the negative electrode current collector layer; c' Formation of a solid electrolyte layer: A solid electrolyte layer covering the negative electrode material layer is formed on the negative electrode material layer; d' Formation of a positive electrode material layer: A positive electrode material layer is formed on the solid electrolyte layer; e' Forming a positive current collector layer: A positive current collector layer is formed on the positive electrode material layer, and it has a positive electrode lead-out end. The positive electrode lead-out end and the negative electrode lead-out end are spatially offset, and the positive electrode lead-out end is connected to the positive electrode input end of the functional structure layer through a connecting conductor.

[0081] The methods and conditions used in each step of forming a thin-film solid-state battery through steps a'-e' are basically the same as those used in step ae, and will not be repeated here.

[0082] S3. A dense encapsulation layer is formed on the surface of the power layer to prevent air from entering the power layer.

[0083] In some embodiments, the sealing layer is an aluminum oxide layer.

[0084] In some embodiments, the thickness of the sealing layer is 50 nm to 200 nm.

[0085] In some embodiments, the step of forming a sealing layer includes placing a mask on the surface of the negative electrode current collector layer and depositing aluminum oxide using atomic vapor deposition (ALD).

[0086] S4. Forming a reinforced encapsulation layer: A reinforced encapsulation layer is formed on the sealed encapsulation layer to improve the overall strength of the encapsulation layer.

[0087] In some embodiments, the step of forming the reinforced encapsulation layer includes: applying a polymer sealant onto the sealed encapsulation layer to form the reinforced encapsulation layer.

[0088] In some embodiments, the thickness of the reinforcing encapsulation layer is 0.1 mm to 0.3 mm.

[0089] In some embodiments, the material of the reinforcing encapsulation layer is selected from butyl rubber, silicone, epoxy resin, or polypropylene sealant.

[0090] The present application is further illustrated below with reference to embodiments. It should be understood that these embodiments are merely illustrative, as various modifications and variations will be apparent to those skilled in the art within the scope of the disclosure of this application. Unless otherwise stated, all parts, percentages, and ratios reported in the following embodiments are based on mass, and all reagents used in the embodiments are commercially available or synthesized by conventional methods and can be used directly without further processing, and the instruments used in the embodiments are commercially available.

[0091] Example 1 See Figure 1 The highly integrated ultra-thin active chip provided in this embodiment has the following characteristics: Figure 1 The structure shown is prepared using the following specific steps: (1) Provide commercially available monocrystalline silicon chips and fabricate lithium-ion thin-film solid-state batteries on the monocrystalline silicon wafer on the back of the chips; the fabrication process of lithium-ion thin-film solid-state batteries is as follows: (a) Fabrication of the positive current collector layer: Using the back side of a single-crystal silicon wafer as the substrate, under room temperature, vacuum of 0.5 Pa, and argon atmosphere, a platinum target is used with a magnetron sputtering power of 100 W for 30 min to deposit a 50 nm thick platinum positive current collector layer on the substrate. During the magnetron sputtering process, a mask is used to make this current collector layer protrude to one side. This protruding part serves as the positive lead-out terminal of the battery, and this lead-out terminal serves as a connecting conductor connected to the positive power input terminal in the functional structure layer of the chip.

[0092] (b) Making the positive electrode material layer: Lithium cobalt oxide powder, carbon black powder, polyvinylidene fluoride and N-methylpyrrolidone are prepared into a slurry. The slurry is printed on the positive electrode current collector layer by nano 3D printing and dried to obtain a positive electrode layer with a thickness of 300nm.

[0093] (c) Fabrication of solid electrolyte layer: A mask larger than the positive electrode material layer is placed, and magnetron sputtering is used. Under the conditions of a vacuum of 0.8 Pa, an argon to nitrogen volume ratio of 9:1, and a total gas flow rate of 30 sccm, lithium phosphate is used as the target material, the power is 200 W, and the deposition time is 180 min. Sputtering is carried out in a mixed atmosphere of argon and nitrogen to obtain an LPON solid electrolyte layer with a thickness of 550 nm.

[0094] (d) Fabrication of the negative electrode material layer: For inorganic solid electrolytes, silicon with a purity greater than 99.9% is used under vacuum of 0.5 Pa and argon flow rate of 20 sccm. The power of the silicon target is controlled at 200 W, the power of the lithium target is 50 W, the power of the graphite target is 60 W, and the power of the boron phosphide target is 30 W. Co-sputtering is controlled for 120 min to obtain a negative electrode material layer with a thickness of 200 nm, so that the negative electrode capacity / positive electrode capacity is 1.05.

[0095] (e) Fabrication of the negative current collector layer: Under the conditions of room temperature, vacuum degree of 0.5 Pa, and argon atmosphere, a nickel target is used, and the magnetron sputtering power is 100 W for 30 min to deposit a nickel positive current collector layer with a thickness of 50 nm on the substrate. During the magnetron sputtering process, a mask is used to make this current collector layer protrude in a certain direction so that it does not overlap with the positive current collector lead-out end; this protrusion is the negative lead-out end of the battery, and this lead-out end is connected to the negative power input end of the functional structure layer as a connecting conductor.

[0096] (2) Make the encapsulation layer: Place a mask on the surface of the negative electrode current collector layer and perform alumina deposition using atomic vapor deposition (ALD) with a deposition thickness of 50 nm; then coat it with a butyl rubber layer with a thickness of 0.3 mm to form the encapsulation layer.

[0097] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A highly integrated ultra-thin active circuit, characterized in that, include: The circuit structure layer includes a supporting substrate and a functional structure layer. The supporting substrate has a front side and a back side disposed opposite to each other in the thickness direction. The functional structure layer is disposed on the front side of the supporting substrate. The circuit structure layer is a chip or a PCB board. The power layer is a thin-film solid-state battery used to provide operating power for the functional structure layer. The thickness of the thin-film solid-state battery is 7.2μm~12.2μm. The power layer includes a positive electrode current collector layer, a positive electrode material layer, a solid electrolyte layer, a negative electrode material layer, and a negative electrode current collector layer stacked sequentially. A connecting conductor is used to electrically connect the power layer and the functional structure layer; the positive current collector layer of the power layer is connected to the positive input terminal of the functional structure layer through the connecting conductor, and the negative current collector layer of the power layer is connected to the negative input terminal of the functional structure layer through the connecting conductor. The surface of the power layer away from the supporting substrate is further provided with a sealing layer and a reinforcing encapsulation layer in sequence; the sealing layer is an atomic vapor deposition alumina film with a thickness of 50nm~200nm; the reinforcing encapsulation layer is a polymer sealant with a thickness of 0.1mm~0.3mm; wherein the location of the power layer and the arrangement of the connecting conductors satisfy any of the following configurations: Configuration A: The power layer is disposed on the back side of the support substrate, and the connecting conductor passes through the support substrate to realize the electrical connection between the power layer and the functional structure layer; Configuration B: The power layer is disposed on the side of the functional structure layer away from the supporting substrate, and one end of the connecting conductor is connected to the power layer and the other end is connected to the functional structure layer on the front side of the supporting substrate. Configuration C: The power layer and the functional structure layer are disposed on the front side of the support substrate at a distance from each other, and the connecting conductor is connected between the two; Furthermore, when the power layer is configured, it is formed directly on the back side of the support substrate, the side of the functional structure layer away from the support substrate, or the front side of the support substrate where the functional structure layer is not provided, depending on configuration A, B, or C.

2. The highly integrated ultra-thin active circuit according to claim 1, characterized in that, When the circuit structure layer is a chip, the location of the power layer and the arrangement of the connecting conductors satisfy any one of configuration A, configuration B and configuration C; When the circuit structure layer is a PCB board, the location of the power layer and the arrangement of the connecting conductors satisfy either configuration A or configuration C.

3. The highly integrated ultra-thin active circuit according to claim 1, characterized in that, The thickness of the positive electrode current collector layer is 10nm~100nm; the thickness of the positive electrode material layer is 300nm~6000nm; the thickness of the solid electrolyte layer is 200nm~3000nm; the thickness of the negative electrode material layer is 200nm~3000nm; the thickness of the negative electrode current collector layer is 10nm~100nm; the thickness of the sealing layer is 50nm~200nm; the thickness of the reinforcing encapsulation layer is 0.1mm~0.3mm; the material of the reinforcing encapsulation layer is butyl rubber, silicone, epoxy resin or polypropylene sealant.

4. The highly integrated ultra-thin active circuit according to claim 1, characterized in that, Forming the power layer includes forming a positive current collector layer, a positive electrode material layer, a solid electrolyte layer, a negative electrode material layer, and a negative current collector layer; wherein, the step of forming the positive electrode material layer includes: preparing the lithium-ion battery positive electrode material into a slurry, applying the slurry onto the positive current collector layer by 3D printing or screen printing, and obtaining the positive electrode material layer by drying.

5. The highly integrated ultra-thin active circuit according to claim 4, characterized in that, The positive electrode material is selected from at least one of lithium cobalt oxide, NMC ternary material, lithium manganese oxide, lithium iron phosphate, or lithium-rich manganese; the material of the positive electrode current collector layer is selected from nickel, aluminum, gold, silver, or platinum; and the material of the negative electrode current collector layer is selected from nickel, copper, gold, silver, or platinum.

6. The highly integrated ultra-thin active circuit according to claim 4, characterized in that, The steps for forming the solid electrolyte layer include: covering the positive electrode material layer with a battery separator, applying an uncured organic electrolyte precursor onto the separator by printing or printing method, and then performing a curing treatment to form an organic solid electrolyte layer; the raw materials for preparing the organic electrolyte precursor include a monomer, a lithium salt, a plasticizer, and an initiator, wherein the monomer is N,N-dimethylacrylamide, the lithium salt is lithium bis(trifluoromethanesulfonyl)imide, the plasticizer is a mixture of succinic anionyl nitrile and fluoroethylene carbonate, and the initiator is azobisisobutyronitrile.

7. The highly integrated ultra-thin active circuit according to claim 6, characterized in that, When forming the organic solid electrolyte layer, the mass ratio of the monomer to the initiator is 100:1, the mass ratio of the lithium salt to the plasticizer is 1:2, and the mass ratio of the succinic anionyl ester to the fluoroethylene carbonate is 1:

1.

8. The highly integrated ultra-thin active circuit according to claim 4, characterized in that, The steps for forming the negative electrode material layer include: co-sputtering with a silicon target, a lithium target, a graphite target and a boron phosphide target to deposit a silicon-based composite negative electrode material layer on the solid electrolyte layer.

9. The highly integrated ultra-thin active circuit according to claim 8, characterized in that, When forming the silicon-based composite anode material layer, based on the total mass of the silicon-based composite anode material as 100%, the mass content of silicon is 10%~50%, the mass content of lithium is 5%~20%, the mass content of carbon is 5%~20%, the mass content of phosphorus is 0.1%~5%, and the mass content of boron is 0.1%~5%.

10. The highly integrated ultra-thin active circuit according to claim 8, characterized in that, When forming the silicon-based composite anode material layer, the sputtering power of the silicon target is 200W, the sputtering power of the lithium target is 50W, the sputtering power of the graphite target is 60W, the sputtering power of the boron phosphide target is 30W, and the total sputtering time is 120min.

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