Semiconductor device with elevated source / drain regions and method of manufacturing the same

Abstract

A method of fabricating a semiconductor device is provided. The method includes forming an isolation region defining an active region over a substrate; forming a preliminary channel layer over the active region; forming a gate stack over the preliminary channel layer; forming a spacer layer over side surfaces and an upper surface of the gate stack, wherein the spacer layer is formed to leave an exposed portion of the preliminary channel layer; forming a channel layer by removing the exposed portion of the preliminary channel layer, wherein the channel layer is formed to leave an exposed portion of the active region, and forming a raised source / drain region over the exposed portion of the active region.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0056152, filed on April 29, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to a semiconductor device having elevated source / drain regions and a method of manufacturing the semiconductor device. Background Technology

[0003] Due to their characteristics such as miniaturization, versatility, and / or low manufacturing cost, semiconductor devices have become key components in the electronics industry. To improve the driving performance of transistors in semiconductor devices, semiconductor devices with transistor structures featuring elevated source / drain regions have been proposed. Summary of the Invention

[0004] One embodiment of this disclosure provides a transistor structure with raised source / drain regions.

[0005] One embodiment of this disclosure provides a semiconductor device having a transistor structure.

[0006] Embodiments of this disclosure provide a method for forming a transistor structure and a method for manufacturing a semiconductor device.

[0007] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device may include: forming an isolation region defining an active region on a substrate; forming a preliminary channel layer on the active region; forming a gate stack on the preliminary channel layer; forming a spacer layer on a side surface and a top surface of the gate stack, wherein the spacer layer is formed to leave an exposed portion of the preliminary channel layer; forming a channel layer by removing the exposed portion of the preliminary channel layer, wherein the channel layer is formed to leave an exposed portion of the active region; and forming a raised source / drain region on the exposed portion of the active region.

[0008] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming a crystalline silicon-germanium layer over an active region; forming a gate stack over the crystalline silicon-germanium layer; forming a spacer layer over the side surfaces and top surfaces of the gate stack to leave exposed portions of the crystalline silicon-germanium layer; removing the exposed portions of the crystalline silicon-germanium layer to leave exposed portions of the active region; and forming raised source / drain regions over the exposed portions of the active region. The exposed portions of the crystalline silicon-germanium layer have a first lateral width. The exposed portions of the active region have a second lateral width. The second lateral width is greater than the first lateral width.

[0009] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming a crystalline silicon-germanium layer over an active region; forming a gate stack over the crystalline silicon-germanium layer; forming a spacer layer over a side surface and a top surface of the gate stack to leave an exposed portion of the crystalline silicon-germanium layer; removing a portion of the crystalline silicon-germanium layer, leaving an exposed portion of the active region; and forming a raised source / drain region over the exposed portion of the active region. The raised source / drain region includes: a top having a side surface in contact with the spacer layer, the top having a first lateral width; and a bottom having a side surface in contact with the crystalline silicon-germanium layer, the bottom having a second lateral width. The second lateral width is greater than the first lateral width.

[0010] According to one embodiment of this disclosure, a semiconductor device includes: an isolation region defining an active region disposed in a substrate; a channel layer disposed over the active region; a gate stack disposed over the channel layer; a spacer layer disposed over a side surface and a top surface of the gate stack; and a raised source / drain region disposed over the active region. The raised source / drain region includes a top and a bottom, the top having a side surface contacting the spacer layer, and the bottom having a side surface contacting the channel layer. The top has a first lateral width. The bottom has a second lateral width. The second lateral width is greater than the first lateral width.

[0011] According to one embodiment of this disclosure, a semiconductor device includes: a silicon-germanium layer above an active region; a gate stack above the silicon-germanium layer; a spacer layer above a side surface and a top surface of the gate stack; and a raised source / drain region above the active region. The raised source / drain region includes a top and a bottom, the top having a side surface contacting the spacer layer, and the bottom having a side surface contacting the silicon-germanium layer. The top has a first lateral width. The bottom has a second lateral width. The second lateral width is greater than the first lateral width.

[0012] According to one embodiment of this disclosure, a semiconductor device includes: an active region comprising a single-crystal silicon layer; a silicon-germanium layer disposed over the active region; a gate stack disposed over the silicon-germanium layer; a spacer layer disposed over a side surface and a top surface of the gate stack to leave an exposed portion of the silicon-germanium layer; a raised source / drain region disposed over the exposed portion of the active region; an insulating liner layer conformally disposed over the spacer layer and the raised source / drain region; an interlayer insulating layer disposed over the insulating liner layer; and a contact plug connected to the raised source / drain region and perpendicularly extending through the interlayer insulating layer and the insulating liner layer. The raised source / drain region includes a top and a bottom, the top having a side surface contacting the spacer layer, and the bottom having a side surface contacting the silicon-germanium layer. The top has a first lateral width. The bottom has a second lateral width. The second lateral width is greater than the first lateral width.

[0013] These and other features and advantages of the embodiments of this disclosure will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a schematic layout of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figures 2 to 14 It is along Figure 1 The longitudinal cross-sectional view taken by line I-I' is used to illustrate a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0016] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of particular embodiments are provided as examples to illustrate the technical concepts disclosed in this application. However, it should be understood that those skilled in the art can perform various other examples or embodiments based on the technical concepts of this disclosure in various forms without departing from the scope of this disclosure. Therefore, the present invention is not limited to the described examples or embodiments.

[0017] Cross-shading throughout the figures indicates corresponding or similar areas between figures, rather than indicating material related to these areas.

[0018] When one element is identified as "connected" or "coupled" to another element, these elements can be directly connected or coupled, or they can be connected or coupled through an intermediate element between the elements. When two elements are identified as "directly connected" or "directly coupled," one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.

[0019] When one element is identified as being "above", "on top of", "below", or "under" another element, these elements can be in direct contact with each other, or intermediate elements can be placed between the elements.

[0020] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “under,” “below,” “above,” “upper,” “side,” “upper part,” “topmost,” “lower part,” “bottommost,” “front,” “rear,” “left,” “right,” “column,” “row,” and “level,” as well as other terms that suggest relative spatial relationships or directions, are used for the purpose of description or reference to the accompanying drawings only and are not otherwise limiting. Other spatial relationships or orientations not shown in the drawings or described in the specification may also be within the scope of this disclosure.

[0021] Terms such as "first" and "second" are used to distinguish various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be named the second element, and in another example, the second element may be named the first element.

[0022] In the description, when an element included in an embodiment is described in the singular, the element can be interpreted as including multiple elements that perform the same or similar functions.

[0023] The concept has been disclosed in conjunction with the examples and embodiments described below. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and concept of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. Therefore, the scope of this disclosure is not limited to the following description. All variations within the meaning and equivalent scope of the claims are included within its scope.

[0024] Figure 1 This is a schematic layout illustrating a semiconductor device according to an embodiment of the present disclosure. (Refer to...) Figure 1 The semiconductor device may include an isolation region 15, an active region 11, a first gate line GLa and a second gate line GLb, and a contact plug 75. The isolation region 15 may define the active region 11. The first gate line GLa and the second gate line GLb may extend parallel to each other through the active region 11. The contact plug 75 may be disposed on the active region 11 to be adjacent to the side surfaces of the first gate line GLa and the second gate line GLb. In one embodiment, the active region 11 may also extend in a row direction R. In one embodiment, the first gate line GLa and the second gate line GLb may also extend in a column direction C. The row direction and the column direction may be perpendicular to each other.

[0025] Figures 2 to 14 It is along Figure 1 A longitudinal cross-sectional view taken along line I-I' illustrates a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. (Refer to...) Figure 2 The method may include: forming an isolation region 15 defining an active region 11 in a substrate 10, forming a preliminary channel layer 20p on the surface of the active region 11, and forming gate stacks GSa and GSb on the preliminary channel region 20p.

[0026] Substrate 10 may include a single-crystal silicon layer. For example, substrate 10 may include a single-crystal silicon wafer or a silicon-on-insulator (SOI) substrate.

[0027] Forming the isolation region 15 may include: forming an isolation trench 15T in the substrate 10, forming an isolation liner layer such as a silicon oxide layer on the inner wall of the isolation trench 15T, and forming a filling insulating material such as a silicon nitride layer on the isolation liner layer to fill the isolation trench 15T.

[0028] The active region 11 defined by the isolation region 15 can be used as the channel region, source region, and drain region of a transistor. The active region 11 can be a region doped with N-type ions such as phosphorus (P) or arsenic (As). The surface of the active region 11 can be a {100} plane in the Miller index.

[0029] Forming the preliminary channel layer 20p may include performing an epitaxial growth process to form a crystalline silicon-germanium layer (c-SiGe) on the active region 11. The preliminary channel layer 20p may be formed only on the surface of the active region 11 and may not be formed on the isolation region 15.

[0030] Forming the gate stacks GSa and GSb may include: forming a first gate stack GSa and a second gate stack GSb disposed adjacent to each other on the initial channel layer 20p. The first gate stack GSa and the second gate stack GSb may respectively correspond to Figure 1 The first gate line GLa and the second gate line GLb. Forming the first gate stack GSa and the second gate stack GSB may include: forming a first material layer for gate dielectric layers 30a and 30b on the initial channel layer 20p, forming a second material layer for gate electrode layers 40a and 40b on the first material layer, forming a third material layer for gate capping layers 50a and 50b on the second material layer, and patterning the first to third material layers by performing a patterning process including photolithography and etching processes.

[0031] Figure 3 It is shown in detail Figure 2 A diagram showing the gate stacks GSa and GSb. (Refer to...) Figure 3The gate dielectric layer 30a may include an interface insulating layer 31a and a high-k dielectric layer 32a on the interface insulating layer 31a. The gate dielectric layer 30b may include an interface insulating layer 31b and a high-k dielectric layer 32b on the interface insulating layer 31b. The interface insulating layers 31a and 31b may be formed directly on the preliminary channel layer 20p. Each of the interface insulating layers 31a and 31b may include a silicon oxide layer or a silicon-germanium oxide layer formed by performing an oxidation process or a deposition process. Each of the high-k dielectric layers 32a and 32b may include at least one of a hafnium oxide layer, a molybdenum oxide layer, a zirconium oxide layer, or other metal oxide layers formed by performing a deposition process.

[0032] Gate electrode layer 40a may include a lower gate electrode layer 41a and an upper gate electrode layer 45a. Gate electrode layer 40b may include a lower gate electrode layer 41b and an upper gate electrode layer 45b. Lower gate electrode layers 41a and 41b may respectively include a first lower gate electrode layer 42a and 42b, a second lower gate electrode layer 43a and 43b, and a third lower gate electrode layer 44a and 44b. Upper gate electrode layers 45a and 45b may respectively include a first upper gate electrode layer 46a and 46b and a second upper gate electrode layer 47a and 47b.

[0033] Each of the first lower gate electrode layers 42a and 42b may include a barrier layer or a work function control layer. Each of the first lower gate electrode layers 42a and 42b may include a metal nitride layer. For example, each of the first lower gate electrode layers 42a and 42b may include at least one of a titanium nitride layer, a tantalum nitride layer, a tungsten nitride layer, and an aluminum nitride layer.

[0034] Each of the second lower gate electrode layers 43a and 43b may include a work function control layer. For example, each of the second lower gate electrode layers 43a and 43b may include a metal layer such as an aluminum layer. In one embodiment, the second lower gate electrode layers 43a and 43b may include a dipole material layer. For example, each of the second lower gate electrode layers 43a and 43b may include at least one of a lanthanum layer, a lanthanum oxide layer, an aluminum layer, a lanthanum aluminum layer, or a lanthanum aluminum oxide layer. In another embodiment, the second lower gate electrode layers 43a and 43b may be omitted.

[0035] Each of the third lower gate electrode layers 44a and 44b may include a barrier layer. Each of the third lower gate electrode layers 44a and 44b may include a metal nitride layer. For example, each of the third lower gate electrode layers 44a and 44b may include at least one of a titanium nitride layer, a tantalum nitride layer, a tungsten nitride layer, and an aluminum nitride layer. In one embodiment, each of the third lower gate electrode layers 44a and 44b may include a metal silicide layer. In one embodiment, at least one of the first lower gate electrode layers 42a and 42b or the third lower gate electrode layers 44a and 44b may be omitted.

[0036] Each of the first upper gate electrode layers 46a and 46b may include a polysilicon layer. Each of the second upper gate electrode layers 47a and 47b may include a metal layer. In one embodiment, the upper gate electrode layers 45a and 45b may further include metal silicide layers disposed between the first upper gate electrode layers 46a and 46b and the second upper gate electrode layers 47a and 47b, respectively.

[0037] Reference Figure 4 The method may further include conformally forming inner spacer layers 61a and 61b on two side surfaces and the top surface of each of the gate stacks GSa and GSB, respectively. The inner spacer layers 61a and 61b may expose a portion of the initial channel layer 20p. The lower ends of the inner spacer layers 61a and 61b may contact the initial channel layer 20p. The lower ends of the inner spacer layers 61a and 61b may have a foot shape or a folded edge shape. Forming the inner spacer layers 61a and 61b may include: forming a silicon nitride-based insulating layer by performing a first spacer layer deposition process, and patterning the insulating layer to partially expose the surface of the initial channel layer 20p by performing a first spacer etch-back process. The method may further include: forming a low-concentration ion implantation layer (not shown) in the initial channel layer 20p by performing a lightly doped drain (LDD) implantation process using the inner spacer layers 61a and 61b as ion implantation masks. LDD implantation processes may include implanting P-type ions, such as boron (B).

[0038] Reference Figure 5 The method may further include: conformally forming a preliminary intermediate spacer layer 62p on the exposed portions of the inner spacer layers 61a and 61b and the preliminary channel layer 20p, and conformally forming a preliminary outer spacer layer 63p on the preliminary intermediate spacer layer 62p. Forming the preliminary intermediate spacer layer 62p may include: performing a second spacer layer deposition process to conformally form a silicon oxide-based insulating layer on the side and top surfaces of the inner spacer layers 61a and 61b, the exposed portions of the preliminary channel layer 20p, and the isolation region 15. Forming the preliminary outer spacer layer 63p may include: performing a third spacer layer deposition process to conformally form a silicon nitride-based insulating layer on the surface of the preliminary intermediate spacer layer 62p.

[0039] Reference Figure 6The method may further include: performing a second spacer etch-back process to etch back the initial outer spacer layer 63p, thereby forming outer spacer layers 63a and 63b. The portion of the initial outer spacer layer 63p on top of the gate stacks GSa and GSb, and the portion of the initial outer spacer layer 63p on the exposed portion of the initial channel layer 20p, may be removed. The portion of the initial intermediate spacer layer 62p on top of the gate stacks GSa and GSb, and on the exposed portion of the initial channel layer 20p, may be exposed.

[0040] Reference Figure 7 The method may further include: performing a third spacer etch-back process to etch back the initial intermediate spacer layer 62p, thereby forming intermediate spacer layers 62a and 62b. The portion of the initial intermediate spacer layer 62p on top of the gate stacks GSa and GSb, and the portion of the initial intermediate spacer layer 62p on the exposed portion of the initial channel layer 20p, may be removed. The portions of the inner spacer layers 61a and 61b on top of the gate stacks GSa and GSb may be exposed.

[0041] Reference Figure 8 The method may further include forming channel layers 20a and 20b by partially removing the exposed preliminary channel layer 20p. Channel layers 20a and 20b may have recesses R in the lateral direction (shown within the dashed lines of region A). Recessing the exposed portion of the preliminary channel layer 20p may include performing an isotropic etching process. The isotropic etching process may include a wet etching process or a radial dry etching process. Each recess R of channel layers 20a and 20b may have an undercut shape. Intermediate spacer layers 62a and 62b and outer spacer layers 63a and 63b may protrude in a cantilever shape over the recesses R. A portion of the active region 11 may be exposed by the recesses R.

[0042] Figure 9 yes Figure 8 A magnified view of region A. (Refer to...) Figure 9 The space between the outer spacer layers 63a and 63b can have a first lateral width W1 in the lateral direction, and the recess R between the channel layers 20a and 20b can have a second lateral width W2 in the lateral direction. The second width W2 can be greater than the first width W1.

[0043] Reference Figure 10 The method may further include performing an epitaxial growth process to form a raised source / drain region 70 on an exposed portion of the active region 11. The raised source / drain region 70 may comprise a single-crystal silicon layer. The exposed surface of the active region 11 may be flat and unsloping, and may have a {100} plane in the Miller index. Therefore, the raised source / drain region 70 may be grown to have a flat upper surface in the vertical direction.

[0044] Figure 11 yes Figure 10 A magnified view of region B. (Refer to...) Figure 11 Each raised source / drain region 70 may have a top 70T between outer spacer layers 63a and 63b and a bottom 70B between channel layers 20a and 20b. The top 70T of the raised source / drain region 70 may have a third lateral width W3 in the lateral direction. The bottom 70B of the raised source / drain region 70 may have a fourth lateral width W4 in the lateral direction. The top 70T of the raised source / drain region 70 may contact the side surfaces of the outer spacer layers 63a and 63b. The bottom 70B of the raised source / drain region 70 may contact the side surfaces of the channel layers 20a and 20b. The fourth lateral width W4 may be greater than the third lateral width W3.

[0045] Reference Figure 12 The method may further include forming an inner liner layer 64, an interlayer insulating layer 65, and a cover insulating layer 66. Forming the inner liner layer 64 may include conformally forming a silicon nitride-based insulating layer by performing a deposition process. For example, the inner liner layer 64 may be formed on the exposed surfaces of the outer spacer layers 63a and 63b, the exposed surfaces of the intermediate spacer layers 62a and 62b, the exposed surfaces of the inner spacer layers 61a and 61b, the exposed surfaces of the raised source / drain regions 70, and the exposed surfaces of the isolation region 15. Forming the interlayer insulating layer 65 may include forming a silicon nitride-based insulating layer by performing a deposition process. The interlayer insulating layer 65 may be formed to be thicker than the inner liner layer 64 to cover the inner liner layer 64. In one embodiment, the method may further include planarizing the upper surface of the interlayer insulating layer 65 by performing a chemical mechanical polishing (CMP) process. Forming the cover insulating layer 66 may include forming a silicon nitride-based insulating layer by performing a deposition process. The overlay insulating layer 66 can have etching selectivity relative to the interlayer insulating layer 65.

[0046] Reference Figure 13 The method may further include forming a contact hole 75H. The contact hole 75H may perpendicularly penetrate the overlay insulating layer 66, the interlayer insulating layer 65, and the inner liner layer 64 to expose a raised source / drain region 70. The contact hole 75H may extend into the raised source / drain region 70. The upper surface of the raised source / drain region 70 may be recessed. The method may further include implanting ions through the contact hole 75H to form an ion implantation region 72 in the upper portion of the raised source / drain region 70. The ion implantation region 72 may reduce contact resistance. The ion implantation region 72 may include P-type ions, such as boron (B).

[0047] Reference Figure 14The method may further include: filling the contact hole 75H with a conductive material to form a contact plug 75, and forming a pad pattern 77 on the contact plug 75. Forming the contact plug 75 may include: conformally forming a contact barrier layer (not shown) on the inner wall and bottom surface of the contact hole 75H, and filling the contact hole 75H with a conductive material (e.g., one or more types of conductive materials) on the contact barrier layer. Each contact plug 75 may have a cylindrical shape. In a top view, each pad pattern 77 may have a circular or polygonal shape. In one embodiment, each pad pattern 77 may be a line pattern extending in a horizontal direction.

[0048] According to embodiments of this disclosure, the raised source / drain regions can only grow in the vertical direction, and adjacent raised source / drain regions cannot contact or connect with each other.

[0049] According to embodiments of this disclosure, the raised source / drain region may have a top and a bottom, the top having a first lateral width and the bottom having a second lateral width. The second lateral width may be greater than the first lateral width. Therefore, a raised source / drain region having a top and a bottom may have a lower source / drain region resistance than a raised source / drain region having a top and a bottom with the same lateral width.

[0050] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the concept and scope of this disclosure as defined in the appended claims. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A method for manufacturing a semiconductor device, comprising: An isolation region defining the active region is formed on the substrate; A preliminary channel layer is formed above the active region; A gate stack is formed on the initial channel layer; A spacer layer is formed over the side and top surfaces of the gate stack, wherein the spacer layer is formed to retain the exposed portion of the initial channel layer; A channel layer is formed by removing the exposed portion of the initial channel layer, wherein the channel layer is formed to retain the exposed portion of the active region; and An elevated source / drain region is formed above the exposed portion of the active region.

2. The method according to claim 1, wherein, The formation of the preliminary channel layer includes: An epitaxial growth process is performed on the active region to form a crystalline silicon-germanium layer on the active region.

3. The method according to claim 1, wherein, Forming the gate stack includes: A gate dielectric layer comprising a high-k dielectric material layer is formed on top of the initial channel layer; A lower gate electrode layer comprising a first metal nitride layer is formed on the gate dielectric layer; An upper gate electrode layer comprising a metal layer is formed on the lower gate electrode layer; and An insulating gate cover layer is formed on top of the upper gate electrode layer.

4. The method according to claim 3, wherein, Forming the gate dielectric layer includes: A silicon oxide-based interface insulating layer is formed on top of the initial channel layer; and A high-k dielectric layer is formed on top of the interface insulating layer.

5. The method according to claim 3, wherein, Forming the lower gate electrode layer includes: A first metal nitride layer is formed on the gate dielectric layer; A function control layer is formed on top of the first metal nitride layer; and A second metal nitride layer is formed on top of the work function control layer.

6. The method according to claim 3, wherein, Forming the upper gate electrode layer includes: A polysilicon layer is formed on top of the lower gate electrode layer, and The metal layer is formed on top of the polycrystalline silicon layer.

7. The method according to claim 1, wherein, Forming the spacer layer includes: An inner spacer layer is conformally formed on the side and top surfaces of the gate stack; An intermediate spacer layer is conformally formed on the side surface of the inner spacer layer; and An outer spacer layer is conformally formed on the side surface of the intermediate spacer layer.

8. The method according to claim 7, wherein, Forming the inner spacer layer includes: A preliminary inner spacer layer is formed on the side and top surfaces of the gate stack and on the exposed portions of the preliminary channel layer by performing a first spacer deposition process; and The initial inner spacer layer above the exposed portion of the initial channel layer is removed by performing a first spacer etching process.

9. The method according to claim 8, wherein, Forming the intermediate spacer layer includes: A preliminary intermediate spacer layer is conformally formed over the side and top surfaces of the inner spacer layer and the exposed portion of the preliminary channel layer by performing a second spacer deposition process; and The initial intermediate spacer layer is removed by performing a second spacer etching process over the upper surface of the inner spacer layer and the exposed portion of the initial channel layer.

10. The method according to claim 9, wherein, Forming the outer spacer layer includes: A preliminary outer spacer layer is formed over the side and top surfaces of the preliminary intermediate spacer layer by performing a third spacer deposition process; and The initial outer spacer layer is removed by performing a third spacer etching process, which is applied to the upper surface of the initial intermediate spacer layer and the exposed portion of the initial channel layer.

11. The method according to claim 1, further comprising: An inner liner layer is conformally formed on the surface of the spacer layer; An interlayer insulation layer is formed on the inner liner layer; as well as A covering insulation layer is formed on top of the interlayer insulation layer.

12. The method according to claim 11, wherein, Conformally forming the liner layer includes: conformally forming the liner layer over the surface of the raised source / drain regions.

13. The method of claim 11, further comprising: A contact hole is formed perpendicularly through the covering insulating layer and the interlayer insulating layer to expose the raised source / drain region; An ion implantation region is formed by implanting ions into the exposed source / drain regions within a contact hole; as well as A contact plug is formed by filling the contact hole with a conductive material.

14. The method according to claim 1, in, Forming the trench layer by removing the exposed portion of the preliminary trench layer includes: recessing the preliminary trench layer in the lateral direction by performing an isotropic etching process.

15. The method of claim 14, wherein: The exposed portion of the initial channel layer has a first lateral width. The surface of the exposed portion of the active region has a second lateral width, and The second horizontal width is greater than the first horizontal width.

16. The method of claim 15, wherein: The elevated source / drain region includes a top with a third lateral width and a bottom with a fourth lateral width, and The fourth horizontal width is greater than the third horizontal width.

17. The method of claim 16, wherein: The top side surface contacts the outer spacer layer, and The side surface of the bottom is in contact with the channel layer.

18. A method for manufacturing a semiconductor device, comprising: A crystalline silicon-germanium layer is formed on top of the active region; A gate stack is formed on the crystalline silicon-germanium layer; A spacer layer is formed over the side and top surfaces of the gate stack, while retaining the exposed portion of the crystalline silicon-germanium layer; Remove the exposed portion of the crystalline silicon-germanium layer, while retaining the exposed portion of the active region; as well as An elevated source / drain region is formed above the exposed portion of the active region. in: The exposed portion of the crystalline silicon-germanium layer has a first lateral width. The exposed portion of the active region has a second lateral width, and The second horizontal width is greater than the first horizontal width.

19. The method according to claim 18, in, Removing the exposed portion of the crystalline silicon-germanium layer includes recessing the crystalline germanium layer in the lateral direction.

20. A method for manufacturing a semiconductor device, comprising: A crystalline silicon-germanium layer is formed on top of the active region; A gate stack is formed on the crystalline silicon-germanium layer; A spacer layer is formed over the side and top surfaces of the gate stack, while retaining the exposed portion of the crystalline silicon-germanium layer; A portion of the crystalline silicon-germanium layer is removed, while the exposed portion of the active region is retained; as well as An elevated source / drain region is formed above the exposed portion of the active region. The elevated source / drain regions include: The top has a side surface in contact with the spacer layer, and the top has a first lateral width; and The bottom has a side surface in contact with the crystalline silicon-germanium layer, and the bottom has a second lateral width. The second horizontal width is greater than the first horizontal width.

21. A semiconductor device, comprising: An isolation region, which is disposed in the substrate, defines the active region; A channel layer is disposed above the active region; A gate stack is disposed above the channel layer; A spacer layer is disposed on the side and top surfaces of the gate stack; as well as The elevated source / drain region is positioned above the active region. in: The raised source / drain region includes a top and a bottom, the top having a side surface in contact with the spacer layer, and the bottom having a side surface in contact with the channel layer. The top has a first lateral width. The bottom has a second lateral width, and The second horizontal width is greater than the first horizontal width.

22. The semiconductor device according to claim 21, wherein, The channel layer includes a crystalline silicon-germanium layer.

23. The semiconductor device according to claim 21, wherein, The gate stack includes: A gate dielectric layer, which includes a high-k dielectric layer; A lower gate electrode layer is disposed on the gate dielectric layer and includes a first metal nitride layer; An upper gate electrode layer, disposed above the lower gate electrode layer and including a metal layer; and An insulating gate cover layer is disposed on the upper gate electrode layer.

24. The semiconductor device according to claim 23, wherein, The gate dielectric layer includes: A silicon oxide-based interface insulating layer is disposed above the channel layer; and The high-k dielectric layer is disposed on the interface insulating layer.

25. The semiconductor device according to claim 24, wherein, The lower gate electrode layer includes: The first metal nitride layer; A work function control layer is disposed on top of the first metal nitride layer; and A second metal nitride layer is disposed on the work function control layer.

26. The semiconductor device according to claim 23, wherein, The upper gate electrode layer includes: A polycrystalline silicon layer disposed above the lower gate electrode layer; and The metal layer is disposed on the polycrystalline silicon layer.

27. The semiconductor device according to claim 21, wherein, The spacer layer includes: An inner spacer layer is conformally disposed on the side and top surfaces of the gate stack; An intermediate spacer layer, conformally disposed on the side surface of the inner spacer layer; and An outer spacer layer is conformally disposed on the side surface of the intermediate spacer layer.

28. The semiconductor device according to claim 27, wherein: The inner spacer layer includes a first insulating layer based on silicon nitride. The intermediate spacer layer includes a second insulating layer based on silicon nitride, and The outer spacer layer includes a third insulating layer based on silicon nitride.

29. The semiconductor device according to claim 27, in, The inner spacer layer is conformally disposed on the side and top surfaces of the gate stack and the top surface of the channel layer.

30. The semiconductor device according to claim 29, in, The intermediate spacer layer is formed on the side surface of the inner spacer layer, but not on the upper surface of the inner spacer layer.

31. The semiconductor device according to claim 29, in, The outer spacer layer is formed on the side surface of the intermediate spacer layer, but not on the upper surface of the inner spacer layer.

32. The semiconductor device according to claim 21, further comprising: An inner liner layer, which is conformally formed on the outer spacer layer; An interlayer insulation layer is disposed on the inner liner layer; as well as A covering insulation layer is disposed on top of the interlayer insulation layer.

33. The semiconductor device according to claim 32, in, The inner liner is conformally formed on the surface of the raised source / drain region.

34. The semiconductor device according to claim 32, further comprising: The contact plug extends vertically through the overlay insulation layer, the interlayer insulation layer, and the inner liner, and extends into the raised source / drain region; as well as An ion implantation region is disposed in the source / drain region below the contact plug.

35. A semiconductor device, comprising: A silicon-germanium layer, above its active region; A gate stack is placed on top of the silicon-germanium layer; A spacer layer is disposed above the side and top surfaces of the gate stack; as well as The elevated source / drain region, which is above the active region, The raised source / drain region includes a top and a bottom, the top having a side surface in contact with the spacer layer, and the bottom having a side surface in contact with the silicon-germanium layer. in: The top has a first lateral width. The bottom has a second lateral width, and The second horizontal width is greater than the first horizontal width.

36. The semiconductor device according to claim 35, wherein: The active region includes a single-crystal silicon layer, and The silicon-germanium layer comprises a crystalline silicon-germanium layer epitaxially grown over the active region.

37. The semiconductor device of claim 35, further comprising: An inner liner layer is conformally disposed above the gate stack, the spacer layer, and the raised source / drain regions.

38. The semiconductor device of claim 37, further comprising: An interlayer insulating layer is placed on top of the inner liner layer; A covering insulating layer is placed on top of the interlayer insulating layer; A contact plug, which passes vertically through the overlay insulation layer, the interlayer insulation layer, and the inner liner layer, connects to the raised source / drain region.

39. The semiconductor device according to claim 35, wherein, The spacer layer includes: An inner spacer layer is conformally disposed on the side and top surfaces of the gate stack and in contact with the crystalline silicon-germanium layer. An intermediate spacer layer, conformally disposed on the side surface of the inner spacer layer, but not on the upper surface of the inner spacer layer; and An outer spacer layer is conformally disposed on the side surface of the intermediate spacer layer, but not on the upper surface of the intermediate spacer layer.

40. A semiconductor device, comprising: The active region includes a monocrystalline silicon layer; A silicon-germanium layer is disposed on the active region; A gate stack is disposed on the silicon-germanium layer; A spacer layer is disposed above the side and top surfaces of the gate stack, and retains the exposed portion of the silicon-germanium layer; An elevated source / drain region is disposed above the exposed portion of the active region; An insulating inner liner layer is conformally disposed above the spacer layer and the raised source / drain regions; An interlayer insulation layer is disposed on the insulating inner liner layer; as well as A contact plug, which perpendicularly passes through the interlayer insulation layer and the insulating liner layer, connects to the raised source / drain region. The raised source / drain region includes a top and a bottom, the top having a side surface in contact with the spacer layer, and the bottom having a side surface in contact with the silicon-germanium layer. in: The top has a first lateral width. The bottom has a second lateral width, and The second horizontal width is greater than the first horizontal width.

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