Semiconductor device and method of forming the same

Abstract

Integrated circuits include active regions separated from each other by isolation structures. Dielectric isolation structures are formed as gate metal cut regions and source / drain cut regions. The cuts in the gate metal and source / drain regions are formed in the same etch process. Prior to the etch process, a capping component is deposited at selected locations on the gate metal to prevent the etch process from cutting the gate metal at those locations. The dielectric isolation structures are then formed at the gate cut regions and source / drain cut regions in the same process. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have yielded multiple generations of integrated circuits, each featuring smaller and more complex circuits than the previous generation. Throughout the development of integrated circuits, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization process typically provides benefits through increased production efficiency and reduced associated costs. However, such miniaturization also increases the complexity of handling and manufacturing integrated circuits. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first semiconductor fin extending in a first lateral direction; forming a second semiconductor fin extending in the first lateral direction; depositing a first isolation structure between the first semiconductor fin and the second semiconductor fin; depositing a gate metal extending in a second lateral direction transverse to the first lateral direction across the first semiconductor fin, the second semiconductor fin, and the first isolation structure; growing a first source / drain region of a first transistor extending partially above the first isolation structure in the first fin; growing a second source / drain region of a second transistor extending partially above the first isolation structure in the second fin; depositing a cover member in a groove in the top surface of the gate metal; and forming a dielectric isolation structure extending in the first lateral direction between the first source / drain region and the second source / drain region and between a first portion and a second portion of the gate metal, the dielectric isolation structure electrically isolating the first source / drain region and the second source / drain region from each other, and electrically isolating the first portion and the second portion of the first gate metal from each other.

[0004] Other embodiments of this application provide a method of forming a semiconductor device, comprising: forming a first isolation structure between a first semiconductor fin and a second semiconductor fin; forming a second isolation structure between the second semiconductor fin and a third semiconductor fin, the first semiconductor fin and the second semiconductor fin, as well as the first isolation structure and the second isolation structure, extending in a first lateral direction; depositing gate metal extending across the first semiconductor fin and the second semiconductor fin, as well as the first isolation structure and the second isolation structure, in a second lateral direction different from the first lateral direction; depositing a cover member on the gate metal at a first location above the second isolation structure; electrically isolating a first portion of the gate metal from a second portion of the gate metal by forming a first trench using an etching process, the first trench extending through the gate metal in the first lateral direction above the isolation structure and extending between a first source / drain region of the first semiconductor fin and a second source / drain region of the second semiconductor fin, the first source / drain region and the second source / drain region extending partially above the first isolation structure; and forming a second trench extending in the first lateral direction on the second isolation structure using the etching process, wherein the first cover member protects the gate metal at the first location from being etched by the etching process.

[0005] Further embodiments of this application provide a semiconductor device, including: a first active region extending in a first lateral direction; a second active region extending in the first lateral direction; a third active region extending in the first lateral direction; a first isolation structure located between the first active region and the second active region; a second isolation structure located between the second active region and the third active region; a gate metal extending across the first active region, the second active region, the third active region, the first isolation structure, and the second isolation structure in a second lateral direction different from the first lateral direction; and a first transistor located in the first... The active region includes a first source / drain region extending partially above the first isolation structure; a second transistor located in the second active region and including a second source / drain region extending partially above the first isolation structure; a cover member located in a recess in the top surface of the gate metal above the first isolation structure; and a first dielectric isolation structure extending in the first lateral direction between the first source / drain region and the second source / drain region and between a first portion and a second portion of the gate metal, the dielectric isolation structure electrically isolating the first portion and the second portion of the gate metal from each other. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1 to 23 These are cross-sectional and top views of an integrated circuit at various processing stages according to some embodiments.

[0008] Figure 24 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0009] Figure 25 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0012] Terms indicating relative degree, such as “about” or “basically”, should be interpreted as those skilled in the art would take into account current technical specifications.

[0013] This disclosure generally relates to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured devices. Examples of nanostructured devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, the active region spacing between nanostructured devices is typically uniform, the source / drain epitaxial structure is symmetrical, and a metal gate surrounds all four sides of the nanostructure (e.g., a nanosheet).

[0014] GAA transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with pitches, for example, smaller than those achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0015] Embodiments of this disclosure enable the formation of transistor arrays that efficiently and effectively isolate the source / drain regions of adjacent transistors and the gate electrodes of adjacent transistors. After forming the source / drain regions and gate metal of the transistors, a dielectric isolation structure is formed in the same dicing / isolation process to separate adjacent portions of the gate metal (at the gate dicing location) and adjacent source / drain regions of different transistors (at the source / drain dicing locations). Prior to this process, a cover member is formed at selected locations on the gate metal where the gate is not diced. After forming the cover member, the dicing / isolation process includes an etching process that etches the source / drain regions and gate metal at desired locations, while the gate metal is protected by the cover member at other locations. The dicing / isolation process includes forming a dielectric isolation structure extending through the dicing location. This allows for further scaling down the distance between adjacent active regions. Wafer yield and device performance are improved with a simple and efficient process.

[0016] While the accompanying drawings and description focus primarily on examples of nanostructured transistors including channel stacks, the principles of this disclosure extend to other types of transistors. These principles extend to MOS transistors, FinFET transistors, and other types of transistors.

[0017] Figures 1 to 18These are cross-sectional and top views of an integrated circuit 100 manufactured according to some embodiments of the present disclosure. The manufacturing process produces a plurality of transistors 101, as will be described in further detail below.

[0018] Figure 1 This is a cross-sectional view of integrated circuit 100 during an intermediate processing stage. Integrated circuit 100 includes a substrate 102. Substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., having P-type or N-type dopants) or undoped. The semiconductor material of substrate 102 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium; or combinations thereof. Other substrates, such as single-layer, multilayer, or gradient substrates, may be used.

[0019] Integrated circuit 100 includes a semiconductor stack 103, which includes a plurality of alternating semiconductor layers 104 and sacrificial semiconductor layers 106. Figure 1 In one example, the stack 103 includes three semiconductor layers 104 and three sacrificial semiconductor layers 106. However, in practice, different numbers of semiconductor layers 104 and sacrificial semiconductor layers 106 may be used without departing from the scope of embodiments of this disclosure.

[0020] As will be further elaborated below, the semiconductor layer 104 will be patterned to form a stacked channel for multiple transistors. As will be elaborated further below, the sacrificial semiconductor layer 106 will eventually be completely removed and used to enable the formation of gate metal and other structures around the semiconductor nanostructure.

[0021] In some embodiments, the semiconductor layer 104 may be formed of a first semiconductor material, such as silicon, silicon carbide, etc., and the sacrificial semiconductor layer 106 may be formed of a second semiconductor material, such as silicon germanium, etc. Each layer of the multilayer stack 103 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0022] Due to the high etch selectivity between the materials of semiconductor layer 104 and sacrificial semiconductor layer 106, the sacrificial semiconductor layer 106 of the second semiconductor material can be removed without significantly etching the semiconductor layer 104 of the first semiconductor material, thereby allowing the semiconductor layer 104 to be released to form the stacked channel region of the transistor, as will be explained in more detail below.

[0023] In one example, semiconductor layer 104 is silicon, and sacrificial semiconductor layer 106 is silicon-germanium. In some embodiments, sacrificial semiconductor layer 106 has a germanium concentration between 10% and 50%, but other concentrations may be used without departing from the scope of embodiments of this disclosure. This makes sacrificial semiconductor layer 106 selectively etchable relative to semiconductor layer 104. Other materials and concentrations may be used without departing from the scope of embodiments of this disclosure.

[0024] Figure 2A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 2B The integrated circuit 100 according to some embodiments is in Figure 2A A top view of the processing stage shown. Figure 2A The cross-sectional view is from Figure 2B Cut along cutting line 2A.

[0025] exist Figure 2A In the present invention, a plurality of semiconductor fins 108a-108d have been formed by stacked components 103. In the following discussion, some reference numerals include the suffixes “a”, “b”, “c”, or “d”. The suffixes may be omitted when the reference is not specific to a particular single structure. For example, when the reference is used for each of the semiconductor fins, semiconductor fins 108a-108d may be simply referred to as semiconductor fin 108.

[0026] Semiconductor fins 108 are formed by forming trenches 110 in the stack 103 and the substrate 102. Although Figure 1 Not shown, but a hard mask layer is first formed and patterned on the stack 103. Trench 110 is formed using an anisotropic etching process, which etches in the downward direction in the presence of the patterned hard mask. The etching process defines semiconductor fins 108 by forming trench 110 through the sacrificial semiconductor layer 106, semiconductor layer 104, and substrate 102. The semiconductor fins 108 extend in the X direction and are spaced apart from each other in the Y direction by the trench 110.

[0027] Each semiconductor fin 108 corresponds to an active region or active area of ​​the integrated circuit 100. Each active region corresponds to the location of the source / drain and channel regions forming a transistor. Semiconductor fin 108a corresponds to a first active region. Semiconductor fin 108b corresponds to a second active region. Semiconductor fin 108c corresponds to a third active region. Semiconductor fin 108d corresponds to a fourth active region. In some embodiments, the substrate 102 of each semiconductor fin corresponds to a doped well region.

[0028] In some embodiments, each semiconductor fin 108 corresponds to a region of a P-type transistor or a region of an N-type transistor. In a specific example given herein, semiconductor fins 108a and 108b correspond to regions forming P-type transistors, and semiconductor fins 108c and 108d correspond to regions forming N-type transistors. Other distributions of P-type and N-type transistors may be utilized without departing from the scope of embodiments of this disclosure.

[0029] exist Figure 2A and Figure 2B In this process, a shallow isolation structure 112 has been formed by depositing dielectric material in the grooves 110 between the fins 108. Figure 2A The shallow isolation structure 112 is shown as a single dielectric material layer. However, in practice, multiple dielectric layers can be used to form the isolation structure 112. The dielectric layer can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. In an exemplary embodiment, the dielectric material of the isolation structure 112 includes silicon oxide. However, without departing from the scope of embodiments of this disclosure, the dielectric material may include SiN, SiCN, SiOC, SiOCN, or other dielectric materials.

[0030] After depositing the dielectric material of the isolation structure 112, an etch-back process has been performed to recess the top of the shallow isolation structure 112 below the bottommost sacrificial semiconductor layer 106. This results in the shallow isolation structure 112 having a top surface below the bottom surface of the bottommost sacrificial semiconductor layer 106 of each fin. Other processes can be used to form the shallow isolation structure 112 without departing from the scope of embodiments of this disclosure. Each isolation structure 112 extends in the X direction beside and between two adjacent semiconductor fins 108.

[0031] In some embodiments, the isolation structure 112 comprises SiO2, an oxide formed of tetraethyl orthosilicate (TEOS), or other suitable dielectric material. In some embodiments, the isolation structure 112 has a depth between 50 nm and 100 nm.

[0032] Figure 3A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 3B It is integrated circuit 100 in Figure 3A A top view of the processing stage shown. Figure 3A The cross-sectional view is from Figure 3B Cut along cutting line 3A.

[0033] exist Figure 3A and Figure 3BIn this circuit, a sacrificial gate structure 114 has been formed above the fin 108. Each sacrificial gate structure 114 extends in the Y direction across the semiconductor fin 108 and the isolation structure 112. The layout of the sacrificial gate structure 114 corresponds to the layout of the gate metal or gate structure of the transistor. In particular, the sacrificial gate structure 114 will eventually be replaced with gate metal. As will be explained in more detail below, according to the circuit layout of the integrated circuit 100, efficient processes will be used to cut the gate metal at selected locations between the semiconductor fins 108 to electrically isolate the gate metals of adjacent transistors. The sacrificial gate structure 114 corresponds to the corresponding gate metal layout locations G1-G3.

[0034] The sacrificial gate structure 114 includes a dielectric layer 116. In an exemplary embodiment, the dielectric layer 116 comprises silicon oxide. However, alternatively, without departing from the scope of embodiments of this disclosure, the dielectric layer 116 may comprise SiN, SiCN, SiOC, SiOCN, or other dielectric materials. In some embodiments, the dielectric layer 116 has a low-k dielectric material. The dielectric layer 116 may be deposited by CVD, ALD, or PVD.

[0035] The sacrificial gate structure includes a sacrificial gate layer 118 on dielectric layer 116. The sacrificial gate layer 118 may include a material with high etch selectivity relative to isolation structure 112. In an exemplary embodiment, the sacrificial gate layer 118 includes polysilicon. However, the sacrificial gate layer 118 may be a conductive, semi-conductive, or non-conductive material, and may be or include amorphous silicon, polysilicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 118 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques used for depositing the selected material.

[0036] In some embodiments, the sacrificial gate structure 114 includes a dielectric layer on the sacrificial gate layer 118. In an exemplary embodiment, the dielectric layer includes SiN. However, alternatively, without departing from the scope of embodiments of this disclosure, the dielectric layer may include SiO, SiCN, SiOC, SiOCN, or other dielectric materials. The dielectric layer may be deposited by CVD, ALD, or PVD.

[0037] exist Figure 3A and Figure 3BIn this embodiment, a gate spacer layer 120 has been formed on the sidewalls of the sacrificial gate structure 114. Specifically, the gate spacer layer 120 is formed on the sidewalls of the dielectric layer 116 and the sacrificial gate layer 118. The gate spacer layer 120 is also formed on the top surface of the sacrificial gate structure 114, the top semiconductor layer 104 of each semiconductor fin 108, and other exposed surfaces. The gate spacer layer 120 can be formed by PVD, CVD, ALD, or other suitable deposition processes. In a specific example shown herein, the gate spacer layer 120 comprises SiOCN. Alternatively, the gate spacer layer 120 may comprise one or more of SiO, SiN, SiON, SiCN, SiOC, or other suitable dielectric materials. In some embodiments, the gate spacer layer 120 has a width between 2 nm and 8 nm, but other thicknesses may be utilized without departing from the scope of embodiments of this disclosure.

[0038] exist Figure 3A and Figure 3B In this process, an etching process has been performed to pattern the gate spacer layer 120. The etching process includes an anisotropic etching process that etches in the downward direction. The anisotropic etching process removes the gate spacer layer 120 from the horizontal surface of the gate spacer 120, which has a smaller vertical thickness. After the gate spacer layer is patterned, the vertically thicker portion of the gate spacer layer 120 remains on the sidewall of the sacrificial gate structure 114.

[0039] As in Figure 3B As can be seen in the top view, after the patterned gate spacer layer 120, dielectric structures 121 remain on the top surface of the isolation structure 112 as the remainder of the gate spacer layer 120. As will be explained in more detail below, these dielectric structures 121 will suppress lateral growth of the lower portion of the source / drain region.

[0040] Figure 4A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 4B This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 4C It is integrated circuit 100 in Figure 4A A top view of the processing stage shown. Figure 4A The cross-sectional view is from Figure 4C Cut along cutting line 4A. Figure 4B The cross-sectional view is from Figure 4C Cut along cutting line 4B.

[0041] exist Figures 4A to 4CIn some embodiments, source / drain trenches 124 have been formed. After patterning the gate spacer layer 120, one or more etching processes are performed to form the source / drain trenches 124 in the fins 108. Forming the source / drain trenches 124 includes etching through each of the semiconductor layers 104, each of the sacrificial semiconductor layers 106, and portions of the substrate 102. Therefore, the removal operations may include suitable etching operations for removing material from the semiconductor layers 104, the sacrificial semiconductor layers 106, and the substrate 102. Etching processes may include reactive ion etching (RIE), neutral beam etching (NBE), atomic layer etching (ALE), etc.

[0042] The formation of the source / drain trench 124 results in the formation of a stack 126 of channel 105. Specifically, the remaining portion of the semiconductor layer 104, after the formation of the source / drain trench 124, now corresponds to a stacked channel 105 of the transistor. The formation of the source / drain trench 124 results in the formation of a plurality of sacrificial semiconductor nanostructures 107 from the sacrificial semiconductor layer 106. A substrate 102 is exposed at the bottom of each source / drain trench 124. Each stack 126 of channel 105 corresponds to a stacked channel of an individual transistor, as will be explained in more detail below.

[0043] Semiconductor fin 108a includes a stacked channel 105a and a sacrificial semiconductor nanostructure 107a. Semiconductor fin 108b includes a stacked channel 105b and a sacrificial semiconductor nanostructure 107b. Semiconductor fin 108c includes a stacked channel 105c and a sacrificial semiconductor nanostructure 107c. Semiconductor fin 108d includes a stacked channel 105d and a sacrificial semiconductor nanostructure 107d.

[0044] Figure 5 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 5 In this process, a selective etching process has been implemented to recess the exposed end portion of the sacrificial semiconductor nanostructure 107 without substantially etching the channel 105. More specifically, a groove is formed in the end portion of the sacrificial semiconductor nanostructure 107 relative to the adjacent channel 105. The groove can be formed by performing an etching process that selectively etches the material of the sacrificial semiconductor nanostructure 107 relative to the materials of the channel 105 and the substrate 102.

[0045] exist Figure 5In the trench, an internal spacer 130 has been formed. The internal spacer 130 is formed by depositing a dielectric layer on the exposed surfaces of the channel 105, the gate spacer layer 120, the sacrificial semiconductor nanostructure 107, and the substrate 102 in a conformal deposition process. Most notably, the dielectric layer fills the trench. The dielectric layer may include SiCN, SiOCN, SiON, SiN, or other suitable dielectric materials. The dielectric layer can be formed by suitable deposition methods, such as CVD, ALD, PVD, or other deposition processes.

[0046] The internal spacer 130 is formed by performing an anisotropic etching process in the downward direction. During the anisotropic etching process, the gate spacer layer 120 and the sacrificial gate structure 114 serve as a mask. The dielectric layer is removed from all locations exposed by the mask. As a result, the dielectric layer is removed from the trench 124. The portion of the dielectric layer retained in the trench corresponds to the internal spacer 130. The internal spacer 130 contacts the end of the sacrificial semiconductor nanostructure 107 and the channel 105. As will be further explained in detail below, the internal spacer 130 separates the gate metal from the source / drain regions.

[0047] Figures 6A to 6C This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 6D It is integrated circuit 100 in Figures 6A to 6C A top view of the processing stage shown. Figures 6A to 6C The cross-sectional views are taken along cut lines 6A, 6B, and 6C, respectively. Cut line 6A is taken through the portion of semiconductor fin 108a. Cut line 6B is taken in the Y direction through each of semiconductor fins 108a-108d, and more particularly through the source / drain regions 136a-136d of the transistor, as will be described in more detail below. Cut line 6C is taken in the Y direction through each of semiconductor fins 108a-108d, and more particularly through the gate metal 148 of the gate layout G2, as will be described in more detail below.

[0048] exist Figures 6A to 6D In this embodiment, a bottom semiconductor layer 132 has been formed on the substrate 102 and each source / drain trench 124. In some embodiments, the bottom semiconductor layer 132 comprises an intrinsic semiconductor material. In some embodiments, the semiconductor material of the semiconductor layer 132 is the same as the semiconductor material of the substrate 102.

[0049] exist Figures 6A to 6DIn this embodiment, a bottom dielectric structure 134 has been formed on the bottom semiconductor layer 132 in each source / drain trench 124. In some embodiments, the bottom semiconductor layer 132 comprises an intrinsic semiconductor material. The bottom dielectric structure 134 may comprise SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The bottom dielectric structure 134 may be formed by ALD, CVD, or PVD followed by a selected patterning process. The bottom dielectric structure 134 may help prevent leakage current from flowing between the source / drain regions 136 and the bottom semiconductor layer 132. In some embodiments, the bottom dielectric structure 134 has a thickness between 2 nm and 8 nm.

[0050] exist Figures 6A to 6D In the middle, a dielectric structure 135 has been formed in the groove of the isolation structure 112, such as in Figure 6B This is most clearly visible in the image. In some embodiments, the recess is formed by one or more etching processes that selectively etch the material of the isolation structure 112 relative to the material of the dielectric structure 121. The dielectric structure 135 may include SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The dielectric structure 135 may be formed by ALD, CVD, or PVD. In some embodiments, the recess in the isolation structure may be performed prior to the formation of the source / drain region 136. In some embodiments, the dielectric structure 135 is formed in the same process used to form the bottom dielectric structure 134.

[0051] exist Figures 6A to 6D In some embodiments, source / drain regions 136 have been formed in the source / drain trench 124. The source / drain regions 136 are epitaxially grown from the channel 105. The source / drain regions 136 grow on the exposed portion of the fin 108 and contact the channel 105. For each stack 126 of the channel 105, there are two source / drain regions 136. Some stacks 126 of the channel 105 may share the source / drain regions 136 with stacks 126 of the channel 105 adjacent to each other in the X direction.

[0052] Source / drain regions 136a are formed in semiconductor fin 108a. A channel 105a of each stack extends in the X direction between two adjacent source / drain regions 136a, as shown in... Figure 6AThis is most easily seen in the diagram. Source / drain regions 136b are formed in semiconductor fin 108b. A channel 105b of each stack extends in the X direction between two adjacent source / drain regions 136b. Source / drain regions 136c are formed in semiconductor fin 108c. A channel 105c of each stack extends in the X direction between two adjacent source / drain regions 136c. Source / drain regions 136d are formed in semiconductor fin 108d. A channel 105d of each stack extends in the X direction between two adjacent source / drain regions 136d.

[0053] The source / drain region 136 may comprise any acceptable semiconductor material, such as materials suitable for N-type or P-type devices. In some embodiments, for an N-type region, the source / drain region 136 comprises a material to which tensile strain is applied in the channel region, such as silicon, SiC, SiCP, SiP, etc. According to some embodiments, for a P-type transistor, the source / drain region 136 comprises a material to which compressive strain is applied in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain region 136 may have a surface protruding from the corresponding surface of the fin and may have a facet. Adjacent source / drain regions 136 may be merged in some embodiments to form a single source / drain region 136 over two adjacent fins 108.

[0054] In some embodiments, an in-situ doping process can be performed during the formation of the source / drain region 136 to implant an N-type or P-type dopant into the source / drain region 136, depending on the conductivity type of the transistor or region being formed. The N-type dopant may include phosphorus, arsenic, antimony, or other suitable N-type dopant materials. The P-type dopant may include boron, gallium, indium, or other suitable P-type dopant materials. The source / drain region 136 can be implanted with a dopant followed by an annealing process. The source / drain region 136 may have a conductivity of approximately 10... 19 cm -3 Peace Treaty 10 21 cm -3 The concentration of impurities between them.

[0055] As previously explained, in the specific examples given herein, semiconductor fins 108a and 108b correspond to the locations of P-type transistors. Therefore, source / drain regions 136a and 136b are P-type source / drain regions. As previously explained, in the specific examples given herein, semiconductor fins 108c and 108d correspond to the locations of N-type transistors. Therefore, source / drain regions 136c and 136d are N-type source / drain regions. In some embodiments, the P-type source / drain region 136 comprises one or more of boron-doped SiGe / Si or SiB. In some embodiments, the N-type source / drain region comprises one or both of SiP and SiAs.

[0056] In some embodiments, although Figure 6A and Figure 6B Each source / drain region 136 is shown as a single epitaxial layer, but in reality, each source / drain region 136 comprises multiple epitaxial layers. A first epitaxial layer of the source / drain region 136 is grown at the end of the channel 105. A second epitaxial layer of the source / drain region 136 is grown on the first epitaxial layer covering the sides of the internal spacer 130. A final epitaxial layer filling the source / drain trench 124 of the source / drain region 136 is grown on the second epitaxial layer. Each epitaxial layer of the source / drain region 136 may have a different material and doping distribution.

[0057] exist Figures 6A to 6D In some embodiments, a dielectric pad layer 138, a contact etch stop layer (CESL) 140, and an interlayer dielectric (ILD) 142 have been formed. In some embodiments, the dielectric pad layer 138 is a thin dielectric layer conformally deposited on the exposed surfaces of the source / drain regions 136, the exposed surfaces of the dielectric structure 121, the exposed surfaces of the isolation structure 112, the exposed surfaces of the dielectric structure 138, and the exposed surfaces of the gate spacer layer 120. The dielectric pad layer 138 may include SiO, SiN, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric pad layer 138 may be deposited by ALD, CVD, PVD, or other suitable deposition processes.

[0058] CESL 140 may include a thin dielectric layer conformally deposited on dielectric pad layer 138. CESL 140 may include SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. CESL 140 may be deposited by CVD, ALD, PVD, or other suitable deposition processes. In a particular example, dielectric pad layer 138 includes silicon oxide, and CESL 140 includes silicon nitride. Dielectric pad layer 138 and CESL 140 together correspond to CESL bilayer 141. In some embodiments, the thickness of CESL bilayer 141 is between 3 nm and 6 nm, but other thicknesses may be used without departing from the scope of embodiments of this disclosure.

[0059] Interlayer dielectric layer 142 covers CESL 140. Interlayer dielectric layer 142 fills the remaining spacing between adjacent sacrificial gate structures 114. Interlayer dielectric layer 142 may correspond to the bottommost interlayer dielectric layer of integrated circuit 100. In some embodiments, interlayer dielectric layer 142 may be referred to as ILD0. Although not shown herein, additional interlayer dielectric layers may be formed above interlayer dielectric layer 142. A network of conductive vias and metal lines may be formed in the upper interlayer dielectric layer. Interlayer dielectric layer 142 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. Interlayer dielectric layer 142 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0060] In some embodiments, a CMP process is performed after the deposition of the interlayer dielectric layer 142. The result of the CMP process is that the top surfaces of the interlayer dielectric layer 142, CESL 140, gate spacer layer 120, and sacrificial gate layer 118 are coplanar. The CMP process can also reduce the height of the sacrificial gate structure 114 and the gate spacer layer 120.

[0061] As in Figure 6B As can be seen, each of the source / drain layers 136 extends laterally above the isolation region 112. Furthermore, P-type source / drain regions 136a and 136b have been grown together above the adjacent isolation region 112. N-type source / drain regions 136c and 136d have also been grown together above the adjacent isolation region 112. The growth of adjacent source / drain regions together across the isolation region 112 can be termed a “bridge.” This is generally undesirable, depending on the circuit layout. Such a bridge is a factor limiting the downward scaling of the spacing between adjacent semiconductor fins. However, as will be explained in more detail below, embodiments of this disclosure provide an efficient and effective method and structure for cleaving adjacent source / drain regions 136.

[0062] exist Figures 6A to 6DIn some embodiments, the sacrificial gate layer 118 has been removed. The sacrificial gate layer 118 can be removed by an etching process that selectively etches the material of the sacrificial gate layer 118 relative to adjacent materials such as dielectric layer 116 and gate spacer layer 120. The removal of the sacrificial gate layer 118 creates gate trenches between the gate spacer layers 120.

[0063] exist Figures 6A to 6D In some embodiments, an etching process has been performed to remove the sacrificial semiconductor nanostructure 107. The sacrificial semiconductor nanostructure 107 can be removed by a selective etching process using an etchant selective to the material of the channel 105, thereby removing the sacrificial semiconductor nanostructure 107 without substantially etching the channel 105. The removal of the sacrificial semiconductor nanostructure 107 is referred to as “releasing” the channel 105. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, combinations thereof, etc. In some embodiments, the etching process rounds the sides of the channel 105. The etching process also creates gaps between the channels 105.

[0064] exist Figures 6A to 6D In some embodiments, a gate dielectric has been formed. The gate dielectric includes an interface gate dielectric layer 144 and a high-k gate dielectric layer 146. In some embodiments, the interface gate dielectric layer 144 has been deposited on an exposed portion of the channel 105. The interface gate dielectric layer 144 is formed directly on the exposed portion of the channel 105. The high-k gate dielectric layer 146 is formed on the interface gate dielectric layer 144 and on other exposed surfaces (such as the exposed sidewalls of the gate spacer layer 120 and the internal spacers 130).

[0065] Interface gate dielectric layer 144 surrounds channel 105. Interface gate dielectric layer 144 may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. Interface gate dielectric layer 144 may include a relatively low-k dielectric relative to a high-k dielectric (such as hafnium oxide or other high-k dielectric materials that can be used in the gate dielectric of a transistor). High-k dielectrics may include dielectric materials having a dielectric constant higher than that of silicon oxide. Interface gate dielectric layer 144 may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Interface gate dielectric layer 144 may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for interface gate dielectric layer 144 without departing from the scope of embodiments of this disclosure. Interface gate dielectric layer 144 in Figure 6A As shown in the image. Although Figure 6CAlthough not shown, the interface gate dielectric layer 144 is also present on the surface of the channel 105 between the channel 105 and the high-K gate dielectric layer 146.

[0066] A high-k gate dielectric layer 146 is deposited in a conformal deposition process. The conformal deposition process deposits the high-k gate dielectric layer 146 on the interface gate dielectric layer 144, on the substrate 102, and on the gate spacer layer 120. The high-k gate dielectric layer 146 surrounds the channel 105. The high-k gate dielectric layer 146 has a thickness between 1 nm and 3 nm. The high-k dielectric layer comprises one or more layers of dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The high-k gate dielectric layer 146 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials may be used for the high-k gate dielectric layer 146 without departing from the scope of embodiments of this disclosure.

[0067] exist Figures 6A to 6D In some embodiments, gate metal 148 has been deposited. Gate metal 148 is deposited in place of sacrificial gate layer 118 and sacrificial semiconductor nanostructure 107. Thus, gate metal 148 is positioned in a gate trench above hard mask layer 124 and hard mask layer 150. Gate metal 148 also surrounds channel 105.

[0068] like Figure 6C As can be seen, the gate metal 148 of gate layout G2 is short-circuited together around all channels 105. Each stack of channels 105a, 105b, 105c, and 105d represents an independent transistor 101a, 101b, 101c, and 101d, respectively. More specifically, each location where the gate metal 148 intersects with the semiconductor fin 108 corresponds to the location of an independent transistor 101. Figures 6A to 6D In the processing stage shown, the gate electrodes of all transistors 101a-101d in gate region G2 are short-circuited together. This also applies to the other gate regions G1 and G3. As will be described in more detail below, embodiments of this disclosure provide an efficient and effective method and structure for dicing gate metal 148 at selected locations. More specifically, gate metal 148 and source / drain regions 136 are diced using a single process, forming a dielectric isolation structure and a break.

[0069] Figure 6D The gate metal 148 of each gate region G1-G3 extends uninterruptedly across fins 108a-108d. Figure 6DThe dashed lines in the diagram indicate the locations of semiconductor fins 108a-108d located in the gate regions G1-G3, the gate spacer layer 120, a portion of the high-K gate dielectric layer 146 on the sidewall of the gate spacer layer 120, the interlayer dielectric layer 142, and the CESL double layer 141.

[0070] exist Figures 6A to 6D The diagram illustrates a single gate metal 148 as the gate electrode of transistor 101. However, in practice, gate metal 148 can comprise various gate metals. For example, gate metal 148 can comprise one or more pad layers, one or more function layers, and gate fill material filling the remaining space between gate spacer layers 120. Gate metal 148 can comprise one or more of Ti, TiN, Ta, TaN, Al, Cu, Co, Ru, W, Au, or other suitable conductive materials. Gate metal 148 can be deposited by PVD, ALD, or CVD.

[0071] After the gate metal 148 is formed, a CMP process is performed to reduce the height of the gate metal 148 and to create a flat top surface for the remaining structure.

[0072] According to some embodiments, the critical dimension of the semiconductor fin 108 in the Y direction is between 10 nm and 90 nm. Other dimensions may be used without departing from the scope of embodiments of this disclosure.

[0073] Figure 7A and Figure 7B This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 7A The cross-sectional view corresponds to Figure 6B The location of the cross-sectional view is shown, but it is in the subsequent processing stage. Figure 7B The cross-sectional view corresponds to Figure 6C The location of the cross-sectional view is in the subsequent processing stage.

[0074] exist Figure 7A and Figure 7B In this embodiment, a dielectric layer 152 has been formed on the top surface of the integrated circuit 100. Specifically, the dielectric layer 152 is located on the top surface of the gate metal 148, the interlayer dielectric layer 142, and other exposed structures. In some embodiments, the dielectric layer 152 comprises SiN, SiON, SiOCN, SiOC, or other suitable materials. According to some embodiments, the dielectric layer 152 helps prevent oxidation of the underlying structures.

[0075] exist Figure 7A and Figure 7BIn this embodiment, layer 154 has been formed on dielectric layer 152. In some embodiments, layer 154 has a material selected for use as a stop layer for subsequent CMP processes. In some embodiments, layer 154 comprises amorphous silicon. Other materials may be used without departing from the scope of embodiments of this disclosure. Layer 154 may be deposited by ALD, CVD, PVD or other suitable deposition processes.

[0076] exist Figure 7A and Figure 7B In this embodiment, a hard mask layer 156 has been formed on the dielectric layer 154. In some embodiments, the hard mask layer 156 has a material selected for use as a stop layer for subsequent CMP processes. In some embodiments, the hard mask layer 156 comprises SiN, SiON, SiOCN, SiOC, or other suitable materials. Other materials may be used without departing from the scope of embodiments of this disclosure. The hard mask layer 156 may be deposited by ALD, CVD, PVD, or other suitable deposition processes.

[0077] In some embodiments, the hard mask layer 156 may be referred to as a reverse-cut gate metal layer. In particular, the trenches formed in the hard mask layer 156 correspond to locations where the gate metal 148 will not be cut, as will be explained in more detail below.

[0078] Figure 8A and Figure 8B This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 8C This is a top view of an integrated circuit 100 according to some embodiments. Figure 8A and Figure 8B The cross-sectional view is from Figure 8C Cut along cutting lines 8A and 8B.

[0079] exist Figures 8A to 8C In some embodiments, an etching process has been performed in conjunction with photolithography to form a plurality of trenches 158. The trenches 158 extend downward through the hard mask layer 156, layer 154, and dielectric layer 152. A portion of the trenches 158 extends into the dielectric layer 142 and the gate metal 148. Specifically, the bottom of the trenches 158 corresponds to the gate metal 148 (see...). Figure 8B ) and interlayer dielectric layer 142 (see Figure 8A The groove 158 is a recess in the top surface of the semiconductor fins 108b and 108c. The trench 158 extends in the X direction above the isolation structure 112 between the semiconductor fins 108b and 108c (see [link]). Figure 8C The location of trench 158 corresponds to the location where the gate metal 148 will not be cut.

[0080] Figure 8CThe top view shows the gate metal 148 exposed at some locations in the trench 158 and the interlayer dielectric layer 142 exposed at other locations. The gate regions G1-G3 and the semiconductor fins 108a-108d are located in... Figure 8C It is shown in dashed lines.

[0081] Figure 9A , Figure 9B and Figure 9C This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 9D This is a top view of an integrated circuit 100 according to some embodiments. Figure 9A and Figure 9B The cross-sectional view is from Figure 9D Cut along cutting lines 9A and 9B.

[0082] exist Figures 9A to 9D In some embodiments, a cover member structure 160 has been formed in the recess of the gate metal 148 at the bottom of the trench 158. The cover member is formed by a deposition process that selectively grows the cover member structure 160 on the gate metal 148, but not on the exposed dielectric structure. (As in...) Figure 9A As can be seen, the covering component structure 160 does not exist in the recess in the interlayer dielectric layer 142. Figure 9B The cover member structure 160 is shown filling the recess in the gate metal 148 and extending above the dielectric layer 152, and is centered between the top and bottom surfaces of layer 154. Other heights of the cover member structure 160 may be utilized without departing from the scope of embodiments of this disclosure. Figure 9C A trench 158 extending between the two gate regions G1 and G2 is shown. Although Figure 9C The diagram shows that trench 158 extends only in the X direction between gate regions G1 and G2, but in reality, trench 158 extends in the X direction as shown in the diagram. Figure 9D It extends as shown in the diagram, such as the gate region G3.

[0083] In some embodiments, the overlay structure 160 is formed in a CVD, ALD, or PVD process. In some embodiments, the selective growth mechanism is defined as selectively growing on the surface of the gate metal 140 after exchanging electrons with the material surface. Therefore, this is applicable to conductive materials (e.g., gate metal 148) but not to dielectric materials. In one example, according to some embodiments, the overlay structure includes ruthenium. In one example, the gate metal 148 includes tungsten. Ruthenium is chosen because, in some embodiments, the gate metal 148 can be selectively etched relative to ruthenium. Therefore, in locations where the gate metal 148 is covered by ruthenium, the gate metal 148 will not be etched during subsequent metal gate dicing processes. Other materials may be used for the overlay structure 160 and the gate metal 148 without departing from the scope of embodiments of this disclosure. In some embodiments, the thickness of the overlay structure 160 is between 2 nm and 20 nm, but other dimensions may be utilized without departing from the scope of embodiments of this disclosure. In some embodiments, the overlay structure 160 has a width between 10 nm and 30 nm in the Y direction. In some embodiments, the covering component structure is a covering metal or a covering metal structure.

[0084] Figure 10A and Figure 10B This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 10A and Figure 10B In this process, a dielectric layer 162 has been deposited on the hard mask layer 156 and in the trench 158. The dielectric layer 162 can be deposited by CVD, ALD, PVD or other suitable deposition processes. The dielectric layer 162 may include SiN, SiON, SiOCN, SiOC or other suitable dielectric materials.

[0085] Figure 11A and Figure 11B This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 11A and Figure 11B In this process, CMP technology has been implemented. CMP removes the dielectric layer 162 and hard mask layer 156 located above the top surface of layer 154. As previously explained, layer 154 is the stop layer for the CMP process. Therefore, dielectric layer 162 is located at the interlayer dielectric layer 142 (see...). Figure 11A The recessed neutralization and cover component structure 160 in the ) (see Figure 11B The remaining portion of the layer has a top surface that is coplanar with the top surface of layer 154.

[0086] Figure 12A and Figure 12B This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 12A and Figure 12BIn this process, a hard mask layer 164 has been deposited on the top surface of layer 154 and the remainder of dielectric layer 162. Hard mask layer 164 may include SiN, SiON, SiOCN, SiC, or other suitable dielectric materials. Hard mask layer 164 can be deposited using CVD, ALD, PVD, or other suitable deposition processes.

[0087] Figure 13A and Figure 13B This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 13A and Figure 13B In the process, an etching process has been performed in conjunction with photolithography to form trench 166. Trench 166 extends in the X direction over the isolation structure 112 located laterally between adjacent fins. The location of trench 166 corresponds to the location where the gate metal 148 will be cut (except for the location blocked by the cover member structure 160) and the location where the source / drain region 136 will be cut. The etching process partially etches to the gate metal 148 (see...). Figure 13B ) and interlayer dielectric layer 142 (see Figure 13A In the ), the unetched gate metal 148 is covered by the cover component structure 160. Figure 13A and Figure 13B The etching process shown can be referred to as the initial etching step of the etching process to cut the gate metal 148 and the source / drain region 136.

[0088] Figure 14A and Figure 14B This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 14C This is a top view of an integrated circuit 100 according to some embodiments. Figure 14A and Figure 14B The cross-sectional view is from Figure 14C Cut along cutting lines 14A and 14B.

[0089] exist Figures 14A to 14C In some embodiments, a further etching step in the etching process has been implemented. For example... Figure 14AAs can be seen, the etching process extends the depth of the trench 166 through the source / drain region 136. Most specifically, the source / drain regions 136 are etched at locations where they connect thin, adjacent source / drain regions. Specifically, the trench 166 extending downward between semiconductor fins 108a and 108b cuts the portions of the source / drain regions 136a and 136b that have grown together, thereby physically and electrically isolating them from each other. The trench 166 extending downward between semiconductor fins 108b and 108c cuts the portions of the source / drain regions 136b and 136c that have grown together, thereby physically and electrically isolating them from each other. The trench 166 extending downward between semiconductor fins 108c and 108d cuts the portions of the source / drain regions 136c and 136c that have grown together, thereby physically and electrically isolating them from each other.

[0090] In some embodiments, trenches 166 have a tapered profile, wherein their width decreases with depth (narrower at the bottom than at the top). In some embodiments, to form trenches 166, different materials should be etched, such as dielectric layer 142 (oxide in some embodiments), CESL 140 (nitride in some embodiments), and source / drain regions 136 (silicon in some embodiments), thus producing different profiles. Therefore, in some embodiments, different sidewall profiles may appear on dielectric layer 142, source / drain regions 136a, layer 121, etc., due to the different materials. For example, if the etchant is more favorable for etching the dielectric material of dielectric layer 142 than the semiconductor material of source / drain regions 136, the sidewalls of dielectric layer 142 can be etched more, and it will extend deeper in the Y direction. In some embodiments, trenches for dicing source / drain regions 136 have a different depth than trenches for dicing gate metal.

[0091] like Figure 14BAs can be seen, the etching process extends the depth of the trench 166 through the gate metal 148 (except where there are overlay structures 160). More specifically, the gate metal 148 is etched at those locations. Specifically, the trench 166 extending downward between semiconductor fins 108a and 108b divides the gate metal 148 into gate metal portions 148a and 148bc. Gate metal portion 148a encloses the channel 148a of transistor 101a. Gate metal portion 148a corresponds to the gate electrode of transistor 101a. Gate metal portion 148bc encloses the channel 105b of transistor 101b and the channel 105c of transistor 101c. Gate metal portion 148bc corresponds to the common gate electrode of transistors 105b and 105c. In other words, the gate electrodes of transistors 105b and 105c are short-circuited together. Gate metal portions 148a and 148bc are electrically and physically isolated from each other. According to the circuit layout, the cover component structure 160 is positioned at the location where the gate electrodes of adjacent transistors are expected to be electrically short-circuited to each other.

[0092] A trench 166 extending downward between semiconductor fins 108c and 108d cuts through gate metal portion 148d from gate metal portion 148bc. Gate metal portions 148bc and 148d are electrically and physically isolated from each other.

[0093] The formation of trench 166 includes etching through portions of hard mask layer 164, layer 154, dielectric layer 152, interlayer dielectric layer 142, CESL layer 140, dielectric layer 138, dielectric structure 121 and isolation structure 112.

[0094] Figure 15A and Figure 15B This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 15A and Figure 15B In this process, a dielectric liner layer 170 has been conformally deposited on all exposed surfaces. Most notably, the dielectric liner layer 170 lines the sidewalls of the trench 166. The dielectric liner layer 170 comprises one of SiN, SiON, SiOCN, SiCN, or other suitable dielectric materials. The dielectric liner layer 170 can be deposited using ALD, CVD, PVD, or other suitable deposition processes.

[0095] exist Figure 15A and Figure 15BIn some embodiments, a dielectric layer 172 has been deposited on the dielectric pad layer 170. Most specifically, the dielectric layer fills the remaining portion of the trench 166. The dielectric layer 172 comprises one of SiN, SiON, SiOCN, SiCN, or other suitable dielectric materials. The dielectric layer 172 can be deposited by ALD, CVD, PVD, or other suitable deposition processes. In one example, the dielectric pad layer 170 comprises SiN, and the dielectric layer 172 comprises SiO. In some embodiments, the dielectric layer 172 comprises tetraethyl orthosilicate. In some embodiments, a single dielectric layer is used instead of both the dielectric layer 172 and the dielectric pad layer 170.

[0096] Figure 16A and Figure 16B This is a cross-sectional view of an integrated circuit 100 according to one embodiment. Figure 16C This is a top view of an integrated circuit 100 according to some embodiments. Figure 16A and Figure 16B The cross-sectional view is from Figure 16C Cut along cutting lines 16A and 16B.

[0097] exist Figures 16A to 16C In some embodiments, a dielectric isolation structure 174 has been formed in trench 166. More specifically, a CMP process has been performed to remove excess layer above the top surface of interlayer dielectric layer 142. As a result, hard mask layer 164, layer 154, and dielectric layer 152 have been removed. Layer 154 can be removed by using methods or chemicals in the CMP process of etching layer 154, thereby rendering it unusable as a stop layer for that particular CMP process. Furthermore, excess material from dielectric pad layer 170 and dielectric layer 172 has been removed.

[0098] The CMP process leaves a dielectric isolation structure 174 in trench 166, consisting of a dielectric liner layer 170 and a dielectric layer 172. The dielectric isolation structure 174 electrically isolates and physically separates adjacent source / drain regions 136 from each other. The dielectric isolation structure 174 also electrically isolates and physically separates adjacent portions of the gate metal 148. In some embodiments, the dielectric isolation structure 174 has a width in the Y direction between portions of the gate metal 148. In some embodiments, the dielectric isolation structure 174 has a depth between 110 nm and 160 nm. Other dimensions may be utilized without departing from the scope of embodiments of this disclosure.

[0099] As described above, the gate metal 148 and the source / drain region 136 are cut in the same process. A common ground cover 160 is used to prevent the gate metal 148 from being placed at the selected location. A dielectric isolation structure 174 is formed in the same process between adjacent portions of the source / drain region 136 and the gate metal 148.

[0100] In some embodiments, the lateral surface of the source / drain region 136 above the isolation structure 112 is vertical. In some embodiments, the width of the dielectric isolation structure 174 is between 10 nm and 30 nm, but other widths may be used without departing from the scope of embodiments of this disclosure. In some embodiments, the depth of the dielectric isolation structure 174 relative to the top of the gate metal 148 is between 80 nm and 180 nm, but other dimensions may be used without departing from the scope of embodiments of this disclosure.

[0101] Figure 17 This is a cross-sectional view of an integrated circuit 100 according to some embodiments.

[0102] exist Figure 17 In this process, a dielectric layer 176 has been deposited on the gate metal 148, the gate spacer layer 120, and other exposed surfaces. The dielectric layer 176 may include SiN, SiCN, SiON, SiOCN, SiOC, or other suitable dielectric materials. The dielectric layer 176 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0103] exist Figure 17 In some embodiments, an interlayer dielectric layer 178 has been deposited. The interlayer dielectric layer 178 may include SiO, SiN, SiON, SiOC, SiOCN, or other suitable deposition processes. The interlayer dielectric layer 178 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0104] Figure 17 The source / drain region 136 is shown to include a first epitaxial layer 137. As previously described, the source / drain region 136 may include a first epitaxial layer grown from the end of the channel 105, a second epitaxial layer grown on the first epitaxial layer, and a main epitaxial fill layer.

[0105] exist Figure 17In this process, the source / drain regions 136 have been recessed, and a silicide layer 180 has been formed in preparation for forming the source / drain contacts 182. The formation of the silicide layer 180 may include: depositing a thin metal layer, such as Ti, Ni, Al, Ta, or other suitable materials; and performing a thermal annealing process that forms the silicide layer 180 from the metal layer. Therefore, the silicide layer 180 may include titanium silicide, nickel silicide, aluminum silicide, tantalum silicide, or other suitable silicides.

[0106] After forming the silicide layer 180, source / drain contacts 182 are formed on the silicide layer 180. The source / drain contacts 182 comprise a metal, such as W, Ta, Ti, Al, Ru, Co, Au, or other suitable materials. The source / drain contacts 182 can be formed by PVD, ALD, CVD, or other suitable deposition processes. In some embodiments, the source / drain contacts 182 comprise one or more pad layers of TiN, TaN, or other materials, followed by the deposition of a metal filler material for the source / drain contacts 182. Figure 17 In the process, a pad layer 184 is formed before the source / drain contacts 182 are formed. The pad layer may include a dielectric material or a conductive material.

[0107] exist Figure 17 In this process, a dielectric layer 186 has been formed on the source / drain contact 182 and the interlayer dielectric layer 178. The dielectric layer 186 may include SiN, SiCN, SiON, SiOCN, SiOC, or other suitable dielectric materials. The dielectric layer 186 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0108] exist Figure 17 In this process, an interlayer dielectric layer 188 has been formed on the dielectric layer 186. The interlayer dielectric layer 188 may include SiO, SiN, SiCN, SiON, SiOCN, SiOC, or other suitable dielectric materials. The interlayer dielectric layer 188 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0109] exist Figure 17 In the diagram, a conductive via 190 has been formed to contact the selected source / drain contact 182. The conductive via can be formed by first forming holes in dielectric layers 188 and 186 to expose the selected source / drain contact. The holes can be filled by depositing a conductive material. The conductive material can include W, Ti, Al, Au, Co, Cu, TiN, TaN, or other suitable conductive materials. The conductive material can be deposited using PVD, ALD, CVD, or other suitable deposition processes. Dashed box 191 shows the outline of a gate contact configured to contact the gate metal 148 at a selected location, or in… Figure 17In the cutting, or offset in the Y direction.

[0110] Figure 18 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 18 The view relative to Figures 1 to 17 The view is flipped vertically. Figure 18 In the process, after forming metal lines and conductive vias on transistor 101, the integrated circuit is flipped to form metal lines and conductive vias on the back side of integrated circuit 100.

[0111] In some embodiments, this includes a CMP or polishing process to remove portions of the semiconductor substrate 102 to expose the isolation structure 112, depositing a back-side substrate material such as one or more dielectric layers, and forming trenches to expose the source / drain regions 136. A silicide 192 is formed on the back side of the source / drain trench 136. The silicide 192 may be substantially similar to the silicide 180. In some embodiments, the silicide 192 comprises TiSi, MoSi, RuSi, Zr Eiffel material, or other suitable materials. The silicide 192 may have a thickness between 1 nm and 5 nm, but other dimensions may be utilized without departing from the scope of embodiments of this disclosure.

[0112] Then, a back-side source / drain contact 194 electrically connected to the source / drain region 136 is formed. In some embodiments, the back-side source / drain contact 194 comprises W, Ru, Mo, or other suitable materials. In some embodiments, the back-side source / drain contact 194 has a critical dimension between 8 nm and 16 nm, but other materials may be used without departing from the scope of embodiments of this disclosure.

[0113] A dielectric liner layer 196 can be deposited in a back-side trench. The dielectric liner layer 196 may include SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The dielectric liner layer 196 may have a thickness between 1 nanometer and 5 nm, but other thicknesses may be used without departing from the scope of embodiments of this disclosure.

[0114] Figures 19 to 21 This is a cross-sectional view of the integrated circuit 100 at various processing stages according to some embodiments.

[0115] Figure 19 The integrated circuit 100 according to some embodiments is substantially similar to that regarding Figures 6A to 6D The diagram shows a cross-sectional view of the processing stage. In other words, the source / drain region 136 and the gate metal 148 have been formed. Figure 19 and Figures 1 to 18The difference is that the semiconductor fins 108 are spaced further apart, so that the source / drain regions 136 are not connected to each other above the isolation structure 112.

[0116] Figure 20 The integrated circuit 100 according to some embodiments is substantially similar to that regarding Figure 11A and Figure 11B The diagram shows a cross-sectional view of the processing stage. The remainder of dielectric layer 162 is shown in a recess in the interlayer dielectric layer 142. Although Figure 20 Although not shown, the cover component structure 160 has been formed at the selected location.

[0117] Figure 21 The integrated circuit 100 according to some embodiments is substantially similar to that regarding Figures 16A to 16C The diagram shows a cross-sectional view of the processing stage. Specifically, a dielectric isolation structure 174 has been formed between adjacent portions of the gate metal 148 and between adjacent source / drain regions 136.

[0118] Figure 22A and Figure 22B The integrated circuit 100 according to some embodiments is substantially similar to Figures 16A to 16C The diagram shows a cross-sectional view of the processing stage. A dielectric isolation structure 174 has been formed. Figure 22A and Figure 22B The difference in structure is that the dielectric isolation structure 174 is shallower and does not extend near the bottom of the isolation structure 112.

[0119] Figure 23 The integrated circuit 100 according to some embodiments is substantially similar to Figures 16A to 16C The diagram shows a cross-sectional view of the processing stage. A dielectric isolation structure 174 has been formed. Figure 23 The structural difference lies in that adjacent source / drain regions 136 are further spaced apart, thus preventing bridging, and the dielectric isolation structure 174 does not cut through the source / drain regions 136. The dielectric isolation structure 174 is shallower and does not extend near the bottom of the trench isolation structure 112.

[0120] Figure 24 This is a flowchart of a method 2400 for forming an integrated circuit according to some embodiments. Method 2400 can utilize... Figures 1 to 23 The described structure, process, and system.

[0121] In method 2402, method 2400 includes forming a first semiconductor fin extending in a first lateral direction. In method 2404, method 2400 includes forming a second semiconductor fin extending in the first lateral direction. In method 2406, method 2400 includes depositing a first isolation structure between the first semiconductor fin and the second semiconductor fin. An example of the first semiconductor fin and the second semiconductor fin is... Figure 2B The first semiconductor fin 108a and the second semiconductor fin 108b. An example of the first isolation structure is... Figure 2B The isolation structure 112. In 2408, method 2400 includes a gate metal deposited across a first semiconductor fin, a second semiconductor fin, and a first isolation structure, extending in a second lateral direction transverse to the first lateral direction. An example of the gate metal is... Figures 6A to 6D The gate metal 148. In 2410, method 2400 includes growing a first source / drain region in the first fin that extends partially above the first isolation structure, forming a first transistor. In 2412, method 2400 includes growing a second source / drain region in the second fin that extends partially above the first isolation structure, forming a second transistor. An example of the first source / drain region and the second source / drain region is... Figure 6B The first source / drain region 136a and the second source / drain region 136b. In 2414, method 2400 includes depositing a cover component in a groove in the top surface of the gate metal. An example of the cover component is... Figure 9B Covering component 160. In 2416, method 2400 includes forming a dielectric isolation structure extending in a first lateral direction between a first source / drain region and a second source / drain region and between a first portion and a second portion of the gate metal, the dielectric isolation structure electrically isolating the first source / drain region and the second source / drain region from each other, and electrically isolating the first portion and the second portion of the first gate metal from each other. An example of the dielectric isolation structure is... Figures 16A to 16C The dielectric isolation structure 174.

[0122] Figure 25 This is a flowchart of a method 2500 for forming an integrated circuit according to some embodiments. Method 2500 can utilize... Figures 1 to 23 The described structure, process, and system. In 2502, method 2500 includes forming a first isolation structure between a first semiconductor fin and a second semiconductor fin. An example of the first semiconductor fin and the second semiconductor fin is... Figure 2B Semiconductor fins 108a and 108b. In method 2504, method 2500 includes forming a second isolation structure between the second semiconductor fin and the third semiconductor fin, the first semiconductor fin and the second semiconductor fin, and the first isolation structure and the second isolation structure extending in a first lateral direction. An example of the first isolation structure and the second isolation structure is... Figure 2B The isolation structure 112. In 2506, method 2500 includes depositing gate metal extending across the first semiconductor fin and the second semiconductor fin, as well as the first isolation structure and the second isolation structure, in a second lateral direction transverse to the first lateral direction. An example of gate metal is... Figures 6A to 6D The gate metal 148. In 2508, method 2500 includes depositing a cover portion on the gate metal at a first location above the second isolation structure. An example of the cover portion is... Figure 9B Covering component 160. In 2510, method 2500 includes electrically isolating a first portion of gate metal from a second portion of gate metal by forming a first trench using an etching process. The first trench extends through the gate metal in a first lateral direction over the isolation structure and extends between a first source / drain region of a first semiconductor fin and a second source / drain region of a second semiconductor fin, the first and second source / drain regions extending partially over the first isolation structure. An example of the first trench is... Figure 14B Trench 166. An example of the second source / drain region is Figure 14A The source / drain regions 136a and 136b. In 2512, method 2500 includes forming a second trench extending in a first lateral direction over the second isolation structure using an etching process, wherein the first cover member protects the gate metal from being etched by the etching process at the first location. An example of the second trench is... Figure 14B The groove 166 is on the cover part 160.

[0123] Embodiments of this disclosure enable the formation of transistor arrays that efficiently and effectively isolate the source / drain regions of adjacent transistors and the gate electrodes of adjacent transistors. After forming the source / drain regions and gate metal of the transistors, a dielectric isolation structure is formed in the same dicing / isolation process to separate adjacent portions of the gate metal (at the gate dicing location) and adjacent source / drain regions of different transistors (at the source / drain dicing locations). Prior to this process, a cover member is formed at selected locations on the gate metal where the gate is not diced. After forming the cover member, the dicing / isolation process includes an etching process that etches the source / drain regions and gate metal at desired locations, while the gate metal is protected by the cover member at other locations. The dicing / isolation process includes forming a dielectric isolation structure extending through the dicing location. This allows for further scaling down the distance between adjacent active regions. Wafer yield and device performance are improved with a simple and efficient process.

[0124] The formation and processing of the first and second gate spacer sublayers result in high resistance to subsequent etching processes. As a result, portions of the gate spacer layer are not undesirably removed. This further prevents leakage and short circuits between the subsequently formed gate metal and source / drain contact metal. It also reduces the capacitance between the gate metal and source / drain contact metal. Therefore, transistors with improved switching speeds and other electrical characteristics can be appropriately formed. Integrated circuits incorporating transistors have improved functionality. Wafer yield is increased, and the performance of electronic devices mounted with integrated circuits is improved.

[0125] In some embodiments, the method includes: forming a first semiconductor fin extending in a first lateral direction; forming a second semiconductor fin extending in the first lateral direction; and forming a first isolation structure between the first semiconductor fin and the second semiconductor fin. The method includes: forming a gate metal extending in a second lateral direction transverse to the first lateral direction across the first semiconductor fin, the second semiconductor fin, and the first isolation structure; forming a first source / drain region extending partially above the first isolation structure in the first fin, where a first transistor is formed; and forming a second source / drain region extending partially above the first isolation structure in the second fin, where a second transistor is formed. The method includes: forming a cover member in a recess in the top surface of the gate metal; and forming a dielectric isolation structure extending in the first lateral direction between the first source / drain region and the second source / drain region, and between a first portion and a second portion of the gate metal. The dielectric isolation structure electrically isolates the first source / drain region and the second source / drain region from each other, and electrically isolates the first portion and the second portion of the first gate metal from each other.

[0126] In some embodiments, the method includes: forming a first isolation structure between a first semiconductor fin and a second semiconductor fin; and forming a second isolation structure between a second semiconductor fin and a third semiconductor fin. The first semiconductor fin and the second semiconductor fin, as well as the first isolation structure and the second isolation structure, extend in a first lateral direction. The method includes: forming gate metal extending across the first semiconductor fin and the second semiconductor fin, as well as the first isolation structure and the second isolation structure, in a second lateral direction transverse to the first lateral direction; and forming a cover member on the gate metal at a first location above the second isolation structure. The method includes: electrically isolating a first portion of gate metal from a second portion of gate metal by forming a first trench using an etching process, the first trench extending through the gate metal in the first lateral direction above the isolation structure and extending between a first source / drain region of the first semiconductor fin and a second source / drain region of the second semiconductor fin. The first source / drain region and the second source / drain region partially extend above the first isolation structure. The method includes: forming a second trench extending in the first lateral direction on the second isolation structure using an etching process. The first cover member protects the gate metal at the first location from being etched by the etching process.

[0127] In some embodiments, the device includes: a first active region extending in a first lateral direction; a second active region extending in the first lateral direction; and a third active region extending in the first lateral direction. The device includes: a first isolation structure located between the first and second active regions; and a second isolation structure located between the second and third active regions. The device includes: gate metal extending across the first active region, the second active region, the third active region, the first isolation structure, and the second isolation structure in a second lateral direction lateral to the first lateral direction. The device includes: a first transistor located in the first active region and including a first source / drain region extending partially above the first isolation structure; and a second transistor located in the second active region and including a second source / drain region extending partially above the first isolation structure. The device includes: a cover member located in a recess in the top surface of the gate metal above the first isolation structure; and a first dielectric isolation structure extending in the first lateral direction between the first and second source / drain regions and between a first portion and a second portion of the gate metal. The dielectric isolation structure electrically isolates the first and second portions of the gate metal from each other.

[0128] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first semiconductor fin extending in a first lateral direction; forming a second semiconductor fin extending in the first lateral direction; depositing a first isolation structure between the first semiconductor fin and the second semiconductor fin; depositing a gate metal extending in a second lateral direction transverse to the first lateral direction across the first semiconductor fin, the second semiconductor fin, and the first isolation structure; growing a first source / drain region of a first transistor extending partially above the first isolation structure in the first fin; growing a second source / drain region of a second transistor extending partially above the first isolation structure in the second fin; depositing a cover member in a groove in the top surface of the gate metal; and forming a dielectric isolation structure extending in the first lateral direction between the first source / drain region and the second source / drain region and between a first portion and a second portion of the gate metal, the dielectric isolation structure electrically isolating the first source / drain region and the second source / drain region from each other, and electrically isolating the first portion and the second portion of the first gate metal from each other.

[0129] In some embodiments, the method further includes: recessing the gate metal to form the groove therein; and depositing the cover member in the groove on the second portion of the gate metal. In some embodiments, the method further includes: forming a third semiconductor fin extending in the first lateral direction; and forming a second isolation structure between the second semiconductor fin and the third semiconductor fin, wherein the groove and the cover member are located above the second isolation structure. In some embodiments, the second portion of the gate metal is a common gate electrode of the second transistor and the third transistor of the third semiconductor fin. In some embodiments, the method further includes: forming a first mask structure over the first gate metal, the first semiconductor fin and the second semiconductor fin, and the first source / drain region and the second source / drain region; forming the groove in the first gate metal by forming a first trench through the first mask structure; and forming the cover member by selectively depositing the cover member in the recess of the first gate metal. In some embodiments, the method further includes: forming a second mask structure over the first gate metal, the first semiconductor fin and the second semiconductor fin, the first isolation structure and the first source / drain region and the second source / drain region; patterning the mask structure to form a second trench and a third trench, the second trench extending over the first isolation structure in the first lateral direction, the third trench exposing the cover member; and forming the dielectric isolation structure in the second trench. In some embodiments, forming the second trench includes removing portions of the first source / drain region, the second source / drain region and the first gate metal using an etching process. In some embodiments, the cover member prevents the third trench from extending into the first gate metal. In some embodiments, forming the dielectric isolation structure includes: forming a first dielectric layer lining the sidewalls of the second trench; and depositing a second dielectric layer in the second trench. In some embodiments, the third trench extends between the third source / drain region of the third transistor and the fourth source / drain region of the fourth transistor.

[0130] Other embodiments of this application provide a method of forming a semiconductor device, comprising: forming a first isolation structure between a first semiconductor fin and a second semiconductor fin; forming a second isolation structure between the second semiconductor fin and a third semiconductor fin, the first semiconductor fin and the second semiconductor fin, as well as the first isolation structure and the second isolation structure, extending in a first lateral direction; depositing gate metal extending across the first semiconductor fin and the second semiconductor fin, as well as the first isolation structure and the second isolation structure, in a second lateral direction different from the first lateral direction; depositing a cover member on the gate metal at a first location above the second isolation structure; electrically isolating a first portion of the gate metal from a second portion of the gate metal by forming a first trench using an etching process, the first trench extending through the gate metal in the first lateral direction above the isolation structure and extending between a first source / drain region of the first semiconductor fin and a second source / drain region of the second semiconductor fin, the first source / drain region and the second source / drain region extending partially above the first isolation structure; and forming a second trench extending in the first lateral direction on the second isolation structure using the etching process, wherein the first cover member protects the gate metal at the first location from being etched by the etching process.

[0131] In some embodiments, forming the first trench includes removing at least a portion of the first source / drain region and at least a portion of the second source / drain region. In some embodiments, the method further includes forming a first dielectric isolation structure in the first trench extending between the first and second portions of the gate metal and between the first and second source / drain regions. In some embodiments, the method further includes forming a second dielectric isolation structure in the second trench extending between a third source / drain region of the first semiconductor fin and a fourth source / drain region of the third semiconductor fin. In some embodiments, forming the cover member includes: exposing the gate metal at the first location; and performing a deposition process that selectively grows the cover member on the gate metal but not on a dielectric surface. In some embodiments, the first dielectric isolation structure is laterally separated from the first source / drain region by an interlayer dielectric layer.

[0132] Further embodiments of this application provide a semiconductor device, including: a first active region extending in a first lateral direction; a second active region extending in the first lateral direction; a third active region extending in the first lateral direction; a first isolation structure located between the first active region and the second active region; a second isolation structure located between the second active region and the third active region; a gate metal extending across the first active region, the second active region, the third active region, the first isolation structure, and the second isolation structure in a second lateral direction different from the first lateral direction; and a first transistor located in the first... The active region includes a first source / drain region extending partially above the first isolation structure; a second transistor located in the second active region and including a second source / drain region extending partially above the first isolation structure; a cover member located in a recess in the top surface of the gate metal above the first isolation structure; and a first dielectric isolation structure extending in the first lateral direction between the first source / drain region and the second source / drain region and between a first portion and a second portion of the gate metal, the dielectric isolation structure electrically isolating the first portion and the second portion of the gate metal from each other.

[0133] In some embodiments, the cover member is a cover metal. In some embodiments, the semiconductor device further includes: a third transistor located in the third active region and including a third source / drain region; a fourth transistor located in the second active region and including a fourth source / drain region; and a second dielectric structure extending in the first lateral direction between the third and fourth source / drain regions and adjacent to a side of a gate metal adjacent to the cover member. In some embodiments, the cover member includes ruthenium, and the gate metal includes tungsten.

[0134] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A first semiconductor fin extending in the first lateral direction is formed; A second semiconductor fin is formed extending in the first lateral direction; A first isolation structure is deposited between the first semiconductor fin and the second semiconductor fin; A gate metal is deposited across the first semiconductor fin, the second semiconductor fin, and the first isolation structure, extending in a second lateral direction that is transverse to the first lateral direction; A first source / drain region extending above the first isolation structure is partially grown in the first fin; A second source / drain region extending partially above the first isolation structure is grown in the second fin; A cover component is deposited in a groove on the top surface of the gate metal; as well as A dielectric isolation structure extending in the first lateral direction is formed between the first source / drain region and the second source / drain region and between the first portion and the second portion of the gate metal, the dielectric isolation structure electrically isolating the first source / drain region and the second source / drain region from each other, and electrically isolating the first portion and the second portion of the first gate metal from each other.

2. The method according to claim 1, further comprising: The gate metal is recessed to form the groove therein; as well as The cover member is deposited in the groove on the second portion of the gate metal.

3. The method according to claim 2, further comprising: A third semiconductor fin is formed extending in the first lateral direction; as well as A second isolation structure is formed between the second semiconductor fin and the third semiconductor fin, wherein the groove and the cover member are located above the second isolation structure.

4. The method according to claim 3, wherein, The second portion of the gate metal is the common gate electrode of the second transistor and the third transistor of the third semiconductor fin.

5. The method according to claim 1, further comprising: A first mask structure is formed above the first gate metal, the first semiconductor fin, the second semiconductor fin, the first source / drain region, and the second source / drain region; The groove is formed in the first gate metal by forming a first trench through the first mask structure; as well as The cover member is formed by selectively depositing the cover member in the recess of the first gate metal.

6. The method according to claim 5, further comprising: A second mask structure is formed above the first gate metal, the first semiconductor fin and the second semiconductor fin, the first isolation structure, and the first source / drain region and the second source / drain region; The mask structure is patterned to form a second trench and a third trench, the second trench extending over the first isolation structure in the first lateral direction, and the third trench exposing the cover member; as well as The dielectric isolation structure is formed in the second trench.

7. The method according to claim 6, wherein, Forming the second trench includes removing portions of the first source / drain region, the second source / drain region, and the first gate metal using an etching process.

8. The method according to claim 7, wherein, The cover component prevents the third trench from extending into the first gate metal.

9. A method for forming a semiconductor device, comprising: A first isolation structure is formed between the first semiconductor fin and the second semiconductor fin; A second isolation structure is formed between the second semiconductor fin and the third semiconductor fin, and the first semiconductor fin and the second semiconductor fin, as well as the first isolation structure and the second isolation structure, extend in a first lateral direction; Gate metal deposited in a second lateral direction different from the first lateral direction, extending across the first semiconductor fin and the second semiconductor fin, as well as the first isolation structure and the second isolation structure; A covering component is deposited on the gate metal at a first location above the second isolation structure; A first portion of the gate metal is electrically isolated from a second portion of the gate metal by forming a first trench using an etching process. The first trench extends through the gate metal in the first lateral direction above the isolation structure and extends between a first source / drain region of the first semiconductor fin and a second source / drain region of the second semiconductor fin. The first source / drain region and the second source / drain region extend partially above the first isolation structure. as well as A second trench extending in the first lateral direction is formed on the second isolation structure using the etching process, wherein the first cover member protects the gate metal from being etched by the etching process at the first location.

10. A semiconductor device, comprising: The first active region extends in the first lateral direction; The second active region extends in the first lateral direction; The third active region extends in the first lateral direction; A first isolation structure is located between the first active region and the second active region; The second isolation structure is located between the second active region and the third active region; The gate metal extends across the first active region, the second active region, the third active region, the first isolation structure, and the second isolation structure in a second lateral direction different from the first lateral direction; A first transistor is located in the first active region and includes a first source / drain region that extends partially over the first isolation structure; The second transistor is located in the second active region and includes a second source / drain region that extends partially over the first isolation structure; The cover component is located in a groove in the top surface of the gate metal above the first isolation structure; as well as A first dielectric isolation structure extends in the first lateral direction between the first source / drain region and the second source / drain region and between the first portion and the second portion of the gate metal, the dielectric isolation structure electrically isolating the first portion and the second portion of the gate metal from each other.

Images