Semiconductor structure and method of forming the same

Abstract

A method for forming a gate structure according to embodiments of the present disclosure includes providing a structure including a substrate, first nanostructures over a first region of the substrate, and second nanostructures over a second region of the substrate; depositing a gate dielectric layer over the first and second nanostructures; depositing a first work function metal layer over the first and second nanostructures; depositing a diffusion barrier layer over the first work function metal layer; selectively removing the diffusion barrier layer and the first work function metal layer from the first nanostructures over the first region; depositing a second work function metal layer over the first and second nanostructures; and depositing a metal fill layer over the second work function metal layer. Embodiments of the present application also relate to semiconductor structures and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs. However, such miniaturization also increases the complexity of handling and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology has evolved towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or portion thereof disposed above more than one side of the channel region. FinFETs and gate-all-around (GAA) transistors (both also known as non-planar transistors) are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have an elevated channel enclosed by gates on more than one side (e.g., the gates enclose the top and sidewalls of a semiconductor material “fin” extending from the substrate). Compared to planar transistors, such a configuration provides better control of the channel and significantly reduces SCE (particularly by reducing subthreshold leakage, i.e., the coupling between the source and drain of the FinFET in the “off” state). GAA transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because of this configuration, GAA transistors can also be called gate-around transistors (SGT) or multi-bridge channel (MBC) transistors. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. These shapes of the channel region also give GAA transistors different names. For example, a GAA transistor with a nanosheet channel region can be called a nanosheet transistor.

[0004] To meet improved power consumption and other design requirements, multi-gate transistors with different threshold voltages are desired. Summary of the Invention

[0005] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a first channel member over a first region of a substrate and forming a second channel member over a second region of the substrate; forming an interface layer over the first channel member and the second channel member; forming a gate dielectric layer over the interface layer; selectively depositing a barrier layer over the gate dielectric layer over the second region; after the selective deposition, depositing a dipole dopant layer over the gate dielectric layer over the first region and the barrier layer over the second region; performing a dipole drive process; after performing the dipole drive process, removing the dipole dopant layer from the gate dielectric layer over the first region and the barrier layer over the second region; after removing the dipole dopant layer, removing the barrier layer from the second region; and forming a gate electrode over the first region and the second region, wherein the gate electrode comprises a titanium-based material.

[0006] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a structure including: a first nanostructure extending between a first source / drain pair; and a second nanostructure extending between a second source / drain pair; forming an interface layer over the first nanostructure and the second nanostructure; depositing a gate dielectric layer over the first nanostructure and the second nanostructure; depositing a barrier layer over the gate dielectric layer over the first nanostructure and the second nanostructure; selectively removing the barrier layer from the gate dielectric layer over the first nanostructure; and, after the selective removal, in the second nanostructure... A dipole dopant layer is deposited over the gate dielectric layer above the first nanostructure and the barrier layer above the second nanostructure, such that the dipole dopant layer is spaced apart from the second nanostructure by the barrier layer; after depositing the dipole dopant layer, a dipole drive process is performed; after the process, the dipole dopant layer is removed; after removing the dipole dopant layer, the barrier layer is removed from above the second nanostructure; and after removing the barrier layer, a gate electrode is formed to enclose each of the first nanostructure and each of the second nanostructure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the interface layer.

[0007] Further embodiments of this application provide a semiconductor structure including: a first base fin and a second base fin; an isolation member disposed between the first base fin and the second base fin; a first nanostructure stacked on top of the first base fin; a second nanostructure stacked on top of the second base fin; a first interface layer encapsulating each of the first nanostructures; a second interface layer encapsulating the second nanostructures; a first gate dielectric layer located above the first interface layer; a second gate dielectric layer located above the second interface layer; and a gate electrode located above the first gate dielectric layer and the second gate dielectric layer, wherein the nitrogen content in the first interface layer is greater than the nitrogen content in the second interface layer, wherein the aluminum content in the second gate dielectric layer is greater than the aluminum content in the first gate dielectric layer, and wherein the gate electrode comprises a titanium-based material. Attached Figure Description

[0008] The various aspects of embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of this disclosure and should therefore not be considered as limiting the scope, as embodiments of this disclosure can be equally applied to other embodiments.

[0009] Figure 1 A schematic process is shown for selectively introducing dipole dopants into device regions according to various aspects of embodiments of the present disclosure.

[0010] Figure 2 It shows when using Figure 1 The schematic process illustrates the dopant concentration gradient in the interface layer and gate dielectric layer when dipole dopants are selectively introduced.

[0011] Figure 3 This is a flowchart illustrating a method for forming a semiconductor device according to various aspects of embodiments of the present disclosure.

[0012] Figures 4 to 22 It shows that according to Figure 1 Partial cross-sectional views of the first and second regions of the precursor structure in the method at various manufacturing stages.

[0013] Figure 23 The embodiments of this disclosure are shown in practice. Figure 3 The method described herein is used to select semiconductor structures when forming fin field-effect transistors (FinFETs).

[0014] Figures 24 to 26A schematic process is shown for selectively introducing a dipole dopant into up to two device regions according to various aspects of embodiments of the present disclosure.

[0015] Figure 27 Semiconductor devices in more than two device regions are shown according to various embodiments of the present disclosure. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] For ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, as understood by those skilled in the art, the term is intended to encompass values ​​within a reasonable range that takes into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing parts having numerically related characteristics, a numerical value or range encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For instance, a material layer having a thickness of "about 5 nm" could include a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%.

[0019] GAA transistors have gate structures that extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can include multiple sheet-like or wire-like nanoscale channel components stacked on top of each other or placed side by side. To meet improved power consumption and other design requirements, multi-gate transistors with different threshold voltages are desired. One approach to fabricating multi-threshold devices is by introducing different amounts of dipole dopant into different device regions. However, selectively introducing dipole dopant can be challenging. For example, dipole dopant may gradually penetrate into regions that should be dopant-free, and the dipole driving process may introduce additional variables. When this occurs, high minimum operating voltages and high gate leakage currents can result due to severe dry ion bombardment damage, high nitrogen doping, and dipole-high-k dielectric mixing.

[0020] This disclosure relates to the formation of multi-gate transistors with different threshold voltages. According to some embodiments, a barrier layer is formed on a dipole-free region. Then, a dipole dopant source layer is formed on the gate dielectric layer in the dipole-driven region and the barrier layer in the dipole-free region. Subsequently, a dipole-driven process is performed. Due to the presence of the barrier layer, the concentration of dipole dopant in the gate dielectric layer in the dipole-driven region is greater than the concentration of dipole dopant in the gate dielectric layer in the dipole-free region. Furthermore, the nitrogen concentration in the gate dielectric layer in the dipole-driven region is greater than the nitrogen concentration in the gate dielectric layer in the dipole-free region. The process of this disclosure provides benefits including a reduced minimum operating voltage and a reduced gate leakage current.

[0021] Figure 1 A schematic process for selectively introducing dipole dopants into the device region is shown. Instead of viewing the multi-gate transistor as a whole, Figure 1 The focus is on the interface layer 240 and the gate dielectric layer 242, and how each layer interacts with them. Figure 1Stages (A), (B), (C), (D), (E), (F), (G), and (H) are schematically shown. In stage (A), a barrier layer 270 is globally deposited over the gate dielectric layer 242 and the interface layer 240. In some embodiments, the interface layer 240 may include silicon oxide or hafnium silicate, and the gate dielectric layer 242 may include hafnium oxide or other high-k dielectric materials. According to embodiments of this disclosure, the barrier layer 270 is a dielectric layer capable of mitigating the diffusion of dipole dopants. For example, the barrier layer 270 may include titanium oxide (TiO), titanium nitride (TiN), titanium tungsten nitride (TiWN), tungsten carbonitride (WCN), tungsten nitride (TsN), aluminum nitride (AlN), or titanium aluminum carbide (TiAlC). In one embodiment, the barrier layer 270 includes aluminum oxide or aluminum nitride. To pattern the barrier layer 270, a mask layer 272 is deposited and patterned on the barrier layer 270. In the depicted embodiment, mask layer 272 is a photoresist layer and is patterned using photolithography. Figure 1 In stage (A), the patterned mask layer 272 covers the second region 20, while the first region 10 is not covered by the patterned mask layer 272 or does not perpendicularly overlap with the patterned mask layer 272. Figure 1 In stage (B), a patterned mask layer 272 is used as an etching mask to selectively remove the barrier layer 270 above the first region 10. The etching process in stage (B) can be dry etching using a fluorine-containing gas, a chlorine-containing gas, or oxygen. In stage (B), the barrier layer 270 is selectively removed from above the first region 10.

[0022] After selectively removing the barrier layer 270, the patterned mask layer 272 is removed in stage (C) using an ashing process 300. In some embodiments, the ashing process 300 implements nitrogen (N2) and hydrogen (H2). Due to the absence of the mask layer 272 and the barrier layer 270, the ashing process 300 can introduce nitrogen into the interface layer 240, as by... Figure 1 The "N" in the text indicates this. (Brief reference) Figure 2 . Figure 2 The bottom diagram shows a representative nitrogen concentration [N] in the interface layer 240 and gate dielectric layer 242 in the first region 10 and the second region 20. Figure 2 In this configuration, the absence of a barrier layer 270 above the first region 10 allows more nitrogen to be introduced into the interface layer 240 above the first region 10 during the ashing process 300. Because the dipole dopant layer 280 has not yet been deposited, mixing of dipole dopant and nitrogen above the first region 10 is avoided. Mixing of dipole dopant and nitrogen can lead to increased leakage. Conversely, the patterned mask layer 272 and barrier layer 270 significantly reduce nitrogen introduction into the interface layer 240 above the second region 20. (Still referring to...) Figure 1In stage (D), a dipole dopant layer 280 (or dipole dopant source layer 280) is deposited over the first region 10 and the second region 20. Over the first region 10, the dipole dopant layer 280 is deposited directly on the gate dielectric layer 242. Over the second region 20, the dipole dopant layer 280 is spaced from the gate dielectric layer 242 by a barrier layer 270. The dipole dopant layer 280 may include an n-dipole dopant or a p-dipole dopant. Exemplary n-dipole dopant may include lanthanum (La), yttrium (Y), lutetium (Lu), strontium (Sr), erbium (Er), or magnesium (Mg). Exemplary p-dipole dopant may include titanium (Ti), aluminum (Al), or niobium (Nb). The dipole dopant layer 280 may be a nitride or oxide of these exemplary dipole dopant materials. For example, when the desired n-dipole dopant is lanthanum (La), the dipole dopant layer 280 may be lanthanum oxide or lanthanum nitride. When the desired n-dipole dopant is magnesium (Mg), the dipole dopant layer 280 may be magnesium oxide or magnesium nitride. When the desired p-dipole dopant is aluminum, the dipole dopant layer 280 may be aluminum oxide or aluminum nitride. In one embodiment, the dipole dopant layer 280 comprises lanthanum oxide or lanthanum nitride.

[0023] In stage (E), a dipole drive-in process 400 is performed to promote and accelerate the diffusion of dipole dopants into the gate dielectric layer. In some embodiments, the dipole drive-in process 400 may include an annealing process having an annealing temperature or process temperature between about 500°C and about 800°C. Figure 1 As shown, in stage (F), the dipole drive process 400 not only drives the dipole dopant (D) into the gate dielectric layer 242 above the first region 10, but also drives the metal dopant (M) from the barrier layer 270 into the gate dielectric layer 242 above the second region 20. (See reference...) Figure 2 . Figure 2The top diagram shows a representative metal dopant concentration [M] in the interface layer 240 and gate dielectric layer 242 in the first region 10 and the second region 20. Because the barrier layer 270 is disposed over the second region 20 during the dipole drive process 400, the metal dopant concentration [M] in the gate dielectric layer 242 over the second region 20 is significantly higher than the metal dopant concentration [M] over the first region 10. When the barrier layer 270 comprises aluminum oxide, the metal dopant M is aluminum (Al). After the dipole drive process 400, the dipole dopant layer 280 is selectively removed, exposing the gate dielectric layer 242 over the first region 10 and the barrier layer 270 over the second region 20. In stage (G), the barrier layer 270 over the second region 20 is also removed. Finally, in stage (H), a first gate electrode 260 is formed over the first region 10, and a second gate electrode 262 is formed over the second region 20. The first gate electrode 260 and the second gate electrode 262 may have similar compositions. Each of them may include at least one work function layer, an optional diffusion barrier layer, and a metal filler. Because the work function layer includes the element titanium, it can be said that the first gate electrode 260 and the second gate electrode 262 include a titanium-based material.

[0024] Based on the above description and Figure 2 As illustrated in the diagram, the method of this disclosure allows for the introduction of more dipole dopant into the interface layer 240 in the first region 10, reducing gate leakage, and more metal dopant into the interface layer in the second region 20. This allows transistors formed over the first region 10 and the second region 20 to have different threshold voltages, and leakage current is reduced due to the mixing of dipole dopant and nitrogen. In embodiments where the dipole dopant from the dipole dopant layer 280 is lanthanum and the metal dopant from the barrier layer 270 is aluminum, the dipole dopant can lower the threshold voltage for n-type transistors, and the metal dopant can increase the threshold voltage for n-type transistors. The effect on p-type transistors may be completely opposite. In embodiments where the dipole dopant from the dipole dopant layer 280 is lanthanum and the metal dopant from the barrier layer 270 is aluminum, the dipole dopant can increase the threshold voltage for p-type transistors, and the metal dopant can lower the threshold voltage for p-type transistors.

[0025] Figure 3 This is a flowchart illustrating a method 100 for forming a semiconductor structure for a multi-gate device according to various aspects of embodiments of the present disclosure. Method 100 is merely an example and is not intended to limit the embodiments of the present disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and for additional embodiments of the method, some steps described may be replaced, eliminated, or moved around. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 20 Description method 100, Figures 2 to 20 These are partial cross-sectional views of the precursor structure 200 at different manufacturing stages according to an embodiment of method 100. Because the precursor structure 200 will be manufactured into a semiconductor device 200 or semiconductor structure 200 at the end of the manufacturing process, the precursor structure 200 may be referred to as a semiconductor device 200 or semiconductor structure 200, depending on the context. Furthermore, throughout this application and across different embodiments, the same reference numerals denote the same components having similar structures and compositions, unless otherwise stated. Source / drain regions may refer to the source or drain, individually or collectively, depending on the context.

[0026] refer to Figures 3 to 11 Method 100 includes block 102, wherein a first nanostructure 2080 is formed between two first source / drain components 232 above a first region 10 of substrate 202, and a second nanostructure 2080 is formed between two second source / drain components 234 above a second region 20 of substrate 202. The operation in block 102 includes forming a stack 204 above substrate 202. Figure 4 As shown in the diagram); a portion of the patterned stack 204 and substrate 202 is used to form a fin structure 212 (as shown in the diagram). Figure 5 As shown in the diagram); a dummy gate stack 220 is formed above the channel region of the fin structure 212 (as shown in the diagram). Figure 6 and Figure 7 As shown in the diagram); forming a gate spacer layer 226 and recessing the source / drain regions 212SD of the fin structure 212 (as shown in the diagram); Figure 8 As shown in the diagram); forming the first source / drain component 232 and the second source / drain component 234 ( Figure 9 As shown); deposited contact etch stop layer (CESL) 236 and interlayer dielectric (ILD) layer 238 (as shown); Figure 10 As shown in the figure); and removing the dummy gate stack 220 and releasing the first nanostructure 2080 and the second nanostructure 2080 in the first region 10 and the second region 20 (as ... Figure 11 (as shown in the image).

[0027] refer to Figure 4Substrate 202 is part of precursor structure 200 undergoing the various operations of method 100. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, substrate 202 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 202 may optionally include an epitaxial layer (epi layer), which may be strained for performance enhancement, and may include silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structures, and / or may have other suitable enhancement components. Substrate 202 may include various doping configurations as known in the art depending on design requirements. For example, substrate 202 may include p-type wells (i.e., p-type dopant distributions) and n-type wells (i.e., n-type dopant distributions). In some embodiments, the n-type dopant used to form the n-type well may include phosphorus (P) or arsenic (As), and the p-type dopant used to form the p-type well may include boron (B). Suitable doping for n-type or p-type wells may include ion implantation and / or diffusion processes of the dopant. In the depicted embodiment, substrate 202 includes a first region 10 and a second region 20. Although the first region 10 and the second region 20 are in Figure 4 It is shown as discontinuous, but it should be noted that the first region 10 and the second region 20 can be adjacent to each other.

[0028] Still referencing Figure 4 The stack 204 includes a sacrificial layer 206 of a first semiconductor interleaved with a channel layer 208 composed of a second semiconductor. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layer 206 comprises silicon germanium (SiGe), and the channel layer 208 comprises silicon (Si). It should be noted that the three (3) layers of the sacrificial layer 206 and the three (3) layers of the channel layer 208 are as follows Figure 4 The alternating arrangements shown are for illustrative purposes only and are not intended to limit the scope beyond what is specifically described in the claims. It will be understood that any number of epitaxial layers may be formed in the stack 204. The number of layers depends on the desired number of channel components for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0029] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness between about 5 nm and about 20 nm, and all channel layers 208 may have a substantially uniform second thickness between about 3 nm and about 10 nm. The first and second thicknesses may be identical or different. As described in more detail below, channel layers 208 or portions thereof may be used as channel members for subsequently formed multi-gate devices, and the thickness of each of the channel layers 208 is selected based on device performance considerations. The sacrificial layers 206 in the channel regions may eventually be removed and used to define the vertical distance between adjacent channel regions for subsequently formed multi-gate devices, and the thickness of each of the sacrificial layers 206 is selected based on device performance considerations.

[0030] The layers in stack 204 can be deposited at temperatures between about 600°C and about 800°C using molecular beam epitaxy (MBE), vapor deposition (VPE), and / or other suitable epitaxial growth processes. As noted above, in at least some instances, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, and the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially free of dopants (i.e., having a dopant content from about 0 cm⁻¹). -3 To approximately 1×10 17 cm -3 (intrinsic dopant concentration), where, for example, no intentional doping is performed during the epitaxial growth process for the stack 204.

[0031] refer to Figure 5 The fin-shaped structure 212 is formed by a portion of the stack 204 and the substrate 202. To pattern the stack 204, a hard mask layer 210 can be deposited over the stack 204. Figure 4 (As shown in the diagram) to form an etching mask. The hard mask layer 210 can be a single layer or multiple layers. For example, the hard mask layer 210 may include a pad oxide layer and a pad nitride layer above the pad oxide layer. The fin structure 212 can be patterned using photolithography and etching processes from portions of the stack 204 and the substrate 202. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. Figure 5As shown, the etching process forms trenches extending through portions of the stack 204 and the substrate 202. The trenches define a fin structure 212, including a base fin 212B formed from the substrate 202. In some embodiments, dual-patterning or multi-patterning processes can be used to define the fin structure, which has a smaller pitch than, for example, that achievable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over the substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 212 by etching portions of the stack 204 and the substrate 202. Figure 5 As shown, the fin structure 212, together with the sacrificial layer 206 and the channel layer 208 therein, extends vertically along the Z direction and longitudinally along the X direction.

[0032] Adjacent to the fin structure 212 forms an isolation component 214. In some embodiments, the isolation component 214 may be formed in a trench to isolate the fin structure 212 from an adjacent active region, which may be another fin structure. The isolation component 214 may also be referred to as a shallow trench isolation (STI) component 214. For example, in some embodiments, a dielectric layer is first deposited over a substrate 202 to fill the trench. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In various instances, the dielectric layer may be deposited using CVD processes, subatmospheric pressure CVD (SACVD) processes, flowable CVD processes, spin-coating processes, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by dry etching processes, wet etching processes, and / or combinations thereof to form the STI component 214. like Figure 5 As shown, although the base fin 212B is disposed in or surrounded by the STI component 214, the remainder of the fin structure 212 formed by the stack 204 rises above the STI component 214 after being recessed.

[0033] Now for reference Figure 6 and Figure 7 A dummy gate stack 220 is formed over the channel region 212C of the fin structure 212. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 220 serves as a placeholder to undergo various processes and is removed and replaced by a functional gate structure. Other processes and configurations are possible. Figure 7In some embodiments shown, the dummy gate stack 220 is formed above the fin structure 212, and the fin structure 212 in the first region 10 and the second region 20 can each be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 7 As shown, the channel region 212C is disposed between the two source / drain regions 212SD along the X direction.

[0034] The formation of the dummy gate stack 220 may include depositing layers in the dummy gate stack 220 and patterning these layers. (See reference...) Figure 6 A dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 can be deposited over the precursor structure 200. In some embodiments, the dummy dielectric layer 216 can be formed on the fin structure 212 using chemical vapor deposition (CVD), ALD, oxygen plasma oxidation, thermal oxidation, or other suitable processes. In some instances, the dummy dielectric layer 216 may comprise silicon oxide. When the dummy dielectric layer 216 is formed using an oxidation process, it can be selectively formed on the exposed surfaces of the fin structure 212, such as... Figure 6 As shown in the diagram. Subsequently, the dummy electrode layer 218 can be deposited over the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable processes. In some instances, the dummy electrode layer 218 may comprise polysilicon. For patterning purposes, a gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable processes. The gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, as shown. Figure 7 As shown in the diagram. For example, the patterning process may include a photolithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 above the silicon oxide layer 223. Figure 7 As shown, no dummy gate stack 220 is disposed above the source / drain region 212SD of the fin structure 212.

[0035] Now for reference Figure 8At least one gate spacer layer 226 is deposited over the dummy gate stack 220 in the first region 10 and the second region 20. In some embodiments, the at least one gate spacer layer 226 is conformally deposited over the precursor structure 200, including over the top surface and sidewalls of the dummy gate stack 220. The term “conformal” is used herein to conveniently describe a layer having a substantially uniform thickness over the respective regions. The at least one gate spacer layer 226 may be a single layer or multiple layers. In the depicted embodiments, the at least one gate spacer layer 226 includes a first spacer layer 226-1 and a second spacer layer 226-2 disposed above the first spacer layer 226-1. The composition of the first spacer layer 226-1 may differ from the composition of the second spacer layer 226-2. In some embodiments, the dielectric constant of the first spacer layer 226-1 is greater than the dielectric constant of the second spacer layer 226-2. At least one gate spacer layer 226 (including a first spacer layer 226-1 and a second spacer layer 226-2) may comprise silicon oxide, silicon carbonitride, silicon carbon oxycarbonate, silicon carbonitride, or silicon nitride. At least one gate spacer layer 226 may be deposited over the dummy gate stack 220 using processes such as CVD, subatmospheric pressure CVD (SACVD), ALD, or other suitable processes. For ease of reference and simplicity, at least one gate spacer layer 226 may also be referred to as gate spacer layer 226.

[0036] Still referencing Figure 8 The source / drain regions 212SD of the fin structure 212 are recessed to form a source / drain trench 228. In some embodiments, the source / drain regions 212SD not covered by the dummy gate stack 220 and the gate spacer layer 226 are etched by dry etching or a suitable etching process to form the source / drain trench 228. For example, the dry etching process can be implemented with oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma and / or combinations thereof. Figure 8 In some embodiments illustrated, the source / drain regions 212SD of the fin structure 212 are recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. In some embodiments, the source / drain trench 228 extends into the substrate 202 beneath the stack 204.

[0037] refer to Figure 9An internal spacer component 230 is formed. After forming the source / drain trench 228, the sacrificial layer 206 in the channel region 212C is selectively and partially recessed to form internal spacer recesses, while the exposed channel layer 208 is substantially unetched. In embodiments where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), selectively and partially recessing the sacrificial layer 206 may include a SiGe oxidation process followed by SiGe oxide removal. In this embodiment, the SiGe oxidation process may include the use of ozone (O3). In some other embodiments, selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree to which the sacrificial layer 206 is recessed is controlled by the duration of the etching process. A selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. A selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). After forming the internal spacer recess, an internal spacer material layer is deposited over the precursor structure 200 (including within the internal spacer recess). The internal spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material, and may be deposited using CVD, PECVD, SACVD, ALD, or other suitable methods. The deposited internal spacer material layer is then etched back to remove excess internal spacer material layer located above the sidewalls of the gate spacer layer 226 and the channel layer 208, thereby forming the internal spacer component 230. In some embodiments, the etching process for forming the internal spacer component 230 can be a dry etching process, which includes using oxygen-containing gases, hydrogen (H2), nitrogen (N2), fluorine-containing gases (e.g., NF3, CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases (e.g., CF3I), other suitable gases and / or plasma and / or combinations thereof. Although not explicitly shown, a cleaning process can be performed after the etching process to remove native oxides and debris from the surface of the channel layer 208.

[0038] Still referencing Figure 9A first source / drain component 232 is formed over the source / drain region 212SD in the first region 10, and a second source / drain component 234 is formed over the source / drain region 212SD in the second region 20. Each of the first source / drain component 232 and the second source / drain component 234 can be epitaxially and selectively formed from the exposed sidewalls of the channel layer 208 and the exposed surface of the substrate 202, while the sidewalls of the sacrificial layer 206 remain covered by the internal spacer component 230. Suitable epitaxial processes for forming the first source / drain component 232 and the second source / drain component 234 include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process may use a gaseous precursor that interacts with the composition of the substrate 202 and the channel layer 208. In some embodiments, the parameters of the epitaxial growth process are selected such that the first source / drain component 232 and the second source / drain component 234 are not epitaxially deposited on the internal spacer component 230. That is, overgrowth of the first source / drain component 232 and the second source / drain component 234 can be merged on some of the internal spacer components 230.

[0039] The first source / drain component 232 and the second source / drain component 234 may have the same conductivity type and may each include more than one epitaxial layer. When the first source / drain component 232 and the second source / drain component 234 are n-type, they may include silicon (Si) doped with an n-type dopant (such as phosphorus (P) or arsenic (As)). When the first source / drain component 232 and the second source / drain component 234 are p-type, they may include silicon germanium (SiGe) doped with a p-type dopant (such as boron (B)). When each of the first source / drain component 232 and the second source / drain component 234 is n-type and includes multiple epitaxial layers, the epitaxial layer closer to the channel layer 208 and the substrate 202 may include a lower n-type dopant concentration, and the epitaxial layer farther from the channel layer 208 and the substrate may include a higher n-type dopant concentration. Similarly, when each of the first source / drain component 232 and the second source / drain component 234 is p-type and includes multiple epitaxial layers, the epitaxial layer closer to the channel layer 208 and the substrate 202 may include a lower p-type dopant concentration, and the epitaxial layer farther from the channel layer 208 and the substrate may include a higher p-type dopant concentration. Furthermore, when each of the first source / drain component 232 and the second source / drain component 234 is p-type and includes multiple epitaxial layers, the epitaxial layer closer to the channel layer 208 and the substrate 202 may include a lower germanium (Ge) content, and the epitaxial layer farther from the channel layer 208 and the substrate may include a higher germanium (Ge) content.

[0040] refer to Figure 10A contact etch stop layer (CESL) 236 and an interlayer dielectric (ILD) layer 238 are deposited over the first source / drain component 232 and the second source / drain component 234. CESL 236 may comprise silicon nitride, silicon oxynitride, and / or other materials known in the art. ILD layer 238 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, CESL 236 is first conformally deposited over the first region 10 and the second region 20 using CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) processes and / or other suitable deposition or oxidation processes, and ILD layer 238 is deposited over CESL 236 using spin coating, FCVD, CVD, or other suitable deposition techniques. In some embodiments, after forming the ILD layer 238, the precursor structure 200 may be annealed to improve the integrity of the ILD layer 238. For example... Figure 10 As shown, after depositing CESL 236 and ILD layers 238, planarization processes, such as chemical mechanical polishing (CMP), can be performed to remove excess material. Figure 10 As shown, the planarization process also exposes the dummy electrode layer 218 of the dummy gate stack 220 in the first region 10 and the second region 20.

[0041] Now for reference Figure 11The exposed dummy gate stack 220 is removed, and the sacrificial layer 206 in the channel region 212C is selectively removed to release the first nanostructure 2080 in the first region 10 and the second nanostructure 2080 in the second region 20. Removal of the dummy gate stack 220 may include one or more etching processes selectively targeting the material in the dummy gate stack 220. For example, removal of the dummy gate stack 220 may be performed using selective wet etching, selective dry etching, or a combination thereof. After removal of the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed. Thereafter, the sacrificial layer 206 in the channel region 212C is selectively removed to release the first nanostructure 2080 in the first region 10 and the second nanostructure 2080 in the second region 20. The first nanostructure 2080 in the first region 10 and the second nanostructure 2080 in the second region 20 may also be referred to as the channel member 2080. Selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some other embodiments, selective removal includes SiGe oxidation followed by removal of silicon germanium oxide. For example, oxidation can be provided by ozone cleaning, and then silicon germanium oxide can be removed by an etchant such as NH4OH.

[0042] refer to Figure 3 and Figure 12 Method 100 includes block 104, wherein an interface layer 240 is formed over the first nanostructure 2080 and the second nanostructure 2080. For example... Figure 12 As shown, a first nanostructure 2080 is disposed above the base fin 212B in the first region 10, and a second nanostructure 2080 is disposed above the base fin 212B in the second region 20. Because the base fin 212B is patterned by the substrate 202, the base fin 212B includes the same composition as the substrate 202. The interface layer 240 may comprise silicon oxide or silicon oxynitride or other suitable materials. In some embodiments, the interface layer 240 may be deposited over the surface of the first nanostructure 2080, the surface of the second nanostructure, and the top surface of the base fin 212B using suitable methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), ozone oxidation, thermal oxidation, or other suitable methods. The interface layer 240 serves to control and reduce gate leakage current and improve the gate dielectric layer 242 ( Figure 13The interface layer 240 acts as an interfacial bond between the semiconductor surface (shown in the diagram) and the nanostructure (including the first nanostructure 2080 in the first region 10 and the second nanostructure 2080 in the second region 20). In the depicted embodiment, the interface layer 240 is formed using thermal oxidation, and the interface layer 240 is selectively deposited on the semiconductor surface rather than on the dielectric surface (such as the top surface of the isolation member 214).

[0043] refer to Figure 3 and Figure 13 Method 100 includes block 106, wherein a gate dielectric layer 242 is deposited over interface layer 240. In some embodiments, gate dielectric layer 242 is a high-k dielectric layer because its dielectric constant is greater than that of silicon dioxide (~3.9). In some instances, the dielectric constant of gate dielectric layer 242 is more than twice that of interface layer 240 or the dielectric constant of isolation component 214, such as between three and about five times. In some embodiments, gate dielectric layer 242 may include doped or undoped hafnium oxide (HfO2), doped or undoped zirconium oxide (ZrO2), doped or undoped titanium oxide (TiO2), or doped or undoped aluminum oxide (Al2O3). For example, the gate dielectric layer 242 may comprise hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), or hafnium aluminum oxide (HfAlO), hafnium tantalum oxide (HfTaO), hafnium zirconium oxide (HfZrO), zirconium silicon oxide (ZrSiO2), hafnium titanium oxide (HfTiO), or combinations thereof. At the end of the operation in block 106, each of the first nanostructure 2080 in the first region 10 and the second nanostructure 2080 in the second region 20 is enclosed by the interface layer 240 and the gate dielectric layer 242. Furthermore, as... Figure 13 As shown, the deposition of the gate dielectric layer 242 may not be selective, and the gate dielectric layer 242 may be deposited over the isolation member 214.

[0044] refer to Figure 3 and Figure 14 Method 100 includes block 108, wherein a barrier layer 270 is deposited over a gate dielectric layer 242. The barrier layer 270 may be a metal oxide capable of slowing the diffusion of dipole dopants. In some embodiments, the barrier layer 270 comprises aluminum oxide. The barrier layer 270 may be deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or metal-organic chemical vapor deposition (MCCVD). Figure 14As shown, the barrier layer 270 is deposited to enclose each of the first nanostructure 2080 above the first region 10 and the second nanostructure 2080 above the second region 20. The barrier layer 270 does not completely fill the gap perpendicular to the space between two adjacent first nanostructures 2080 and second nanostructures 2080, thereby allowing the subsequently deposited dipole dopant layer 280 to enclose each of the first nanostructure 2080 and second nanostructure 2080. Figure 1 Phase (A) shows that the barrier layer 270 is deposited directly on the gate dielectric layer 242.

[0045] refer to Figure 3 and Figures 15 to 17 Method 100 includes block 110, wherein a blocking layer 270 above a first region 10 is selectively removed. The operation in block 110 includes forming a mask layer 272 over a second region 20. Figure 15 As shown); remove the blocking layer 270 above the first region 10 (as shown); Figure 16 As shown); and the mask layer 272 is removed using an ashing process 300 (as shown); Figure 17 (As shown). Now refer to Figure 15 Mask layer 272 may include a photoresist layer, a bottom anti-reflective coating (BARC), or a combination thereof. In an exemplary process, mask layer 272 is first deposited over precursor structure 200 using spin coating or flowable CVD (FCVD). Photolithography and etching processes are then performed to pattern mask layer 272 such that the patterned mask layer 272 covers the second region 20, while the first region 10 is not covered by mask layer 272. (The last sentence appears to be incomplete and possibly refers to a different process.) Figure 16 When the patterned mask layer 272 is used as an etching mask, the barrier layer 270 is removed from the first region 10, including over the surface of the gate dielectric layer 242 surrounding the first nanostructure 2080, over the isolation member 214, and over the base fin 212B. Removal of the barrier layer 270 over the first region 10 can be achieved using a selective wet etching process. The selective wet etching process may include the use of hydrogen fluoride (HF), phosphoric acid (H3PO4), hydrochloric acid (HCl), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), or combinations thereof. Figure 1 Phase (B) shows the selective removal of the barrier layer 270 from above the gate dielectric layer 242 in the first region 10.

[0046] Then refer to Figure 17 An ashing process 300 is performed to remove the mask layer 272 from above the second region 20. In some embodiments, the ashing process 300 may include plasma using nitrogen (N2) and hydrogen (H2). (As described above...) Figure 1 The stage (C) described in the diagram. Ashing process 300 can introduce nitrogen into the first region 10. As... Figure 2As shown, nitrogen has been observed to diffuse into the interface layer 240 in the first region 10. In some embodiments, the nitrogen concentration in the interface layer 240 is derived from the interface with the channel ( Figure 1 The depth of the second region 20 gradually increases towards a substantially intermediate point within the interface layer 240, and then gradually decreases towards the interface with the gate dielectric layer 242. A barrier layer 270 in the second region 20 blocks the introduction of material into the second region 20. (As...) Figure 2 As shown, little or no nitrogen penetrates into the interface layer 240 in the second region 20.

[0047] refer to Figure 3 and Figure 18 Method 100 includes block 112, wherein a dipole dopant layer 280 is deposited over a first nanostructure 2080 and a second nanostructure 2080. In block 112, the dipole dopant layer 280 is deposited directly over a gate dielectric layer 242 in a first region 10 and a barrier layer 270 in a second region 20. That is, over the second region 20, the dipole dopant layer 280 is spaced apart from the gate dielectric layer 242 by the barrier layer 270. As the name suggests, the dipole dopant layer 280 includes elements capable of inducing dipoles, which can lower or raise the threshold voltage of a transistor. The dipole dopant layer 280 may include an n-dipole dopant or a p-dipole dopant. Exemplary n-dipole dopant may include lanthanum (La), yttrium (Y), lutetium (Lu), strontium (Sr), erbium (Er), or magnesium (Mg). Exemplary p-dipole dopant may include titanium (Ti) or niobium (Nb). In one embodiment, the dipole dopant layer 280 includes lanthanum oxide. In box 112, the dipole dopant layer 280 can be deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or metal-organic chemical vapor deposition (MCCVD). Figure 1 Phase (D) shows the deposition of a dipole dopant layer 280 over the first region 10 and the second region 20.

[0048] refer to Figure 3 and Figure 19 Method 100 includes block 114, in which a dipole drive-in process 400 is performed. In some embodiments, the dipole drive-in process 400 may be an annealing process having an annealing temperature between about 500°C and about 800°C. The dipole drive-in process 400 not only drives a dipole dopant (D) into the gate dielectric layer 242 above the first region 10, but also drives a metal dopant (M) from the barrier layer 270 into the gate dielectric layer 242 above the second region 20. As described above... Figure 2As described, because the barrier layer 270 only covers the second region 20 when the dipole drive process 400 is performed, the dopant concentration [M] in the gate dielectric layer 242 above the second region 20 is significantly higher than the dopant concentration [M] above the first region 10. When the barrier layer 270 comprises aluminum oxide or aluminum nitride, the metal dopant M is aluminum (Al). Because the dipole dopant layer 280 is spaced from the gate dielectric layer 242 above the second region 20 by the barrier layer 270, little or no dipole dopant penetrates into the gate dielectric layer 242 above the second region 20.

[0049] refer to Figure 3 and Figure 20 Method 100 includes block 116, wherein a dipole dopant layer 280 is removed from over the first region 10 and the second region 20. Following the dipole drive-in process 400, the dipole dopant layer 280 is selectively removed from the precursor structure 200, exposing the gate dielectric layer 242 over the first region 10 and the barrier layer 270 over the second region 20. In some embodiments, the dipole dopant layer 280 may be removed using wet etching. The wet etching in block 116 may include the use of hydrogen chloride (HCl).

[0050] refer to Figure 3 and Figure 21 Method 100 includes block 118, wherein a barrier layer 270 is removed over the second region 20. In some embodiments, a selective wet etching process can be used to remove the barrier layer 270 over the first region 10. The selective wet etching process may include the use of hydrogen fluoride (HF), phosphoric acid (H3PO4), hydrochloric acid (HCl), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), or combinations thereof. Figure 1 Phase (G) shows the selective removal of the barrier layer 270 from above the gate dielectric layer 242 in the second region 20.

[0051] refer to Figure 3 and Figure 22Method 100 includes block 120, wherein a first gate electrode 260 is formed to encapsulate a first nanostructure 2080, and a second gate electrode 262 is formed to encapsulate a second nanostructure 2080. In the depicted embodiments, transistors formed over the first region 10 and the second region 20 have the same conductivity type and different threshold voltages. In some embodiments, the transistors formed over the first region 10 and the second region 20 are n-type transistors. In some alternative embodiments, the transistors formed over the first region 10 and the second region 20 are p-type transistors. When the transistors over the first region 10 and the second region 20 are n-type transistors, the first gate electrode 260 and the second gate electrode 262 include an n-type work function layer and a metal filler. In these embodiments, the n-type work function layer may include an aluminum-containing layer, such as aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), aluminum tantalum (TaAl), aluminum tantalum carbide (TaAlC), aluminum titanium nitride (TiAlN), or combinations thereof. The metal filler layer may include tungsten (W). When the transistors above the first region 10 and the second region 20 are p-type transistors, the first gate electrode 260 and the second gate electrode 262 include a p-type power function layer, a diffusion barrier layer, an n-type power function layer, and a metal filler. In these embodiments, the p-type power function layer may include titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), or molybdenum (Mo). The diffusion barrier layer may include titanium aluminum carbide (TiAlC), titanium nitride (TiN), titanium oxynitride (TiNO), hafnium oxide (HfO), or tungsten nitride (WN). The n-type power function layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), or combinations thereof. The metal filler layer may include tungsten (W). Because at least one of the n-type and p-type power function layers includes the element titanium, it can be said that the first gate electrode 260 and the second gate electrode 262 include a titanium-based material. For ease of reference, the first gate electrode 260, the gate dielectric layer 242, and the interface layer 240 can be referred to as the first gate structure, and the second gate electrode 262, the gate dielectric layer 242, and the interface layer 240 can be referred to as the second gate structure.

[0052] It should be understood, and it can be implemented. Figure 3 Method 100 can be used to form other types of multi-gate devices. For example, method 100 can be applied to form FinFETs or complementary field-effect transistors (CFETs) with different threshold voltages. Figure 23 A FinFET formed over the first region 10 and the second region 20 is shown. Instead... Figure 22 The first nanostructure 2080 and the second nanostructure 2080 shown are shown. Figure 23The FinFET in the design includes a fin structure 2082 located above the first region 10 and the second region 20. Because... Figure 23 The interface layer 240 and the gate dielectric layer 242 in the middle have undergone the above bonding. Figures 1 to 22 The described dipole doping process means that the interface layer 240 in the first region 10 includes nitrogen, the gate dielectric layer 242 in the first region 10 includes a dipole dopant, and the gate dielectric layer 242 in the second region 20 includes a metal dopant from the barrier layer 270.

[0053] Figure 1 illustrative process and Figure 3 Method 100 describes implementing different dipole doping in two regions to achieve multi-gate transistors with different threshold voltages. Figures 24 to 26 A schematic process for applying different dipole doping to three regions—region 10, region 20, and region 30—is shown. Figure 24 In stage (A), a barrier layer 270 is deposited over the gate dielectric layer 242 in the first region 10, the second region 20, and the third region 30. A patterned mask layer 272 is disposed over the barrier layer 270 in the second region 20. Using the patterned mask layer 272 as an etching mask, the barrier layer 270 over the first region 10 and the third region 30 is etched away to expose the gate dielectric layer 242, as shown. Figure 24 As shown in stage (B). In stage (C), an ashing process 300 is performed to remove the patterned mask layer 272. The ashing process 300 introduces nitrogen into the interface layer 240 in the first region 10 and the third region 30. In stage (D), a dipole dopant layer 280 is deposited over the first region 10, the second region 20, and the third region 30. In the second region 20, the gate dielectric layer 242 is spaced apart from the dipole dopant layer 280 by a barrier layer 270. A dipole drive-in process 400 is performed, as follows. Figure 25 Stage (E) is shown in the diagram. Following the dipole drive process 400, in... Figure 25 In stage (F), the barrier layer 270 and the dipole dopant layer 280 are removed. The dipole drive-in process 400 drives the dipole dopant (D) in the dipole dopant layer 280 into the gate dielectric layer 242 in the first region 10 and the third region 30. Furthermore, the dipole drive-in process 400 drives the metal dopant (M) in the barrier layer 270 into the gate dielectric layer 242 in the second region 20. In stage (G), another barrier layer 290 is deposited and patterned to cover the first region 10 and the second region 20. For ease of reference, the barrier layer 270 may be referred to as the first barrier layer 270, and the other barrier layer 290 may be referred to as the second barrier layer 290. Although in Figure 25Not explicitly shown, however, an ashing process 300 is performed to remove the mask layer above the second barrier layer 290. This operation further increases the nitrogen concentration in the interface layer 240 in the third region 30. In stage (H), another dipole dopant layer 292 is deposited over the first region 10, the second region 20, and the third region 30. For ease of reference, the dipole dopant layer 280 may be referred to as the first dipole dopant layer 280, and the other dipole dopant layer 292 may be referred to as the second dipole dopant layer 292. Over the first region 10 and the second region 20, the second dipole dopant layer 292 is spaced from the gate dielectric layer 242 by the second barrier layer 290.

[0054] Now for reference Figure 26 In stage (I), the dipole dopant process 400 is performed again. The dipole dopant process 400 further increases the dipole dopant concentration (D) in the gate dielectric layer 242 of the third region 30 to an increased dipole dopant concentration (D'). It also increases the metal dopant concentration (M) in the gate dielectric layer 242 of the second region 20 to an increased metal dopant concentration (M'). Figure 26 In stage (J), the second dipole dopant layer 292 and the second barrier layer 290 are removed sequentially, as follows: Figure 26 The process is illustrated in stage (J). In stage (K), a first gate electrode 260, a second gate electrode 262, and a third gate electrode 264 are formed over the first region 10, the second region 20, and the third region 30, respectively. In some embodiments, the first gate electrode 260, the second gate electrode 262, and the third gate electrode 264 may have similar compositions. Due to different dipole dopant concentrations, different metal dopant concentrations, and different nitrogen concentrations, the formed transistors have different threshold voltages.

[0055] When using Figures 24 to 26 With the doping scheme shown, GAA transistors with different threshold voltages can be formed in the first region 10, the second region 20, and the third region 30, such as... Figure 27 As shown in the image. It should be noted that, Figure 27 The nanostructure 2080 shown is similar to Figure 10 and Figure 11The first source / drain component 232 and the second source / drain component 234 shown extend between their source / drain components. According to embodiments of this disclosure, implementing a barrier layer 270 during dipole drive-in helps overcome p-type work function roll-off and undesirable mixing of the gate dielectric layer and the dipole dopant layer. The disclosed process also helps overcome threshold voltage variations (i.e., Sigma) between the transmission gate transistor and the pull-down transistor in static random access memory (SRAM) applications. In SRAM technology, transmission gate transistors are used to read and write data, and pull-down transistors maintain the state of the cell. Variations in the threshold voltages of these transmission gate and pull-down transistors can lead to high gate leakage current or high standby current, affecting yield. The process and structure of embodiments of this disclosure can reduce threshold voltage variations.

[0056] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a first channel member over a first region of a substrate and forming a second channel member over a second region of the substrate; forming an interface layer over the first channel member and the second channel member; forming a gate dielectric layer over the interface layer; selectively depositing a barrier layer over the gate dielectric layer over the second region; after the selective deposition, depositing a dipole dopant layer over the gate dielectric layer over the first region and the barrier layer over the second region; performing a dipole drive process; after performing the dipole drive process, removing the dipole dopant layer from the gate dielectric layer over the first region and the barrier layer over the second region; after removing the dipole dopant layer, removing the barrier layer from the second region; and forming a gate electrode over the first region and the second region, wherein the gate electrode comprises a titanium-based material.

[0057] In some embodiments, the barrier layer comprises aluminum oxide. In some embodiments, the dipole dopant layer comprises lanthanum oxide. In some embodiments, the dipole drive process is performed such that elements in the dipole dopant layer diffuse into the gate dielectric layer in the first region and elements in the barrier layer diffuse into the gate dielectric layer in the second region. In some embodiments, the elements in the dipole dopant layer comprise lanthanum (La), yttrium (Y), lutetium (Lu), strontium (Sr), erbium (Er), or magnesium (Mg), and the elements in the barrier layer comprise aluminum (Al). In some embodiments, the dipole drive process comprises a process temperature between about 500°C and about 800°C. In some embodiments, selectively depositing the barrier layer comprises: depositing a global barrier layer over the gate dielectric layer over the first and second regions; forming a mask layer over the global barrier layer over the second region; removing the mask layer over the first region; etching the barrier layer over the first region while the barrier layer in the second region is covered by the mask layer; and selectively removing the mask layer over the second region after the etching. In some embodiments, the selective removal includes using an ashing process, wherein the ashing process includes using hydrogen (H2) and nitrogen (N2). In some embodiments, the ashing process causes nitrogen to diffuse into the interface layer above the first region.

[0058] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a structure including: a first nanostructure extending between a first source / drain pair; and a second nanostructure extending between a second source / drain pair; forming an interface layer over the first nanostructure and the second nanostructure; depositing a gate dielectric layer over the first nanostructure and the second nanostructure; depositing a barrier layer over the gate dielectric layer over the first nanostructure and the second nanostructure; selectively removing the barrier layer from the gate dielectric layer over the first nanostructure; and, after the selective removal, in the second nanostructure... A dipole dopant layer is deposited over the gate dielectric layer above the first nanostructure and the barrier layer above the second nanostructure, such that the dipole dopant layer is spaced apart from the second nanostructure by the barrier layer; after depositing the dipole dopant layer, a dipole drive process is performed; after the process, the dipole dopant layer is removed; after removing the dipole dopant layer, the barrier layer is removed from above the second nanostructure; and after removing the barrier layer, a gate electrode is formed to enclose each of the first nanostructure and each of the second nanostructure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the interface layer.

[0059] In some embodiments, the dipole drive process is performed such that elements in the dipole dopant layer diffuse into the gate dielectric layer above the first nanostructure, and elements in the barrier layer diffuse into the gate dielectric layer above the first nanostructure. In some embodiments, the elements in the dipole dopant layer include lanthanum (La), yttrium (Y), lutetium (Lu), strontium (Sr), erbium (Er), or magnesium (Mg), wherein the elements in the barrier layer include aluminum (Al). In some embodiments, the barrier layer includes aluminum oxide. In some embodiments, the dipole dopant layer includes lanthanum oxide. In some embodiments, selective removal of the barrier layer includes using an ashing process, wherein the ashing process includes using hydrogen (H2) and nitrogen (N2).

[0060] Further embodiments of this application provide a semiconductor structure including: a first base fin and a second base fin; an isolation member disposed between the first base fin and the second base fin; a first nanostructure stacked on top of the first base fin; a second nanostructure stacked on top of the second base fin; a first interface layer encapsulating each of the first nanostructures; a second interface layer encapsulating the second nanostructures; a first gate dielectric layer located above the first interface layer; a second gate dielectric layer located above the second interface layer; and a gate electrode located above the first gate dielectric layer and the second gate dielectric layer, wherein the nitrogen content in the first interface layer is greater than the nitrogen content in the second interface layer, wherein the aluminum content in the second gate dielectric layer is greater than the aluminum content in the first gate dielectric layer, and wherein the gate electrode comprises a titanium-based material.

[0061] In some embodiments, the first gate dielectric layer and the second gate dielectric layer include a dipole-inducing element, wherein the concentration of the dipole-inducing element in the first gate dielectric layer is greater than the concentration of the dipole-inducing element in the second gate dielectric layer. In some embodiments, the dipole-inducing element includes lanthanum (La), yttrium (Y), lutetium (Lu), strontium (Sr), erbium (Er), or magnesium (Mg). In some embodiments, the first interface layer is connected to the top surface of the first base fin. In some embodiments, the gate electrode comprises a titanium-based material.

[0062] This disclosure provides embodiments of a process for forming a gate structure of a multi-gate device. In one embodiment, a method is provided. The method includes: forming a first channel member over a first region of a substrate and forming a second channel member over a second region of the substrate; forming an interface layer over the first channel member and the second channel member; forming a gate dielectric layer over the interface layer; selectively depositing a barrier layer over the gate dielectric layer over the second region; depositing a dipole dopant layer over the gate dielectric layer over the first region and the barrier layer over the second region after the selective deposition; performing a dipole drive process; removing the dipole dopant layer from the gate dielectric layer over the first region and the barrier layer over the second region after performing the dipole drive process; removing the barrier layer from the second region after removing the dipole dopant layer; and forming a gate electrode over the first region and the second region. The gate electrode comprises a titanium-based material.

[0063] In some embodiments, the barrier layer comprises aluminum oxide. In some embodiments, the dipole dopant layer comprises lanthanum oxide. In some embodiments, the dipole drive process is performed such that elements in the dipole dopant layer diffuse into the gate dielectric layer in the first region and elements in the barrier layer diffuse into the gate dielectric layer in the second region. In some embodiments, the elements in the dipole dopant layer comprise lanthanum (La), yttrium (Y), lutetium (Lu), strontium (Sr), erbium (Er), or magnesium (Mg). The elements in the barrier layer comprise aluminum (Al). In some embodiments, the dipole drive process comprises a process temperature between about 500°C and about 800°C. In some embodiments, selectively depositing the barrier layer comprises: depositing a global barrier layer over the gate dielectric layer over the first and second regions; forming a mask layer over the global barrier layer over the second region; removing the mask layer over the first region; etching the barrier layer over the first region while the barrier layer in the second region is covered by the mask layer; and selectively removing the mask layer over the second region after etching. In some embodiments, selective removal comprises using an ashing process. The ashing process comprises using hydrogen (H2) and nitrogen (N2). In some embodiments, the ashing process causes nitrogen to diffuse into the interface layer above the first region.

[0064] In another embodiment, a method is provided. The method includes: providing a structure comprising: a first nanostructure extending between a first source / drain pair; and a second nanostructure extending between a second source / drain pair; forming an interface layer over the first nanostructure and the second nanostructure; depositing a gate dielectric layer over the first nanostructure and the second nanostructure; depositing a barrier layer over the gate dielectric layer over the first nanostructure and the second nanostructure; selectively removing the barrier layer from the gate dielectric layer over the first nanostructure; after selective removal, depositing a dipole dopant layer over the gate dielectric layer over the first nanostructure and the barrier layer over the second nanostructure, such that the dipole dopant layer is spaced apart from the second nanostructure by the barrier layer; performing a dipole drive process after depositing the dipole dopant layer; removing the dipole dopant layer after performing the process; removing the barrier layer from the second nanostructure after removing the dipole dopant layer; and forming a gate electrode to enclose each of the first nanostructure and each of the second nanostructure after removing the barrier layer. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the interface layer.

[0065] In some embodiments, a dipole drive process is performed such that elements in the dipole dopant layer diffuse into the gate dielectric layer above the first nanostructure, and elements in the barrier layer diffuse into the gate dielectric layer above the first nanostructure. In some embodiments, the elements in the dipole dopant layer include lanthanum (La), yttrium (Y), lutetium (Lu), strontium (Sr), erbium (Er), or magnesium (Mg), and the elements in the barrier layer include aluminum (Al). In some embodiments, the barrier layer includes aluminum oxide. In some instances, the dipole dopant layer includes lanthanum oxide. In some embodiments, selective removal of the barrier layer includes using an ashing process, and the ashing process includes using hydrogen (H2) and nitrogen (N2).

[0066] In a further embodiment, a semiconductor structure is provided. The semiconductor structure includes: a first base fin and a second base fin; an isolation member disposed between the first base fin and the second base fin; first nanostructures stacked on top of each other over the first base fin; second nanostructures stacked on top of each other over the second base fin; a first interface layer encapsulating each of the first nanostructures; a second interface layer encapsulating the second nanostructures; a first gate dielectric layer located above the first interface layer; a second gate dielectric layer located above the second interface layer; and a gate electrode located above the first gate dielectric layer and the second gate dielectric layer. The nitrogen content in the first interface layer is greater than the nitrogen content in the second interface layer, and the aluminum content in the second gate dielectric layer is greater than the aluminum content in the first gate dielectric layer. The gate electrode comprises a titanium-based material.

[0067] In some embodiments, the first gate dielectric layer and the second gate dielectric layer include a dipole-inducing element. The concentration of the dipole-inducing element in the first gate dielectric layer is greater than the concentration of the dipole-inducing element in the second gate dielectric layer. In some embodiments, the dipole-inducing element includes lanthanum (La), yttrium (Y), lutetium (Lu), strontium (Sr), erbium (Er), or magnesium (Mg). In some embodiments, the first interface layer is connected to the top surface of the first base fin. In some embodiments, the gate electrode comprises a titanium-based material.

[0068] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the following detailed description. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure. For example, by implementing different thicknesses for bit line conductors and word line conductors, different resistances for the conductors can be achieved. However, other techniques can also be used to change the resistance of metallic conductors.

Claims

1. A method for forming a semiconductor structure, comprising: A first channel member is formed over a first region of the substrate, and a second channel member is formed over a second region of the substrate; An interface layer is formed over the first channel component and the second channel component; A gate dielectric layer is formed above the interface layer; A barrier layer is selectively deposited over the gate dielectric layer above the second region; Following the selective deposition, a dipole dopant layer is deposited over the gate dielectric layer above the first region and the barrier layer above the second region; Implement the dipole drive process; After the dipole drive-in process is performed, the dipole dopant layer is removed from the gate dielectric layer above the first region and the barrier layer above the second region. After removing the dipole dopant layer, the barrier layer is removed from the second region; as well as Gate electrodes are formed above the first region and the second region. The gate electrode comprises a titanium-based material.

2. The method according to claim 1, wherein, The barrier layer comprises aluminum oxide.

3. The method according to claim 1, wherein, The dipole dopant layer includes lanthanum oxide.

4. The method according to claim 1, wherein, The dipole drive process is performed such that elements in the dipole dopant layer diffuse into the gate dielectric layer in the first region and elements in the barrier layer diffuse into the gate dielectric layer in the second region.

5. The method according to claim 4, in, The elements in the dipole dopant layer include lanthanum (La), yttrium (Y), lutetium (Lu), strontium (Sr), erbium (Er), or magnesium (Mg). The element in the barrier layer includes aluminum (Al).

6. The method according to claim 1, wherein, The dipole drive process includes a process temperature between approximately 500°C and approximately 800°C.

7. The method according to claim 1, wherein, Selectively depositing the barrier layer includes: A global barrier layer is deposited over the gate dielectric layer above the first region and the second region; A mask layer is formed above the global blocking layer above the second region; Remove the mask layer above the first region; The barrier layer in the second region is covered by the mask layer while the barrier layer above the first region is etched; and After the etching, the mask layer above the second region is selectively removed.

8. The method according to claim 7, in, The selective removal includes the use of an ashing process. The ashing process includes the use of hydrogen (H2) and nitrogen (N2).

9. A method for forming a semiconductor structure, comprising: A structure is provided, the structure comprising: a first nanostructure extending between a first source / drain component pair; and a second nanostructure extending between a second source / drain component pair; An interface layer is formed over the first nanostructure and the second nanostructure; A gate dielectric layer is deposited over the first nanostructure and the second nanostructure; A barrier layer is deposited over the gate dielectric layer above the first nanostructure and the second nanostructure; The barrier layer is selectively removed from the gate dielectric layer above the first nanostructure; After the selective removal, a dipole dopant layer is deposited over the gate dielectric layer above the first nanostructure and the barrier layer above the second nanostructure, such that the dipole dopant layer is spaced apart from the second nanostructure by the barrier layer. After depositing the dipole dopant layer, a dipole drive-in process is performed; After the above implementation, the dipole dopant layer is removed; After removing the dipole dopant layer, the barrier layer is removed from above the second nanostructure; and After removing the barrier layer, gate electrodes are formed to encapsulate each of the first nanostructure and each of the second nanostructure. The dielectric constant of the gate dielectric layer is greater than that of the interface layer.

10. A semiconductor structure, comprising: First basal fin and second basal fin; An isolation component is disposed between the first base fin and the second base fin; The first nanostructures are stacked on top of each other above the first base fin; The second nanostructures are stacked on top of each other above the second base fin; A first interface layer encapsulates each of the first nanostructures; A second interface layer encapsulates the second nanostructure; The first gate dielectric layer is located above the first interface layer; The second gate dielectric layer is located above the second interface layer; as well as The gate electrode is located above the first gate dielectric layer and the second gate dielectric layer. The nitrogen content in the first interface layer is greater than the nitrogen content in the second interface layer. The aluminum content in the second gate dielectric layer is greater than the aluminum content in the first gate dielectric layer. The gate electrode comprises a titanium-based material.

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