A semiconductor device and a method of fabricating the same

Abstract

The application relates to a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The preparation method comprises the following steps: providing a substrate, wherein a gate dielectric layer is formed on the substrate; forming a polysilicon layer on the gate dielectric layer, and patterning the polysilicon layer to form a plurality of polysilicon gates; forming a protective layer on the surface of the gate dielectric layer, wherein the protective layer covers the sidewalls of the polysilicon gates and the surface of the gate dielectric layer, and the top of the polysilicon gates is exposed; performing ion implantation doping on preset polysilicon gates; removing the protective layer, and performing annealing treatment on the preset polysilicon gates. The preparation method can improve the etching uniformity of polysilicon gate preparation, reduce the sidewall profile roughness, and further improve the electrical performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its fabrication method. Background Technology

[0002] Semiconductor devices typically include a semiconductor substrate and a gate dielectric layer and a polysilicon gate layer stacked sequentially on the substrate. The polysilicon gate layer serves as the control electrode of the device, and its morphology quality directly affects the electrical performance of the device.

[0003] In traditional manufacturing processes, the fabrication of polysilicon gates involves depositing a polysilicon layer on the gate dielectric layer, selectively implanting ions into the corresponding device regions using a photoresist mask, followed by annealing activation, and finally photolithography and etching of the polysilicon layer to form the gate pattern. However, this fabrication process is prone to difficulties in controlling etching uniformity due to the different etching rates between the doped and undoped polysilicon regions. Furthermore, non-volatile byproducts generated during the etching process in the doped polysilicon regions can adhere to the etched sidewalls, forming micromasks that hinder local etching and lead to deterioration of the roughness at the gate sidewall edges in the doped regions. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for fabricating the same, which can improve the etching uniformity of polysilicon gate fabrication and reduce sidewall profile roughness, thereby improving the electrical performance of the semiconductor device.

[0005] The embodiments of the present invention are implemented as follows: In one aspect, the present invention provides a method for fabricating a semiconductor device, comprising: providing a substrate on which a gate dielectric layer is formed; forming a polysilicon layer on the gate dielectric layer and patterning the polysilicon layer to form a plurality of polysilicon gates; forming a protective layer on the surface of the gate dielectric layer, the protective layer covering the sidewalls of the polysilicon gates and the surface of the gate dielectric layer, and exposing the top of the polysilicon gates; performing ion implantation doping on a predetermined polysilicon gate; removing the protective layer and annealing the predetermined polysilicon gate.

[0006] Optionally, forming a protective layer on the surface of the gate dielectric layer includes: forming a protective layer on the gate dielectric layer and the surface of the polysilicon gate, the protective layer covering the surface of the gate dielectric layer, the sidewalls and the top of the polysilicon gate; removing the protective layer on the top of the polysilicon gate, and retaining the protective layer on the sidewalls of the polysilicon gate and the surface of the gate dielectric layer.

[0007] Optionally, ion implantation doping is performed on the preset polysilicon gate, including: forming a photoresist layer on the protective layer and the surface of the polysilicon gate; patterning the photoresist layer to form an opening that exposes the top of the preset polysilicon gate; and using the photoresist layer as a mask to perform ion implantation on the preset polysilicon gate through the opening.

[0008] Optionally, after ion implantation of a preset polysilicon gate through an opening using a photoresist layer as a mask, the method further includes: removing the photoresist layer.

[0009] Optionally, after annealing the preset polysilicon gate, the method further includes: performing angled light doping implantation on the substrate to form a drain light doped region and a source light doped region in the substrate on both sides of the polysilicon gate; performing heavy doping implantation on the substrate to form a drain region on the side of the drain light doped region away from the polysilicon gate, and forming a source region on the side of the source light doped region away from the polysilicon gate.

[0010] Alternatively, the protective layer is an organic bottom anti-reflective layer.

[0011] Optionally, the thickness of the protective layer is between 100 angstroms and 2000 angstroms.

[0012] Optionally, the thickness of the photoresist layer is 50 nanometers to 500 nanometers.

[0013] Optionally, the thickness of the polycrystalline silicon layer is from 100 angstroms to 2000 angstroms.

[0014] In another aspect, the present invention provides a semiconductor device prepared by the above-described semiconductor device preparation method.

[0015] The beneficial effects of this invention include: This application provides a method for fabricating a semiconductor device, comprising: providing a substrate on which a gate dielectric layer is formed; forming a polysilicon layer on the gate dielectric layer and patterning the polysilicon layer to form a plurality of polysilicon gates; forming a protective layer on the surface of the gate dielectric layer, the protective layer covering the sidewalls of the polysilicon gates and the surface of the gate dielectric layer, and exposing the top of the polysilicon gates; performing ion implantation doping on a predetermined polysilicon gate; removing the protective layer and annealing the predetermined polysilicon gate. Compared to existing processes that selectively dope a polysilicon layer before patterning it, this application places the polysilicon patterning step before ion implantation doping. This ensures the polysilicon layer remains undoped during patterning, avoiding the etching uniformity degradation caused by different etching rates between doped and undoped regions. Furthermore, since the polysilicon layer is undoped during patterning, no non-volatile byproducts are generated during etching, preventing the micromask effect and effectively improving the edge roughness of the polysilicon gate sidewalls, thus enhancing gate morphology quality. After polysilicon gate patterning, this application forms a protective layer on the gate dielectric layer surface. This protective layer covers the polysilicon gate sidewalls and the gate dielectric layer surface, exposing the top of the polysilicon gate. This ensures that subsequent ion implantation enters the pre-defined polysilicon gate only through the exposed top, while the sidewalls and the gate dielectric layer on the substrate surface are shielded by the protective layer, preventing damage to the gate sidewalls from ion implantation. After the protective layer completes its doping protection function, it is removed and then annealed to activate the doped ions. This process ensures selective doping while maintaining the quality of the polysilicon gate morphology, thereby improving the electrical performance and reliability of the semiconductor device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 2 This is one of the fabrication flowcharts of a semiconductor device provided in an embodiment of the present invention; Figure 3 The second flowchart of semiconductor device fabrication provided in the embodiments of the present invention; Figure 4 The third flowchart of the semiconductor device fabrication process provided in the embodiments of the present invention; Figure 5The fourth flowchart of the semiconductor device fabrication process provided in the embodiments of the present invention; Figure 6 Fifth of the semiconductor device fabrication flowcharts provided in the embodiments of the present invention; Figure 7 This is the sixth flowchart illustrating the fabrication process of a semiconductor device provided in an embodiment of the present invention.

[0018] Icons: 110 - Substrate; 111 - First region; 112 - Second region; 120 - Gate dielectric layer; 130 - Polysilicon layer; 140 - Polysilicon gate; 150 - Protective layer; 160 - Photoresist layer; 161 - Opening; 171 - Source region; 172 - Drain region; 173 - Lightly doped drain region; 174 - Lightly doped source region; 180 - Shallow trench isolation structure; A - NMOS device; B - PMOS device. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed during use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0023] Please refer to Figure 1 This embodiment provides a method for fabricating a semiconductor device, including the following steps: Step S100: Provide a substrate 110, on which a gate dielectric layer 120 is formed.

[0024] Specifically, such as Figure 2 As shown, a semiconductor substrate 110 is provided. The substrate 110 can be a single-crystal silicon substrate 110, a germanium-silicon substrate 110, or other commonly used semiconductor substrate materials in the art. Shallow trenches are etched into the substrate 110, and then an insulating material, such as silicon oxide, is filled into the shallow trenches to form a shallow trench isolation structure 180. This structure isolates the substrate 110 into a first region 111 and a second region 112. Subsequently, an NMOS device A is formed in the first region 111, and a PMOS device B is formed in the second region 112. The shallow trench isolation structure 180 can isolate electrical signals between adjacent NMOS devices A and PMOS devices B. Next, well regions are formed on the substrate 110. The well regions include P-wells and N-wells. A P-well is formed in the first region 111 to form the well region of the NMOS device A, and an N-well is formed in the second region 112 to form the well region of the PMOS device B. Specifically, ion implantation is used to implant impurity ions of the corresponding conductivity type into the substrate 110. P-type ions, such as boron ions, are implanted to form P-wells, and N-type ions, such as phosphorus or arsenic ions, are implanted to form N-wells. After ion implantation, high-temperature annealing is performed to push the wells together, forming well regions with the required depth and doping concentration in the substrate 110. The device types in the first region 111 and the second region 112 are not limited to SRAM, NMOS, PMOS, CMOS, passive devices, diodes, fuses, etc.; NMOS and PMOS are used as examples here. Subsequently, a gate dielectric layer 120 can be formed on the substrate 110 using methods such as thermal oxidation, chemical vapor deposition, or atomic layer deposition. This gate dielectric layer 120 can be a silicon oxide layer, a silicon oxynitride layer, or a high dielectric constant material layer. In one specific embodiment of this application, the gate dielectric layer 120 is a silicon oxide layer.

[0025] Step S200: A polysilicon layer 130 is formed on the gate dielectric layer 120, and the polysilicon layer 130 is patterned to form a plurality of polysilicon gates 140.

[0026] Specifically, such as Figure 2 As shown, a polysilicon layer 130 is formed on the gate dielectric layer 120. In one embodiment of this invention, the thickness of the polysilicon layer 130 can be from 100 angstroms to 2000 angstroms; for example, in a preferred embodiment, the thickness of the polysilicon layer 130 is 500 angstroms. The polysilicon layer 130 is formed in an undoped state, that is, it does not contain any N-type or P-type dopant ions.

[0027] Further, the undoped polysilicon layer 130 is patterned to form multiple polysilicon gates 140. The polysilicon gates 140 are formed on the surface of the substrate 110 between shallow trench isolations, and are formed above the well regions. Preferably, the polysilicon gates 140 are formed in the middle region above the well regions to ensure that the subsequently formed lightly doped drain region, lightly doped source region, source region, and drain region fall within the well regions on both sides of the polysilicon gate 140, thus ensuring the electrical performance of the device. The patterning process specifically includes: coating the surface of the polysilicon layer 130 with photoresist, forming a patterned photoresist mask through exposure and development processes, and then using this photoresist mask as a mask to etch the polysilicon layer 130. The etching stops at the surface of the gate dielectric layer 120. After removing the remaining photoresist mask, multiple independent polysilicon gates 140 are obtained. Figure 3 As shown, in this embodiment, polysilicon gates 140 are formed in the first region 111 and the second region 112 of the substrate 110 to form the gate of NMOS device A and the gate of PMOS device B, respectively. The gate of NMOS device A and the gate of PMOS device B are isolated by a shallow trench isolation structure 180.

[0028] Since the polysilicon layer 130 is in an undoped state during patterning, all the polysilicon gates 140 formed are also in an undoped state. Each polysilicon gate 140 has a consistent etching rate during etching, which helps ensure etching uniformity and critical dimension consistency. Simultaneously, the undoped polysilicon does not generate non-volatile byproducts caused by doping during etching, avoiding the micromask effect. This effectively controls the line edge roughness of the polysilicon gate 140 sidewalls, improving the electrical performance and reliability of the semiconductor device while ensuring the morphological quality of the polysilicon gate 140.

[0029] Step S300: A protective layer 150 is formed on the surface of the gate dielectric layer 120. The protective layer 150 covers the sidewalls of the polysilicon gate 140 and the surface of the gate dielectric layer 120, and exposes the top of the polysilicon gate 140.

[0030] Specifically, such as Figure 5 As shown, a protective layer 150 is formed on the surface of the gate dielectric layer 120. This protective layer 150 covers the surface of the gate dielectric layer 120, the sidewalls of the polysilicon gate 140, and the surface of the gate dielectric layer 120 to prevent leakage and to avoid bombardment damage to the sidewalls of the polysilicon gate 140 during subsequent ion doping. However, the protective layer 150 does not cover the top of the pre-defined polysilicon gate, allowing the top of the pre-defined polysilicon gate to form a channel for ion implantation, facilitating ion implantation doping within the polysilicon gate 140.

[0031] In this embodiment, step S300, forming a protective layer 150 on the surface of the gate dielectric layer 120, can be accomplished by the following steps: Step S310: A protective layer 150 is formed on the surface of the gate dielectric layer 120 and the polysilicon gate 140, such as... Figure 4 As shown, the protective layer 150 is disposed on the surface of the gate dielectric layer 120, the sidewalls and top of the polysilicon gate 140. That is, the protective layer 150 conformally covers the entire surface of the structure, including the top and sidewalls of the polysilicon gate 140, and the exposed surface of the gate dielectric layer 120 between adjacent polysilicon gates 140.

[0032] Step S320: Remove the protective layer 150 on top of the polysilicon gate 140, while retaining the protective layer 150 on the sidewalls of the polysilicon gate 140 and the surface of the gate dielectric layer 120. The top of the protective layer 150 is flush with the top of the polysilicon gate 140. Figure 5 As shown. Specifically, anisotropic etching of the protective layer 150 is performed using an etch-back process. Since the polysilicon gate 140 is a structure protruding from the surface of the gate dielectric layer 120, the protective layer 150 on top of the polysilicon gate 140 is thinner than the protective layer 150 formed on the surface of the gate dielectric layer 120, while the equivalent thickness of the protective layer 150 on the sidewalls of the polysilicon gate 140 and the surface of the gate dielectric layer 120 is thicker in the vertical direction. By controlling the etching time, the protective layer 150 on top of the polysilicon gate 140 can be selectively removed while retaining the protective layer 150 on the sidewalls and the surface of the gate dielectric layer 120. After this step, the top of the polysilicon gate 140 is exposed to form a channel for ion implantation, while the sidewalls of the polysilicon gate 140 and the surface of the gate dielectric layer 120 are still covered by the protective layer 150, with the top of the protective layer 150 flush with the top of the polysilicon gate 140.

[0033] In this embodiment, the material of the protective layer 150 can be an organic bottom anti-reflective layer.

[0034] In one specific embodiment of this application, the thickness of the protective layer 150 is 100 angstroms to 2000 angstroms, for example, in a preferred embodiment, the thickness of the protective layer 150 is 1000 angstroms.

[0035] Step S400: Ion implantation doping is performed on the preset polysilicon gate. This step is performed after the polysilicon gate 140 has been patterned and the protective layer 150 has been formed. After the gate morphology has been etched, dopant ions are selectively introduced into a portion of the gate by ion implantation to adjust its conductivity type and electrical parameters.

[0036] It should be noted that, in this step, ion implantation doping of the preset polysilicon gate refers to ion implantation only on the device region that needs to be doped, while other regions are not implanted, thereby achieving selective doping. For example, in this embodiment, the polysilicon gate 140 is located in the first region 111 and the second region 112 of the substrate 110 to form the gate of NMOS device A and the gate of PMOS device B, respectively. During ion implantation, only the polysilicon gate in the NMOS region is implanted, while the polysilicon gate in the PMOS region is not implanted.

[0037] Since the sidewalls of the polysilicon gate 140 and the surface of the gate dielectric layer 120 are now covered by the protective layer 150, ion implantation can only enter the gate interior through the top of the polysilicon gate 140 exposed by the protective layer 150, without causing bombardment damage to the sidewalls or penetrating the gate dielectric layer 120 into the substrate 110. Thus, step S400 can protect the formed gate morphology and the substrate 110 region while achieving gate doping.

[0038] In this embodiment, step S400 can be implemented through the following steps: Step S410: A photoresist layer 160 is formed on the surface of the protective layer 150 and the polysilicon gate 140. In this embodiment, the thickness of the photoresist layer 160 is 50 nanometers to 500 nanometers. The photoresist layer 160 covers the top of the polysilicon gate 140, the protective layer 150 on the sidewalls of the polysilicon gate 140, and the protective layer 150 covering the surface of the gate dielectric layer 120.

[0039] The photoresist layer 160 serves as a mask layer for ion implantation in subsequent processes, defining the areas to be implanted. If the photoresist layer 160 is too thin, ions may penetrate it and enter areas that do not need implantation during the subsequent ion implantation process; if the photoresist layer 160 is too thick, it increases the difficulty and cost of the photolithography process. Optionally, the thickness of the photoresist layer 160 can be from tens of nanometers to five hundred nanometers. For example, in one specific embodiment of this application, the thickness of the photoresist layer 160 is 50 nanometers to 500 nanometers.

[0040] Step S420: Pattern the photoresist layer 160 to form an opening 161 exposing the top of a preset polysilicon gate, such as... Figure 6As shown, the location of the ion implantation region is defined by a photomask. After exposure and development, an opening 161 is formed in the photoresist layer 160. The position of the opening 161 corresponds to the top position of the polysilicon gate 140 to be doped. The top of the polysilicon gate 140 to be implanted is exposed through the opening 161, while the polysilicon gate 140 that does not need to be implanted remains covered by the photoresist layer 160. The size of the opening 161 is adapted to the size of the top of the polysilicon gate 140 to ensure that subsequent ion implantation can be accurately implanted into the polysilicon gate 140 without implanting into the sidewalls or the surface of the gate dielectric layer 120.

[0041] Step S430: Using the photoresist layer 160 as a mask, ion implantation is performed on the preset polysilicon gate through the opening 161. Since the sidewalls of the polysilicon gate 140 are covered by the protective layer 150, and the surface of the gate dielectric layer 120 is also covered by the protective layer 150, the implanted ions can only enter the preset polysilicon gate through the opening 161, and will not implant into the sidewalls of the preset polysilicon gate or penetrate the gate dielectric layer 120 to enter the substrate 110 region. In other words, this application achieves precise guidance of the ion implantation path through the selective exposure of the protective layer 150 in the vertical direction. Ions can be vertically incident on the preset polysilicon gate, pass through the opening 161, and enter the preset polysilicon gate, while in the lateral and bottom directions, the protective layer 150 completely shields the ions.

[0042] In this embodiment, the ion implantation energy can be from 1 keV to 20 keV. For example, in a preferred embodiment, the ion implantation energy is 10 keV. If the implantation energy is too low, for example, below 1 keV, ions cannot penetrate the surface of the polysilicon gate 140 to enter the interior, and the doping effect cannot be achieved. If the implantation energy is too high, ions may penetrate the thinner polysilicon gate 140 or penetrate the sidewall coverage portion of the protective layer 150, causing sidewall damage or substrate 110 contamination. Therefore, by controlling the implantation energy within the range of 1 keV to 20 keV, combined with the shielding effect of the protective layer 150, it can be ensured that ions are implanted only into the top region of the polysilicon gate 140 with sufficient implantation depth, while avoiding damage to the sidewalls and substrate 110.

[0043] Different types of MOSFETs select completely different types of dopant ions based on their structure and threshold voltage control requirements. In one specific embodiment of this application, ion implantation is performed on the polysilicon gate 140 located in the first region 111 of the substrate 110. If an NMOS device is formed in the first region 111, the dopant ions implanted are N-type ions, such as phosphorus ions or arsenic ions. That is, N-type ion implantation is performed on the polysilicon gate 140 of NMOS device A, while the polysilicon gate 140 of PMOS device B is covered by the photoresist layer 160 and not implanted. This achieves selective doping of different regions in the semiconductor device.

[0044] Optionally, after step S430, the method further includes step S440, removing the photoresist layer 160. Specifically, after ion implantation, the photoresist layer 160 is removed. This removal process can employ conventional photoresist removal processes in the art, such as oxygen plasma ashing. Because oxygen plasma has a high reaction rate with photoresist, while its etching rate for the protective layer 150 and the polysilicon gate 140 is extremely low, the photoresist layer 160 can be cleanly removed without damaging the underlying structure.

[0045] Step S500: Remove the protective layer 150 and anneal the preset polysilicon gate. Specifically, after removing the photoresist layer 160, the protective layer 150 is removed. This removal process can employ conventional organic material removal processes in the art, such as plasma ashing with oxygen-containing gas.

[0046] It should be noted that, in this application, the removal of the photoresist layer 160 and the removal of the protective layer 150 can be carried out sequentially in the same plasma process. First, oxygen plasma is used to remove the photoresist layer 160, and then oxygen-containing gas plasma is used to remove the protective layer 150. The oxygen-containing gas plasma can be oxygen or a mixture of oxygen and argon. Alternatively, they can be carried out in steps, each using an independent removal process.

[0047] After removing the protective layer 150, the preset polysilicon gate is annealed. This annealing process can be rapid thermal annealing, and the specific temperature can be adjusted according to the actual situation. The annealing process activates the implanted dopant ions to form effective conductive dopant, thereby reducing the resistivity of the polysilicon gate 140 and reducing the polysilicon depletion effect.

[0048] After annealing, the fabrication method of this application further includes subsequent standard semiconductor device process steps, namely: performing angled light doping implantation on the substrate 110 to form a drain lightly doped region 173 and a source lightly doped region 174 in the substrate 110 on both sides of the polysilicon gate 140; performing heavy doping implantation on the substrate 110 to form a drain region 172 on the side of the drain lightly doped region 173 away from the polysilicon gate 140, and forming a source region 171 on the side of the source lightly doped region 174 away from the polysilicon gate 140. Figure 7 As shown; wherein, the formation process of the above-mentioned lightly doped drain region 173, lightly doped source region 174, source region 171 and drain region 172 can be carried out using standard semiconductor device fabrication processes known in the art, and will not be described in detail here.

[0049] Therefore, this application provides a method for fabricating a semiconductor device. Compared with the existing process of selectively doping the polysilicon layer 130 before patterning it, this method places the polysilicon patterning step before ion implantation doping, so that the polysilicon layer 130 is still in an undoped state during patterning. This avoids the problem of etching uniformity degradation caused by different etching rates between doped and undoped regions. At the same time, since the polysilicon layer 130 is not doped with ions during patterning, no non-volatile byproducts caused by doping are generated during etching, avoiding the generation of micromask effect. This effectively improves the line edge roughness of the sidewall of the polysilicon gate 140, improves the gate morphology quality, and enhances the electrical performance and reliability of the semiconductor device.

[0050] In another aspect, the present invention provides a semiconductor device prepared by the above-described preparation method. The specific steps and beneficial effects of the preparation method for this semiconductor device have been described in detail above and will not be repeated here.

[0051] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0052] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided on which a gate dielectric layer is formed; A polysilicon layer is formed on the gate dielectric layer, and the polysilicon layer is patterned to form a plurality of polysilicon gates; A protective layer is formed on the surface of the gate dielectric layer, the protective layer covering the sidewalls of the polysilicon gate and the surface of the gate dielectric layer, and exposing the top of the polysilicon gate; Ion implantation doping is performed on the preset polysilicon gate; Remove the protective layer and anneal the preset polysilicon gate.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of a protective layer on the surface of the gate dielectric layer includes: A protective layer is formed on the gate dielectric layer and the surface of the polysilicon gate, the protective layer covering the surface of the gate dielectric layer, the sidewalls and the top of the polysilicon gate; Remove the protective layer on top of the polysilicon gate, and retain the protective layers on the sidewalls of the polysilicon gate and the surface of the gate dielectric layer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of ion implantation doping of the preset polysilicon gate includes: A photoresist layer is formed on the protective layer and the surface of the polysilicon gate; The photoresist layer is patterned to form an opening that exposes the top of a preset polysilicon gate; Using the photoresist layer as a mask, ion implantation is performed on a preset polysilicon gate through the opening.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, After ion implantation of a preset polysilicon gate through the opening using the photoresist layer as a mask, the method further includes: Remove the photoresist layer.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, After annealing the preset polysilicon gate, the method further includes: The substrate is subjected to oblique light doping implantation to form a drain light doped region and a source light doped region in the substrate on both sides of the polysilicon gate. The substrate is heavily doped and implanted to form a drain region on the side of the lightly doped drain region away from the polysilicon gate, and a source region is formed on the side of the lightly doped source region away from the polysilicon gate.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The protective layer is an organic bottom anti-reflective layer.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the protective layer is between 100 angstroms and 2000 angstroms.

8. The method for fabricating a semiconductor device according to claim 3, characterized in that, The thickness of the photoresist layer is 50 nanometers to 500 nanometers.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the polycrystalline silicon layer is between 100 angstroms and 2000 angstroms.

10. A semiconductor device, characterized in that, The semiconductor device is prepared by the method for preparing the semiconductor device according to any one of claims 1-9.

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