Semiconductor structure and method of manufacturing the same
Patent Information
- Application Number
- CN202611454554.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-18
- Publication Date
- 2026-10-30
AI Technical Summary
[0003]然而，对于结构调整后的半导体器件，不同掺杂区之间的位置和设置方式需要进行对应调整，且调整后的半导体器件的中压器件区和低压器件区在制备过程中需要经过多道离子注入工艺，工艺流程复杂
[0040]本申请意想不到的效果是：于衬底内形成相互隔离的第一电压区和第二电压区，所述第二电压区的工作电压小于所述第一电压区的工作电压，以调整半导体结构的应用平台和适用范围；通过于衬底的第一电压区和第二电压区内均形成第一阱区，所述第一电压区中的所述第一阱区两侧形成第二阱区，于所述第二电压区中的所述第一阱区内形成第三阱区，以优化半导体结构的工艺制程，减少生成成本，提升了生产效率和平台竞争力。
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Figure CN123021753A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology
[0002] Generally, semiconductor devices manufactured using a 55nm process typically include high-voltage, medium-voltage, and low-voltage device regions. Based on this, the high-voltage device region can be removed, while portions of the medium-voltage and low-voltage regions are retained. This optimizes the semiconductor device structure, saves area, and allows the restructured semiconductor device to serve as a new platform for mobile phones, wearable devices, and other applications, thereby meeting practical application requirements.
[0003] However, for semiconductor devices with adjusted structures, the positions and arrangement of different doped regions need to be adjusted accordingly. Furthermore, the medium-voltage and low-voltage device regions of the adjusted semiconductor devices require multiple ion implantation processes during fabrication, making the process complex. Therefore, a method is needed to optimize the process flow while fabricating the semiconductor devices described above. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor structure and its manufacturing method to optimize the process and device structure, save production costs and device area, and improve production efficiency and platform competitiveness.
[0005] This application provides a method for manufacturing a semiconductor structure, including:
[0006] A substrate is provided, the substrate comprising a first voltage region and a second voltage region that are isolated from each other, the operating voltage of the second voltage region being lower than the operating voltage of the first voltage region, and a first well region being formed in both the first voltage region and the second voltage region;
[0007] A second well region is formed on both sides of the first well region, and the second well region is also formed within the first well region in the first voltage region;
[0008] A third well region is formed within the first well region in the second voltage region;
[0009] The depths of the third well region, the second well region, and the first well region increase sequentially, and the doping types of the second well region and the third well region are different from those of the first well region.
[0010] In one embodiment, after forming the third well region, the method further includes:
[0011] A fourth well region is formed within the first well region of the second voltage region, the fourth well region being located within the first well region on one side of the third well region, and / or the fourth well region being located within the third well region and extending into the first well region on one side of the third well region;
[0012] The fourth well region has a smaller well depth than the third well region, and the doping type of the fourth well region is the same as that of the third well region.
[0013] In one embodiment, the second voltage region includes a first threshold region, a second threshold region, and a third threshold region that are isolated from each other, and the threshold voltages corresponding to the first threshold region, the second threshold region, and the third threshold region increase sequentially.
[0014] In the first threshold region, the fourth well region is located within the first well region on one side of the third well region;
[0015] In the second threshold region and the third threshold region, the fourth well region is located within the third well region and extends into the first well region on one side of the third well region.
[0016] In one embodiment, after forming the fourth well region, the method further includes:
[0017] A fifth well region is formed within the first well region of the second threshold region and the third threshold region, and the fifth well region is located below the portion of the fourth well region that extends into the first well region;
[0018] The fifth well region has a smaller well depth than the third well region, and the doping type of the fifth well region is different from that of the third well region.
[0019] In one embodiment, after forming the fifth well region, the method further includes:
[0020] A sixth well region is formed within the first well region below the fifth well region in the third threshold region;
[0021] A seventh well region is formed within the third well region below the fourth well region in the third threshold region;
[0022] The depths of the sixth and seventh well regions are smaller than the depth of the third well region, and the doping type of the sixth well region is different from that of the third well region, while the doping type of the seventh well region is the same as that of the third well region.
[0023] Accordingly, this application also provides a semiconductor structure, including:
[0024] The substrate includes a first voltage region and a second voltage region that are isolated from each other, wherein the operating voltage of the second voltage region is lower than the operating voltage of the first voltage region;
[0025] The first well region is located within the first voltage region and the second voltage region;
[0026] The second well region is located on both sides of the first well region and within the first well region in the first voltage region;
[0027] The third well region is located within the first well region of the second voltage region;
[0028] The depths of the third well region, the second well region, and the first well region increase sequentially, and the doping types of the second well region and the third well region are different from those of the first well region.
[0029] In one embodiment, the second voltage region includes a first threshold region, a second threshold region, and a third threshold region that are isolated from each other, and the threshold voltages corresponding to the first threshold region, the second threshold region, and the third threshold region increase sequentially.
[0030] In one embodiment, the semiconductor structure further includes:
[0031] The fourth well region is located within the first well region. The depth of the fourth well region is less than the depth of the third well region, and the doping type of the fourth well region is the same as that of the third well region.
[0032] In the first threshold region, the fourth well region is located on one side of the third well region;
[0033] In the second threshold region and the third threshold region, the fourth well region is located within the third well region and extends into the first well region on one side of the third well region.
[0034] In one embodiment, the semiconductor structure further includes:
[0035] The fifth well region is located within the first well region of the second threshold region and the third threshold region, and the fifth well region is located below the portion of the fourth well region that extends into the first well region;
[0036] The sixth well region is located within the first well region below the fifth well region in the third threshold region;
[0037] The seventh well region is located within the third well region, below the fourth well region in the third threshold region;
[0038] The depths of the fifth, sixth, and seventh well regions are all less than the depth of the third well region. The doping type of the seventh well region is the same as that of the third well region, while the doping types of the fifth and sixth well regions are different from those of the third well region.
[0039] In one embodiment, the semiconductor structure is manufactured using the semiconductor structure manufacturing method described above.
[0040] An unexpected effect of this application is that a first voltage region and a second voltage region are formed in the substrate, which are mutually isolated. The operating voltage of the second voltage region is lower than that of the first voltage region, thereby adjusting the application platform and applicable scope of the semiconductor structure. By forming a first well region in both the first voltage region and the second voltage region of the substrate, forming a second well region on both sides of the first well region in the first voltage region, and forming a third well region in the first well region in the second voltage region, the process of semiconductor structure is optimized, production costs are reduced, and production efficiency and platform competitiveness are improved. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 This is a schematic diagram of the structure corresponding to the step of forming a deep N-well in a semiconductor device manufacturing method in a related technology.
[0043] Figure 2 This is a schematic diagram of the structure corresponding to the step of forming a medium-voltage N-well in a semiconductor device manufacturing method in a related technology.
[0044] Figure 3 This is a schematic diagram of the structure corresponding to the step of forming a medium-voltage P-well in a semiconductor device manufacturing method in a related technology.
[0045] Figure 4 This is a schematic diagram of the structure corresponding to the step of forming a low-voltage N-well in a semiconductor device manufacturing method in a related technology.
[0046] Figure 5 This is a schematic diagram of the structure corresponding to the step of forming a low-voltage P-well in a semiconductor device manufacturing method in a related technology.
[0047] Figure 6This is a schematic diagram of the structure corresponding to the step of forming a low-voltage standard threshold voltage p-well in a semiconductor device manufacturing method in a related technology.
[0048] Figure 7 This is a schematic diagram of the structure corresponding to the step of forming a low-voltage standard threshold voltage n-well in a semiconductor device manufacturing method in a related technology.
[0049] Figure 8 This is a schematic diagram of the structure corresponding to the step of forming a low-voltage, high-threshold-voltage p-well in a semiconductor device manufacturing method in a related technology.
[0050] Figure 9 This is a schematic diagram of the structure corresponding to the step of forming a low-voltage, high-threshold-voltage n-well in a semiconductor device manufacturing method in a related technology.
[0051] Figure 10 This is a top view schematic diagram of the different device regions in a semiconductor device manufacturing method in a related technology.
[0052] Figure 11 This is a schematic diagram of the cross-sectional structure of the medium-voltage device unit region in a semiconductor device manufacturing method in a related technology.
[0053] Figure 12 This is a schematic diagram of the cross-sectional structure corresponding to the low threshold voltage region of the low-voltage device unit region in a semiconductor device manufacturing method in a related technology.
[0054] Figure 13 This is a schematic diagram of the cross-sectional structure corresponding to the standard threshold voltage region of the low-voltage device unit region in a semiconductor device manufacturing method in a related technology.
[0055] Figure 14 This refers to the low-voltage device cell region in a semiconductor device manufacturing method within a related technology.
[0056] Figure 15 A flowchart illustrating a method for manufacturing a semiconductor structure according to one embodiment of this application.
[0057] Figure 16 This is a schematic diagram of the structure corresponding to the step of forming the first well region in the manufacturing method of a semiconductor structure provided in one embodiment of this application.
[0058] Figure 17 This is a schematic diagram of the structure corresponding to the step of forming the second well region in the manufacturing method of the semiconductor structure provided in one embodiment of this application.
[0059] Figure 18 This is a schematic diagram of the structure corresponding to the step of forming the third well region in the manufacturing method of a semiconductor structure provided in one embodiment of this application.
[0060] Figure 19 This is a schematic diagram of the structure corresponding to the step of forming the fourth well region in the manufacturing method of the semiconductor structure provided in one embodiment of this application.
[0061] Figure 20 This is a schematic diagram of the structure corresponding to the step of forming the fifth well region in the manufacturing method of a semiconductor structure provided in one embodiment of this application.
[0062] Figure 21 This is a schematic diagram of the structure corresponding to the step of forming the sixth well region in the manufacturing method of the semiconductor structure provided in one embodiment of this application.
[0063] Figure 22 This is a schematic diagram of the structure corresponding to the step of forming the seventh well region in the manufacturing method of a semiconductor structure provided in one embodiment of this application.
[0064] Figure 23 This is a top view of the semiconductor structure manufacturing method provided in one embodiment of the present application, corresponding to the steps of forming the seventh well region, the gate, and the source / drain injection region.
[0065] Figure 24 for Figure 23 A schematic diagram of the cross-sectional structure of the first voltage region along the direction perpendicular to the gate extension.
[0066] Figure 25 for Figure 23 A schematic diagram of the cross-sectional structure of the first threshold region along the direction perpendicular to the gate extension.
[0067] Figure 26 for Figure 23 A schematic diagram of the cross-sectional structure of the second threshold region along the direction perpendicular to the gate extension.
[0068] Figure 27 for Figure 23 A schematic diagram of the cross-sectional structure of the third threshold region along the direction perpendicular to the gate extension.
[0069] The reference numerals in the figures include: 100-substrate; 100a-isolation structure; 101-deep N-well; 102-medium voltage N-well; 103-medium voltage P-well; 104-low voltage N-well; 105-low voltage P-well; 106-low voltage standard threshold voltage P-well; 107-low voltage standard threshold voltage n-well; 108-low voltage high threshold voltage p-well; 109-low voltage high threshold voltage n-well; 110-first mask layer; 111-second mask layer. Film layers; 112-Third mask layer; 113-Fourth mask layer; 114-Fifth mask layer; 115-Sixth mask layer; 116-Seventh mask layer; 117-Eighth mask layer; 118-Ninth mask layer; 120-Gate structure; 130-Heavily doped region; Z1-Medium voltage device cell region; Z2-Low voltage device cell region; z1-Low threshold voltage region; z2-Standard threshold voltage region; z3-High threshold voltage region;
[0070] 200 - Substrate; 201 - Shallow trench isolation structure; 210 - First well region; 210a - First photoresist layer; 220 - Second well region; 220a - Second photoresist layer; 230 - Third well region; 230a - Third photoresist layer; 240 - Fourth well region; 240a - Fourth photoresist layer; 250 - Fifth well region; 250a - Fifth photoresist layer; 260 - Sixth well region; 260a - Sixth photoresist layer; 270 - Seventh well region; 280 - Gate; 290 - Source / drain injection region; 270a - Seventh photoresist layer; X - First voltage region; Y - Second voltage region; Y1 - First threshold region; Y2 - Second threshold region; Y3 - Third threshold region. Detailed Implementation
[0071] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0073] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0074] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0075] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0076] Generally, semiconductor devices manufactured using the 55nm process typically include high-voltage device regions, medium-voltage device regions, and low-voltage device regions. Figures 1 to 10 This is a schematic diagram of some steps in a semiconductor device manufacturing method in a related technology. The following section combines... Figures 1 to 10 This section describes the manufacturing process of the corresponding parts of the low-voltage device region and the medium-voltage device region in the semiconductor device described above.
[0077] First, refer to Figure 1 A substrate 100 is provided, on which an active area (AA) is defined. Subsequently, a patterned first mask layer 110 is formed on the substrate 100 to cover areas of the substrate 100 that do not require a subsequent ion implantation process. Next, an ion implantation process is performed on the substrate 100 based on the first mask layer 110 to form a deep N-well (DNW) in the portion of the substrate 100 not covered by the first mask layer 110. Optionally, the substrate 100 is a P-type substrate, and a plurality of spaced-apart isolation structures 100a are formed within the substrate 100.
[0078] Next, refer to Figure 1 and Figure 2 The first mask layer 110 is removed; a patterned second mask layer 111 is formed on the substrate 100 to cover areas of the substrate 100 that do not require a subsequent ion implantation process; subsequently, an ion implantation process is performed on the substrate 100 based on the second mask layer 111 to form a medium voltage N-well (MNW) in the portion of the substrate 100 not covered by the second mask layer 111. Optionally, a portion of the medium voltage N-well 102 is located within a deep N-well 101, and another portion extends into the substrate 100.
[0079] Then refer to Figure 2 and Figure 3 The second mask layer 111 is removed; a patterned third mask layer 112 is formed on the substrate 100 to cover areas in the substrate 100 that do not require a subsequent ion implantation process; subsequently, an ion implantation process is performed on the substrate 100 based on the third mask layer 112 to form a medium voltage P-well 103 (MPW) in the portion of the substrate 100 not covered by the third mask layer 112. Optionally, the depth of the medium voltage P-well 103 is the same as the depth of the medium voltage N-well 102, and the medium voltage P-well 103 is formed in the substrate 100 on both sides of the medium voltage N-well 102 to form a medium voltage device cell region Z1 (see...). Figure 10 and Figure 11The medium-voltage device unit area Z1 includes, for example, 8V NMOS devices and / or 8V PMOS devices.
[0080] Next, refer to Figure 3 and Figure 4 The third mask layer 112 is removed; a patterned fourth mask layer 113 is formed on the substrate 100 to cover areas of the substrate 100 that do not require a subsequent ion implantation process; subsequently, an ion implantation process is performed on the substrate 100 based on the fourth mask layer 113 to form a low-voltage N-well (LNW) 104 in the portion of the substrate 100 not covered by the fourth mask layer 113. Optionally, the depth of the low-voltage N-well 104 is less than the depth of the medium-voltage N-well 102, and the low-voltage N-well 104 is formed within the deep N-well 101.
[0081] Then refer to Figure 4 and Figure 5 The fourth mask layer 113 is removed; then, a patterned fifth mask layer 114 is formed on the substrate 100 to cover areas of the substrate 100 that do not require a next ion implantation process; subsequently, an ion implantation process is performed on the substrate 100 based on the fifth mask layer 114 to form a low-voltage P-well 105 (LPW) in the portion of the substrate 100 not covered by the fifth mask layer 114. Optionally, the depth of the low-voltage P-well 105 is the same as the depth of the low-voltage N-well 104, and the low-voltage P-well 105 is formed within the deep N-well 101 and located on one side of the low-voltage N-well 104 to form a low-voltage device cell region Z2 (see [reference]). Figure 10 The low-threshold voltage region z1 (i.e., Low Voltage Threshold, LVT, see below) within the low-voltage device cell region Z2 (e.g., including 1.2V NMOS devices and 1.2V PMOS devices). Figure 12 ).
[0082] Next, refer to Figure 5 and Figure 6 The fifth mask layer 114 is removed; then, a patterned sixth mask layer 115 is formed on the substrate 100 to cover areas in the substrate 100 that do not require a subsequent ion implantation process; subsequently, an ion implantation process is performed on the substrate 100 based on the sixth mask layer 115 to form a low voltage standard voltage threshold p-well 106 (LV SVTp) within the low voltage N-well 104. Optionally, the depth of the low voltage standard voltage threshold p-well 106 is less than the depth of the low voltage N-well 104.
[0083] Then refer to Figure 6 and Figure 7 The sixth mask layer 115 is removed; then, a patterned seventh mask layer 116 is formed on the substrate 100 to cover areas in the substrate 100 that do not require a subsequent ion implantation process; subsequently, an ion implantation process is performed on the substrate 100 based on the seventh mask layer 116 to form a low voltage standard voltage threshold n-well 107 (LV SVTn) within the low voltage P-well 105. Optionally, the depth of the low voltage standard voltage threshold n-well 107 is the same as the depth of the low voltage standard voltage threshold p-well 106 to form the low voltage device cell region Z2 (see...). Figure 10 The standard threshold voltage region z2 (i.e., Standard Voltage Threshold, SVT, see [reference]) in [the context of the standard threshold voltage region z2]. Figure 13 ).
[0084] Next, refer to Figure 7 and Figure 8 The seventh mask layer 116 is removed, and a patterned eighth mask layer 117 is formed on the substrate 100 to cover areas in the substrate 100 that do not require a subsequent ion implantation process. Subsequently, an ion implantation process is performed on the substrate 100 based on the eighth mask layer 117 to form a low-voltage high-threshold p-well 108 (LV HVTp) within the low-voltage N-well 104. Optionally, the depth of the low-voltage high-threshold p-well 108 is less than the depth of the low-voltage N-well 104.
[0085] Continue reading Figure 8 Yes, it needs to be stated that... Figure 8 The relative positions of the low-voltage high-threshold p-well 108 and the low-voltage standard-threshold p-well 106 shown are for illustrative purposes only. In actual manufactured semiconductor structures, the well depth of the low-voltage high-threshold p-well 108 is the same as that of the low-voltage standard-threshold p-well 106, and the implantation dose of the ion implantation process corresponding to the low-voltage high-threshold p-well 108 is different from that corresponding to the low-voltage standard-threshold p-well 106.
[0086] Then refer to Figure 8 and Figure 9The eighth mask layer 117 is removed; then, a patterned ninth mask layer 118 is formed on the substrate 100 to cover areas in the substrate 100 that do not require a subsequent ion implantation process; subsequently, an ion implantation process is performed on the substrate 100 based on the ninth mask layer 118 to form a low-voltage high-threshold n-well 109 (LV HVTn) within the low-voltage P-well 105. Optionally, the depth of the low-voltage high-threshold n-well 109 is the same as the depth of the low-voltage high-threshold p-well 108.
[0087] Continue reading Figure 9 Yes, it needs to be stated that... Figure 9 The relative positions of the low-voltage high-threshold n-well 109 and the low-voltage standard-threshold n-well 107 shown are for illustrative purposes only. In actual manufactured semiconductor structures, the well depth of the low-voltage high-threshold n-well 109 is the same as that of the low-voltage standard-threshold n-well 107, and the implantation dose of the ion implantation process corresponding to the low-voltage high-threshold n-well 109 is different from that corresponding to the low-voltage standard-threshold n-well 107, thus forming the low-voltage device cell region Z2 (see...). Figure 10 The high threshold voltage region z3 (i.e., High Voltage Threshold, HVT, see [reference]) in the high threshold voltage region z3. Figure 14 ).
[0088] Figure 10 This is a top view schematic diagram of different device regions in a semiconductor device manufacturing method in a related technology, wherein direction A is the extension direction of the gate structure 120 and direction B is the perpendicular direction of the extension direction of the gate structure 120. Figure 11 for Figure 10 The diagram shows a cross-sectional view of the medium-voltage device unit region Z1 in the semiconductor device along the extension direction (i.e., direction B) of the gate structure 120. Figures 12 to 14 They are respectively Figure 10 The diagram shows a cross-sectional view of different voltage regions in the low-voltage device cell region Z2 of the semiconductor device, perpendicular to the extension direction (i.e., direction B) of the gate structure 120. Figure 12 This is a schematic diagram of the cross-sectional structure corresponding to the low threshold voltage region. Figure 13 This is a schematic diagram of the cross-sectional structure corresponding to the standard threshold voltage region. Figure 14 This is a schematic diagram of the cross-sectional structure corresponding to the high threshold voltage region.
[0089] Next, refer to Figures 10 to 14A gate structure 120 is formed on a substrate 100, and heavily doped regions 130 are formed in the substrate 100 on both sides of the gate structure 120 to form NMOS device units and PMOS device units in each device unit region. The operating voltage of the low-voltage device unit region Z2 (e.g., 1.2V) is less than the operating voltage of the medium-voltage device unit region Z1 (e.g., 8V). The threshold voltages corresponding to the low threshold voltage region Z1, the standard threshold voltage region Z2, and the high threshold voltage region Z3 increase sequentially.
[0090] However, please continue reading Figure 10 When removing the high-voltage device region from the semiconductor device and retaining only portions of the medium-voltage device unit region Z1 and the low-voltage device unit region Z2, the implantation depth of the deep N-well 101 can be adaptively reduced according to structural adjustments. The positions and arrangement of other doped regions also need to be adjusted accordingly based on the semiconductor device's configuration. Therefore, a method is needed to optimize the process flow while fabricating the semiconductor device as described above.
[0091] Therefore, it is necessary to provide a semiconductor structure and its manufacturing method to optimize the process and device structure, save production costs and device area, and improve production efficiency and platform competitiveness.
[0092] Figure 15 A flowchart illustrating a method for manufacturing a semiconductor structure according to one embodiment of this application. See also... Figure 15 One embodiment of this application provides a method for manufacturing a semiconductor structure, which includes the following steps S01 to S03.
[0093] Step S01: Provide a substrate, the substrate including a first voltage region and a second voltage region that are isolated from each other, the operating voltage of the second voltage region is lower than the operating voltage of the first voltage region, and a first well region is formed in both the first voltage region and the second voltage region.
[0094] Step S02: A second well region is formed on both sides of the first well region, and the second well region is also formed within the first well region in the first voltage region.
[0095] Step S03: A third well region is formed within the first well region in the second voltage region; wherein the well depths of the third well region, the second well region, and the first well region increase sequentially, and the doping types of the second well region and the third well region are different from the doping type of the first well region.
[0096] The semiconductor structure manufacturing method described above forms a first voltage region and a second voltage region that are isolated from each other in the substrate. The operating voltage of the second voltage region is lower than that of the first voltage region, so as to adjust the application platform and applicable range of the semiconductor structure. By forming a first well region in both the first voltage region and the second voltage region of the substrate, forming a second well region on both sides of the first well region in the first voltage region, and forming a third well region in the first well region in the second voltage region, the process technology and device structure of the semiconductor structure are optimized, the production cost is reduced and the device area is saved, and the production efficiency and platform competitiveness are improved.
[0097] See Figure 16 In one embodiment, a substrate 200 is provided, and the process of forming a first well region 210 within the substrate 200 includes: forming a patterned first photoresist layer 210a on the substrate 200, and performing an ion implantation process on the substrate 200 based on the first photoresist layer 210a to form the first well region 210 within the substrate 200. Optionally, after forming the first well region 210, the first photoresist layer 210a is removed using an ashing process and a wet cleaning process.
[0098] It should be noted that, for reference Figure 16 and Figure 23 ( Figure 23 In one embodiment, the substrate 200 includes a first voltage region X and a second voltage region Y disposed adjacently, and the operating voltage corresponding to the first voltage region X is greater than the operating voltage corresponding to the second voltage region Y. Further, the second voltage region Y includes a first threshold region Y1, a second threshold region Y2, and a third threshold region Y3 that are isolated from each other, and the threshold voltages corresponding to the first threshold region Y1, the second threshold region Y2, and the third threshold region Y3 increase sequentially.
[0099] Continue reading Figure 16 In one embodiment, a shallow trench isolation structure 201 is formed in the substrate 200 before the first well region 210 is formed in the substrate 200, so as to achieve isolation between different well regions.
[0100] Then refer to Figure 17 and Figure 23 In one embodiment, a second well region 220 is formed on both sides of the first well region 210, and the second well region 220 is also formed within the first well region 210 in the first voltage region X. The well depth of the second well region 220 is less than the well depth of the first well region 210, and the doping type of the second well region 220 is different from that of the first well region 210.
[0101] For example, the process of forming a second well region 220 within a substrate 200 includes: forming a patterned second photoresist layer 220a on the substrate 200, and performing an ion implantation process on the substrate 200 based on the second photoresist layer 220a to form the second well region 220 within the substrate 200. Optionally, after forming the second well region 220, the second photoresist layer 220a is removed using an ashing process and a wet cleaning process.
[0102] Next, refer to Figure 18 and Figure 23 In one embodiment, a third well region 230 is formed within a first well region 210 in a second voltage region Y; wherein the depth of the third well region 230 is less than the depths of the second well region 220 and the first well region 210 respectively, and the doping type of the third well region 230 is different from that of the first well region 210.
[0103] For example, the process of forming a third well region 230 within the first well region 210 includes: forming a patterned third photoresist layer 230a on a substrate 200, and performing an ion implantation process on the substrate 200 based on the third photoresist layer 230a to form the third well region 230 within the first well region 210. Optionally, after forming the third well region 230, the third photoresist layer 230a is removed using an ashing process and a wet cleaning process.
[0104] Then refer to Figure 19 and Figure 23 In one embodiment, after forming the third well region 230, the method of manufacturing the semiconductor structure further includes: forming a fourth well region 240 within a first well region 210 of the second voltage region Y, wherein the fourth well region 240 is located within a first well region 210 on one side of the third well region 230, and / or the fourth well region 240 is located within the third well region 230 and extends into a first well region 210 on one side of the third well region 230; wherein the well depth of the fourth well region 240 is less than the well depth of the third well region 230, and the doping type of the fourth well region 240 is the same as the doping type of the third well region 230.
[0105] For example, the process of forming a fourth well region 240 within the first well region 210 of the second voltage region Y includes: forming a patterned fourth photoresist layer 240a on a substrate 200, and performing an ion implantation process on the substrate 200 based on the fourth photoresist layer 240a to form the fourth well region 240 within the first well region 210 of the second voltage region Y. Optionally, after forming the fourth well region 240, the fourth photoresist layer 240a is removed using an ashing process and a wet cleaning process.
[0106] See Figures 25 to 27In one embodiment, in the first threshold region Y1, the fourth well region 240 is located within the first well region 210 on one side of the third well region 230; in the second threshold region Y2 and the third threshold region Y3, the fourth well region 240 is located within the third well region 230 and extends into the first well region 210 on one side of the third well region 230.
[0107] Next, refer to Figure 20 and Figure 23 In one embodiment, after forming the fourth well region 240, the method of manufacturing the semiconductor structure further includes: forming a fifth well region 250 within the first well region 210 of the second threshold region Y2 and the third threshold region Y3, wherein the fifth well region 250 is located below the portion of the fourth well region 240 that extends into the first well region 210; wherein the well depth of the fifth well region 250 is less than the well depth of the third well region 230, and the doping type of the fifth well region is different from the doping type of the third well region 230.
[0108] For example, the process of forming a fifth well region 250 within the first well region 210 of the second threshold region Y2 and the third threshold region Y3 includes: forming a patterned fifth photoresist layer 250a on a substrate 200, and performing an ion implantation process on the substrate 200 based on the fifth photoresist layer 250a to form the fifth well region 250 within the first well region 210 of the second threshold region Y2 and the third threshold region Y3. Optionally, after forming the fifth well region 250, the fifth photoresist layer 250a is removed using an ashing process and a wet cleaning process.
[0109] Then refer to Figures 21 to 23 In one embodiment, after forming the fifth well region 250, the method of manufacturing the semiconductor structure further includes: forming a sixth well region 260 in a first well region 210 below the fifth well region 250 in the third threshold region Y3; and forming a seventh well region 270 in a third well region 230 below the fourth well region 240 in the third threshold region Y3; wherein the well depths of the sixth well region 260 and the seventh well region 270 are respectively less than the well depth of the third well region 230, and the doping type of the sixth well region 260 is different from the doping type of the third well region 230, while the doping type of the seventh well region 270 is the same as the doping type of the third well region 230.
[0110] For example, see [link to relevant documentation]. Figures 21 to 23The process of forming a sixth well region 260 and a seventh well region 270 within the first well region 210 of the second threshold region Y2 and the third threshold region Y3 includes: forming a patterned sixth photoresist layer 260a on the substrate 200; performing an ion implantation process on the substrate 200 based on the sixth photoresist layer 260a to form the sixth well region 260 within the first well region 210 below the fifth well region 250 in the third threshold region Y3; forming a patterned seventh photoresist layer 270a on the substrate 200; and performing an ion implantation process on the substrate 200 based on the seventh photoresist layer 270a to form the seventh well region 270 within the third well region 230 below the fourth well region 240 in the third threshold region Y3. Optionally, after forming the sixth well region 260 and the seventh well region 270, the sixth photoresist layer 260a and the seventh photoresist layer 270a are removed by an ashing process and a wet cleaning process, respectively.
[0111] Next, refer to Figures 23 to 27 After forming the seventh well region 270, the semiconductor structure manufacturing method further includes: forming a gate 280 on a substrate 200; and forming source / drain implantation regions 290 in the substrate 200 on both sides of the gate 280. Optionally, the implantation depth of the source / drain implantation regions 290 is less than the implantation depth of the fourth well region 240.
[0112] See Figure 23 In one embodiment, the semiconductor structure includes a first voltage region X and a second voltage region Y, and the operating voltage of the second voltage region Y is less than the operating voltage of the first voltage region X. The second voltage region Y includes a first threshold region Y1, a second threshold region Y2 and a third threshold region Y3 with successively increasing threshold voltages.
[0113] Continue reading Figure 23 In one embodiment, the first voltage region X is the medium voltage (MV) region, the second voltage region Y is the low voltage (LV) region, the first threshold region Y1 is the low voltage threshold (LVT) region, the second threshold region Y2 is the standard voltage threshold (SVT) region, and the third threshold region Y3 is the high voltage threshold (HVT) region.
[0114] In one embodiment, substrate 200 is a P-type substrate, first well region 210 is a medium-voltage N-well (MVNW or MNW), second well region 220 is a medium-voltage P-well (MVPW or MPW), third well region 230 is a low-voltage P-well (LVPW or LPW), fourth well region 240 is a low-voltage standard voltage threshold p-well (LV SVTp), fifth well region 250 is a low-voltage standard voltage threshold n-well (LVSVTn), sixth well region 260 is a low-voltage high voltage threshold n-well (LV HVTn), and seventh well region 270 is a low-voltage high voltage threshold p-well (LV HVTp). In other embodiments of this application, the doping type of each doped region as described above can be adjusted according to actual needs, and this application does not impose any restrictions on this.
[0115] contrast Figure 10 and Figure 23 , Figure 11 and Figure 24 , Figure 12 and Figure 25 , Figure 13 and Figure 26 , Figure 14 and Figure 27 As is known, in a typical platform with high-voltage devices, the substrate 100 includes a deep N-well 101, a medium-voltage N-well 102, and a low-voltage N-well 104. In a semiconductor structure manufacturing method provided in one embodiment of this application, in a platform without high-voltage devices, the original deep N-well and medium-voltage N-well are merged to form a new intermediate sub-well. At the same time, the relevant parameters of the ion implantation process of the medium-voltage N-well are adjusted accordingly, such as the ion implantation energy and implantation dose. Subsequently, the merged medium-voltage well is merged with the low-voltage N-well. At the same time, the relevant parameters of the ion implantation process of the low-voltage N-well are adjusted accordingly. An inversion ion implantation process is performed on the low-voltage N-well to optimize the electrical performance of the PMOS device formed in the low threshold voltage region. The final low-voltage N-well corresponds to the first well region 210 in this application.
[0116] As can be seen, the semiconductor structure manufacturing method described above optimizes the semiconductor structure without affecting its normal operation, saves the cost of two photomasks, thereby helping to reduce the production cost of the semiconductor structure and save device area, and improve production efficiency and platform competitiveness.
[0117] Accordingly, please continue to refer to Figures 23 to 27 One embodiment of this application also provides a semiconductor structure, including a substrate 200, a first well region 210, a second well region 220, and a third well region 230 located within the substrate 200. The substrate 200 includes a first voltage region X and a second voltage region Y that are isolated from each other. The operating voltage of the second voltage region Y is lower than the operating voltage of the first voltage region X. The first well region 210 is located within the first voltage region X and the second voltage region Y. The second well region 220 is located on both sides of the first well region 210 and within the first well region 210 in the first voltage region X. The third well region 230 is located within the first well region 210 in the second voltage region Y. The well depths of the third well region 230, the second well region 220, and the first well region 210 increase sequentially, and the doping types of the second well region 220 and the third well region 230 are different from the doping types of the first well region 210.
[0118] As described above, the semiconductor device has a first voltage region and a second voltage region isolated from each other in the substrate. The operating voltage of the second voltage region is lower than that of the first voltage region, so as to adjust the application platform and applicable range of the semiconductor structure. By setting a first well region in both the first voltage region and the second voltage region of the substrate, a second well region is formed on both sides of the first well region in the first voltage region, and a third well region is formed in the first well region in the second voltage region, so as to optimize the device structure of the semiconductor structure, reduce the production cost and save the device area, and improve the production efficiency and platform competitiveness.
[0119] Continue reading Figures 23 to 27 In one embodiment, the second voltage region Y includes a first threshold region Y1, a second threshold region Y2 and a third threshold region Y3 that are isolated from each other, and the threshold voltages corresponding to the first threshold region Y1, the second threshold region Y2 and the third threshold region Y3 increase sequentially.
[0120] See Figures 23 to 27 In one embodiment, the semiconductor structure further includes a fourth well region 240 located within the first well region 210, the depth of the fourth well region 240 being less than the depth of the third well region 230, and the doping type of the fourth well region 240 being the same as that of the third well region 230; in the first threshold region Y1, the fourth well region 240 is located on one side of the third well region 230; in the second threshold region Y2 and the third threshold region Y3, the fourth well region 240 is located within the third well region 230 and extends into the first well region 210 on one side of the third well region 230.
[0121] Continue reading Figures 23 to 27 In one embodiment, the semiconductor structure further includes a fifth well region 250, a sixth well region 260, and a seventh well region 270. The fifth well region 250 is located within a first well region 210 in the second threshold region Y2 and the third threshold region Y3, and is located below the portion of the fourth well region 240 that extends into the first well region 210. The sixth well region 260 is located within the first well region 210 below the fifth well region 250 in the third threshold region Y3. The seventh well region 270 is located within a third well region 230 below the fourth well region 240 in the third threshold region Y3. The well depths of the fifth well region 250, the sixth well region 260, and the seventh well region 270 are all less than the well depth of the third well region 230. The doping type of the seventh well region 270 is the same as that of the third well region 230, while the doping types of the fifth well region 250 and the sixth well region 260 are different from those of the third well region 230.
[0122] In one embodiment, substrate 200 is a P-type substrate, first well region 210 is a medium-voltage N-well (MVNW or MNW), second well region 220 is a medium-voltage P-well (MVPW or MPW), third well region 230 is a low-voltage P-well (LVPW or LPW), fourth well region 240 is a low-voltage standard voltage threshold p-well (LV SVTp), fifth well region 250 is a low-voltage standard voltage threshold n-well (LVSVTn), sixth well region 260 is a low-voltage high voltage threshold n-well (LV HVTn), and seventh well region 270 is a low-voltage high voltage threshold p-well (LV HVTp). In one embodiment, the semiconductor structure is manufactured using the semiconductor structure manufacturing method described above.
[0123] An unexpected effect of this application is that a first voltage region and a second voltage region are formed in the substrate, which are mutually isolated. The operating voltage of the second voltage region is lower than that of the first voltage region, so as to adjust the application platform and applicable scope of the semiconductor structure. By forming a first well region in both the first voltage region and the second voltage region of the substrate, forming a second well region on both sides of the first well region in the first voltage region, and forming a third well region in the first well region in the second voltage region, the process technology and device structure of the semiconductor structure are optimized, the production cost is reduced and the device area is saved, and the production efficiency and platform competitiveness are improved.
[0124] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0126] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first voltage region and a second voltage region that are isolated from each other, the operating voltage of the second voltage region being lower than the operating voltage of the first voltage region, and a first well region being formed in both the first voltage region and the second voltage region; A second well region is formed on both sides of the first well region, and the second well region is also formed within the first well region in the first voltage region; A third well region is formed within the first well region in the second voltage region; The depths of the third well region, the second well region, and the first well region increase sequentially, and the doping types of the second well region and the third well region are different from those of the first well region.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After forming the third well region, the method further includes: A fourth well region is formed within the first well region of the second voltage region, the fourth well region being located within the first well region on one side of the third well region, and / or the fourth well region being located within the third well region and extending into the first well region on one side of the third well region; The fourth well region has a smaller well depth than the third well region, and the doping type of the fourth well region is the same as that of the third well region.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The second voltage region includes a first threshold region, a second threshold region, and a third threshold region that are isolated from each other, and the threshold voltages corresponding to the first threshold region, the second threshold region, and the third threshold region increase sequentially. In the first threshold region, the fourth well region is located within the first well region on one side of the third well region; In the second threshold region and the third threshold region, the fourth well region is located within the third well region and extends into the first well region on one side of the third well region.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, After forming the fourth well region, the method further includes: A fifth well region is formed within the first well region of the second threshold region and the third threshold region, and the fifth well region is located below the portion of the fourth well region that extends into the first well region; The fifth well region has a smaller well depth than the third well region, and the doping type of the fifth well region is different from that of the third well region.
5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, After forming the fifth well region, the method further includes: A sixth well region is formed within the first well region below the fifth well region in the third threshold region; A seventh well region is formed within the third well region below the fourth well region in the third threshold region; The depths of the sixth and seventh well regions are smaller than the depth of the third well region, and the doping type of the sixth well region is different from that of the third well region, while the doping type of the seventh well region is the same as that of the third well region.
6. A semiconductor structure, characterized in that, include: The substrate includes a first voltage region and a second voltage region that are isolated from each other, wherein the operating voltage of the second voltage region is lower than the operating voltage of the first voltage region; The first well region is located within the first voltage region and the second voltage region; The second well region is located on both sides of the first well region and within the first well region in the first voltage region; The third well region is located within the first well region of the second voltage region; The depths of the third well region, the second well region, and the first well region increase sequentially, and the doping types of the second well region and the third well region are different from those of the first well region.
7. The semiconductor structure according to claim 6, characterized in that, The second voltage region includes a first threshold region, a second threshold region, and a third threshold region that are isolated from each other, and the threshold voltages corresponding to the first threshold region, the second threshold region, and the third threshold region increase sequentially.
8. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure also includes: The fourth well region is located within the first well region. The depth of the fourth well region is less than the depth of the third well region, and the doping type of the fourth well region is the same as that of the third well region. In the first threshold region, the fourth well region is located on one side of the third well region; In the second threshold region and the third threshold region, the fourth well region is located within the third well region and extends into the first well region on one side of the third well region.
9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes: The fifth well region is located within the first well region of the second threshold region and the third threshold region, and the fifth well region is located below the portion of the fourth well region that extends into the first well region; The sixth well region is located within the first well region below the fifth well region in the third threshold region; The seventh well region is located within the third well region, below the fourth well region in the third threshold region; The depths of the fifth, sixth, and seventh well regions are all less than the depth of the third well region. The doping type of the seventh well region is the same as that of the third well region, while the doping types of the fifth and sixth well regions are different from those of the third well region.
10. The semiconductor structure according to claim 6, characterized in that, It is manufactured using the semiconductor structure manufacturing method described in any one of claims 1 to 5.