Ion implantation method, preparation method, device and apparatus for silicon-on-insulator
Patent Information
- Application Number
- CN202510546500.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2026-10-30
AI Technical Summary
[0004]有鉴于此，本发明提供了一种绝缘体上硅的离子注入方法、制备方法、器件及设备，以解决阈值电压受顶层硅厚度的影响容易产生偏差的问题
[0004]有鉴于此，本发明提供了一种绝缘体上硅的离子注入方法、制备方法、器件及设备，以解决阈值电压受顶层硅厚度的影响容易产生偏差的问题。
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Figure CN123021759A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and specifically to an ion implantation method, preparation method, device, and equipment for silicon on insulator. Background Technology
[0002] Silicon on Insulator (SOI) typically consists of a top silicon layer, a buried oxide (BOX) layer, and a substrate. As integrated circuit devices continue to shrink and their performance improves, SOI technology plays a crucial role in reducing power consumption, increasing device speed, and enhancing radiation resistance.
[0003] In traditional Complementary Metal Oxide Semiconductor (CMOS) processes, ion implantation (IMP) is used to control the doping of the channel and well regions to achieve the desired threshold voltage (VTL). The ion implantation parameters are typically fixed. However, for SOI devices, variations in the thickness of the top silicon layer directly affect the electrostatic properties of the semiconductor device, thus significantly impacting the VTL. If fixed ion implantation parameters are used without considering variations in the top silicon thickness, threshold voltage deviations and inconsistencies can easily occur, consequently affecting the performance and yield of the semiconductor device. Summary of the Invention
[0004] In view of this, the present invention provides an ion implantation method, preparation method, device and equipment for silicon on insulator, so as to solve the problem that the threshold voltage is easily deviated by the thickness of the top silicon layer.
[0005] In a first aspect, the present invention provides an ion implantation method for silicon-on-insulator (SiO2), the SiO2 comprising a top layer silicon for forming a target semiconductor device, the ion implantation method comprising: obtaining a detection thickness of the top layer silicon; obtaining a target threshold voltage required for the target semiconductor device; determining target ion implantation parameters based on the detection thickness, the target threshold voltage, and a mapping model, wherein the mapping model is used to characterize the correspondence between the thickness of the top layer silicon, the threshold voltage, and the ion implantation parameters, the target ion implantation parameters being the ion implantation parameters required for the target semiconductor device to reach the target threshold voltage, the ion implantation parameters including ion implantation dose and ion implantation energy; and controlling an ion implanter to perform ion implantation processing on the well region of the top layer silicon based on the target ion implantation parameters.
[0006] In one alternative implementation, the mapping model is a data table characterizing the correspondence between multiple top silicon thicknesses, multiple device types, multiple threshold voltages, and multiple ion implantation parameters; or the mapping model is a fitted curve characterizing the variation relationship between ion implantation dose parameters and threshold voltages under different top silicon thicknesses.
[0007] In an alternative implementation, before determining the target ion implantation parameters based on the detected thickness, target threshold voltage, and mapping model, the ion implantation method for silicon on insulator further includes: establishing a mapping model based on the target ion implantation parameters corresponding to the multiple top silicon thicknesses determined by detection.
[0008] In an optional implementation, before determining the target ion implantation parameters based on the detected thickness, target threshold voltage, and mapping model, the ion implantation method for silicon on insulator further includes: determining whether the detected thickness is a desired thickness, wherein the desired thickness is the thickness that the top silicon is ideally expected to reach; and when the detected thickness is the desired thickness, controlling an ion implanter to perform ion implantation on the well region of the top silicon according to preset ion implantation parameters, wherein the preset ion implantation parameters are the ion implantation parameters required for the top silicon to form a target semiconductor device at the desired thickness.
[0009] In one alternative implementation, the target ion implantation parameters are determined based on the detected thickness, the target threshold voltage, and the mapping model, including: when the detected thickness is not the desired thickness, determining the target ion implantation parameters based on the detected thickness, the target threshold voltage, and the mapping model.
[0010] In one optional implementation, after controlling the ion implanter to perform ion implantation on the well region of the top silicon according to the target ion implantation parameters, the ion implantation method for silicon on insulator further includes: obtaining a detection threshold voltage, wherein the detection threshold voltage is a threshold voltage obtained after testing the target semiconductor device; and iteratively optimizing the mapping model based on the detection threshold voltage.
[0011] In one alternative implementation, obtaining the detection thickness of the top silicon layer includes obtaining the detection thickness of the top silicon layer from an ellipsometry or an X-ray reflectometer.
[0012] In one optional implementation, the ion implantation parameters further include ion implantation elements. The target ion implantation parameters are determined based on the detection thickness, target threshold voltage, and mapping model, including: determining the ion implantation dose and ion implantation energy based on the detection thickness, target threshold voltage, and mapping model; and determining the ion implantation elements based on the type of the target semiconductor device.
[0013] In a second aspect, the present invention provides a method for fabricating a semiconductor device, the method comprising: providing silicon-on-insulator (SOI), wherein the SOI includes a top layer of silicon for forming a target semiconductor device; performing ion implantation on a well region of the top layer of silicon based on target ion implantation parameters provided by the ion implantation method for SOI of the first aspect or any corresponding embodiment thereof; and performing annealing and film deposition processes on the top layer of silicon after ion implantation to form the target semiconductor device.
[0014] Thirdly, the present invention provides a semiconductor device, which is prepared by the semiconductor device preparation method of the first aspect or any corresponding embodiment described above.
[0015] Fourthly, the present invention provides an ion implantation apparatus for silicon-on-insulator (SiI), comprising a thickness measuring instrument, a control module, and an ion implanter; the thickness measuring instrument and the control module are communicatively connected, and the ion implanter and the control module are communicatively connected; the thickness measuring instrument is used to detect the thickness of the top silicon layer to obtain the detected thickness; the control module is used to obtain the detected thickness of the top silicon layer from the thickness measuring instrument; the control module is also used to obtain the target threshold voltage required for the target semiconductor device; the control module is also used to determine target ion implantation parameters based on the detected thickness, the target threshold voltage, and a mapping model, wherein the mapping model is used to characterize the correspondence between the thickness of the top silicon layer, the threshold voltage, and the ion implantation parameters, and the target ion implantation parameters are the ion implantation parameters required for the target semiconductor device to reach the target threshold voltage, including the ion implantation dose and the ion implantation energy; the control module is also used to control the ion implanter to perform ion implantation treatment on the well region of the top silicon layer according to the target ion implantation parameters.
[0016] Fifthly, the present invention provides a semiconductor device fabrication system, comprising: an ion implantation apparatus for silicon-on-insulator as described in the third aspect above or any corresponding embodiment thereof. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of a silicon-on-insulator structure according to an embodiment of the present invention;
[0019] Figure 2This is a schematic diagram of another silicon-on-insulator structure according to an embodiment of the present invention;
[0020] Figure 3 This is a schematic diagram of the structure of an ion implantation device for silicon on insulator according to an embodiment of the present invention;
[0021] Figure 4 This is a schematic flowchart of an ion implantation method for silicon on an insulator according to an embodiment of the present invention;
[0022] Figure 5 and Figure 6 This is a schematic diagram of an ion implantation process according to an embodiment of the present invention;
[0023] Figure 7 This is a schematic flowchart of another method for ion implantation of silicon on an insulator according to an embodiment of the present invention;
[0024] Figure 8 This is a schematic flowchart of another method for ion implantation of silicon on an insulator according to an embodiment of the present invention.
[0025] Reference numerals: 110, substrate; 120, buried oxide layer; 130, top silicon layer; 131, trap region; 140, trap-rich layer; 310, thickness measuring instrument; 320, control module; 330, ion implanter. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.
[0027] All other embodiments obtained by those skilled in the art without inventive effort based on the embodiments described herein are within the scope of protection of this invention.
[0028] The ion implantation method for silicon on insulators provided by this invention can be applied to the ion implantation step in the semiconductor device fabrication process.
[0029] For example, semiconductor devices can refer to devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), N-type input / output (IO) transistors, P-type IO transistors, low-noise amplifiers (LNAs), or switch transistors (SWs).
[0030] The ion implantation method for silicon-on-insulator (SOI) provided by this invention dynamically adjusts the ion implantation parameters of the well region according to the actual thickness of the top silicon layer during the fabrication of semiconductor devices. This enables precise control of the threshold voltage of the semiconductor device, ensuring the consistency of the threshold voltage, thereby improving the performance and yield of the semiconductor device.
[0031] The ion implantation method for silicon on insulators provided by this invention relies on the ion implantation equipment for silicon on insulators. For ease of understanding, the structure of silicon on insulators and the composition of the ion implantation equipment for silicon on insulators will be described below with reference to the accompanying drawings.
[0032] like Figure 1 As shown, SOI generally includes a substrate 110, a buried oxide layer 120 and a top silicon layer 130 stacked from bottom to top. For example, the buried oxide layer 120 is disposed on the upper surface of the substrate 110 and the top silicon layer 130 is disposed on the upper surface of the buried oxide layer 120.
[0033] Specifically, the substrate 110 (SI Base) is typically made of silicon and serves as the underlying support structure to provide mechanical support for the SOI. The substrate 110 has high resistivity to reduce unnecessary current conduction within the substrate 110 and lower substrate noise interference.
[0034] The top silicon (130) can be made of mono-crystal silicon. Top silicon (130) is the primary area for manufacturing semiconductor devices. Utilizing the excellent electrical properties of mono-crystal silicon, various functions (such as signal processing and logic operations) can be implemented. Due to differences in wafer manufacturing processes, the thickness of the top silicon (130) in SOI may vary within or between batches, ranging from 10 nm to tens of nm.
[0035] The buried oxide layer 120 can be made of silicon dioxide (SiO2), an electrical isolation substrate 110, and a top silicon layer 130, thereby reducing parasitic capacitance, reducing leakage current, improving device performance and reliability, and enhancing the device's radiation resistance.
[0036] Optionally, SOI can also be as follows: Figure 2 The diagram shows a substrate 110, a trap-rich layer 140, a buried oxide layer 120, and a top silicon layer 130 stacked from bottom to top.
[0037] Specifically, the trap-rich layer 140 is located between the substrate 110 and the buried oxide layer 120, and has a large number of trap states that can trap electrons or holes. By trapping and releasing charge carriers, the electrical characteristics of the semiconductor device can be adjusted, affecting parameters such as the device threshold voltage and carrier mobility, thereby optimizing device performance.
[0038] like Figure 3 As shown, the ion implantation equipment for silicon on insulators includes a thickness measuring instrument 310, a control module 320, and an ion implanter 330.
[0039] The thickness measuring instrument 310 and the ion implanter 330 are both communicatively connected to the control module 320. The thickness measuring instrument 310 is used to detect the thickness of the top silicon layer 130 and sends the detected thickness (denoted as the detected thickness) to the control module 320. After determining the ion implantation parameters based on the detected thickness, the control module 320 controls the ion implanter 330 to perform ion implantation on the well region. The specific function of the control module 320 is described in detail below.
[0040] For example, the thickness measuring instrument 310 can be an ellipsometer, an X-ray reflectometer, or other devices that can non-destructively measure thickness. The control module 320 can be an electronic device such as a computer or server, or a central processing unit (CPU) or microcontroller unit (MCU).
[0041] The ion implantation method for silicon on insulators provided in this application will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0042] This embodiment provides an ion implantation method for silicon on insulators, which can be used in the control module 320 described above. Figure 4 This is a schematic flowchart of an ion implantation method for silicon on an insulator according to an embodiment of the present invention, as shown below. Figure 4 As shown, the method includes the following steps:
[0043] Step S401: Obtain the thickness of the top silicon layer.
[0044] Specifically, after obtaining SOI, the thickness of the top silicon layer can be measured using the thickness measuring instrument 310 described above. The thickness of the top silicon layer 130 detected by the thickness measuring instrument 310 is the detected thickness, and the control module 320 can obtain the detected thickness of the top silicon layer from the thickness measuring instrument 310.
[0045] Step S402: Obtain the target threshold voltage required for the target semiconductor device.
[0046] Specifically, there are various types of semiconductor devices. For example, a semiconductor device can be an N-type SW transistor, an N-type IO transistor, or a P-type IO transistor, and each type of semiconductor device corresponds to a specific threshold voltage.
[0047] For example, the threshold voltage for an N-type SW transistor can be 0.57, and the threshold voltage for an N-type IO transistor can be 0.44. The specific threshold voltage for a semiconductor device can be determined by the designer based on requirements.
[0048] The target semiconductor device can be one of the various semiconductor devices selected by the operator to be processed from the SOI. The target threshold voltage is the specific threshold voltage corresponding to the target semiconductor device. For example, if the operator chooses to process the SOI into an N-type SW transistor, then the target semiconductor device is an N-type SW transistor, and the target threshold voltage can be 0.57.
[0049] For example, the target threshold voltage can be input by the operator through a human-machine interface device (such as a mouse, keyboard, or touch screen) to the control module, so that the control module can obtain the target threshold voltage; the control module can also obtain the target threshold voltage from the process control system.
[0050] Step S403: Determine the target ion implantation parameters based on the detected thickness, target threshold voltage, and mapping model.
[0051] The mapping model characterizes the relationship between the thickness of the top silicon layer, the threshold voltage, and the ion implantation parameters. This model can be determined experimentally and pre-configured in the control module. The target ion implantation parameters are those required for the target semiconductor device to reach the target threshold voltage. These parameters include the ion implantation dose and the ion implantation energy.
[0052] Specifically, after determining the detection thickness and the target threshold voltage, the thickness of the top silicon corresponding to the detection thickness and the threshold voltage corresponding to the target threshold voltage can be found from the mapping model, and the ion implantation parameters that both correspond to are determined as the target ion implantation parameters.
[0053] In some implementations, the mapping model can be a data table characterizing the correspondence between multiple top silicon thicknesses, multiple device types, multiple threshold voltages, and multiple ion implantation parameters.
[0054] For example, a data table could be as shown in Table 1. The thickness range of the top silicon layer in Table 1 is merely an example and is not limited to this. For instance, after determining the maximum and minimum thickness of the top silicon layer, the data could be... As a level, the thickness of multiple top-layer silicon layers, discrete from the minimum and maximum values, is used as the thickness of multiple top-layer silicon layers in the data table.
[0055] For example, if the minimum thickness of the top silicon layer is... The maximum thickness of the top silicon layer is by If it is a single grade, then the thickness of multiple top-layer silicon layers in the data table includes and
[0056] Table 1 Data Table
[0057]
[0058] Specifically, if the operator determines that the semiconductor device is an N-type SW transistor, then the target threshold voltage can be determined to be 0.57V. At this point, the measured thickness is... At this time, the ion implantation dose can be 155 ions / cm. 2 The ion implantation energy A1 was determined as the target ion implantation parameter.
[0059] In other implementations, the mapping model can be a fitted curve characterizing the relationship between the ion implantation dose parameter and the threshold voltage at different top silicon thicknesses.
[0060] The number of fitted curves is consistent with the number of thicknesses of the top silicon layer. For example, if the thicknesses of multiple top silicon layers include... and The number of fitted curves is 7, and the thickness of each of the 7 fitted curves corresponds one-to-one with the thickness of the 7 top silicon layers.
[0061] Specifically, if the determined detection thickness is If the target threshold voltage is 0.57V, then look up the mapping model. The corresponding fitting curve is obtained, and then the ion implantation parameter corresponding to 0.57V in the fitting curve is determined as the target ion implantation parameter.
[0062] Step S404: Based on the target ion implantation parameters, control the ion implanter to perform ion implantation on the well region of the top silicon layer.
[0063] The well region of the top silicon layer is a region with a specific doping type and concentration formed by processes such as ion implantation or diffusion. The well region can be used to build different types of semiconductor devices, and the location of the well region can be set by the designer based on the semiconductor device processing requirements.
[0064] Specifically, after determining the target ion implantation parameters, the ion implanter can be controlled to perform ion implantation on the well region of the top silicon layer using the target ion implantation parameters.
[0065] For example, such as Figure 5 and Figure 6As shown, a top silicon layer may include multiple well regions 131. The control module can determine the target threshold voltage of each well region based on the semiconductor device to be formed in each well region, and then determine the target ion implantation parameters of each well region through the above step S403, and control the ion implanter to perform ion implantation processing on each well region in sequence.
[0066] The ion implantation method for silicon-on-insulator (SiI) provided in this embodiment first obtains the detection thickness and target threshold voltage of the top silicon layer. Then, based on the established mapping module, detection thickness, and target threshold voltage, target ion implantation parameters are determined, and ion implantation is performed on the well region of the top silicon layer based on these parameters. The parameters used in this embodiment for ion implantation consider the influence of the top silicon thickness on the threshold voltage and are adaptively adjusted, enabling precise control of the threshold voltage of the semiconductor device. This results in a more consistent and controllable threshold voltage for the final semiconductor device. Furthermore, the control module achieves precise matching of ion doping dosage by dynamically adjusting the ion implantation parameters, reducing subsequent parameter adjustment processes and testing costs. Simultaneously, this improves the yield and performance consistency of the semiconductor device, meeting the threshold voltage control requirements of advanced process nodes.
[0067] This embodiment also provides another ion implantation method for silicon on insulators, which can be used in the control module described above, such as... Figure 7 As shown, the method includes the following steps:
[0068] Step S701: Obtain the thickness of the top silicon layer.
[0069] Please see details Figure 4 Step S401 of the illustrated embodiment will not be described again here.
[0070] Step S702: Obtain the target threshold voltage required for the target semiconductor device.
[0071] Please see details Figure 4 Step S402 of the illustrated embodiment will not be described again here.
[0072] Step S703: Establish a mapping model based on the target ion implantation parameters corresponding to the multiple top silicon thicknesses determined by detection.
[0073] For example, the mapping model can be a data table or a fitted curve.
[0074] Specifically, step S703 may include steps a1 to a6:
[0075] Step a1: Obtain various semiconductor devices and the corresponding threshold voltage for each semiconductor device.
[0076] For example, various semiconductor devices include N-type SW transistors, N-type I / O transistors, and P-type I / O transistors. The threshold voltage of an N-type SW transistor is 0.57V, the threshold voltage of an N-type I / O transistor is 0.44V, and the threshold voltage of a P-type I / O transistor is -0.422V.
[0077] Step a2: Obtain the thickness of the top silicon layer in multiple different SOIs.
[0078] For example, the thickness of the top silicon layer can include and
[0079] Step a3: Determine the initial ion implantation parameters, and control the ion implanter to perform ion implantation on the top silicon of various thicknesses based on the initial ion implantation parameters to create the well region of the target semiconductor device.
[0080] The initial ion implantation parameters can be empirical values set by the staff.
[0081] Step a4: After ion implantation, monitor the actual threshold voltage of the final target semiconductor device.
[0082] Specifically, after the target semiconductor device is formed, the electrical performance of each target semiconductor device is tested to detect and determine the threshold voltage (i.e., the actual threshold voltage) of the target semiconductor device.
[0083] Step a5: Adjust the initial ion implantation parameters according to the difference between the actual threshold voltage of the target semiconductor device and the target threshold voltage to obtain the target ion implantation parameters.
[0084] The target ion implantation parameters are the initial ion implantation parameters when the actual threshold voltage matches the target threshold voltage.
[0085] For example, the initial ion implantation parameters can be adjusted according to the difference between the actual threshold voltage and the target threshold voltage of the target semiconductor device. For instance, if the actual threshold voltage is less than the target threshold voltage, the initial ion implantation parameters are updated to the sum of the initial ion implantation parameters and the gradient; if the actual threshold voltage is greater than the target threshold voltage, the initial ion implantation parameters are updated to the difference between the initial ion implantation parameters and the gradient; if the actual threshold voltage is equal to the target threshold voltage, the initial ion implantation parameters are determined as the target ion implantation parameters.
[0086] For example, taking an N-type silicon-controlled semiconductor device as an example, the thickness of the top silicon layer is... The target ion implantation parameters include an ion implantation dose of 155 ions / cm². 2 The thickness of the top silicon layer is The target ion implantation parameters at that time included an ion implantation dose of 140 ions / cm².2 Top silicon thickness The target ion implantation parameters include an ion implantation dose of 125 ions / cm². 2 .
[0087] Step a6: Based on the target ion implantation parameters corresponding to the target threshold voltage at the thickness of each top silicon layer, establish a mapping model.
[0088] For example, the mapping model can be shown in Table 1.
[0089] Step S704: Determine the target ion implantation parameters based on the detected thickness, target threshold voltage, and mapping model.
[0090] Specifically, step S704 includes steps S7041 and S7042:
[0091] Step S7041: Determine the ion implantation dose and ion implantation energy based on the detected thickness, target threshold voltage, and mapping model.
[0092] Step S7042: Determine the ion implantation element based on the type of the target semiconductor device.
[0093] For example, the ion implantation elements include boron (B), arsenic (As), and phosphorus (P).
[0094] Specifically, when the target semiconductor device is an N-type IO tube, LNA, or N-type SW tube, the ion implantation element can be As or P; when the target semiconductor device is a P-type IO tube, the ion implantation element can be B.
[0095] Step S705: Based on the target ion implantation parameters, control the ion implanter to perform ion implantation on the well region of the top silicon layer.
[0096] Please see details Figure 4 Step S404 of the illustrated embodiment will not be described again here.
[0097] Step S706: Obtain the detection threshold voltage.
[0098] The detection threshold voltage is the threshold voltage obtained after testing the target semiconductor device, which refers to the semiconductor device fabricated from the top silicon layer after processing in step S705.
[0099] Specifically, after the target semiconductor device is finally formed, electrical performance tests (such as threshold voltage measurement) are performed on the target semiconductor device to detect and determine the threshold voltage of the target semiconductor device (i.e., detect the threshold voltage).
[0100] Step S707: Based on the detection threshold voltage, iteratively optimize the mapping model.
[0101] For example, after determining the detection threshold voltage, if the difference between the detection threshold voltage and the target threshold voltage is less than or equal to a preset threshold voltage (e.g., 0.05V), the mapping model remains unchanged; if the difference between the detection threshold voltage and the target threshold voltage is greater than the preset threshold voltage, the mapping model is iteratively optimized. The preset threshold voltage can be set by the designer according to requirements.
[0102] Specifically, when the difference between the detection threshold voltage and the target threshold voltage is greater than the preset threshold voltage, if the detection threshold voltage is less than the target threshold voltage, the target ion implantation parameters are iteratively optimized to the sum of the target ion implantation parameters and the gradient; if the detection threshold voltage is greater than the target threshold voltage, the target ion implantation parameters are iteratively optimized to the difference between the target ion implantation parameters and the gradient.
[0103] It should be understood that in this embodiment, the target ion implantation parameters are determined by an iteratively optimized mapping model when the top silicon is ion implanted for the next time.
[0104] Optionally, the iterative optimization process does not have to continue indefinitely. For example, when the number of iterations reaches a preset number (which can be determined by the designer based on the processing requirements), the mapping model of that iteration can be used as the final mapping model. After that, the control module can continuously determine the target ion implantation parameters based on the final mapping model.
[0105] In this embodiment, a mapping model is established based on the target ion implantation parameters corresponding to different top silicon thicknesses determined by detection. This improves the accuracy of the mapping model, thereby enhancing the control precision of the threshold voltage (VTL) of the semiconductor device. Furthermore, after each processing step, the mapping model is iteratively optimized based on the detected threshold voltage. This allows for real-time optimization of the mapping model using continuously increasing data, further improving its accuracy, precisely controlling the device's threshold voltage (VTL), and enhancing performance consistency.
[0106] This embodiment also provides another method for ion implantation of silicon on insulators, which can be used in the aforementioned control module, such as... Figure 8 As shown, the method includes the following steps:
[0107] Step S801: Obtain the detection thickness of the top silicon layer from an ellipsometry or X-ray reflectometer.
[0108] Specifically, an ellipsometer is an optical measuring instrument used to detect the thickness of thin films, optical constants, and microstructure of materials, while an X-ray reflectometer uses the property of X-rays reflecting off the sample surface to perform measurements.
[0109] Ellipsometry offers higher accuracy for measuring film thickness at the nanometer or even sub-nanometer level. Moreover, by measuring changes in polarized light, ellipsometers obtain film thickness information without the need for calibration using standard samples of known thickness. The measurement results are unaffected by factors such as sample surface roughness, and changes in thickness can be monitored in real time.
[0110] X-ray reflectometers can accurately measure the thickness of each layer of a film by analyzing the reflection and interference of X-rays in multilayer films, and can clearly distinguish the interfaces between layers. X-ray reflectometers also have strong penetrating power, enabling non-contact measurement of large-sized samples without the need for special sample treatment.
[0111] Step S802: Obtain the target threshold voltage required for the target semiconductor device.
[0112] Please see details Figure 4 Step S402 of the illustrated embodiment will not be described again here.
[0113] Step S803: Determine whether the detected thickness is the expected thickness.
[0114] The desired thickness refers to the ideal thickness of the top silicon layer, which can be pre-configured by the designer in the control module. For example, the desired thickness can be...
[0115] Step S804: When the detected thickness is the desired thickness, control the ion implanter to perform ion implantation on the well region of the top silicon according to the preset ion implantation parameters.
[0116] The preset ion implantation parameters are the ion implantation parameters required for the top silicon layer to form the target semiconductor device at the desired thickness.
[0117] Step S805: When the detected thickness is not the desired thickness, determine the target ion implantation parameters based on the detected thickness, the target threshold voltage, and the mapping model.
[0118] Specifically, the process of determining target ion implantation parameters based on detection thickness, target threshold voltage, and mapping model and Figure 4 Step S403 in the illustrated embodiment is the same and will not be described again here.
[0119] Step S806: Based on the target ion implantation parameters, control the ion implanter to perform ion implantation on the well region of the top silicon layer.
[0120] Please see details Figure 4 Step S404 of the illustrated embodiment will not be described again here.
[0121] In this embodiment, after determining the detection thickness, the detection thickness and the expected thickness are compared. When the detection thickness is the expected thickness, ion implantation can be performed directly according to the configured default value (preset ion implantation parameters), which omits the process of determining the target ion implantation parameters, thereby improving the efficiency of ion implantation and reducing costs.
[0122] This embodiment also provides a method for fabricating a semiconductor device, the method comprising steps b1 to b3:
[0123] Step b1, provide silicon on insulator.
[0124] Silicon-on-insulator (SiInsulator) includes a top layer of silicon used to form the target semiconductor device. The structure of SiInsulator can be as follows: Figure 1 or Figure 2 As shown.
[0125] Step b2: Based on the target ion implantation parameters provided by the ion implantation method for silicon-on-insulator in any of the above embodiments, ion implantation is performed on the well region of the top silicon layer.
[0126] Step b3 involves annealing and film deposition processes on the top silicon layer after ion implantation to form the target semiconductor device.
[0127] Specifically, the annealing process activates the implanted impurity ions, allowing them to better integrate into the silicon lattice, while also repairing damage to the silicon lattice caused during ion implantation. The film deposition process is used to form other structures of the semiconductor device, such as the gate oxide layer and metal interconnect layers, ultimately manufacturing the target semiconductor device with the target threshold voltage.
[0128] For example, the annealing process and the film formation process can be the annealing process and film formation process commonly used in the preparation of semiconductor devices in this field, and will not be specifically described here.
[0129] This embodiment also provides a semiconductor device, which can be prepared by the semiconductor device preparation method provided in any of the above embodiments.
[0130] This embodiment also provides an ion implantation device for silicon on insulators, such as... Figure 3 As shown, the ion implantation equipment for silicon on insulators includes a thickness measuring instrument 310, a control module 320, and an ion implanter 330.
[0131] The thickness measuring instrument 310 and the control module 320 are connected in communication, and the ion implanter 330 and the control module 320 are also connected in communication.
[0132] Thickness measuring instrument 310 is used to detect the thickness of the top silicon layer to obtain the detected thickness. Control module 320 is used to acquire the detected thickness of the top silicon layer from the thickness measuring instrument; control module 320 is also used to acquire the target threshold voltage required for the target semiconductor device; control module 320 is also used to determine the target ion implantation parameters based on the detected thickness, the target threshold voltage, and the mapping model, wherein the mapping model is used to characterize the correspondence between the thickness of the top silicon layer, the threshold voltage, and the ion implantation parameters, and the target ion implantation parameters are the ion implantation parameters required for the target semiconductor device to reach the target threshold voltage, including ion implantation dose and ion implantation energy; control module 320 is also used to control the ion implanter to perform ion implantation treatment on the well region of the top silicon layer according to the target ion implantation parameters.
[0133] This embodiment also provides a semiconductor device fabrication system, including: an ion implantation device for silicon-on-insulator provided in any of the above embodiments.
[0134] For example, the semiconductor device fabrication system further includes a moving device, an annealing device, and a film deposition device. The annealing device is used to anneal the top silicon layer after ion implantation, the film deposition device is used to deposit a film on the annealed top silicon layer to form a semiconductor device, the moving device is used to move the silicon on insulator to the ion implantation device, the moving device is also used to move the ion-implanted silicon on insulator to the annealing device, and the moving device is also used to move the annealed silicon on insulator to the film deposition device.
[0135] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship as shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0136] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0137] In the description of this specification, the references to terms such as "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0138] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0139] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the present invention.
Claims
1. A method for ion implantation of silicon on an insulator, characterized in that, Silicon-on-insulator includes a top silicon layer for forming a target semiconductor device, and the ion implantation method for the silicon-on-insulator includes: Obtain the thickness of the top silicon layer; To obtain the target threshold voltage required for the target semiconductor device; Based on the detected thickness, the target threshold voltage, and the mapping model, the target ion implantation parameters are determined. The mapping model is used to characterize the correspondence between the thickness of the top silicon layer, the threshold voltage, and the ion implantation parameters. The target ion implantation parameters are the ion implantation parameters required for the target semiconductor device to reach the target threshold voltage. The ion implantation parameters include ion implantation dose and ion implantation energy. Based on the target ion implantation parameters, the ion implanter is controlled to perform ion implantation on the well region of the top silicon layer.
2. The ion implantation method for silicon on an insulator according to claim 1, characterized in that, The mapping model is a data table characterizing the correspondence between multiple top silicon thicknesses, multiple device types, multiple threshold voltages, and multiple ion implantation parameters; or the mapping model is a fitted curve characterizing the variation relationship between ion implantation dose parameters and threshold voltages under different top silicon thicknesses.
3. The ion implantation method for silicon on an insulator according to claim 1, characterized in that, Before determining the target ion implantation parameters based on the detected thickness, the target threshold voltage, and the mapping model, the ion implantation method for silicon on insulator further includes: The mapping model is established based on the target ion implantation parameters corresponding to the multiple top silicon thicknesses determined by detection.
4. The ion implantation method for silicon on an insulator according to claim 1, characterized in that, Before determining the target ion implantation parameters based on the detected thickness, the target threshold voltage, and the mapping model, the ion implantation method for silicon on insulator further includes: Determine whether the detected thickness is the desired thickness, wherein the desired thickness is the thickness that the top silicon layer is ideally expected to achieve; When the detected thickness is the desired thickness, the ion implanter is controlled to perform ion implantation on the well region of the top silicon according to the preset ion implantation parameters, wherein the preset ion implantation parameters are the ion implantation parameters required for the top silicon to form a target semiconductor device at the desired thickness.
5. The ion implantation method for silicon on an insulator according to claim 4, characterized in that, The step of determining the target ion implantation parameters based on the detected thickness, the target threshold voltage, and the mapping model includes: When the detected thickness is not the desired thickness, the target ion implantation parameters are determined based on the detected thickness, the target threshold voltage, and the mapping model.
6. The ion implantation method for silicon on an insulator according to any one of claims 1 to 5, characterized in that, After controlling the ion implanter to perform ion implantation on the well region of the top silicon according to the target ion implantation parameters, the ion implantation method for silicon on insulator further includes: A detection threshold voltage is obtained, wherein the detection threshold voltage is a threshold voltage obtained after testing the target semiconductor device; Based on the detection threshold voltage, the mapping model is iteratively optimized.
7. The ion implantation method for silicon on an insulator according to any one of claims 1 to 5, characterized in that, The ion implantation parameters further include ion implantation elements. Determining the target ion implantation parameters based on the detected thickness, the target threshold voltage, and the mapping model includes: The ion implantation dose and ion implantation energy are determined based on the detected thickness, the target threshold voltage, and the mapping model. The ion implantation element is determined based on the type of the target semiconductor device.
8. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes: Silicon-on-insulator is provided, wherein the silicon-on-insulator includes a top silicon layer for forming a target semiconductor device; Based on the target ion implantation parameters provided by the ion implantation method for silicon-on-insulator according to any one of claims 1 to 7, the well region of the top silicon is subjected to ion implantation. The top silicon layer after ion implantation is subjected to annealing and film deposition processes to form the target semiconductor device.
9. A semiconductor device, characterized in that, The semiconductor device is prepared by the semiconductor device preparation method according to claim 8.
10. An ion implantation apparatus for silicon on an insulator, characterized in that, The ion implantation equipment for silicon on insulators includes a thickness measuring instrument, a control module, and an ion implanter. The thickness measuring instrument is communicatively connected to the control module, and the ion implanter is communicatively connected to the control module. The thickness measuring instrument is used to detect the thickness of the top silicon layer to obtain the detected thickness. The control module is used to obtain the detected thickness of the top silicon layer from the thickness measuring instrument; The control module is also used to obtain the target threshold voltage required by the target semiconductor device; The control module is further configured to determine target ion implantation parameters based on the detected thickness, the target threshold voltage, and the mapping model. The mapping model is used to characterize the correspondence between the thickness of the top silicon layer, the threshold voltage, and the ion implantation parameters. The target ion implantation parameters are the ion implantation parameters required for the target semiconductor device to reach the target threshold voltage. The ion implantation parameters include ion implantation dose and ion implantation energy. The control module is also used to control the ion implanter to perform ion implantation on the well region of the top silicon according to the target ion implantation parameters.