Array substrate, preparation method thereof and display panel

Abstract

Array substrate, preparation method thereof and display panel, solve the problem of low yield of display panel in the prior art. The array substrate comprises: a substrate; a first conductive layer located on one side of the substrate; a first inorganic insulating layer located on the side of the first conductive layer away from the substrate and in contact with the first conductive layer, the first inorganic insulating layer comprising at least one conductive via, the overall projection of the first inorganic insulating layer on the substrate and the overall projection of the conductive via on the substrate being a solid pattern, the solid pattern covering the projection of the first conductive layer on the substrate; the surface of the first inorganic insulating layer close to the first conductive layer being a concave-convex surface, the surface of the first inorganic insulating layer away from the substrate being a plane; and a second conductive layer located on the side of the first inorganic insulating layer away from the substrate and in contact with the first inorganic insulating layer, the projection of the second conductive layer on the substrate being located within the solid pattern, the projection of the second conductive layer on the substrate and the projection of the first conductive layer on the substrate partially overlapping.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and its fabrication method, and a display panel. Background Technology

[0002] In recent years, flexible organic light-emitting diode (AMOLED) technology has become a rising star in the display field due to its numerous advantages. However, the yield rate of AMOLED products still needs to be improved. Summary of the Invention

[0003] In view of this, the present application provides an array substrate and its preparation method, as well as a display panel, which solves the problem of low yield of display panels in the prior art.

[0004] A first aspect of this application provides an array substrate, comprising: a substrate; a patterned first conductive layer located on one side of the substrate; a first inorganic insulating layer located on the side of the first conductive layer away from the substrate and in contact with the first conductive layer, the first inorganic insulating layer including at least one conductive via, the orthographic projection of the first inorganic insulating layer on the substrate and the orthographic projection of the conductive via on the substrate being a solid pattern, the solid pattern covering the orthographic projection of the first conductive layer on the substrate; the surface of the first inorganic insulating layer near the first conductive layer being an uneven surface, the surface of the first inorganic insulating layer away from the substrate being a plane; and a patterned second conductive layer located on the side of the first inorganic insulating layer away from the substrate and in contact with the first inorganic insulating layer, the orthographic projection of the second conductive layer on the substrate being located within the solid pattern, the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the first conductive layer on the substrate partially overlapping.

[0005] In conjunction with the first aspect, in some possible implementations, the array substrate further includes a second inorganic insulating layer and a patterned third conductive layer, wherein the second inorganic insulating layer is located between the second conductive layer and the third conductive layer, the surface of the second inorganic insulating layer in contact with the second conductive layer is an uneven surface, and the surface of the second inorganic insulating layer in contact with the third conductive layer is a plane.

[0006] In conjunction with the first aspect, in some possible implementations, the first conductive layer includes a first gate signal line; the third conductive layer includes a first constant voltage signal line, the orthographic projection of the first constant voltage signal line on the substrate and the orthographic projection of the first gate signal line on the substrate overlap; the first constant voltage signal line includes a first overlapping portion located at the overlapping point, and a first portion and a second portion located on both sides of the first overlapping portion, the first portion contacting the first overlapping portion, and the second portion contacting the first overlapping portion; the linewidth of the first overlapping portion, the linewidth of the first portion and the linewidth of the second portion are equal; preferably, the first gate signal line includes a second overlapping portion located at the overlapping point, and a third portion and a fourth portion located on both sides of the second overlapping portion, the third portion contacting the second overlapping portion, and the fourth portion contacting the second overlapping portion; the linewidth of the second overlapping portion, the linewidth of the third portion and the linewidth of the fourth portion are equal; preferably, the first gate signal line includes at least one of a scan signal line and a light emission control signal line; preferably, the first constant voltage signal line includes at least one of an initialization signal line and a power supply voltage signal line.

[0007] In conjunction with the first aspect, in some possible implementations, the array substrate includes a first pixel circuit region and a second pixel circuit region disposed adjacent to each other; the third conductive layer includes a second constant voltage signal line and a third constant voltage signal line, the second constant voltage signal line being located in the first pixel circuit region and the third constant voltage signal line being located in the second pixel circuit region; at least a portion of the second constant voltage signal line and at least a portion of the third constant voltage signal line are parallel.

[0008] In conjunction with the first aspect, in some possible implementations, the third conductive layer further includes a fourth constant voltage signal line, the central axis of which is located on the boundary line between the first pixel circuit area and the second pixel circuit area; the second constant voltage signal line and the third constant voltage signal line are axially symmetrical about the fourth constant voltage signal line.

[0009] In conjunction with the first aspect, in some possible implementations, the first conductive layer further includes a second gate signal line, and the orthogonal projections of the second constant voltage signal line, the third constant voltage signal line and the fourth constant voltage signal line on the substrate overlap with the orthogonal projection of the second gate signal line on the substrate.

[0010] In conjunction with the first aspect, in some possible implementations, the maximum thickness of the first inorganic insulating layer is greater than or equal to 0.5 micrometers and less than or equal to 0.7 micrometers.

[0011] In conjunction with the first aspect, in some possible implementations, the array substrate further includes a planarization layer located on the side of the second conductive layer away from the substrate, the maximum thickness of the planarization layer being greater than or equal to 1.1 micrometers and less than or equal to 1.7 micrometers.

[0012] A second aspect of this application provides a method for fabricating an array substrate, comprising: fabricating a patterned first conductive layer on a substrate; fabricating a first insulating material layer on the side of the first conductive layer away from the substrate, wherein the surface of the first insulating material layer away from the substrate is planar; thinning the first insulating material layer to obtain a first inorganic insulating layer; and fabricating a patterned second conductive layer on the side of the first inorganic insulating layer away from the substrate.

[0013] A third aspect of this application provides a display panel, including the array substrate provided in any of the above embodiments, or the array substrate obtained according to the preparation method provided in the above embodiments.

[0014] According to the array substrate and its preparation method and display panel provided in the embodiments of this application, the surface of the first inorganic insulating layer away from the first conductive layer is a plane, that is, the surface of the first inorganic insulating layer away from the first conductive layer is not affected by the patterning of the first conductive layer, so that the second conductive layer is no longer affected by the patterning of the first conductive layer, thereby avoiding the risk of short circuit and open circuit in the second conductive layer and improving the yield of the display product. Attached Figure Description

[0015] Figure 1a This is a circuit diagram of a pixel circuit in a related technology.

[0016] Figure 1b This is a partial layout of a display panel in related technologies.

[0017] Figure 1c for Figure 1b The diagram shows a cross-sectional view of the display panel along line A1A2.

[0018] Figure 1d for Figure 1b The diagram shows a cross-sectional view of the display panel along line B1B2.

[0019] Figure 2 This is a schematic cross-sectional view of the array substrate provided in the first embodiment of this application.

[0020] Figure 3 This is a schematic cross-sectional view of the array substrate provided in the second embodiment of this application.

[0021] Figure 4 This is a partial layout of the array substrate provided in the third embodiment of this application.

[0022] Figure 5a This is a partial layout of the array substrate provided in the fourth embodiment of this application.

[0023] Figure 5b Another partial layout of the array substrate provided in the fourth embodiment of this application.

[0024] Figure 6 This is a schematic cross-sectional view of the array substrate provided in the fifth embodiment of this application.

[0025] Figure 7 This is a schematic flowchart illustrating a method for fabricating an array substrate according to an embodiment of this application.

[0026] Figures 8a-8e To execute Figure 7 A schematic diagram of the structure of the intermediate product obtained during the preparation method shown.

[0027] Figure 9 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application. Detailed Implementation

[0028] In related technologies, the array substrate is a multi-layer stacked structure. The stacked multi-layers constitute pixel circuits and various signal lines, which are used to drive light-emitting devices to emit light at a predetermined brightness in order to realize the display function.

[0029] Figure 1a This is a circuit diagram of a pixel circuit in a related technology. For example... Figure 1a As shown, the pixel circuit is an 8T1C pixel circuit, which specifically includes eight transistors and one capacitor Cst. The eight transistors are denoted as transistor Ti, and i is taken from 1 to 8 in sequence.

[0030] In this configuration, the control electrode of the first transistor T1 is connected to the first plate of capacitor Cst, the first electrode of the first transistor T1 is connected to the second electrode of the fifth transistor T5, and the second electrode of the first transistor T1 is connected to the first electrode of the sixth transistor T6. The first electrode of the second transistor T2 is connected to the data voltage signal line Data, the second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1, and the control electrode of the second transistor T2 is connected to the first scan signal line S1. The first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, the second electrode of the third transistor T3 is connected to the control electrode of the first transistor T1, and the control electrode of the third transistor T3 is connected to the second scan signal line S2. The first electrode of the fourth transistor T4 is connected to the first initialization signal line Vref1, the second electrode of the fourth transistor T4 is connected to the second electrode of the first transistor T1, and the control electrode of the fourth transistor T4 is connected to the third scan signal line S3. The control electrode of the fifth transistor T5 is connected to the light emission control signal line Em, the first electrode of the fifth transistor T5 is connected to the high-voltage power supply signal line Elvdd, and the second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1. The control electrode of the sixth transistor T6 is connected to the light-emitting control signal line Em. The first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1. The second electrode of the sixth transistor T6 is connected to the anode of the OLED. The control electrode of the seventh transistor T7 is connected to the fourth scan signal line S4. The first electrode of the seventh transistor T7 is connected to the second initialization signal line Vref2. The second electrode of the seventh transistor T7 is connected to the anode of the OLED. The control electrode of the eighth transistor T8 is connected to the fourth scan signal line S4. The first electrode of the eighth transistor T8 is connected to the third initialization signal line Vref3. The second electrode of the eighth transistor T8 is connected to the second electrode of the first transistor T1.

[0031] The high-voltage power signal line Elvdd is used to transmit the high-voltage power signal Vdd, and the low-voltage power signal line Elvss is used to transmit the low-voltage power signal Vss. The light-emitting control signal line Em is used to transmit the light-emitting control signal em. The data signal line Data is used to transmit the data signal Vdata. The first scan signal line S1 is used to transmit the first scan signal Scan1, the second scan signal line S2 is used to transmit the second scan signal Scan2, and the third scan signal line S3 is used to transmit the third scan signal Scan3. The first initialization signal line Vref1 is used to transmit the first initialization signal Vf1, the second initialization signal line Vref2 is used to transmit the second initialization signal Vf2, and the third initialization signal line Vref3 is used to transmit the third initialization signal Vf3.

[0032] Figure 1b This is a partial layout of a display panel in related technologies. Figure 1c for Figure 1b The diagram shows a cross-sectional view of the display panel along line A1A2. Figure 1d for Figure 1b The diagram shows a cross-sectional view of the display panel along line B1B2. Figure 1b As shown, an insulating layer 101 is disposed between adjacent metal layers in the display panel. Due to factors such as manufacturing process and film layer structure, a single film layer exhibits unevenness. In this case, combined with... Figure 1b and Figure 1c As shown, in the recesses of the lower metal layer 102, residual metal, such as residual metal Q, is easily left during the patterning of the upper metal layer 103, thus creating a risk of short circuits between adjacent metal lines in the upper metal layer 103. Combined with... Figure 1b and Figure 1d As shown, at the protrusion of the lower metal layer 102, the upper metal layer 103 is prone to breakage, such as crack L, which may cause the metal wires in the upper metal layer 103 to be open-circuited.

[0033] To avoid the aforementioned problems, related technologies employ methods such as increasing the line spacing of the upper metal layer 103 of the insulating layer in recessed areas and increasing the line width of the upper metal layer 103 of the insulating layer in raised areas. However, this method compresses the design space for other pixel traces, increasing the design difficulty and further affecting the design quality of the product.

[0034] In view of this, the present application provides an array substrate and its preparation method, as well as a display panel. By rationally designing the stacked structure in the array substrate, the flatness of the insulating layer is improved, and the influence of the unevenness of the lower metal layer on the linewidth and spacing of the upper metal layer is reduced. This allows the linewidth and spacing of the upper metal layer to be reduced while also improving the yield of the display product.

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a structure is referred to as being "on" or "below" another structure, the structure may be directly on or below the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. Structures referred to herein include any of the following: membrane, element, device, component, assembly.

[0037] When a structure is referred to as being “connected” to another structure, it can be directly connected to the other structure or indirectly connected to the other structure by means of one or more intermediate structures placed between them.

[0038] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0039] In this specification, the term "same-layer arrangement" refers to a structure formed by two (or more) structures through the same patterning process, and their materials may be the same or different.

[0040] Figure 2 This is a schematic cross-sectional view of the array substrate provided in the first embodiment of this application. Figure 2 As shown, the array substrate includes: a substrate 11, a patterned first conductive layer 12, a first inorganic insulating layer 13, and a patterned second conductive layer 14. The first conductive layer 12 is located on one side of the substrate 11. The first inorganic insulating layer 13 is located on the side of the first conductive layer 12 facing away from the substrate 11 and is in contact with the first conductive layer 12. The first inorganic insulating layer 13 includes at least one conductive via H. The orthographic projection of the first inorganic insulating layer 13 onto the substrate 11 and the orthographic projection of the conductive via H onto the substrate 11 are both solid patterns, covering the orthographic projection of the first conductive layer 12 onto the substrate 11. The surface of the first inorganic insulating layer 13 near the first conductive layer 12 is an uneven surface, while the surface of the first inorganic insulating layer 13 facing away from the substrate 11 is planar. The second conductive layer 14 is located on the side of the first inorganic insulating layer 13 away from the substrate 11 and is in contact with the first inorganic insulating layer 13. The orthographic projection of the second conductive layer 14 on the substrate 11 is located within the solid pattern, and the orthographic projection of the second conductive layer 14 on the substrate 11 and the orthographic projection of the first conductive layer 12 on the substrate 11 partially overlap.

[0041] The array substrate includes a substrate 11, and a semiconductor layer, multiple conductive layers, and multiple insulating layers stacked on one side of the substrate 11. An insulating layer is disposed between the semiconductor layer and the conductive layers, and an insulating layer is disposed between adjacent conductive layers. The semiconductor layer, conductive layers, and insulating layers constitute pixel circuits and various signal lines. The conductive layer can be a single metal film layer, for example, the material of the conductive layer is aluminum; the conductive layer can also be a composite film layer of multiple metal material layers stacked, for example, the conductive layer is a titanium / aluminum / titanium composite film layer. The insulating layer can be made of inorganic or organic materials.

[0042] A pixel circuit is used to connect to a light-emitting device to drive the device to emit light at a predetermined brightness, thereby achieving a display function. The pixel circuit includes multiple transistors and capacitors. The transistors may include a low-temperature polycrystalline silicon semiconductor layer or an oxide semiconductor layer. A transistor with a low-temperature polycrystalline silicon semiconductor layer can be called a low-temperature polycrystalline silicon semiconductor transistor, and a transistor with an oxide semiconductor layer can be called an oxide semiconductor transistor. For example, the pixel circuit may be an 8T1C pixel circuit.

[0043] In this embodiment, the insulating layer between the first conductive layer 12 and the second conductive layer 14 is a first inorganic insulating layer 13, meaning the insulating layer is made of an inorganic material. For example, the material of the first inorganic insulating layer 13 can be silicon nitride or silicon oxide. The materials of the first conductive layer 12 and the second conductive layer 14 are the same. For example, the material of the first conductive layer 12 can be copper, aluminum, or titanium.

[0044] Substrate 11 serves to provide support. In some embodiments, substrate 11 may be a glass-based substrate. In some embodiments, substrate 11 may include an organic resin material such as epoxy resin, triazine, silicone resin, or polyimide. In some embodiments, substrate 11 may include a ceramic material such as silicon nitride, aluminum nitride, or aluminum oxide, or may include a metal or metal compound.

[0045] In this embodiment, the array substrate includes a first conductive layer 12 and a second conductive layer 14, with a first inorganic insulating layer 13 disposed between the first conductive layer 12 and the second conductive layer 14. The first inorganic insulating layer 13 is in contact with the first conductive layer 12, and the first inorganic insulating layer 13 is also in contact with the second conductive layer 14. Typically, the inorganic insulating layer 13, for example, the first inorganic insulating layer 13, can be prepared using a chemical vapor deposition process. In this case, since the first conductive layer 12 has a patterned structure, the surface of the first inorganic insulating layer 13 in contact with the first conductive layer 12 will adapt to the patterned structure of the first conductive layer 12. At the same time, the surface of the first inorganic insulating layer 13 away from the first conductive layer 12 will also exhibit an uneven structure adapted to the patterned structure of the first conductive layer 12. In this situation, conductive material residue is easily generated at the corresponding position of the second conductive layer 14 in the recesses of the first conductive layer 12, thereby causing a short circuit between adjacent wires of the second conductive layer 14. At the protrusions of the first conductive layer 12, the corresponding positions of the second conductive layer 14 are prone to breakage, resulting in open circuits in the wires of the second conductive layer 14. However, according to the array substrate provided in this embodiment, the surface of the first inorganic insulating layer 13 facing away from the first conductive layer 12 is planar, that is, the surface of the first inorganic insulating layer 13 facing away from the first conductive layer 12 is not affected by the patterning of the first conductive layer 12. This makes the second conductive layer 14 no longer affected by the patterning of the first conductive layer 12, thereby avoiding the risk of short circuits and open circuits in the second conductive layer 14 and improving the yield of the display product.

[0046] In one embodiment, such as Figure 2 As shown, the maximum thickness D1 of the first inorganic insulating layer 13 is greater than or equal to 0.5 micrometers and less than or equal to 0.7 micrometers. For example, the thickness D of the first inorganic insulating layer 13 is 0.6 micrometers. In this case, the first inorganic insulating layer 13 can provide good insulation without being too thick, thus avoiding affecting the thinness of the display product.

[0047] In one embodiment, the array substrate may further include a light-shielding layer located between the substrate 11 and the first conductive layer 12. The light-shielding layer may be made of a metallic material.

[0048] In one embodiment, the array substrate may further include a buffer layer located between the light-shielding layer and the substrate 11 and the first conductive layer 12. The buffer layer may be made of silicon nitride or silicon oxide.

[0049] Figure 3 This is a schematic cross-sectional view of the array substrate provided in the second embodiment of this application. Figure 3 As shown, the array substrate and Figure 2The difference in the array substrate shown is that, in this embodiment, the array substrate further includes a second inorganic insulating layer 15 and a patterned third conductive layer 16. The second inorganic insulating layer 15 is located between the second conductive layer 14 and the third conductive layer 16, and is in contact with both the second conductive layer 14 and the third conductive layer 16. The surface of the second inorganic insulating layer 15 that contacts the second conductive layer 14 is an uneven surface, while the surface of the second inorganic insulating layer 15 that contacts the third conductive layer 16 is a planar surface.

[0050] For example, the third conductive layer 16 is a composite film layer with multiple layers stacked. For instance, the third conductive layer 16 is a composite film layer of titanium, aluminum, and titanium materials stacked together. The material of the second inorganic insulating layer 15 is silicon nitride or silicon oxide, etc.

[0051] According to the array substrate provided in this embodiment, by setting the surface of the second inorganic insulating layer 15 away from the second conductive layer 14 to be a plane, the risk of short circuit and open circuit of the third conductive layer 16 is avoided, and the yield of the display product is further improved.

[0052] In one embodiment, all inorganic insulating layers in the array substrate adopt the same structure as the first inorganic insulating layer 13 and the second inorganic insulating layer 15, that is, the surface of any inorganic insulating layer facing away from the substrate 11 is planar. This application embodiment does not limit the number of inorganic insulating layers in the array substrate, and can reasonably set them according to actual needs.

[0053] Figure 4 This is a partial layout of the array substrate provided in the third embodiment of this application. (In conjunction with...) Figure 3 and Figure 4 As shown, in this embodiment, the first conductive layer 12 includes a first gate signal line 121. The third conductive layer 16 includes a first constant voltage signal line 161, and the orthographic projection of the first constant voltage signal line 161 on the substrate 11 overlaps with the orthographic projection of the first gate signal line 121 on the substrate 11. The first constant voltage signal line 161 includes a first overlapping portion 61 located at the overlapping point, and a first portion 62 and a second portion 63 located on both sides of the first overlapping portion 61, respectively. The first portion 62 contacts the first overlapping portion 61, and the second portion 63 contacts the first overlapping portion 61. The linewidths of the first overlapping portion 61, the first portion 62, and the second portion 63 are equal.

[0054] In this embodiment, the first gate signal line 121 includes at least one of a scan signal line and a light emission control signal line. The first constant voltage signal line 161 includes at least one of an initialization signal line and a power supply voltage signal line. The scan signal line is, for example, a... Figure 1a Any one of the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3. The initialization signal line is, for example,... Figure 1aAt least one of the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3. The power supply voltage signal line is, for example,... Figure 1a The high-voltage power signal line Elvdd or the low-voltage power signal line Elvss.

[0055] Normally, due to the patterning effect of the first conductive layer 12 and the second conductive layer 14, to avoid the first constant voltage signal line 161 in the third conductive layer 16 from being open-circuited, the linewidth of the first constant voltage signal line 161 is usually increased at the overlapping position of the orthographic projection of the first constant voltage signal line 161 and the orthographic projection of the first gate signal line 121 to avoid the risk of line breakage. However, according to the array substrate provided in this embodiment, by setting the surface of the first inorganic insulating layer 13 facing away from the substrate 11 to be planar, and the surface of the second inorganic insulating layer 15 facing away from the substrate 11 to be planar, the influence of the patterning of the first conductive layer 12 and the second conductive layer 14 on the third conductive layer 16 is avoided. Furthermore, at the overlapping position of the first constant voltage signal line 161 and the first gate signal line 121, the linewidth of the first constant voltage signal line 161 is constant, that is, the linewidth of the first overlapping portion 61, the linewidth of the first portion 62, and the linewidth of the second portion 63 are equal, thereby saving wiring space and facilitating the realization of high-resolution products.

[0056] In this embodiment, the first gate signal line 121 includes a second overlapping portion 21 located at the intersection, and a third portion 22 and a fourth portion 23 located on both sides of the second overlapping portion 21, respectively. The third portion 22 contacts the second overlapping portion 21, and the fourth portion 23 contacts the second overlapping portion 21. The linewidths of the second overlapping portion 21, the third portion 22, and the fourth portion 23 are equal. That is, at the position where the orthographic projections of the first constant voltage signal line 161 and the first gate signal line 121 overlap, the linewidth of the first gate signal line 121 is constant, and no linewidth increase processing is performed, thereby saving wiring space and facilitating the realization of high-resolution products.

[0057] Figure 5a This is a partial layout of the array substrate provided in the fourth embodiment of this application. Figure 5b Another partial layout of the array substrate provided in the fourth embodiment of this application. Figure 5b exist Figure 5a Building upon this foundation, further details on more membrane structures were revealed. Combined with... Figure 3 , Figure 5a and Figure 5bAs shown, in this embodiment, the array substrate includes a first pixel circuit region Q1 and a second pixel circuit region Q2 disposed adjacently. The first pixel circuit region Q1 and the second pixel circuit region Q2 are each a region accommodating one pixel circuit; for example, the first pixel circuit region Q1 is provided with a first pixel circuit, and the second pixel circuit region Q2 is provided with a second pixel circuit. The third conductive layer 16 includes a second constant voltage signal line 162 and a third constant voltage signal line 163. The second constant voltage signal line 162 is located in the first pixel circuit region Q1, and the third constant voltage signal line 163 is located in the second pixel circuit region Q2. At least a portion of the second constant voltage signal line 162 and at least a portion of the third constant voltage signal line 163 are parallel.

[0058] For example, both the second constant voltage signal line 162 and the third constant voltage signal line 163 are first initialization signal lines. For instance, as... Figure 1a As shown, in the 8T1C pixel circuit, the second constant voltage signal line 162 and the third constant voltage signal line 163 are used to connect the eighth transistor T8 and the first transistor T1 to transmit the initialization signal to the source or drain of the first transistor T1.

[0059] Specifically, the second constant voltage signal line 162 includes a first sub-segment L1, which is connected to the first terminal of the eighth transistor T8 of the first pixel circuit through a first conductive via H1. The third constant voltage signal line 163 includes a second sub-segment L2, which is connected to the first terminal of the eighth transistor T8 of the second pixel circuit through a second conductive via H2. The first sub-segment L1 and the second sub-segment L2 are parallel.

[0060] The first sub-segment L1 and the second sub-segment L2 extend along a first direction x parallel to the substrate 11. The second constant voltage signal line 162 further includes a third sub-segment L3, which is connected to the first sub-segment L1. The third constant voltage signal line 163 further includes a fourth sub-segment L4, which is connected to the second sub-segment L2. The third sub-segment L3 and the fourth sub-segment L4 are collinear. For example, the third sub-segment L3 extends along a second direction y parallel to the substrate 11.

[0061] The second constant voltage signal line 162 further includes a fifth sub-segment L5, which is connected to the third sub-segment L3. The third constant voltage signal line 163 further includes a sixth sub-segment L6, which is connected to the fourth sub-segment L4. The first pixel circuit includes a first capacitor C1, and the second pixel circuit includes a second capacitor C2. The orthographic projection of the fifth sub-segment L5 on the substrate 11 overlaps with the orthographic projection of the first capacitor C1 on the substrate 11, and the orthographic projection of the sixth sub-segment L6 on the substrate 11 overlaps with the orthographic projection of the second capacitor C2 on the substrate 11.

[0062] The first pixel circuit further includes a first driving transistor T11, and the second pixel circuit further includes a second driving transistor T21. The second constant voltage signal line 162 further includes a seventh sub-segment L7, which is connected to the fifth sub-segment L5. The seventh sub-segment L7 is connected to the first terminal of the first driving transistor T11 through a third conductive via H3. The seventh sub-segment L7 is parallel to the third sub-segment L3. The third constant voltage signal line 163 further includes an eighth sub-segment L8, which is connected to the sixth sub-segment L6. The eighth sub-segment L8 is connected to the first terminal of the second driving transistor T21 through a fourth conductive via H4. The eighth sub-segment L8 is parallel to the fourth sub-segment L4.

[0063] Normally, due to the patterning effect of the first conductive layer 12 and the second conductive layer 14, the spacing between the second constant voltage signal lines 162 and 163 in the third conductive layer 16 is usually increased to avoid short circuits. For example, the wiring of the second constant voltage signal lines 162 and 163 is designed in a figure-eight pattern to avoid the risk of short circuits. However, according to the array substrate provided in this embodiment, by setting the surface of the first inorganic insulating layer 13 facing away from the substrate 11 to be planar, and the surface of the second inorganic insulating layer 15 facing away from the substrate 11 to be planar, the influence of the patterning of the first conductive layer 12 and the second conductive layer 14 on the third conductive layer 16 is avoided. Furthermore, at least a portion of the second constant voltage signal line 162 and at least a portion of the third constant voltage signal line 163 can be parallel without increasing the spacing, thereby saving wiring space and facilitating the realization of high-resolution products.

[0064] In one embodiment, combined Figure 5a and Figure 5b As shown, the third conductive layer also includes a fourth constant voltage signal line 164, the central axis of which is located on the boundary line between the first pixel circuit region Q1 and the second pixel circuit region Q2. The second constant voltage signal line 162 and the third constant voltage signal line 163 are axially symmetrical about the fourth constant voltage signal line 164. For example, the fourth constant voltage signal line 164 is... Figure 1a The first initialization signal line Vref1 in the process.

[0065] In one embodiment, combined Figure 5a and Figure 5bAs shown, the first conductive layer 12 further includes a second gate signal line 122. The orthographic projections of the second constant voltage signal line 162, the third constant voltage signal line 163, and the fourth constant voltage signal line 164 on the substrate 11 overlap with the orthographic projection of the second gate signal line 122 on the substrate 11. For example, the orthographic projection of the first sub-segment L1 of the second constant voltage signal line 162 on the substrate 11 overlaps with the orthographic projection of the second gate signal line 122 on the substrate 11, and the orthographic projection of the second sub-segment L2 of the third constant voltage signal line 163 on the substrate 11 overlaps with the orthographic projection of the second gate signal line 122 on the substrate 11. Exemplarily, the second gate signal line 122 is a light-emitting control signal line Em.

[0066] Figure 6 This is a schematic cross-sectional view of the array substrate provided in the fifth embodiment of this application. Figure 6 The array substrate shown differs from the array substrate provided in any of the above embodiments in that, in this embodiment, the array substrate further includes a planarization layer 17. The planarization layer 17 is located on the side of the second conductive layer 14 facing away from the substrate 11, and the maximum thickness D2 of the planarization layer 17 is greater than or equal to 1.1 micrometers and less than or equal to 1.7 micrometers. For example, the maximum thickness D2 of the planarization layer 17 is 1.5 micrometers, 1.4 micrometers, etc.

[0067] According to the array substrate provided in this embodiment, since the surface of the first inorganic insulating layer 13 facing away from the substrate 11 is flat, the flatness of the array substrate is improved. In other words, the flatness requirement of the array substrate for the planarization layer 17 is reduced. Therefore, the thickness of the planarization layer 17 can be reduced, which saves materials on the one hand and is conducive to the thinning of display products on the other hand.

[0068] In one embodiment, the array substrate includes a plurality of inorganic insulating layers, including a near-planar inorganic insulating layer closest to the planarization layer 17, the surface of which is planar away from the substrate 11. In this case, because the planarization layer 17 has good flatness, the maximum thickness D2 of the planarization layer 17 can be as small as possible, for example, the maximum thickness D2 of the planarization layer 17 is 1.1 micrometers or 1.2 micrometers.

[0069] For example, the array substrate provided in this embodiment is in Figure 3 Based on the array substrate shown, a third inorganic insulating layer 18 and a fourth conductive layer 19 are also included. The third inorganic insulating layer 18 is located between the third conductive layer 16 and the fourth conductive layer 19, and is in contact with both the third conductive layer 16 and the fourth conductive layer 19. The surface of the third inorganic insulating layer 18 that contacts the third conductive layer 16 is an uneven surface, while the surface of the third inorganic insulating layer 18 that contacts the fourth conductive layer 19 is a flat surface. A planarization layer 17 is located on the side of the fourth conductive layer 19 facing away from the substrate 11, and is in contact with the fourth conductive layer 19.

[0070] This application also provides a method for fabricating an array substrate. Figure 7 This is a schematic flowchart illustrating a method for fabricating an array substrate according to an embodiment of this application. Figures 8a-8e To execute Figure 7 A schematic diagram of the structure of the intermediate product obtained during the preparation method shown. Figure 7 As shown, the method 700 for fabricating the array substrate includes:

[0071] Step S710: A patterned first conductive layer is prepared on the substrate.

[0072] For example, see Figure 8a A first conductive material layer is fabricated on a substrate 11 using a physical vapor deposition process, such as sputtering or electroplating. Then, a photolithography process is used to pattern the first conductive material layer, resulting in a patterned first conductive layer 12. The photolithography process includes: first, spin-coating photoresist onto the first conductive material layer and then pre-baking to remove the solvent. Next, aligning a mask with a mask pattern with the first conductive layer 12, the mask is irradiated with ultraviolet light to transfer the mask pattern onto the photoresist. Then, developing the exposed or unexposed areas of the photoresist yields a patterned photoresist layer. For positive photoresist, the development process dissolves the unexposed areas; for negative photoresist, the development process dissolves the exposed areas. Then, a dry etching process is used to remove the first conductive material layer not protected by the photoresist layer. Finally, the patterned photoresist layer is removed.

[0073] For example, the material of the first conductive layer includes copper, aluminum, or titanium.

[0074] Step S720: A first insulating material layer is prepared on the side of the first conductive layer away from the substrate, and the surface of the first insulating material layer away from the substrate is planar.

[0075] See Figure 8b and Figure 8c The first insulating material layer 130 is prepared by chemical vapor deposition until the first insulating material layer 130 fills the depression of the first conductive layer 12, that is, the thickness of the first conductive layer 12 at the depression of the first conductive layer 12 is greater than or equal to the thickness of the first conductive layer 12.

[0076] Step S730: The first insulating material layer is thinned to obtain the first inorganic insulating layer.

[0077] See Figure 8d The first insulating material layer 130 is thinned using a dry etching process to obtain the first inorganic insulating layer 13. For example, the maximum thickness of the first inorganic insulating layer 13 is greater than or equal to 0.5 micrometers and less than or equal to 0.7 micrometers.

[0078] Step S740: A patterned second conductive layer is prepared on the side of the first inorganic insulating layer away from the substrate.

[0079] See Figure 8e The preparation process of the second conductive layer 14 can be the same as that of the first conductive layer 12. This will not be elaborated upon here.

[0080] This application also provides a display panel. Figure 9 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application. Figure 9 As shown, the display panel includes the array substrate 90 provided in any embodiment of this application, or the array substrate 90 prepared according to the preparation method of the array substrate provided in the embodiment of this application. Therefore, the display panel provided in this embodiment has beneficial effects corresponding to the beneficial effects of the array substrate. For example, the display panel has a high yield rate.

[0081] This application also provides a display device, which includes the display panel provided in this application embodiment. The display device is a product with image display function. For example, the display device can be used to display static images, such as pictures or photographs. The display device can also be used to display dynamic images, such as videos.

[0082] The display device can be a laptop, mobile phone, handheld or portable computer, camera, camcorder, in-vehicle smart central control screen, calculator, smartwatch, GPS navigator, electronic photo, electronic billboard or sign, projector, etc. In addition, the display device can also have functions such as taking photos, recording videos, fingerprint recognition, and facial recognition. Accordingly, the display device also includes at least one functional module for implementing the above functions, such as an under-display camera or an under-display fingerprint recognition sensor.

[0083] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0084] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. An array substrate, characterized in that, include: Substrate; A patterned first conductive layer, the first conductive layer being located on one side of the substrate; A first inorganic insulating layer is located on the side of the first conductive layer away from the substrate and is in contact with the first conductive layer. The first inorganic insulating layer includes at least one conductive via. The orthographic projection of the first inorganic insulating layer on the substrate and the orthographic projection of the conductive via on the substrate are a solid pattern, and the solid pattern covers the orthographic projection of the first conductive layer on the substrate. The surface of the first inorganic insulating layer near the first conductive layer is an uneven surface, and the surface of the first inorganic insulating layer away from the substrate is a plane; as well as A patterned second conductive layer is located on the side of the first inorganic insulating layer away from the substrate and is in contact with the first inorganic insulating layer. The orthographic projection of the second conductive layer on the substrate is located within the solid pattern, and the orthographic projections of the second conductive layer on the substrate and the first conductive layer on the substrate partially overlap.

2. The array substrate according to claim 1, characterized in that, It also includes a second inorganic insulating layer and a patterned third conductive layer. The second inorganic insulating layer is located between the second conductive layer and the third conductive layer. The surface of the second inorganic insulating layer that contacts the second conductive layer is an uneven surface, and the surface of the second inorganic insulating layer that contacts the third conductive layer is a plane.

3. The array substrate according to claim 2, characterized in that, The first conductive layer includes a first gate signal line; the third conductive layer includes a first constant voltage signal line, wherein the orthographic projection of the first constant voltage signal line on the substrate and the orthographic projection of the first gate signal line on the substrate overlap. The first constant voltage signal line includes a first overlapping portion located at the intersection, and a first portion and a second portion located on both sides of the first overlapping portion. The first portion contacts the first overlapping portion, and the second portion contacts the first overlapping portion. The line width of the first overlapping portion, the line width of the first portion, and the line width of the second portion are equal. Preferably, the first gate signal line includes a second overlapping portion located at the overlap, and a third portion and a fourth portion located on both sides of the second overlapping portion, wherein the third portion contacts the second overlapping portion, and the fourth portion contacts the second overlapping portion; the line width of the second overlapping portion, the line width of the third portion, and the line width of the fourth portion are equal. Preferably, the first gate signal line includes at least one of a scan signal line and a light emission control signal line; Preferably, the first constant voltage signal line includes at least one of an initialization signal line and a power supply voltage signal line.

4. The array substrate according to claim 2, characterized in that, The array substrate includes a first pixel circuit region and a second pixel circuit region arranged adjacent to each other; the third conductive layer includes a second constant voltage signal line and a third constant voltage signal line, wherein the second constant voltage signal line is located in the first pixel circuit region and the third constant voltage signal line is located in the second pixel circuit region; At least a portion of the second constant voltage signal line is parallel to at least a portion of the third constant voltage signal line.

5. The array substrate according to claim 4, characterized in that, The third conductive layer further includes a fourth constant voltage signal line, the central axis of which is located on the boundary line between the first pixel circuit area and the second pixel circuit area; the second constant voltage signal line and the third constant voltage signal line are axially symmetrical about the fourth constant voltage signal line.

6. The array substrate according to claim 5, characterized in that, The first conductive layer further includes a second gate signal line, and the orthogonal projections of the second constant voltage signal line, the third constant voltage signal line and the fourth constant voltage signal line on the substrate overlap with the orthogonal projection of the second gate signal line on the substrate.

7. The array substrate according to claim 1, characterized in that, The maximum thickness of the first inorganic insulating layer is greater than or equal to 0.5 micrometers and less than or equal to 0.7 micrometers.

8. The array substrate according to claim 1, characterized in that, It also includes a planarization layer located on the side of the second conductive layer away from the substrate, the planarization layer having a maximum thickness greater than or equal to 1.1 micrometers and less than or equal to 1.7 micrometers.

9. A method for fabricating an array substrate, characterized in that, include: A patterned first conductive layer is fabricated on a substrate; A first insulating material layer is prepared on the side of the first conductive layer away from the substrate, and the surface of the first insulating layer away from the substrate is planar; The first insulating material layer is thinned to obtain the first inorganic insulating layer; A patterned second conductive layer is prepared on the side of the first inorganic insulating layer away from the substrate.

10. A display panel, characterized in that, Includes the array substrate according to any one of claims 1-8, or the array substrate obtained by the preparation method according to claim 9.

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