Array substrate, preparation method thereof and display panel

Abstract

The application provides an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate, at least one first pixel circuit located on one side of the substrate, and the at least one first pixel circuit is located in a first pixel circuit area. The first pixel circuit comprises at least one transistor, and the at least one transistor comprises a first transistor. The first transistor comprises a first gate, a second gate, a first insulating layer and a first connecting structure. The first gate is located between the substrate and the second gate. The orthographic projection of the first gate on the substrate and the orthographic projection of the second gate on the substrate overlap. The first insulating layer is located between the first gate and the second gate, and the first insulating layer has a first via hole. The first connecting structure is located in the first via hole, and the first gate and the second gate are electrically connected through the first connecting structure. The first transistor of the first pixel circuit comprises two gates, and signal delay hardly occurs between the two gates.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to array substrates and their fabrication methods and display panels. Background Technology

[0002] In the field of display technology, especially in the development of Organic Light-Emitting Diode (OLED) display panels, the emergence of Low-Temperature Polycrystalline Oxide (LTPO) technology has made it possible to control the power consumption of display panels. LTPO technology can flexibly adjust the screen refresh rate in different scenarios, thereby reducing power consumption. This can save a significant amount of power when displaying static content, which helps extend battery life for mobile devices. However, due to limitations in related technologies, current display panels still cannot meet these requirements. Summary of the Invention

[0003] In view of this, embodiments of this application provide an array substrate, a method for fabricating the same, and a display panel.

[0004] The first aspect of this application provides an array substrate, including a first pixel circuit region, a second pixel circuit region and a hole region, wherein the first pixel circuit region is located between the second pixel circuit region and the hole region;

[0005] The array substrate includes:

[0006] Substrate;

[0007] At least one first pixel circuit is located on one side of a substrate, and the at least one first pixel circuit is located in a first pixel circuit region; the first pixel circuit includes at least one transistor, the at least one transistor includes a first transistor, the first transistor includes a first gate, a second gate, a first insulating layer and a first connection structure, the first gate is located between the substrate and the second gate, and the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the second gate on the substrate; the first insulating layer is located between the first gate and the second gate, and the first insulating layer has a first via; the first connection structure is located in the first via, and the first gate and the second gate are electrically connected through the first connection structure.

[0008] In one embodiment, the first via is located at the point where the orthogonal projections of the first gate and the second gate on the substrate overlap;

[0009] And / or, along a direction parallel to the plane of the substrate, the width of the first gate is greater than the width of the second gate;

[0010] And / or, the material of the first gate includes a metal, and the material of the second gate includes cesium tungsten oxide;

[0011] And / or, in the first direction, the width of the first via is less than or equal to 6 μm, in the second direction, the width of the first via is less than or equal to 6 μm, and the first direction intersects the second direction.

[0012] In one embodiment, at least one transistor further includes: a second transistor, the second transistor including a third gate, a fourth gate, a second insulating layer and a second connection structure, the third gate being located between a substrate and a fourth gate, and the orthographic projection of the third gate on the substrate overlapping the orthographic projection of the fourth gate on the substrate; the second insulating layer being located between the third gate and the fourth gate, and having a second via in the second insulating layer; the second connection structure being located in the second via, and the third gate and the fourth gate being electrically connected through the second connection structure;

[0013] And / or, in the same first pixel circuit, the first transistor corresponds to at least one first via, and the second transistor corresponds to at least one second via;

[0014] And / or, in the same first pixel circuit, the first via and the second via are multiplexed as the same via;

[0015] And / or, in multiple first pixel circuits, multiple first transistors correspond to the same first via, and multiple second transistors correspond to the same second via;

[0016] And / or, in multiple first pixel circuits, the first via and the second via are multiplexed into the same via, and multiple first transistors and multiple second transistors correspond to one via;

[0017] And / or, in the first direction, the width of the second via is less than or equal to 6 μm, in the second direction, the width of the second via is less than or equal to 6 μm, and the first direction intersects the second direction;

[0018] And / or, the first via is uniformly distributed in the first pixel circuit area;

[0019] And / or, the second vias are evenly distributed in the first pixel circuit area;

[0020] And / or, in the same first pixel circuit, the first via and the second via are multiplexed into the same via, and the distance from the via to the first transistor is the same as the distance from the via to the second transistor;

[0021] And / or, along a direction parallel to the plane of the substrate, the width of the third gate is greater than the width of the fourth gate;

[0022] And / or, the material of the third gate includes a metal, and the material of the fourth gate includes cesium tungsten oxide;

[0023] And / or, the second via is located at the point where the orthogonal projections of the third gate and the fourth gate on the substrate overlap;

[0024] And / or, the third gate is disposed in the same layer as the first gate;

[0025] And / or, the second gate and the fourth gate are disposed in the same layer;

[0026] And / or, the first insulating layer and the second insulating layer are disposed in the same layer.

[0027] In one embodiment, the array substrate further includes a conductive layer located on the side of the first pixel circuit away from the substrate. The conductive layer is electrically connected to the first gate and the second gate through a first via, and the conductive layer in the first via forms a first connection structure.

[0028] And / or, the first via penetrates the second gate;

[0029] And / or, the second gate extends into the first via and is electrically connected to the first gate, and the second gate located in the first via forms a first connection structure.

[0030] In one embodiment, it also includes:

[0031] At least one second pixel circuit is located on one side of the substrate and within the second pixel circuit region; the second pixel circuit includes at least one transistor, the at least one transistor including a third transistor, the third transistor including a fifth gate, a sixth gate, a third insulating layer and a third connection structure, the fifth gate being located between the substrate and the sixth gate, and the orthographic projection of the fifth gate on the substrate overlapping with the orthographic projection of the sixth gate on the substrate; the third insulating layer being located between the fifth gate and the sixth gate, and having a third via in the third insulating layer; the third connection structure being located in the third via, and the fifth gate and the sixth gate being electrically connected through the third connection structure;

[0032] And / or, in the second pixel circuit, at least one transistor further includes a fourth transistor, the fourth transistor including a seventh gate, an eighth gate, a fourth insulating layer and a fourth connection structure, the seventh gate being located between the substrate and the eighth gate, the orthogonal projection of the seventh gate on the substrate overlapping the orthogonal projection of the eighth gate on the substrate; the fourth insulating layer being located between the seventh gate and the eighth gate, the fourth insulating layer having a fourth via; the fourth connection structure being located in the fourth via, the seventh gate and the eighth gate being electrically connected through the fourth connection structure.

[0033] In one embodiment, in the same second pixel circuit, the third transistor corresponds to at least one third via, and the fourth transistor corresponds to at least one fourth via.

[0034] And / or, in the same second pixel circuit, the third via and the fourth via are multiplexed as the same via;

[0035] And / or, in multiple second pixel circuits, multiple third transistors correspond to the same third via, and multiple fourth transistors correspond to the same fourth via;

[0036] And / or, in multiple second pixel circuits, the third via and the fourth via are multiplexed as the same via, and multiple first transistors and multiple second transistors correspond to one via;

[0037] And / or, the third via is evenly distributed in the second pixel circuit area;

[0038] And / or, the fourth via is evenly distributed in the second pixel circuit area;

[0039] And / or, in the same second pixel circuit, the third via and the fourth via are multiplexed as the same via, and the distance from the via to the third transistor is the same as the distance from the via to the fourth transistor.

[0040] In one embodiment, the third via is located at the point where the orthogonal projections of the fifth gate and the sixth gate on the substrate overlap;

[0041] And / or, the fourth via is located at the intersection of the orthogonal projections of the seventh gate and the eighth gate on the substrate;

[0042] And / or, in the first direction, the width of the third via is less than or equal to 6 μm, in the second direction, the width of the third via is less than or equal to 6 μm, and the first direction intersects the second direction;

[0043] And / or, in the first direction, the width of the fourth via is less than or equal to 6 μm, in the second direction, the width of the fourth via is less than or equal to 6 μm, and the first direction intersects the second direction;

[0044] And / or, along a direction parallel to the plane of the substrate, the width of the fifth gate is greater than the width of the sixth gate;

[0045] And / or, along a direction parallel to the plane of the substrate, the width of the seventh gate is greater than the width of the eighth gate.

[0046] A second aspect of this application provides a method for fabricating an array substrate, comprising:

[0047] A first gate is fabricated on one side of the substrate, and in the first pixel circuit region;

[0048] A first insulating layer and a second gate are sequentially formed on the side of the first gate facing away from the substrate. The first insulating layer has a first via. A first connection structure is formed in the first insulating layer to obtain a first pixel circuit including at least one transistor. The first gate and the second gate are electrically connected through the first connection structure. The orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the second gate on the substrate.

[0049] In one embodiment, a first insulating layer and a second gate are sequentially fabricated on the side of the first gate facing away from the substrate. The first insulating layer has a first via. The step of fabricating a first connection structure in the first insulating layer includes:

[0050] A first insulating layer is formed on the side of the first gate that is away from the substrate, and a first via is formed in the first insulating layer;

[0051] A second gate is fabricated on the side of the first insulating layer away from the substrate. The second gate extends into the first via and is electrically connected to the first gate. The second gate located in the first via forms a first connection structure.

[0052] And / or, on the side of the first gate facing away from the substrate, a first insulating layer and a second gate are sequentially formed, the first insulating layer having a first via, and the step of forming a first connection structure in the first insulating layer includes:

[0053] A first insulating layer and a second gate are sequentially formed on the side of the first gate facing away from the substrate, and a first via is formed through the first insulating layer and the second gate.

[0054] A conductive layer is prepared on the side of the second gate away from the substrate. The conductive layer is electrically connected to the first gate and the second gate through a first via. The conductive layer located in the first via forms a first connection structure.

[0055] A third aspect of this application provides a display panel, including the aforementioned array substrate, or including an array substrate prepared by the aforementioned preparation method.

[0056] According to the array substrate provided in the embodiments of this application, in the first pixel circuit area located between the hole area and the second pixel circuit area, the first transistor of the first pixel circuit includes two gates. The two gates are directly connected through a via in the first insulating layer, so that the potentials of the two gates are almost the same and there is almost no signal delay between the two gates, which is beneficial to improve the uneven display phenomenon in the display panel corresponding to the first pixel circuit area. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of an 8T1C pixel circuit in the prior art.

[0058] Figure 2 This is a top view of the array substrate in one embodiment of this application.

[0059] Figure 3 for Figure 2 A schematic diagram of a cross-sectional structure of the array substrate along the AA' direction.

[0060] Figure 4This is a top view of the array substrate in another embodiment of this application.

[0061] Figure 5 for Figure 2 A schematic diagram of another cross-sectional structure of the array substrate along the AA' direction.

[0062] Figure 6 for Figure 2 A schematic diagram of another cross-sectional structure of the array substrate along the AA' direction.

[0063] Figure 7 for Figure 2 A schematic diagram of another cross-sectional structure of the array substrate along the AA' direction.

[0064] Figure 8 for Figure 2 A schematic diagram of another cross-sectional structure of the array substrate along the AA' direction.

[0065] Figure 9 for Figure 2 A schematic diagram of a cross-sectional structure of the array substrate along the BB' direction.

[0066] Figure 10 for Figure 2 A schematic diagram of another cross-sectional structure of the array substrate along the BB' direction.

[0067] Figure 11 This is a schematic diagram of the fabrication process of an array substrate in one embodiment of this application. Detailed Implementation

[0068] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0069] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented even without certain specific details. In some instances, methods and means well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0070] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0071] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0072] OLED display panels, such as flexible active-matrix organic light-emitting diode (AMOLED), use LTPO technology to achieve 1-120Hz refresh rate compatibility. For example, display panels employing an 8T1C pixel circuit diagram are shown below. Figure 1 The 8T1C pixel circuit diagram shown uses an IGZO active layer for the active layers of transistors T3 and T4, which connect the gate potential of driving transistor T1. This reduces leakage current at the gate of driving transistor T1, achieving a low refresh rate. For 8T1C products, transistors T3 and T4 typically operate with single-sided driving and employ a bottom-gate plus top-gate design. The bottom gate width is usually larger than the top gate, resulting in a lower electrical load and signal delay for the bottom gate compared to the top gate. In existing technology, during the wiring process in the via area, to reduce the via bezel, the bottom and top gates of transistors T3 and T4 are connected together with wires before wiring. This causes a difference in the delay of transistors T3 and T4 in the via area compared to the non-via area, resulting in uneven display in the via area.

[0073] In view of this, the first aspect of this application provides an array substrate, referring to... Figure 2 The schematic diagram of the top view of the array substrate shown shows that the array substrate includes a first pixel circuit area S1, a second pixel circuit area S2 and a hole area S3, with the first pixel circuit area S1 located between the second pixel circuit area S2 and the hole area S3.

[0074] Optionally, refer to Figure 3 The schematic diagram of the cross-sectional structure of the array substrate shown includes: a substrate 100 and at least one first pixel circuit 200.

[0075] Optionally, at least one first pixel circuit 200 is located on one side of the substrate 100, and at least one first pixel circuit 200 is located in the first pixel circuit region S1; the first pixel circuit 200 includes at least one transistor 210, the at least one transistor 210 includes a first transistor 211, the first transistor 211 includes a first gate 2111, a second gate 2112, a first insulating layer 2113 and a first connection structure 2114, the first gate 2111 is located between the substrate 100 and the second gate 2112, and the orthographic projection of the first gate 2111 on the substrate 100 overlaps with the orthographic projection of the second gate 2112 on the substrate 100; the first insulating layer 2113 is located between the first gate 2111 and the second gate 2112, and the first insulating layer 2113 has a first via 2115; the first connection structure 2114 is located in the first via 2115, and the first gate 2111 and the second gate 2112 are electrically connected through the first connection structure 2114.

[0076] According to the array substrate provided in the embodiments of this application, in the first pixel circuit region S1 located between the hole region S3 and the second pixel circuit region S2, the first transistor 211 of the first pixel circuit 200 includes two gates. The two gates are directly connected through the first via 2115 in the first insulating layer 2113, so that the potentials of the two gates are almost the same and there is almost no signal delay between the two gates, which is beneficial to improve the uneven display phenomenon in the display panel corresponding to the first pixel circuit region S1.

[0077] For example, the width of the first gate 2111 is greater than the width of the second gate 2112 in a direction parallel to the plane of the substrate 100.

[0078] Optionally, refer to Figure 3 The first via 2115 is located at the point where the orthogonal projections of the first gate 2111 and the second gate 2112 on the substrate 100 overlap. As a result, the trace distance of the first connection structure 2114 between the first gate 2111 and the second gate 2112 is shorter, which is more conducive to avoiding the risk of signal delay between the first gate 2111 and the second gate 2112, and is more conducive to improving the display unevenness phenomenon in the display panel corresponding to the first pixel circuit area S1.

[0079] For example, the material of the first gate 2111 includes metals (e.g., metals including but not limited to aluminum, molybdenum, titanium, etc.), and the material of the second gate 2112 includes cesium tungsten oxide (GATO).

[0080] For example, refer to Figure 4The schematic top view of the array substrate shows that, in the first direction x, the width of the first via 2115 is less than or equal to 6μm (e.g., it can be 1μm, 2μm, 3μm, 4μm, 5μm, or 6μm, etc.), and in the second direction y, the width of the first via 2115 is less than or equal to 6μm (e.g., it can be 1μm, 2μm, 3μm, 4μm, 5μm, or 6μm, etc.). The first direction x intersects the second direction y. Therefore, the size of the first via 2115 is appropriate and will hardly affect the routing of other traces.

[0081] It is understandable that the width of the first via 2115 in the first direction x refers to the maximum distance between the edges of the first via 2115 in the first direction x; the width of the first via 2115 in the second direction y refers to the maximum distance between the edges of the first via 2115 in the second direction y.

[0082] In one embodiment, refer to Figure 5 The schematic cross-sectional structure of the array substrate shown includes at least one transistor 210, which further includes a second transistor 212. The second transistor 212 includes a third gate 2121, a fourth gate 2122, a second insulating layer 2123, and a second connection structure 2124. The third gate 2121 is located between the substrate 100 and the fourth gate 2122, and the orthographic projection of the third gate 2121 on the substrate 100 overlaps with the orthographic projection of the fourth gate 2122 on the substrate 100. The second insulating layer 2123 is located between the third gate 2121 and the fourth gate 2122, and has a second via 2125. The second connection structure 2124 is located in the second via 2125, and the third gate 2121 and the fourth gate 2122 are electrically connected through the second connection structure 2124. The second transistor 212 of the first pixel circuit 200 includes two gates, which are directly connected through the second connection structure 2124 in the second via 2125, so that the potentials of the two gates are almost the same and there is almost no signal delay between the two gates, which helps to improve the uneven display phenomenon in the display panel corresponding to the first pixel circuit area S1.

[0083] For example, along a direction parallel to the plane of the substrate 100, the width of the third gate 2121 is greater than the width of the fourth gate 2122.

[0084] For example, the material of the third gate 2121 includes metals (e.g., metals including but not limited to aluminum, molybdenum, titanium, etc.), and the material of the fourth gate 2122 includes cesium tungsten oxide (GATO).

[0085] For example, the second via 2125 is located at the point where the orthogonal projections of the third gate 2121 and the fourth gate 2122 on the substrate 100 overlap. Therefore, the trace distance of the second connection structure 2124 between the third gate 2121 and the fourth gate 2122 is shorter, which is more conducive to avoiding the risk of signal delay between the third gate 2121 and the fourth gate 2122, and more conducive to improving the display unevenness phenomenon in the display panel corresponding to the first pixel circuit area S1.

[0086] For example, refer to Figure 5 In the same first pixel circuit 200, the first transistor 211 corresponds to at least one first via 2115, and the second transistor 212 corresponds to at least one second via 2125.

[0087] For example, refer to Figure 6 The schematic diagram of the cross-sectional structure of the array substrate shown shows that in the same first pixel circuit 200, the first via 2115 and the second via 2125 are multiplexed into the same via 2110, which helps to reduce the number of vias and facilitates the arrangement of other lines.

[0088] For example, in the same first pixel circuit 200, the first via 2115 and the second via 2125 are multiplexed into the same via 2110, and the distance from the via 2110 to the first transistor 211 is the same as the distance from the via 2110 to the second transistor 212.

[0089] It should be noted that the statement that the distance from via 2110 to the first transistor 211 is the same as the distance from via 2110 to the second transistor 212 means that the distance from via 2110 to the first transistor 211 is equal to the distance from via 2110 to the second transistor 212, or that the absolute value of the difference between the distance from via 2110 to the first transistor 211 and the distance from via 2110 to the second transistor 212 is greater than 0 and less than or equal to 5%, or that the absolute value of the difference between the distance from via 2110 to the first transistor 211 and the distance from via 2110 to the second transistor 212 is greater than 0 and less than or equal to 5%.

[0090] For example, in a plurality of first pixel circuits 200, a plurality of first transistors 211 correspond to the same first via 2115, and a plurality of second transistors 212 correspond to the same second via 2125.

[0091] For example, in a plurality of first pixel circuits 200, the first via 2115 and the second via 2125 are multiplexed into the same via 2110, and a plurality of first transistors 211 and a plurality of second transistors 212 correspond to one via 2110. For example, the distance from the via 2110 to the first transistor 211 of each corresponding first pixel circuit 200 is the same, and for another example, the distance from the via 2110 to the second transistor 212 of each corresponding first pixel circuit 200 is the same.

[0092] For example, in the first direction x, the width of the second via 2125 is less than or equal to 6μm (e.g., it can be 1μm, 2μm, 3μm, 4μm, 5μm, or 6μm, etc.), and in the second direction y, the width of the second via 2125 is less than or equal to 6μm (e.g., it can be 1μm, 2μm, 3μm, 4μm, 5μm, or 6μm, etc.), and the first direction x intersects the second direction y. Therefore, the size of the second via 2125 is suitable and will hardly affect the routing of other traces.

[0093] For example, the first via 2115 is evenly distributed in the first pixel circuit area S1; the second via 2125 is evenly distributed in the first pixel circuit area S1. This results in a more uniform display image on the display panel corresponding to the first pixel circuit area S1, leading to higher display quality.

[0094] For example, refer to Figure 5 or Figure 6 The third gate 2121 is disposed on the same layer as the first gate 2111; the second gate 2112 is disposed on the same layer as the fourth gate 2122; and the first insulating layer 2113 is disposed on the same layer as the second insulating layer 2123.

[0095] In one embodiment, refer to Figure 7 The schematic diagram of the cross-sectional structure of the array substrate shown shows that the array substrate also includes a conductive layer 300 located on the side of the first pixel circuit 200 away from the substrate 100. The conductive layer 300 is electrically connected to the first gate 2111 and the second gate 2112 through the first via 2115. The conductive layer 300 in the first via 2115 forms a first connection structure 2114.

[0096] For example, a fifth insulating layer 500 is provided between the conductive layer 300 and the second gate 2112 and the fourth gate 2122.

[0097] For example, the first via 2115 penetrates the second gate 2112. As a result, the trace distance of the first connection structure 2114 is shorter, which is more conducive to reducing the risk of signal delay between the first gate 2111 and the second gate 2112.

[0098] Understandably, referring to Figure 7The conductive layer 300 is electrically connected to the third gate 2121 and the fourth gate 2122 through the second via 2125, and the conductive layer 300 located in the second via 2125 forms the second connection structure 2124.

[0099] For example, the second via 2125 penetrates the fourth gate 2122. As a result, the trace distance of the second connection structure 2124 is shorter, which is more conducive to reducing the risk of signal delay between the third gate 2121 and the fourth gate 2122.

[0100] For example, refer to Figure 8 The schematic diagram of the cross-sectional structure of the array substrate shown shows that the second gate 2112 extends into the first via 2115 and is electrically connected to the first gate 2111. The second gate 2112 located in the first via 2115 forms the first connection structure 2114.

[0101] For example, refer to Figure 8 The fourth gate 2122 extends into the second via 2125 and is electrically connected to the third gate 2121. The fourth gate 2122 located in the second via 2125 forms the second connection structure 2124.

[0102] In one embodiment, refer to Figure 9 The schematic diagram of the cross-sectional structure of the array substrate shown further includes: at least one second pixel circuit 400, located on one side of the substrate 100 and in the second pixel circuit region S2; the second pixel circuit 400 includes at least one transistor 410, the at least one transistor 410 includes a third transistor 411, the third transistor 411 includes a fifth gate 4111, a sixth gate 4112, a third insulating layer 4113 and a third connection structure 4114, the fifth gate 4111 is located between the substrate 100 and the sixth gate 4112, and the orthographic projection of the fifth gate 4111 on the substrate 100 overlaps with the orthographic projection of the sixth gate 4112 on the substrate 100; the third insulating layer 4113 is located between the fifth gate 4111 and the sixth gate 4112, and has a third via 4115 in the third insulating layer 4113; the third connection structure 4114 is located in the third via 4115, and the fifth gate 4111 and the sixth gate 4112 are electrically connected through the third connection structure 4114.

[0103] It is understandable that the first pixel circuit area S1 corresponds to the transition area between the normal display area and the hole area in the display panel; the second pixel circuit area S2 can be the normal display area of ​​the corresponding display panel.

[0104] It is understandable that in the prior art, the two gates of the dual-gate transistors in the first pixel circuit region S1 and the second pixel circuit region S2 are led out in different ways. Therefore, the signal delay in the second pixel circuit region S2 is not obvious, while the signal delay in the first pixel circuit region S1 is significant. In this embodiment, the two gates of the dual-gate third transistor 411 in the second pixel circuit region S2 are connected through a third connection structure 4114 in the third via 4115, which helps to improve the signal delay in the second pixel circuit region S2 and further enhances the display quality of the display panel.

[0105] For example, the width of the fifth gate 4111 is greater than the width of the sixth gate 4112 in a direction parallel to the plane of the substrate 100.

[0106] In one embodiment, the third via 4115 is located at the point where the orthogonal projections of the fifth gate 4111 and the sixth gate 4112 on the substrate 100 overlap. Therefore, the trace distance of the third connection structure 4114 between the fifth gate 4111 and the sixth gate 4112 is shorter, which is more conducive to avoiding the risk of signal delay between the fifth gate 4111 and the sixth gate 4112, and more conducive to improving the display unevenness phenomenon in the display panel corresponding to the second pixel circuit area S2.

[0107] For example, the material of the fifth gate 4111 includes metals (e.g., metals including but not limited to aluminum, molybdenum, titanium, etc.), and the material of the sixth gate 4112 includes cesium tungsten oxide (GATO).

[0108] For example, in the first direction x, the width of the third via 4115 is less than or equal to 6μm (e.g., it can be 1μm, 2μm, 3μm, 4μm, 5μm, or 6μm, etc.), and in the second direction y, the width of the third via is less than or equal to 6μm (e.g., it can be 1μm, 2μm, 3μm, 4μm, 5μm, or 6μm, etc.), and the first direction x intersects the second direction y. Therefore, the size of the third via 4115 is appropriate and will hardly affect the routing of other traces.

[0109] It is understandable that the width of the third via 4115 in the first direction x refers to the maximum distance between the edges of the third via 4115 in the first direction x; the width of the third via 4115 in the second direction y refers to the maximum distance between the edges of the third via 4115 in the second direction y.

[0110] For example, refer to Figure 9In the second pixel circuit 400, at least one transistor 410 further includes a fourth transistor 412. The fourth transistor 412 includes a seventh gate 4121, an eighth gate 4122, a fourth insulating layer 4123, and a fourth connection structure 4124. The seventh gate 4121 is located between the substrate 100 and the eighth gate 4122, and the orthographic projection of the seventh gate 4121 on the substrate 100 overlaps with the orthographic projection of the eighth gate 4122 on the substrate 100. The fourth insulating layer 4123 is located between the seventh gate 4121 and the eighth gate 4122, and has a fourth via 4125. The fourth connection structure 4124 is located in the fourth via 4125, and the seventh gate 4121 and the eighth gate 4122 are electrically connected through the fourth connection structure 4124.

[0111] For example, along a direction parallel to the plane of the substrate 100, the width of the seventh gate 4121 is greater than the width of the eighth gate 4122.

[0112] For example, the material of the seventh gate 4121 includes metals (e.g., metals including but not limited to aluminum, molybdenum, titanium, etc.), and the material of the eighth gate 4122 includes cesium tungsten oxide (GATO).

[0113] For example, the fourth via 4125 is located at the point where the orthogonal projections of the seventh gate 4121 and the eighth gate 4122 on the substrate 100 overlap. Therefore, the trace distance of the fourth connection structure 4124 between the seventh gate 4121 and the eighth gate 4122 is shorter, which is more conducive to avoiding the risk of signal delay between the seventh gate 4121 and the eighth gate 4122, and more conducive to improving the display unevenness phenomenon in the display panel corresponding to the first pixel circuit area S1.

[0114] For example, in the first direction x, the width of the fourth via 4125 is less than or equal to 6μm (e.g., it can be 1μm, 2μm, 3μm, 4μm, 5μm, or 6μm, etc.), and in the second direction y, the width of the fourth via 4125 is less than or equal to 6μm (e.g., it can be 1μm, 2μm, 3μm, 4μm, 5μm, or 6μm, etc.), and the first direction x intersects the second direction y. Therefore, the size of the fourth via 4125 is suitable and will hardly affect the routing of other traces.

[0115] In one embodiment, in the same second pixel circuit 400, the third transistor 411 corresponds to at least one third via 4115, and the fourth transistor 412 corresponds to at least one fourth via 4125.

[0116] For example, in the same second pixel circuit 400, the third via 4115 and the fourth via 4125 are multiplexed into the same via 4110, which helps to reduce the number of vias and facilitates the arrangement of other lines.

[0117] For example, in the same second pixel circuit 400, the third via 4115 and the fourth via 4125 are multiplexed into the same via 4110, and the distance from via 4110 to the third transistor 411 is the same as the distance from via 4110 to the fourth transistor 412.

[0118] It should be noted that the distance from via 4110 to the third transistor 411 being the same as the distance from via 4110 to the fourth transistor 412 means that the distance from via 4110 to the third transistor 411 is equal to the distance from via 4110 to the fourth transistor 412, or the absolute value of the difference between the distance from via 4110 to the third transistor 411 and the distance from via 4110 to the fourth transistor 412 is greater than 0 and less than or equal to 5%, or the absolute value of the difference between the distance from via 4110 to the third transistor 411 and the distance from via 4110 to the fourth transistor 412 is greater than 0 and less than or equal to 5%.

[0119] For example, in a plurality of second pixel circuits 400, a plurality of third transistors 411 correspond to the same third via 4115, and a plurality of fourth transistors 412 correspond to the same fourth via 4125.

[0120] For example, in a plurality of second pixel circuits 400, the third via 4115 and the fourth via 4125 are multiplexed into the same via 4110, and a plurality of first transistors 211 and a plurality of second transistors 212 correspond to one via 4110. For example, the distance from the via 4110 to the first transistor 211 of each corresponding first pixel circuit 200 is the same, and for another example, the distance from the via 4110 to the second transistor 212 of each corresponding first pixel circuit 200 is the same.

[0121] For example, the third via 4115 is evenly distributed in the second pixel circuit area S2; the fourth via 4125 is evenly distributed in the second pixel circuit area S2. This results in a more uniform display image on the display panel corresponding to the second pixel circuit area S2, leading to higher display quality.

[0122] For example, the fifth gate 4111 and the seventh gate 4121 are disposed on the same layer; the sixth gate 4112 and the eighth gate 4122 are disposed on the same layer; and the third insulating layer 4113 and the fourth insulating layer 4123 are disposed on the same layer.

[0123] For example, the conductive layer 300 is electrically connected to the fifth gate 4111 and the sixth gate 4112 through the third via 4115, and the conductive layer 300 located in the third via 4115 forms a third connection structure 4114.

[0124] For example, the third via 4115 penetrates the sixth gate 4112. As a result, the trace distance of the third connection structure 4114 is shorter, which is more conducive to reducing the risk of signal delay between the fifth gate 4111 and the sixth gate 4112.

[0125] For example, the sixth gate 4112 extends into the third via 4115 and is electrically connected to the fifth gate 4111, and the sixth gate 4112 located in the third via 4115 forms a third connection structure 4114.

[0126] For example, the conductive layer 300 is electrically connected to the seventh gate 4121 and the eighth gate 4122 through the fourth via 4125, and the conductive layer 300 located in the fourth via 4125 forms the fourth connection structure 4124.

[0127] For example, the fourth via 4125 penetrates the eighth gate 4122. As a result, the trace distance of the fourth connection structure 4124 is shorter, which is more conducive to reducing the risk of signal delay between the seventh gate 4121 and the eighth gate 4122.

[0128] For example, the eighth gate 4122 extends into the fourth via 4125 and is electrically connected to the seventh gate 4121, and the eighth gate 4122 located in the fourth via 4125 forms the fourth connection structure 4124.

[0129] For example, the first transistor 211, the second transistor 212, the third transistor 411, and the fourth transistor 412 are arranged on the same layer. For instance, the first gate 2111 and the fifth gate 4111 are arranged on the same layer; the second gate 2112 and the sixth gate 4112 are arranged on the same layer; the first insulating layer 2113 and the third insulating layer 4113 are arranged on the same layer; the third gate 2121 and the first gate 2111 are arranged on the same layer; the second gate 2112 and the fourth gate 2122 are arranged on the same layer; the first insulating layer 2113 and the second insulating layer 2123 are arranged on the same layer; the fifth gate 4111 and the seventh gate 4121 are arranged on the same layer; the sixth gate 4112 and the eighth gate 4122 are arranged on the same layer; and the third insulating layer 4113 and the fourth insulating layer 4123 are arranged on the same layer.

[0130] For example, refer to Figure 10The schematic diagram of the cross-sectional structure of the array substrate shown indicates that the first insulating layer 2113 further includes a first sub-insulating layer 21131 and a second sub-insulating layer 21132. The first transistor 211 further includes a first active layer 2116 located between the first gate 2111 and the second gate 2112. The first sub-insulating layer 21131 is located between the first gate 2111 and the first active layer 2116, and the second sub-insulating layer 21132 is located between the first active layer 2116 and the second gate 2112. The second transistor 212 further includes a second active layer 2126 located between the third gate 2121 and the fourth gate 2122. The first sub-insulating layer 21131 is located between the third gate 2121 and the second active layer 2126, and the second sub-insulating layer 21132 is located between the third gate 2121 and the second active layer 2126. 1132 is located between the second active layer 2126 and the fourth gate 2122; the third transistor 411 also includes a third active layer 4116 located between the fifth gate 4111 and the sixth gate 4112, a first sub-insulating layer 21131 located between the fifth gate 4111 and the third active layer 4116, and a second sub-insulating layer 21132 located between the third active layer 4116 and the sixth gate 4112; the fourth transistor 412 also includes a fourth active layer 4126 located between the seventh gate 4121 and the eighth gate 4122, a first sub-insulating layer 21131 located between the seventh gate 4121 and the fourth active layer 4126, and a second sub-insulating layer 21132 located between the fourth active layer 4126 and the eighth gate 4122.

[0131] For example, refer to Figure 1 The pixel circuit diagram shown includes a fifth transistor T2, a sixth transistor T5, a seventh transistor T6, an eighth transistor T7, a ninth transistor T8, and a capacitor Cst. The eight transistors and one capacitor constitute an 8T1C pixel circuit. The operation mode of the pixel circuit and the signals connected to it can be referred to in the existing 8T1C pixel circuit, which will not be described in detail here.

[0132] The second aspect of this application provides a method for fabricating an array substrate, referring to... Figure 11 The diagram shows a process flow chart for fabricating an array substrate, which includes the following steps.

[0133] S100: A first gate is fabricated on one side of the substrate, in the first pixel circuit region.

[0134] It should be noted that the substrate, the first pixel circuit area, and the first gate are the same as described above, and will not be repeated here.

[0135] S200: A first insulating layer and a second gate are sequentially formed on the side of the first gate away from the substrate. The first insulating layer has a first via. A first connection structure is formed in the first insulating layer to obtain a first pixel circuit including at least one transistor.

[0136] The first gate and the second gate are electrically connected through a first connection structure, and the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the second gate on the substrate.

[0137] It should be noted that the first insulating layer, the second gate, the first via, the first connection structure, and the first pixel circuit are consistent with the previous description, and will not be repeated here.

[0138] In one embodiment, a first insulating layer and a second gate are sequentially fabricated on the side of the first gate facing away from the substrate. The first insulating layer has a first via. The step of fabricating a first connection structure in the first insulating layer includes: fabricating the first insulating layer on the side of the first gate facing away from the substrate, forming the first via in the first insulating layer; fabricating the second gate on the side of the first insulating layer facing away from the substrate, the second gate extending into the first via and electrically connected to the first gate, and the second gate located in the first via forming the first connection structure. Thus, the electrical connection between the first gate and the second gate can be achieved directly using existing film layers, saving fabrication steps.

[0139] In another embodiment, a first insulating layer and a second gate are sequentially fabricated on the side of the first gate facing away from the substrate. The first insulating layer has a first via. The step of fabricating a first connection structure in the first insulating layer includes: sequentially fabricating the first insulating layer and the second gate on the side of the first gate facing away from the substrate, and forming a first via penetrating the first insulating layer and the second gate; fabricating a conductive layer on the side of the second gate facing away from the substrate, the conductive layer being electrically connected to the first gate and the second gate through the first via, and the conductive layer located in the first via forming the first connection structure. Thus, the first via penetrates the second gate, and the conductive layer penetrates the second gate and is electrically connected to the first gate.

[0140] It should be noted that in the first pixel circuit, the third gate is disposed on the same layer as the first gate; the second gate is disposed on the same layer as the fourth gate; the first insulating layer is disposed on the same layer as the second insulating layer; and the second transistor can be fabricated by referring to the method of the first transistor, which will not be elaborated further here.

[0141] It should be noted that the first and second transistors in the first pixel circuit are arranged on the same layer as the third and fourth transistors in the second pixel circuit. The fabrication method of the third and fourth transistors can be referred to the fabrication method of the first transistor, which will not be elaborated further here.

[0142] A third aspect of this application provides a display panel, including the aforementioned array substrate, or including an array substrate prepared by the aforementioned preparation method.

[0143] It should be noted that, in addition to the array substrate described above, the display panel may also include the structures that a conventional display panel should have, such as light-emitting devices and encapsulation layers, which will not be elaborated on further here.

[0144] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0145] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. An array substrate, characterized in that, It includes a first pixel circuit area, a second pixel circuit area, and a hole area, wherein the first pixel circuit area is located between the second pixel circuit area and the hole area; The array substrate includes: Substrate; At least one first pixel circuit is located on one side of the substrate, and at least one first pixel circuit is located in the first pixel circuit region; the first pixel circuit includes at least one transistor, the at least one transistor includes a first transistor, the first transistor includes a first gate, a second gate, a first insulating layer and a first connection structure, the first gate is located between the substrate and the second gate, and the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the second gate on the substrate; the first insulating layer is located between the first gate and the second gate, and the first insulating layer has a first via; the first connection structure is located in the first via, and the first gate and the second gate are electrically connected through the first connection structure.

2. The array substrate according to claim 1, characterized in that, The first via is located at the point where the orthogonal projections of the first gate and the second gate on the substrate overlap; And / or, along a direction parallel to the plane where the substrate is located, the width of the first gate is greater than the width of the second gate; And / or, the material of the first gate includes a metal, and the material of the second gate includes cesium tungsten oxide; And / or, in a first direction, the width of the first via is less than or equal to 6 μm, in a second direction, the width of the first via is less than or equal to 6 μm, and the first direction intersects the second direction.

3. The array substrate according to claim 1, characterized in that, At least one of the transistors further includes: a second transistor, the second transistor including a third gate, a fourth gate, a second insulating layer, and a second connection structure, the third gate being located between the substrate and the fourth gate, the orthographic projection of the third gate on the substrate overlapping the orthographic projection of the fourth gate on the substrate; the second insulating layer being located between the third gate and the fourth gate, the second insulating layer having a second via; the second connection structure being located in the second via, the third gate and the fourth gate being electrically connected through the second connection structure; And / or, in the same first pixel circuit, the first transistor corresponds to at least one first via, and the second transistor corresponds to at least one second via; And / or, in the same first pixel circuit, the first via and the second via are multiplexed as the same via; And / or, in a plurality of first pixel circuits, a plurality of first transistors correspond to the same first via, and a plurality of second transistors correspond to the same second via; And / or, in multiple first pixel circuits, the first via and the second via are multiplexed as the same via, and multiple first transistors and multiple second transistors correspond to one via; And / or, in the first direction, the width of the second via is less than or equal to 6 μm, and in the second direction, the width of the second via is less than or equal to 6 μm, wherein the first direction intersects the second direction; And / or, the first via is uniformly distributed in the first pixel circuit area; And / or, the second via is uniformly distributed in the first pixel circuit area; And / or, in the same first pixel circuit, the first via and the second via are multiplexed as the same via, and the distance from the via to the first transistor is the same as the distance from the via to the second transistor; And / or, along a direction parallel to the plane where the substrate is located, the width of the third gate is greater than the width of the fourth gate; And / or, the material of the third gate includes a metal, and the material of the fourth gate includes cesium tungsten oxide; And / or, the second via is located at the point where the orthogonal projections of the third gate and the fourth gate on the substrate overlap; And / or, the third gate is disposed in the same layer as the first gate; And / or, the second gate and the fourth gate are disposed in the same layer; And / or, the first insulating layer and the second insulating layer are disposed in the same layer.

4. The array substrate according to claim 1, characterized in that, The array substrate further includes a conductive layer located on the side of the first pixel circuit away from the substrate. The conductive layer is electrically connected to the first gate and the second gate through the first via, and the conductive layer in the first via forms the first connection structure. And / or, the first via penetrates the second gate; And / or, the second gate extends into the first via and is electrically connected to the first gate, and the second gate located in the first via forms the first connection structure.

5. The array substrate according to claim 3, characterized in that, Also includes: At least one second pixel circuit is located on one side of the substrate and in the second pixel circuit area; The second pixel circuit includes at least one transistor, and the at least one transistor includes a third transistor. The third transistor includes a fifth gate, a sixth gate, a third insulating layer, and a third connection structure. The fifth gate is located between the substrate and the sixth gate, and the orthographic projection of the fifth gate on the substrate overlaps with the orthographic projection of the sixth gate on the substrate. The third insulating layer is located between the fifth gate and the sixth gate, and the third insulating layer has a third via; the third connection structure is located in the third via, and the fifth gate and the sixth gate are electrically connected through the third connection structure; And / or, in the second pixel circuit, at least one of the transistors further includes a fourth transistor, the fourth transistor including a seventh gate, an eighth gate, a fourth insulating layer and a fourth connection structure, the seventh gate being located between the substrate and the eighth gate, and the orthographic projection of the seventh gate on the substrate overlapping the orthographic projection of the eighth gate on the substrate; The fourth insulating layer is located between the seventh gate and the eighth gate, and the fourth insulating layer has a fourth via; the fourth connection structure is located in the fourth via, and the seventh gate and the eighth gate are electrically connected through the fourth connection structure.

6. The array substrate according to claim 5, characterized in that, In the same second pixel circuit, the third transistor corresponds to at least one of the third vias, and the fourth transistor corresponds to at least one of the fourth vias; And / or, in the same second pixel circuit, the third via and the fourth via are multiplexed as the same via; And / or, in a plurality of second pixel circuits, a plurality of third transistors correspond to the same third via, and a plurality of fourth transistors correspond to the same fourth via; And / or, in multiple second pixel circuits, the third via and the fourth via are multiplexed as the same via, and multiple first transistors and multiple second transistors correspond to one via; And / or, the third via is uniformly distributed in the second pixel circuit area; And / or, the fourth via is uniformly distributed in the second pixel circuit area; And / or, in the same second pixel circuit, the third via and the fourth via are multiplexed as the same via, and the distance from the via to the third transistor is the same as the distance from the via to the fourth transistor.

7. The array substrate according to claim 5, characterized in that, The third via is located at the point where the orthogonal projections of the fifth gate and the sixth gate on the substrate overlap; And / or, the fourth via is located at the point where the orthogonal projections of the seventh gate and the eighth gate on the substrate overlap; And / or, in a first direction, the width of the third via is less than or equal to 6 μm, and in a second direction, the width of the third via is less than or equal to 6 μm, wherein the first direction intersects the second direction; And / or, in a first direction, the width of the fourth via is less than or equal to 6 μm, and in a second direction, the width of the fourth via is less than or equal to 6 μm, wherein the first direction intersects the second direction; And / or, along a direction parallel to the plane where the substrate is located, the width of the fifth gate is greater than the width of the sixth gate; And / or, along a direction parallel to the plane of the substrate, the width of the seventh gate is greater than the width of the eighth gate.

8. A method for fabricating an array substrate, characterized in that, include: A first gate is fabricated on one side of the substrate, and in the first pixel circuit region; A first insulating layer and a second gate are sequentially formed on the side of the first gate facing away from the substrate. The first insulating layer has a first via. A first connection structure is formed in the first insulating layer to obtain a first pixel circuit including at least one transistor. The first gate and the second gate are electrically connected through the first connection structure. The orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the second gate on the substrate.

9. The preparation method according to claim 8, characterized in that, The step of sequentially fabricating a first insulating layer and a second gate on the side of the first gate facing away from the substrate, wherein the first insulating layer has a first via, and fabricating a first connection structure in the first insulating layer includes: The first insulating layer is formed on the side of the first gate opposite to the substrate, and the first via is formed in the first insulating layer; A second gate is fabricated on the side of the first insulating layer away from the substrate. The second gate extends into the first via and is electrically connected to the first gate. The second gate located in the first via forms the first connection structure. And / or, the step of sequentially fabricating a first insulating layer and a second gate on the side of the first gate opposite to the substrate, wherein the first insulating layer has a first via, and fabricating a first connection structure in the first insulating layer includes: A first insulating layer and a second gate are sequentially formed on the side of the first gate facing away from the substrate, and a first via is formed through the first insulating layer and the second gate. A conductive layer is formed on the side of the second gate opposite to the substrate. The conductive layer is electrically connected to the first gate and the second gate through the first via. The conductive layer located in the first via forms the first connection structure.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 7, or includes the array substrate prepared by the preparation method described in claim 8 or 9.

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