Array substrate, preparation method thereof, display panel and display device

Abstract

An array substrate, a manufacturing method thereof, a display panel and a display device, the array substrate comprising: a substrate and a plurality of thin film transistors located on one side of the substrate. The thin film transistor comprises an active layer and a first gate layer, the active layer comprising a channel portion and a drain portion and a source portion located on both sides of the channel portion; the thin film transistor further comprises a first protruding portion with the same material as the channel portion, the first protruding portion being arranged on one side surface of the channel portion; the first gate layer is provided with a recess cavity, the first protruding portion is at least partially located in the recess cavity of the first gate layer, and the first gate layer is coupled with the first protruding portion on at least three sides. The first protruding portion can be regarded as an extension of the channel portion, and the three-side coupling of the first protruding portion with the recess cavity of the first gate layer can increase the coupling area of the first gate layer and the channel portion, thereby enhancing the control ability of the leakage current of the thin film transistor.

Description

Technical Field

[0001] This application belongs to the field of display device technology, and particularly relates to an array substrate and its preparation method, a display panel and a display device. Background Technology

[0002] Currently, organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used and have become the mainstream of display devices due to their advantages such as high image quality, power saving, thin body and wide range of applications. Summary of the Invention

[0003] The purpose of this application is to provide an array substrate and its preparation method, a display panel and a display device to solve the problems existing in the prior art.

[0004] A first aspect of this application provides an array substrate, comprising: a substrate; a plurality of thin-film transistors located on one side of the substrate, the thin-film transistors including an active layer and a first gate layer, the active layer including a channel portion and a drain portion and a source portion located on both sides of the channel portion; the drain portion, the channel portion and the source portion are sequentially disposed along a first direction parallel to the substrate, the orthographic projection of the channel portion on the substrate being located within the orthographic projection of the first gate layer on the substrate; the thin-film transistor further includes a first protrusion of the same material as the channel portion, the first protrusion being disposed on the side surface of the channel portion near the first gate layer; the sum of the thicknesses of the channel portion and the first protrusion in a second direction perpendicular to the substrate is greater than the thickness of the drain portion and the thickness of the source portion; the first gate layer has a cavity, the first protrusion being at least partially located within the cavity of the first gate layer, and the first gate layer being coupled to the first protrusion on at least three sides.

[0005] In one embodiment, the thin-film transistor further includes a second gate layer located on the side of the active layer away from the first gate layer; the orthographic projection of the channel portion on the substrate lies within the orthographic projection of the second gate layer on the substrate; preferably, the thin-film transistor further includes a second protrusion made of the same material as the channel portion, the second protrusion being disposed on the surface of the channel portion near the second gate layer; the second gate layer has a cavity, the second protrusion being at least partially located within the cavity of the second gate layer, and the second gate layer and the second protrusion being coupled on at least three sides; preferably, the first gate layer and the second gate layer are electrically connected through vias.

[0006] In one embodiment, the active layer is made of at least one of polycrystalline silicon and indium gallium zinc oxide.

[0007] In one embodiment, the array substrate further includes a first insulating layer and a second insulating layer, the first insulating layer and the second insulating layer being sequentially stacked on one side surface of the substrate in a direction away from the substrate, and the second insulating layer being used to encapsulate the active layer.

[0008] In one embodiment, the array substrate further includes a circuit layer and a planarization layer; the first insulating layer, the second insulating layer, the circuit layer, and the planarization layer are sequentially stacked in a direction away from the substrate; the drain portion, the source portion, and the first gate layer are all electrically connected to the circuit layer; preferably, the circuit layer includes a plurality of stacked dielectric layers and a plurality of signal traces, the dielectric layers being used to isolate the signal traces.

[0009] In one embodiment, the circuit layer includes a drain electrode and a source electrode, wherein the drain electrode corresponds one-to-one with the drain portion, and the source electrode corresponds one-to-one with the source portion. The drain electrode is used to be electrically connected to the corresponding drain portion, and the source electrode is used to be electrically connected to the corresponding source portion. Preferably, the orthographic projection of the drain electrode on the substrate at least partially overlaps with the orthographic projection of the corresponding drain portion on the substrate, and the orthographic projection of the source electrode on the substrate at least partially overlaps with the orthographic projection of the corresponding source portion on the substrate.

[0010] A second aspect of this application provides a method for fabricating an array substrate, comprising: forming a first insulating layer on a substrate; forming a second insulating layer on the first insulating layer and an active layer and a first protrusion within the second insulating layer; wherein the active layer includes a channel portion and a drain portion and a source portion located on both sides of the channel portion; the active layer is made of the same material as the first protrusion, and the first protrusion is disposed on a side surface of the channel portion near the first gate layer; the sum of the thicknesses of the channel portion and the first protrusion in a second direction perpendicular to the substrate is greater than the thicknesses of the drain portion and the source portion; the drain portion, the channel portion, and the source portion are sequentially disposed along a first direction parallel to the substrate, and the orthographic projection of the channel portion on the substrate lies within the orthographic projection of the first gate layer on the substrate; forming a first gate layer on the second insulating layer; wherein the first gate layer has a cavity, the first protrusion is at least partially located within the cavity of the first gate layer, and the first gate layer is coupled to the first protrusion on at least three sides.

[0011] In one embodiment, the fabrication method further includes: forming a second gate layer on the first insulating layer; wherein the second gate layer is located on the side of the active layer away from the first gate layer; the orthographic projection of the channel portion on the substrate is located within the orthographic projection of the second gate layer on the substrate; preferably, forming a second insulating layer on the first insulating layer and an active layer and a first protrusion within the second insulating layer specifically includes: forming a second insulating layer on the first insulating layer and an active layer, a first protrusion and a second protrusion 215 within the second insulating layer; wherein the active layer and the second protrusion are made of the same material, and the second protrusion is disposed on the side surface of the channel portion near the second gate layer; the second gate layer has a cavity, and the second protrusion is at least partially located within the cavity of the second gate layer, and the second gate layer and the second protrusion are coupled on at least three sides.

[0012] A third aspect of this application provides a display panel including the array substrate as described above. Preferably, the display panel further includes a pixel defining layer disposed on one side of the array substrate.

[0013] A fourth aspect of this application provides a display device, including a display panel as described above.

[0014] The beneficial effects of this application embodiment compared with the prior art are as follows: the first protrusion is made of the same material as the channel portion, and the first protrusion is disposed on the side surface of the channel portion near the first gate layer. The first protrusion is in contact with the first gate layer. Therefore, the first protrusion can be regarded as an extension of the channel portion. Through the three-sided coupling of the cavity of the first gate layer and the first protrusion, the coupling area between the first gate layer and the channel portion can be increased, thereby enhancing the leakage current control capability of the thin film transistor. Attached Figure Description

[0015] Figure 1 This is a cross-sectional schematic diagram of an array substrate provided in an embodiment of this application;

[0016] Figure 2 This is another cross-sectional schematic diagram of an array substrate provided in an embodiment of this application;

[0017] Figure 3 A cross-sectional schematic diagram of a display panel provided in an embodiment of this application;

[0018] Figure 4 This is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0019] Figure 5 A flowchart illustrating a method for fabricating an array substrate according to an embodiment of this application;

[0020] Figure 6 A schematic diagram of an electronic device provided in an embodiment of this application.

[0021] Explanation of reference numerals in the attached drawings: 10, array substrate; 20, display panel; 30, display device; 40, electronic device; 41, memory; 42, processor; 43, computer program; 100, substrate; 200, thin-film transistor; 210, active layer; 211, channel portion; 212, drain portion; 213, source portion; 214, first protrusion portion; 215, second protrusion portion; 220, first gate layer; 230, second gate layer; 240, via; 300, first insulating layer; 310, first insulator layer; 320, second insulator layer; 400, second insulating layer; 500, circuit layer; 510, drain electrode; 520, source electrode; 600, planarization layer; 700, pixel defining layer; 800, light-emitting unit; 810, first electrode; 820, light-emitting functional layer; 830, second electrode. Detailed Implementation

[0022] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0023] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0024] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] Active-matrix organic light-emitting diode (AMOLED) screens are widely used in mobile phones, wearable devices, and other products, with AOD (always-on display) functionality becoming a standard feature. In AOD mode, AMOLED screens typically only display clock images or simple dial images, thus allowing the refresh rate to be reduced to 1–15Hz to lower power consumption.

[0027] However, at low refresh rates, the thin film transistors (TFTs) in AMOLED screens remain off for extended periods. When TFTs are off, continuous leakage is likely to occur, causing the gate voltage of the TFTs to become unstable, resulting in noticeable fluctuations in pixel brightness. The human eye will then perceive a significant increase in screen flicker.

[0028] The main solutions currently available are to add switch-controlled thin-film transistors or to use low-temperature polycrystalline oxide (LTPO) technology, both of which aim to reduce leakage current within a frame, but both have some obvious drawbacks.

[0029] Figure 1 A cross-sectional schematic diagram of an array substrate according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0030] An array substrate 10 includes a substrate 100 and a plurality of thin-film transistors 200 located on one side of the substrate 100.

[0031] The substrate 100 can be made of highly transparent glass or a flexible material. In some embodiments, the substrate 100 can be made of glass.

[0032] Understandably, the material of substrate 100 can be set according to actual needs.

[0033] The thin-film transistor 200 includes an active layer 210 and a first gate layer 220. The active layer 210 includes a channel portion 211 and a drain portion 212 and a source portion 213 located on both sides of the channel portion 211.

[0034] In one embodiment, the active layer 210 is made of at least one of polycrystalline silicon and indium gallium zinc oxide.

[0035] Specifically, the active layer 210 can be made of P-type polycrystalline silicon. That is, P-type ions can be implanted into the polycrystalline silicon material to obtain the active layer 210.

[0036] In some embodiments, when the active layer 210 is made of indium gallium zinc oxide (IGZO), the drain portion 212 and the source portion 213 are obtained by conductiveizing the IGZO. The conductiveizing method includes, but is not limited to, any one of plasma treatment, doping, and implantation. The portion that is not conductiveized is the channel portion 211.

[0037] The drain portion 212, the channel portion 211 and the source portion 213 are arranged sequentially along a first direction parallel to the substrate 100, and the orthogonal projection of the channel portion 211 on the substrate 100 is located within the orthogonal projection of the first gate layer 220 on the substrate 100.

[0038] In some embodiments, the orthographic projection of the channel portion 211 on the substrate 100 can completely overlap with the orthographic projection of the first gate layer 220 on the substrate 100.

[0039] In some embodiments, the orthogonal projection of the channel portion 211 onto the substrate 100 may be slightly smaller than the orthogonal projection of the first gate layer 220 onto the substrate 100.

[0040] The thin-film transistor 200 also includes a first protrusion 214 made of the same material as the channel portion 211, the first protrusion 214 being disposed on the side surface of the channel portion 211 near the first gate layer 220.

[0041] The sum of the thicknesses of the channel portion 211 and the first protrusion portion 214 in the second direction perpendicular to the substrate 100 is greater than the thickness of the drain portion 212 and the thickness of the source portion 213; the first gate layer 220 is provided with a cavity, the first protrusion portion 214 is at least partially located in the cavity of the first gate layer 220, and the first gate layer 220 and the first protrusion portion 214 are coupled on at least three sides.

[0042] It is understood that the first protrusion 214 is made of the same material as the channel portion 211, and the first protrusion 214 is disposed on the side surface of the channel portion 211 near the first gate layer 220. The first protrusion 214 is in contact with the first gate layer 220. Therefore, the first protrusion 214 can be regarded as an extension of the channel portion 211. Through the three-sided coupling of the cavity of the first gate layer 220 and the first protrusion 214, the coupling area between the first gate layer 220 and the channel portion 211 can be increased, thereby enhancing the leakage current control capability of the thin film transistor 200.

[0043] It should be noted that by controlling the voltage applied to the first gate layer 220, the turn-on and turn-off of the thin-film transistor 200 can be controlled. When the thin-film transistor 200 is turned off, the coupling area between the first gate layer 220 and the channel portion 211 can be increased through the three-sided coupling of the cavity of the first gate layer 220 and the first protrusion 214, thereby enhancing the control capability of the leakage current of the thin-film transistor 200.

[0044] The thin-film transistor 200 can function as an output transistor to transmit the operating voltage supplied to the light-emitting unit, or as a driver transistor for a gate-in-panel (GIP) circuit to transmit data signals. This application does not limit the specific function of the thin-film transistor 200 or its specific connection to external circuits.

[0045] The active layers 210 of the multiple thin-film transistors 200 can be disposed in the same layer and with the same material, the first protrusions 214 of the multiple thin-film transistors 200 can be disposed in the same layer and with the same material, and the first gate layers 220 of the multiple thin-film transistors 200 can be disposed in the same layer and with the same material, so as to reduce the number of processes and masks required to fabricate the array substrate 10.

[0046] like Figure 1 As shown, in one embodiment, the thin-film transistor 200 further includes a second gate layer 230, which is located on the side of the active layer 210 away from the first gate layer 220. The orthogonal projection of the channel portion 211 on the substrate 100 is within the orthogonal projection of the second gate layer 230 on the substrate 100.

[0047] It should be noted that by controlling the current applied to the second gate layer 230, the turn-on and turn-off of the thin-film transistor 200 can be controlled.

[0048] By having the first gate layer 220 and the second gate layer 230 jointly control the intermediate channel portion 211 (i.e., applying the same voltage to the first gate layer 220 and the second gate layer 230 simultaneously), the coupling area between the first gate layer 220 and the channel portion 211 is increased. By having the first gate layer 220 and the second gate layer 230 surround the channel portion 211 (the first protrusion 214 and the second protrusion 215), the control power of the thin film transistor 200 can be enhanced and the leakage current of the thin film transistor 200 can be reduced.

[0049] Meanwhile, by applying the same electrical signal to the first gate layer 220 and the second gate layer 230, the carrier mobility of the thin film transistor 200 can be greatly improved, the threshold voltage drift problem of the thin film transistor 200 can be solved, and the stability of the electrical performance of the thin film transistor 200 can be improved, thereby improving the stability of the electrical performance of the driving circuit on the array substrate 10.

[0050] The second protrusions 215 of the multiple thin-film transistors 200 can be disposed in the same layer and made of the same material, and the second gate layers 230 of the multiple thin-film transistors 200 can be disposed in the same layer and made of the same material, so as to reduce the number of processes and masks required to fabricate the array substrate 10.

[0051] like Figure 1As shown, in one embodiment, the thin-film transistor 200 further includes a second protrusion 215 made of the same material as the channel portion 211. The second protrusion 215 is disposed on a side surface of the channel portion 211 near the second gate layer 230. The second gate layer 230 has a cavity, and the second protrusion 215 is at least partially located in the cavity of the second gate layer 230. The second gate layer 230 is coupled to the second protrusion 215 on at least three sides.

[0052] It should be noted that by controlling the current applied to the second gate layer 230, the turn-on and turn-off of the thin-film transistor 200 can be controlled. When the thin-film transistor 200 is turned off, the coupling area between the second gate layer 230 and the channel portion 211 can be increased through the three-sided coupling of the cavity of the second gate layer 230 and the second protrusion 215, thereby enhancing the control capability of the leakage current of the thin-film transistor 200.

[0053] like Figure 2 As shown, in one embodiment, the first gate layer 220 and the second gate layer 230 are electrically connected through a via 240.

[0054] By using via 240 to connect the first gate layer 220 and the second gate layer 230, the voltages of the first gate layer 220 and the second gate layer 230 can be kept consistent.

[0055] Meanwhile, the via 240 can control the leakage current on the side of the active layer 210 to a certain extent.

[0056] In one embodiment, the active layer 210 is made of at least one of polycrystalline silicon and indium gallium zinc oxide.

[0057] Specifically, the active layer 210 can be made of P-type polycrystalline silicon. That is, P-type ions can be implanted into the polycrystalline silicon material to obtain the active layer 210.

[0058] In some embodiments, when the active layer 210 is made of indium gallium zinc oxide (IGZO), the drain portion 212 and the source portion 213 are obtained by conductiveizing the IGZO. The conductiveizing method includes, but is not limited to, any one of plasma treatment, doping, and implantation. The portion that is not conductiveized is the channel portion 211.

[0059] like Figure 2 As shown, in one embodiment, the array substrate 10 further includes a first insulating layer 300 and a second insulating layer 400. The first insulating layer 300 and the second insulating layer 400 are sequentially stacked on one side surface of the substrate 100 along a direction away from the substrate 100. The second insulating layer 400 is used to encapsulate the active layer 210.

[0060] The second gate layer 230 may be disposed between the first insulating layer 300 and the second insulating layer 400, and the first gate layer 220 may be disposed on the side surface of the second insulating layer 400 away from the substrate 100.

[0061] The second insulating layer 400 is used to isolate the active layer 210 from the first gate layer 220 and the second gate layer 230. The first insulating layer 300 is used to isolate the second gate layer 230 from the substrate 100.

[0062] In some embodiments, the material of the first insulating layer 300 may be at least one of dielectric materials such as silicon oxide, silicon nitride, hafnium oxide, and aluminum oxide. The material of the second insulating layer 400 may be at least one of dielectric materials such as silicon oxide, silicon nitride, hafnium oxide, and aluminum oxide.

[0063] In some embodiments, the first insulating layer 300 includes a first insulator layer 310 and a second insulator layer 320, which are sequentially stacked on one side surface of the substrate 100 in a direction away from the substrate 100.

[0064] The materials of the first insulator layer 310 and the second insulator layer 320 can be the same or different, depending on the actual needs.

[0065] For example, the material of the first insulator layer 310 and the material of the second insulator layer 320 can be silicon oxide and silicon nitride, or both the material of the first insulator layer 310 and the material of the second insulator layer 320 can be silicon oxide or silicon nitride.

[0066] In some embodiments, the material of the first gate layer 220 can be at least one of titanium, aluminum, nickel, molybdenum, copper, gold, etc., and the thickness of the first gate layer 220 can be 10nm-30nm.

[0067] The material of the second gate layer 230 can be at least one of ITO, titanium, aluminum, nickel, molybdenum, copper, gold, etc., and the thickness of the second gate layer 230 can be 10nm-30nm.

[0068] For example, in one embodiment, the thickness of the first gate layer 220 can be 20 nm, and the thickness of the second gate layer 230 can be 20 nm.

[0069] Specifically, the first insulating layer 300 and the second insulating layer 400 can be formed using chemical vapor deposition or atomic layer deposition.

[0070] Specifically, the first gate layer 220 and the second gate layer 230 can be formed by magnetron sputtering or electron beam evaporation.

[0071] It should be noted that the first gate layer 220 and the second gate layer 230 can be obtained by first forming a metal layer and then etching the metal layer.

[0072] like Figure 2 As shown, in one embodiment, the array substrate 10 further includes a circuit layer 500 and a planarization layer 600.

[0073] The first insulating layer 300, the second insulating layer 400, the circuit layer 500 and the planarization layer 600 are stacked sequentially in a direction away from the substrate 100; the drain portion 212, the source portion 213 and the first gate layer 220 are all electrically connected to the circuit layer 500.

[0074] Preferably, the circuit layer 500 includes multiple stacked dielectric layers and multiple signal traces, with the dielectric layers used to isolate the signal traces.

[0075] It is understandable that signal traces can be used to achieve electrical connections between thin-film transistors 200, between thin-film transistors 200 and external circuits, or between thin-film transistors 200 and light-emitting units. The number of dielectric layers, the number of signal traces, and the arrangement of signal traces can be set according to actual needs.

[0076] By electrically connecting multiple thin-film transistors 200 to each other, certain control logic can be implemented to control the light-emitting unit based on signals and voltages provided by external circuits.

[0077] For example, by using a driving circuit consisting of multiple thin-film transistors 200 and multiple signal lines, the driving voltage supplied to each light-emitting unit can be controlled, thereby controlling the on / off state of each light-emitting unit.

[0078] In some embodiments, signal traces include clock traces, high-level traces, and low-level traces.

[0079] Clock traces can be used to transmit clock signals, high-level traces can be used to transmit high-level signals, and low-level traces can be used to transmit low-level signals.

[0080] like Figure 2 As shown, in one embodiment, the circuit layer 500 includes a drain electrode 510 and a source electrode 520. The drain electrode 510 corresponds to the drain portion 212, and the source electrode 520 corresponds to the source portion 213. The drain electrode 510 is used to be electrically connected to the drain portion 212, and the source electrode 520 is used to be electrically connected to the source portion 213.

[0081] Preferably, the orthographic projection of the drain electrode 510 on the substrate 100 at least partially overlaps with the orthographic projection of the corresponding drain portion 212 on the substrate 100, and the orthographic projection of the source electrode 520 on the substrate 100 at least partially overlaps with the orthographic projection of the corresponding source portion 213 on the substrate 100.

[0082] The number and position of the drain electrode 510 and the source electrode 520 can be determined based on the number and position of the thin-film transistors 200.

[0083] Specifically, the drain electrode 510 can be electrically connected to the corresponding drain portion 212 through the corresponding through hole, and the source electrode 520 can be electrically connected to the corresponding source portion 213 through the corresponding through hole.

[0084] Understandably, the vias can further limit leakage current on the side of the active layer 210.

[0085] Figure 3 A cross-sectional schematic diagram of a display panel according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0086] A display panel 20 includes an array substrate 10 as described in any of the above embodiments. Specifically, the display panel 20 may be an AMOLED panel or other OLED panels.

[0087] The display panel 20 may include a plurality of light-emitting units disposed on the array substrate 10.

[0088] like Figure 1 , Figure 2 As shown, the array substrate 10 includes a substrate 100 and a plurality of thin-film transistors 200 located on one side of the substrate 100.

[0089] The substrate 100 can be made of highly transparent glass or a flexible material. In some embodiments, the substrate 100 can be made of glass.

[0090] The thin-film transistor 200 includes an active layer 210 and a first gate layer 220. The active layer 210 includes a channel portion 211 and a drain portion 212 and a source portion 213 located on both sides of the channel portion 211.

[0091] The drain portion 212, the channel portion 211 and the source portion 213 are arranged sequentially along a first direction parallel to the substrate 100, and the orthogonal projection of the channel portion 211 on the substrate 100 is within the orthogonal projection of the first gate layer 220 on the substrate 100.

[0092] The thin-film transistor 200 also includes a first protrusion 214 made of the same material as the channel portion 211, the first protrusion 214 being disposed on the side surface of the channel portion 211 near the first gate layer 220.

[0093] The sum of the thicknesses of the channel portion 211 and the first protrusion portion 214 in the second direction perpendicular to the substrate 100 is greater than the thickness of the drain portion 212 and the thickness of the source portion 213; the first gate layer 220 is provided with a cavity, the first protrusion portion 214 is at least partially located in the cavity of the first gate layer 220, and the first gate layer 220 and the first protrusion portion 214 are coupled on at least three sides.

[0094] It is understood that the first protrusion 214 is made of the same material as the channel portion 211, and the first protrusion 214 is disposed on the side surface of the channel portion 211 near the first gate layer 220. The first protrusion 214 is in contact with the first gate layer 220. Therefore, the first protrusion 214 can be regarded as an extension of the channel portion 211. Through the three-sided coupling of the cavity of the first gate layer 220 and the first protrusion 214, the coupling area between the first gate layer 220 and the channel portion 211 can be increased, thereby enhancing the leakage current control capability of the thin film transistor 200.

[0095] like Figure 3 As shown, in one embodiment, the display panel 20 further includes a pixel defining layer 700, which is disposed on one side of the array substrate 10.

[0096] Specifically, the pixel defining layer 700 is disposed on the side surface of the planarization layer 600 away from the substrate 100.

[0097] The pixel defining layer 700 defines a plurality of pixel openings, and a light-emitting unit 800 is formed in each pixel opening. The light-emitting unit 800 includes a first electrode 810, a light-emitting functional layer 820 and a second electrode 830 stacked sequentially in a direction away from the substrate 100.

[0098] The first electrode 810 and the second electrode 830 can be electrically connected to the array substrate 10 to obtain a driving voltage.

[0099] For example, one of the first electrode 810 and the second electrode 830 is an anode, and the other is a cathode. For instance, the first electrode 810 is an anode, and the second electrode 830 is a cathode.

[0100] The first electrode 810 can be electrically connected to the source electrode 520 or the drain electrode 510 of the thin-film transistor 200 through a corresponding via.

[0101] In some embodiments, the display panel 20 may specifically be a low-temperature polyoxide (LTPO) display panel. Compared to low-temperature polysilicon (LTPS) display panels, low-temperature polyoxide (LTPO) display panels have the advantages of low power consumption and good low-frequency display performance.

[0102] Figure 4 A schematic diagram of the structure of a display device 30 according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0103] A display device 30, wherein the display panel 20 of the display device 30 may be a display panel 20 as described in any of the above embodiments.

[0104] The display panel 20 may specifically be a low-temperature polycrystalline oxide (LTPO) display panel 20.

[0105] Since the display device 30 includes the display panel 20 of any of the above embodiments, the display device 30 has the beneficial effects of the display panel 20 of any of the above embodiments, which will not be described again here.

[0106] The display device 30 in this application embodiment includes, but is not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0107] Figure 5 A flowchart of a method for fabricating an array substrate according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0108] The preparation method is used to prepare the array substrate 10 shown in the figure.

[0109] The preparation method includes steps S100 to S300.

[0110] Step S100: Form a first insulating layer 300 on the substrate 100.

[0111] Step S200: Form a second insulating layer 400 on the first insulating layer 300, and an active layer 210 and a first protrusion 214 within the second insulating layer 400.

[0112] The active layer 210 includes a channel portion 211 and a drain portion 212 and a source portion 213 located on both sides of the channel portion 211. The active layer 210 is made of the same material as the first protrusion portion 214, which is disposed on the side surface of the channel portion 211 near the first gate layer 220. The sum of the thicknesses of the channel portion 211 and the first protrusion portion 214 in a second direction perpendicular to the substrate 100 is greater than the thicknesses of the drain portion 212 and the source portion 213. The drain portion 212, the channel portion 211, and the source portion 213 are arranged sequentially along a first direction parallel to the substrate 100, and the orthographic projection of the channel portion 211 on the substrate 100 is within the orthographic projection of the first gate layer 220 on the substrate 100.

[0113] Step S300: A first gate layer 220 is formed on the second insulating layer 400.

[0114] The first gate layer 220 has a cavity, and the first protrusion 214 is at least partially located in the cavity of the first gate layer 220. The first gate layer 220 and the first protrusion 214 are coupled on at least three sides.

[0115] In some embodiments, step S200 specifically includes: forming a second insulating layer 400 located on the first insulating layer 300 and an active layer 210, a first protrusion 214 and a second protrusion 215 located within the second insulating layer 400.

[0116] The active layer 210 is made of the same material as the second protrusion 215, and the second protrusion 215 is disposed on the side surface of the channel portion 211 near the second gate layer 230.

[0117] The second gate layer 230 has a cavity, and the second protrusion 215 is at least partially located in the cavity of the second gate layer 230. The second gate layer 230 and the second protrusion 215 are coupled on at least three sides.

[0118] It should be noted that, in order to construct the second gate layer 230 with a cavity, the bottom and sidewalls of the second gate layer 230 can be constructed using two masks respectively.

[0119] Alternatively, the metal layer can be formed first and then etched. This application does not limit the specific construction process of the second gate layer 230.

[0120] Specifically, the first insulating layer 300 can be formed using chemical vapor deposition or atomic layer deposition. The second gate layer 230 can be formed using magnetron sputtering or electron beam evaporation.

[0121] The specific process to be used can be set according to actual needs.

[0122] Since the active layer 210, the first protrusion 214, and the second protrusion 215 are located in different film layers, the second protrusion 215, the active layer 210, and the first protrusion 214 can be constructed sequentially using a triple photomask. The materials used to construct the second protrusion 215, the active layer 210, and the first protrusion 214 are the same.

[0123] Correspondingly, the second insulating layer 400 can also be constructed in three parts using a three-stage photomask. Alternatively, the second insulating layer 400 on the same layer as the second protrusion 215 and the second insulating layer 400 on the same layer as the active layer 210 can be constructed using only two photomasks. The second insulating layer 400 corresponding to the first protrusion 214 can be constructed by conformal covering, covering the surface of the first protrusion 214 and the surface of the active layer 210.

[0124] It should be noted that in step S200, the insulating material used to construct the second insulating layer 400 can be deposited first, and then patterned and etched before being filled with semiconductor material to construct the second insulating layer 400, the active layer 210, the first protrusion 214, and the second protrusion 215. That is, the construction is performed in the following order: the second insulating layer 400 is on the same layer as the second protrusion 215, the second insulating layer 400 is on the same layer as the active layer 210, the active layer 210, the second insulating layer 400 is on the same layer as the first protrusion 214, the first protrusion 214, and the second insulating layer 400 covering the first protrusion 214.

[0125] Alternatively, it can be constructed in the following order: second protrusion 215, second insulating layer 400 on the same layer as the second protrusion 215, active layer 210, second insulating layer 400 on the same layer as the active layer 210, first protrusion 214, second insulating layer 400 on the same layer as the first protrusion 214, and second insulating layer 400 covering the first protrusion 214.

[0126] The specific construction order can be set according to actual needs.

[0127] To construct the first gate layer 220 with a cavity, specifically, the first gate layer 220 can be constructed by first etching the second insulating layer 400 according to the shape of the first gate layer 220, and then by depositing and filling metal material.

[0128] Alternatively, the first gate layer 220 can be formed by conformally covering the raised second insulating layer 400.

[0129] It is understood that the first protrusion 214 is made of the same material as the channel portion 211, and the first protrusion 214 is disposed on the side surface of the channel portion 211 near the first gate layer 220. The first protrusion 214 is in contact with the first gate layer 220. Therefore, the first protrusion 214 can be regarded as an extension of the channel portion 211. Through the three-sided coupling of the cavity of the first gate layer 220 and the first protrusion 214, the coupling area between the first gate layer 220 and the channel portion 211 can be increased, thereby enhancing the leakage current control capability of the thin film transistor 200.

[0130] It should be noted that by controlling the voltage applied to the first gate layer 220, the turn-on and turn-off of the thin-film transistor 200 can be controlled. When the thin-film transistor 200 is turned off, the coupling area between the first gate layer 220 and the channel portion 211 can be increased through the three-sided coupling of the cavity of the first gate layer 220 and the first protrusion 214, thereby enhancing the control capability of the leakage current of the thin-film transistor 200.

[0131] Figure 6 A schematic diagram of an electronic device according to an embodiment of this application is shown. For ease of explanation, only the parts related to this embodiment are shown, and the details are as follows:

[0132] An electronic device 40 includes a memory 41, a processor 42, and a computer program 43 stored in the memory 41 and executable on the processor 42. When the processor 42 executes the computer program 43, it implements the method for fabricating the array substrate 10 as described in any of the above embodiments.

[0133] The processor 42 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or the processor 42 may be any conventional processor.

[0134] In some embodiments, memory 41 may be an internal storage unit of electronic device 40, such as a hard disk or memory of electronic device 40. In other embodiments, memory 41 may be an external storage device of electronic device 40, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on electronic device 40. Furthermore, memory 41 may include both internal and external storage units of electronic device 40. Memory 41 is used to store operating system, application programs, bootloader, data, and other programs, such as the program code of computer program 43. Memory 41 may also be used to temporarily store data that has been output or will be output.

[0135] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0136] From the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0137] It should be understood that the apparatuses and methods disclosed in the several embodiments provided in this application can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components being combined or integrated into another device. In addition, some features may be omitted or not performed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0138] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units. That is, it can be located in one place or distributed in multiple different locations. Depending on the actual needs, some or all of the units can be selected to achieve the purpose of this solution.

[0139] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit; they can also exist physically separately; or some units can be integrated into one unit while others exist physically separately. The integrated units described above can be implemented in hardware or as software functional units.

[0140] It should be noted that all or part of the above embodiments provided in this application (e.g., part or all of any feature) can be arbitrarily combined or combined with each other.

[0141] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate (10), characterized in that, include: Substrate (100); A plurality of thin-film transistors (200) are located on one side of the substrate (100). The thin-film transistors (200) include an active layer (210) and a first gate layer (220). The active layer (210) includes a channel portion (211) and a drain portion (212) and a source portion (213) located on both sides of the channel portion (211). The drain portion (212), the channel portion (211), and the source portion (213) are arranged sequentially along a first direction parallel to the substrate (100), and the orthographic projection of the channel portion (211) on the substrate (100) is within the orthographic projection of the first gate layer (220) on the substrate (100); The thin-film transistor (200) further includes a first protrusion (214) made of the same material as the channel portion (211), the first protrusion (214) being disposed on the side surface of the channel portion (211) near the first gate layer (220); The sum of the thicknesses of the channel portion (211) and the first protrusion portion (214) in a second direction perpendicular to the substrate (100) is greater than the thickness of the drain portion (212) and the thickness of the source portion (213); The first gate layer (220) has a cavity, and the first protrusion (214) is at least partially located in the cavity of the first gate layer (220). The first gate layer (220) and the first protrusion (214) are coupled on at least three sides.

2. The array substrate (10) as claimed in claim 1, characterized in that, The thin-film transistor (200) further includes a second gate layer (230), which is located on the side of the active layer (210) away from the first gate layer (220); The orthographic projection of the channel portion (211) on the substrate (100) lies within the orthographic projection of the second gate layer (230) on the substrate (100); Preferably, the thin-film transistor (200) further includes a second protrusion (215) made of the same material as the channel portion (211), the second protrusion (215) being disposed on the side surface of the channel portion (211) near the second gate layer (230); The second gate layer (230) has a cavity, and the second protrusion (215) is at least partially located in the cavity of the second gate layer (230). The second gate layer (230) and the second protrusion (215) are coupled on at least three sides. Preferably, the first gate layer (220) and the second gate layer (230) are electrically connected through a via.

3. The array substrate (10) as described in claim 1, characterized in that, The active layer (210) is made of at least one of polycrystalline silicon and indium gallium zinc oxide.

4. The array substrate (10) as claimed in claim 1, characterized in that, The array substrate (10) further includes a first insulating layer (300) and a second insulating layer (400). The first insulating layer (300) and the second insulating layer (400) are sequentially stacked on one side surface of the substrate (100) in a direction away from the substrate (100). The second insulating layer (400) is used to wrap the active layer (210).

5. The array substrate (10) as described in claim 4, characterized in that, The array substrate (10) further includes a circuit layer (500) and a planarization layer (600); The first insulating layer (300), the second insulating layer (400), the circuit layer (500) and the planarization layer (600) are stacked sequentially in a direction away from the substrate (100); The drain portion (212), the source portion (213), and the first gate layer (220) are all electrically connected to the circuit layer (500); Preferably, the circuit layer (500) includes a plurality of stacked dielectric layers and a plurality of signal traces, wherein the dielectric layers are used to isolate the signal traces.

6. The array substrate (10) as described in claim 5, characterized in that, The circuit layer (500) includes a drain electrode (510) and a source electrode (520). The drain electrode (510) corresponds one-to-one with the drain portion (212), and the source electrode (520) corresponds one-to-one with the source portion (213). The drain electrode (510) is used to be electrically connected to the corresponding drain portion (212), and the source electrode (520) is used to be electrically connected to the corresponding source portion (213). Preferably, the orthographic projection of the drain electrode (510) on the substrate (100) at least partially overlaps with the orthographic projection of the corresponding drain portion (212) on the substrate (100), and the orthographic projection of the source electrode (520) on the substrate (100) at least partially overlaps with the orthographic projection of the corresponding source portion (213) on the substrate (100).

7. A method for fabricating an array substrate (10), characterized in that, include: A first insulating layer (300) is formed on the substrate (100); A second insulating layer (400) is formed on the first insulating layer (300), and an active layer (210) and a first protrusion (214) are formed within the second insulating layer (400); A first gate layer (220) is formed on the second insulating layer (400); The active layer (210) includes a channel portion (211) and a drain portion (212) and a source portion (213) located on both sides of the channel portion (211); the active layer (210) is made of the same material as the first protrusion (214), and the first protrusion (214) is disposed on the surface of the channel portion (211) near the first gate layer (220); the channel portion (211) and the first protrusion (214) are perpendicular to the... The sum of the thicknesses of the substrate (100) in the second direction is greater than the thickness of the drain portion (212) and the thickness of the source portion (213); the drain portion (212), the channel portion (211) and the source portion (213) are arranged sequentially along a first direction parallel to the substrate (100), and the orthographic projection of the channel portion (211) on the substrate (100) is within the orthographic projection of the first gate layer (220) on the substrate (100); The first gate layer (220) has a cavity, and the first protrusion (214) is at least partially located in the cavity of the first gate layer (220). The first gate layer (220) and the first protrusion (214) are coupled on at least three sides.

8. The preparation method according to claim 7, characterized in that, The preparation method further includes: A second gate layer (230) is formed on the first insulating layer (300); The second gate layer (230) is located on the side of the active layer (210) away from the first gate layer (220); The orthographic projection of the channel portion (211) on the substrate (100) lies within the orthographic projection of the second gate layer (230) on the substrate (100); Preferably, the formation of a second insulating layer (400) on the first insulating layer (300) and an active layer (210) and a first protrusion (214) within the second insulating layer (400) specifically includes: A second insulating layer (400) is formed on the first insulating layer (300), and an active layer (210), a first protrusion (214), and a second protrusion (215) are formed within the second insulating layer (400); The active layer (210) is made of the same material as the second protrusion (215), and the second protrusion (215) is disposed on the side surface of the channel portion (211) near the second gate layer (230). The second gate layer (230) has a cavity, and the second protrusion (215) is at least partially located in the cavity of the second gate layer (230). The second gate layer (230) and the second protrusion (215) are coupled on at least three sides.

9. A display panel (20), characterized in that, Includes the array substrate (10) as described in any one of claims 1-6; Preferably, the display panel (20) further includes a pixel defining layer (700) disposed on one side of the array substrate (10).

10. A display device (30), characterized in that, include: The display panel (20) as described in claim 9.

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