Array substrate, manufacturing method thereof, electronic paper display module and electronic paper display device

Abstract

The application provides an array substrate and a preparation method, an electronic paper display module and an electronic paper display device. The array substrate comprises a substrate, a plurality of gate lines, a plurality of data lines and a plurality of pixel units arranged on the substrate. Each adjacent two gate lines and each adjacent two data lines cross to define a plurality of array-arranged pixel units. The orthogonal projection of the gate lines and the data lines on the substrate forms a first overlapping area. The pixel unit comprises a thin film transistor, and the thin film transistor comprises a gate layer. The orthogonal projection of the gate layer on the substrate overlaps the first overlapping area. The length direction of the gate layer is parallel to the length direction of the gate line, and the length of the gate layer is greater than the width of the gate layer. The array substrate of the application is beneficial to reducing the overlapping area between the gate layer and the drain layer, thereby being beneficial to reducing the parasitic capacitance between the gate layer and the drain layer and avoiding the overlapping capacitance between the gate layer and the pixel electrode, and further improving the working efficiency of the electronic paper product, and further being beneficial to improving the yield of the display module and the product competitiveness.

Description

Technical Field

[0001] This invention generally relates to the field of display technology, and specifically to an array substrate and its preparation method, an electronic paper display module, and an electronic paper display device. Background Technology

[0002] EPD (Electronic Paper Display) products have an absolute advantage in the field of low power consumption. However, in conventional electronic paper structures, the parasitic capacitance between the gate and drain layers is large, as is the parasitic capacitance between the pixel electrode and the gate, which results in a large load and affects the working efficiency of electronic products. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide an array substrate and its preparation method, an electronic paper display module and an electronic paper display device, which can help reduce the overlap area between the gate layer and the drain layer, as well as the overlap area between the gate layer and the pixel electrode, thereby helping to reduce the parasitic capacitance between the gate layer and the drain layer, and the overlap area between the gate layer and the pixel electrode, thereby improving the working efficiency of electronic paper products and improving the yield rate and product competitiveness of display modules.

[0004] In a first aspect, the present invention provides an array substrate, comprising: a substrate, wherein multiple gate lines, multiple data lines and multiple pixel units are disposed on the substrate, wherein each pair of adjacent gate lines and each pair of adjacent data lines intersect to define the multiple pixel units arranged in an array, the orthographic projections of the gate lines and data lines on the substrate respectively form a first overlapping region, the pixel unit includes a thin-film transistor, the thin-film transistor includes a gate layer, the orthographic projection of the gate layer on the substrate overlaps with the first overlapping region, the length direction of the gate layer is parallel to the length direction of the gate lines, and the length of the gate layer is greater than the width of the gate layer; wherein the length direction of the gate layer refers to the current conduction direction in the thin-film transistor.

[0005] As an optional solution, the gate layer and the gate line are set on the same layer.

[0006] As an optional solution, the thin-film transistor also includes a source layer, a drain layer, and an active layer. One end of the drain layer is connected to the active layer, and one end of the source layer is connected to the active layer. The other end of one of the source layer and the drain layer is connected to a data line. The active layer is located on one side of the gate layer and includes a channel region. A vacancy region is formed in a portion of the gate layer corresponding to the periphery of the channel region. The vacancy region is located at least on the side of the gate layer near the drain layer.

[0007] As an optional solution, the vacant area is set around the perimeter of the trench area.

[0008] As an alternative, the vacancy region is located at the four corners of the gate layer near the channel region.

[0009] As an optional solution, a dielectric layer is disposed between the active layer and the gate layer, and the vacant region is filled with the dielectric layer.

[0010] As an optional solution, the pixel unit also includes a pixel electrode, wherein the orthographic projection of the gate layer on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate.

[0011] As an optional solution, the array substrate also includes a common electrode and a common voltage signal line connected to the common electrode, wherein the orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.

[0012] As an alternative, the orthogonal projection of the pixel electrode on the substrate completely covers the orthogonal projection of the common electrode on the substrate.

[0013] Secondly, the present invention provides a method for fabricating an array substrate according to the first aspect, specifically comprising the following steps:

[0014] Provide substrate,

[0015] Multiple gate lines, multiple data lines, and pixel units are formed on a substrate. Each pair of adjacent gate lines and each pair of adjacent data lines intersects to define multiple pixel units arranged in an array. Each pixel unit includes a thin-film transistor (TFT), and the TFT includes a gate layer. The orthographic projection of the gate layer on the substrate is located at the intersection of the orthographic projections of the gate lines and data lines on the substrate. The length direction of the gate layer is parallel to the length direction of the gate lines, and the length of the gate layer is greater than the width of the gate layer. The length direction of the gate layer refers to the direction of current conduction in the TFT.

[0016] As an optional approach, forming pixel units includes:

[0017] A void region is formed by hollowing out a portion of the area around the channel region corresponding to the gate layer along a direction perpendicular to the substrate. The void region is located at least on the side closest to the drain layer.

[0018] Thirdly, the present invention provides an electronic paper display module, including an array substrate as described in the first aspect.

[0019] Fourthly, the present invention provides an electronic paper display device, including the electronic paper display module of the third aspect.

[0020] The array substrate of the present invention, by adjusting the arrangement of thin-film transistors, ensures that the orthographic projection of the gate layer of the thin-film transistor on the substrate overlaps with the first overlap area formed by the orthographic projections of the gate line and data line on the substrate, and that the length direction of the gate layer is parallel to the length direction of the gate line, and the length of the gate layer is greater than the width of the gate layer. This reduces the overlap capacitance between the gate line and data line, and the overlap capacitance between the gate layer and the drain layer, to the overlap capacitance between the gate line and data line, reliably reducing the overlap area between the gate layer and the drain layer, thereby reducing the parasitic capacitance between the gate layer and the drain layer. Furthermore, the parallel extension direction of the gate layer to the extension direction of the gate line also reduces the overlap area between the pixel electrode and the gate layer, avoiding the top-gate effect, thereby reducing the leakage current of the thin-film transistor, improving the quality and efficiency of the array substrate, and further improving the yield and competitiveness of display products. Attached Figure Description

[0021] Other features, objectives, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0022] Figure 1 This is a schematic diagram of the structure of an existing array substrate;

[0023] Figure 2 This is a schematic diagram of the structure of an array substrate according to an embodiment of this application;

[0024] Figure 3 for Figure 2 Sectional view of AA in the middle;

[0025] Figure 4 This is a schematic layout diagram of an array substrate according to an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of another array substrate structure according to an embodiment of this application;

[0027] Figure 6 for Figure 5 Sectional view of AA in the middle;

[0028] Figure 7 This is a schematic layout diagram of another array substrate according to an embodiment of this application;

[0029] Figure 8 This is a schematic diagram of the structure of an electronic paper display module according to an embodiment of this application.

[0030] In the picture,

[0031] 100. Array substrate;

[0032] 10. Substrate; 20. Gate line; 30. Data line; 40. Pixel unit; A1. First overlapping area;

[0033] 50. Gate layer, 51. Source layer, 52. Drain layer, 53. Channel region, 54. Vacant region, 55. Dielectric layer;

[0034] 60. Pixel electrode; 70. Common electrode; 71. Common voltage signal line;

[0035] 200, Electronic paper display module; 300, Opposite substrate; 400, Electronic ink thin film layer. Detailed Implementation

[0036] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] In the structural design of pixel units in conventional electronic paper products, the gate layer 50 typically adopts a rectangular structure. To accommodate the on-state current of the thin-film transistor and reduce the off-state leakage current, the orthogonal projection of the gate layer 50 onto the substrate 10 usually completely surrounds the orthogonal projection of the channel region 53 of the thin-film transistor onto the substrate 10. However, this structural design increases the overlap area between the gate layer 50 and the drain layer 52, thereby increasing the overlap capacitance (Cgd) between the gate layer 50 and the drain layer 52. Furthermore, the current gate layer 50 is typically positioned perpendicular to the gate line 20, such as... Figure 1 As shown, the overlap area between the gate layer 50 and the pixel electrode 60 is increased (as shown in regions 1 and 2 in the figure), which leads to an increase in the overlap capacitance (Cpg) between the gate layer 50 and the pixel electrode 60. At the same time, the gate layer 50 is located below the pixel electrode 60, which forms a top gate structure and causes excessive leakage current.

[0039] Based on the above problems, in a first aspect, embodiments of this application provide an array substrate 100. By changing the position of the gate layer 50, the orthographic projection of the gate layer 50 on the substrate 10 is located in the first overlap region A1 formed by the orthographic projections of the gate line 20 and the data line 30 on the substrate 10, and the length direction of the gate layer 50 is parallel to the length direction of the gate line 20. In this way, on the one hand, it is beneficial to reduce the overlap capacitance between the gate layer 50 and the drain layer 52. On the other hand, the overlap between the orthographic projection of the gate layer 50 and the orthographic projections of the gate line 20 and the data line 30 on the substrate 10 also helps to reduce the overlap capacitance between the gate layer 50 and the pixel electrode 60, and avoids the formation of a top gate structure, which would cause excessive leakage current.

[0040] Specifically, such as Figure 2-4 As shown, an array substrate according to an embodiment of this application includes: a substrate 10, on which multiple gate lines 20, multiple data lines 30 and multiple pixel units 40 are disposed. Each pair of adjacent gate lines 20 and each pair of adjacent data lines 30 intersect to define the multiple pixel units 40 arranged in an array. The orthographic projections of the gate lines 20 and data lines 30 on the substrate 10 respectively form a first overlapping region A1. The pixel unit 40 includes a thin film transistor, and the thin film transistor includes a gate layer 50. The orthographic projection of the gate layer 50 on the substrate 10 overlaps with the first overlapping region A1. The length direction of the gate layer 50 is parallel to the length direction of the gate lines 20, and the length of the gate layer 50 is greater than the width of the gate layer 50. The length direction of the gate layer 50 refers to the current conduction direction in the thin film transistor, which can also be understood as the direction from the source layer 51 to the drain layer 52.

[0041] It should be noted that the substrate 10 has a display area and a non-display area located outside the display area. Multiple gate lines 20 are disposed on one side of the substrate 10 and located in the display area, and multiple data lines 30 are disposed on the side of the multiple gate lines 20 away from the substrate and located in the display area. A pixel area is defined between every two adjacent gate lines 20 and every two adjacent data lines 30, and a common electrode 70 and a pixel electrode 60 are disposed within the pixel area.

[0042] For example, multiple gate lines 20 can be arranged at intervals along a first direction, and each gate line 20 can extend along a second direction perpendicular to the first direction. Multiple data lines 30 can be arranged at intervals along the second direction, and each data line 30 can extend along the first direction. The multiple gate lines 20 and multiple data lines 30 can intersect each other, thereby defining multiple pixel regions. Pixel units 40 can be respectively provided in each pixel region. The multiple pixel units 40 can be arranged in an array, with the row direction of the multiple pixel units 40 being the second direction and the column direction of the multiple sub-pixel units 40 being the first direction. Each gate line 20 can be connected to a row of pixel units 40 for transmitting scan signals to the corresponding row of pixel units 40; each data line 30 can be connected to a column of pixel units 40 for transmitting data signals to the corresponding column of pixel units 40. Each pixel unit 40 may include a thin film transistor (TFT) and a pixel electrode 60. The drain layer 52 (or source layer 51) of the TFT may be electrically connected to the pixel electrode 60, the source layer 51 (or drain layer 52) of the TFT may be connected to the data line 30, and the gate of the TFT may be connected to the gate line 20.

[0043] It is understood that the orthogonal projections of the gate line 20 and the data line 30 on the substrate 10 form a first overlapping region A1. The gate layer 50 is disposed on the substrate 10. The overlap between the orthogonal projection of the gate layer 50 on the substrate 10 and the first overlapping region A1 can be either that the orthogonal projection of the gate layer 50 on the substrate 10 is located inside the first overlapping region A1, or that the orthogonal projection of the gate layer 50 on the substrate 10 is located completely overlapping with the first overlapping region A1. Of course, in some embodiments, the orthogonal projection of the gate layer 50 on the substrate 10 can also partially overlap with the first overlapping region A1 and partially be located outside the first overlapping region A1. In actual processing, the size of the channel region 53 is determined according to the size of the channel region 53. As long as the orthogonal projection of the gate layer 50 on the substrate 10 has a suitable wrapping distance with the orthogonal projection of the channel region 53 on the substrate 10, it is acceptable.

[0044] It can also be understood that the length direction of the gate layer 50 refers to the direction of current conduction in the thin-film transistor, that is, the direction parallel to the source layer 51 to the drain layer 52 (e.g., Figure 2 If the length direction of the gate layer 50 is parallel to the length direction of the gate line 20 (in the X direction), then the extension direction of the gate layer 50 is parallel to the row direction of the multiple pixel units 40. This helps to minimize the overlap area of ​​the gate layer 50 and the pixel electrode 60 projected onto the substrate 10, thereby reducing the overlap capacitance between the gate layer 50 and the pixel electrode 60 and avoiding the top gate effect. The width of the gate layer 50 refers to the dimension of the gate layer 50 in the direction perpendicular to its length.

[0045] In order to ensure that the thin-film transistor can drive the pixel unit 40 normally, the length L of the channel region 53 should be as short as possible to reduce the short-channel effect. However, the design of the length L of the channel region 53 should be matched with the manufacturing process to avoid excessive leakage current due to excessive length. The width W of the channel region 53 should be selected according to the current driving capability and device size. However, the channel width should be matched with the gate layer 50 wrapping depth to ensure good gate layer 50 control and device performance. Under the condition that the W / L meets the product design performance requirements, the corresponding distance of the gate layer 50 surrounding the channel region 53 is specifically SQRT(Gate Overlay^2 + Channel Dielectric Layer 55 Overlay^2 + (Gate CD Tolerance / 2)^2 + (Channel Dielectric Layer 55 CD Tolerance / 2)^2); where, Gate Overlay refers to the alignment deviation of the gate during the photolithography process; Channel Dielectric Layer 55 Overlay refers to the alignment deviation of the channel dielectric layer 55 during the photolithography process; Gate CD Tolerance refers to the critical dimensional tolerance of the gate; and Channel Dielectric Layer 55 CD Tolerance refers to the critical dimensional tolerance of the channel dielectric layer 55.

[0046] In a preferred embodiment, the orthogonal projection of the gate layer 50 onto the substrate 10 is located within the first overlapping region A1, which helps to reliably reduce the overlapping capacitance between the gate layer 50 and the drain layer 52, as well as the overlapping capacitance between the gate layer 50 and the pixel electrode 60.

[0047] The array substrate of the embodiments of this application solves the problem of large pixel load in electronic paper products in the prior art. The array substrate of this application, by adjusting the arrangement of thin-film transistors, ensures that the orthographic projection of the gate layer 50 of the thin-film transistor on the substrate 10 overlaps with the first overlap region A1 formed by the orthographic projections of the gate line 20 and the data line 30 on the substrate 10, and that the length direction of the gate layer 50 is parallel to the length direction of the gate line 20, and the length of the gate layer is greater than the width of the gate layer 50. This reduces the overlap capacitance of the gate line 20 and the data line 30, and the overlap capacitance of the gate layer 50 and the drain layer 52, to the overlap capacitance of the gate line 20 and the data line 30, reliably reducing the overlap area of ​​the gate layer 50 and the drain layer 52, thereby reducing the parasitic capacitance of the gate layer 50 and the drain layer 52. Furthermore, the parallel extension direction of the gate layer 50 to the extension direction of the gate line 20 also reduces the overlap area between the pixel electrode 60 and the gate layer 50, avoiding the top-gate effect, thereby reducing the leakage current of the thin-film transistor, improving the quality and efficiency of the array substrate, and further improving the yield and competitiveness of the display product.

[0048] In some embodiments, the gate layer 50 is disposed on the same layer as the gate line 20.

[0049] In this embodiment, the gate layer 50 and the gate line 20 are disposed on the same layer, which simplifies the processing technology and allows the gate layer 50 and the gate line 20 to be formed using the same patterning process, thereby improving processing efficiency. The patterning process refers to the steps involved in forming a structure with a specific pattern. This can be a photolithography process, which includes one or more steps such as forming a material layer, coating photoresist, exposure, development, etching, and photoresist stripping. Of course, the patterning process can also be other processes such as imprinting or inkjet printing.

[0050] As a feasible approach, such as Figure 4-5 As shown, the thin-film transistor also includes a source layer 51, a drain layer 52, and an active layer. One end of the drain layer 52 is connected to the active layer, and one end of the source layer 51 is connected to the active layer. The other end of the source layer 51 and the drain layer 51 is connected to the data line 30. The active layer is located on one side of the gate layer 50 and includes a channel region 53. A vacancy region 54 is formed in a portion of the gate layer 50 corresponding to the periphery of the channel region 53. The vacancy region 54 is located at least on the side of the gate layer 50 near the drain layer 52.

[0051] The active layer can be located on the side of the gate layer 50 away from the substrate 10, and a gate insulating layer is also disposed between the active layer and the gate layer 50. The active layer includes a channel region 53 and source layer connection regions and drain layer connection regions located on both sides of the channel region 53. The source layer 51 and drain layer 52 are each disposed on the side of the active layer away from the substrate 10. The source layer 51 is connected to the source layer connection region, and the drain layer 52 is connected to the drain layer connection region. Both the source layer connection region and the drain layer connection region can be doped with dopants (e.g., but not limited to N-type dopants) with a higher doping concentration than the channel region 53. When the voltage signal applied to the gate layer 50 reaches a certain value, a carrier path is formed in the channel region 53, turning on the source layer 51 and drain layer 52 of the thin-film transistor.

[0052] It is understood that the formation of a void region 54 in a portion of the area surrounding the channel region 53 corresponding to the gate layer 50 means that a portion of the area surrounding the channel region 53 corresponding to the gate layer 50 is removed to form a void region 54. The void region 54 can be a via, or it can be filled by the dielectric layer 55. Based on satisfying the reasonable enclosing distance between the orthographic projection of the gate layer 50 on the substrate 10 and the orthographic projection of the channel region 53 on the substrate 10, the void region 54 can be formed in the entire area surrounding the channel region 53 corresponding to the gate layer 50, or the void region 54 can be formed only on one side of the drain layer 52 corresponding to the gate layer 50. This is beneficial to further reduce the overlap area between the gate layer 50 and the drain layer 52, thereby reducing the overlap capacitance (Cgd) between the gate layer 50 and the drain layer 52.

[0053] It is also understood that the gate layer 50, source layer 51, and drain layer 52 can each be made of metal, metal alloy, metal nitride, conductive metal oxide, etc. For example, the gate layer 50 can include gold (Au), gold alloys, silver (Ag), silver alloys, aluminum (Al), aluminum alloys, aluminum nitride (AlN), etc. x ), tungsten (W), tungsten nitride (WN) x ), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrN) x ), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiN) x Platinum (Pt), Tantalum (Ta), Tantalum nitride (TaN) x Neodymium (Nd), Scandium (Sc), Strontium ruthenium oxide (SRO), Zinc oxide (ZnO) x ), Tin oxide (SnO) x Indium oxide (InO) x Gallium oxide (GaO) x Gate layer 50 can be single-layered or multi-layered.

[0054] The active layer may include, for example, inorganic semiconductor materials (e.g., polycrystalline silicon, amorphous silicon, etc.), organic semiconductor materials, and oxide semiconductor materials.

[0055] In this embodiment, the gate layer 50 forms a vacancy region 54. While ensuring the on-state current of the thin-film transistor and reducing the off-state current, it is beneficial to reduce the excess overlap area between the gate layer 50 and the drain layer 52, thereby reducing the overlap capacitance between the gate layer 50 and the drain layer 52.

[0056] In a preferred embodiment, the vacancy area 54 is arranged around the periphery of the channel area 53.

[0057] In this embodiment, the vacancy region 54 is arranged around the periphery of the channel region 53, which is beneficial to further reliably reduce the overlap capacitance between the gate layer 50 and the drain layer 52, and is easy to process.

[0058] In a preferred embodiment, such as Figure 5-7 As shown, the vacancy region 54 is located at the four corners of the gate layer 50 near the channel region 53.

[0059] It is understandable that the position of the vacancy region 54 at the four corners of the gate layer 50 near the channel region 53 means that the gate layer 50 forms the vacancy region 54 on the periphery of the corresponding channel region 53 and near the four corners of the channel region 53. In this way, the gate layer 50 only wraps the channel region, which is beneficial to further reduce the parasitic capacitance between the gate layer 50 and its upper layer.

[0060] In some embodiments, a dielectric layer 55 is disposed between the active layer and the gate layer 50, and the vacancy region 54 is filled with the dielectric layer 55.

[0061] The dielectric layer 55 may be made of, but is not limited to, silicon oxynitride (SiON) and silicon oxide (SiO). x ), silicon nitride (SiN) x ), silicon dioxide (SiO) x C y ), silicon carbide (SiC) x N y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x ), tantalum oxide (TaO) x ), Hafnium oxide (HfO) x Zirconium oxide (ZrO) x Titanium oxide (TiO) x (etc.) The dielectric layer 55 can be formed as a single layer or multiple layers.

[0062] In this embodiment, the vacant area is filled with dielectric layer 55 material, which helps to reduce the overlap capacitance between the gate layer 50 and the drain layer 52 while ensuring the structural stability of the entire array substrate.

[0063] As an alternative implementation, the pixel unit 40 also includes a pixel electrode 60, wherein the orthographic projection of the gate layer 50 on the substrate 10 does not overlap with the orthographic projection of the pixel electrode 60 on the substrate 10.

[0064] It is understood that a passivation layer can be formed on the side of the source layer 51 and drain layer 52 facing away from the substrate 10. The material of the passivation layer can be, but is not limited to, silicon oxynitride (SiON) or silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon dioxide (SiO) x C y ), silicon carbide (SiC) x N y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x ), tantalum oxide (TaO) x ), hafnium oxide (HfO) x Zirconia (ZrOx) and titanium dioxide (TiO) xThe passivation layer can be a single layer or a multilayer structure. The pixel electrode 60 can be disposed on the side of the passivation layer facing away from the substrate 10. A via is formed in the passivation layer along a direction perpendicular to the substrate 10, and the pixel electrode 60 is connected to the drain layer 52 or source layer 51 of the thin-film transistor through the via. The pixel electrode 60 can be made of a transparent conductive material, such as indium tin oxide (ITO). In some embodiments, the pixel electrode 60 can be disposed on the same layer as the data line 30, so that the pixel electrode 60 and the data line 30 can be formed using the same patterning process, eliminating the need to form a separate mask for the pixel electrode 60, simplifying the patterning process of the array substrate, and saving fabrication time and cost.

[0065] It can also be understood that the non-overlapping of the orthogonal projection of the gate layer 50 on the substrate 10 and the orthogonal projection of the pixel electrode 60 on the substrate 10 means that there is no overlapping area between the orthogonal projection areas of the gate layer 50 on the substrate 10 and the orthogonal projection areas of the pixel electrode 60 on the substrate 10.

[0066] In this embodiment, the orthogonal projection of the gate layer 50 on the substrate 10 does not overlap with the orthogonal projection of the pixel electrode 60 on the substrate 10. This helps to avoid the top-gate effect between the pixel electrode 60 and the thin-film transistor, reduce leakage current, ensure the stability of the thin-film transistor, and reliably reduce the overlap capacitance (Cpg) between the pixel electrode 60 and the gate layer 50.

[0067] As an implementation, the array substrate also includes a common electrode 70 and a common voltage signal line 71 connected to the common electrode 70, wherein the orthographic projection of the common electrode 70 on the substrate 10 at least partially overlaps with the orthographic projection of the pixel electrode 60 on the substrate 10.

[0068] The number of common electrodes 70 can be at least one, depending on the actual array substrate structure and display effect. The orthographic projection of the common electrode 70 on the substrate 10 at least partially overlaps with the orthographic projection of the pixel electrode 60 on the substrate 10 to form a storage capacitor. During operation, the common voltage trace can apply a common voltage to the common electrode 70, and the thin-film transistor can apply the driving voltage on the data line 30 to the pixel electrode 60 in response to the scan signal applied on the gate line 20.

[0069] It should be noted that different colored particles undergo electrophoresis under the influence of voltage, thus forming different gray levels on the screen surface. For example, black and white particles can be electrophoresed under the influence of voltage to form black and white colors.

[0070] Electronic paper display panels are single-substrate products, and their basic principle is to drive pixels through a vertical electric field. An array substrate provides pixel electrodes 60 with storage capacitors, which cooperate with a common electrode 70 on the opposing substrate surface to achieve driving. In some embodiments, a storage capacitor is formed between the pixel electrode 60 and the common electrode 70 to store charge. For example, the gate layer 50 may also have a common electrode 70, on which a common voltage for storing charge can be applied. The orthographic projection of the common electrode 70 onto the substrate 10 at least partially overlaps with the orthographic projection of the pixel electrode 60 onto the substrate 10 to form a storage capacitor. In other words, the common electrode 70 and the pixel electrode 60 are overlapped along the column direction to form a storage capacitor. Thus, when a common voltage is applied to the common electrode 70 and a driving voltage is applied to the pixel electrode 60, the pixel electrode 60 and the common electrode 70 can act as electrode plates for storing the capacitor. Of course, in other embodiments, the common electrode 70 may also be formed on other film layers.

[0071] In a preferred embodiment, the greater the overlap area between the pixel electrode 60 and the common electrode 70, the better, thereby increasing the storage capacitance.

[0072] Specifically, the orthogonal projection of the pixel electrode 60 on the substrate 10 completely covers the orthogonal projection of the common electrode 70 on the substrate 10.

[0073] In summary, the array substrate of the embodiments of this application, by adjusting the arrangement of thin-film transistors, ensures that the orthographic projection of the gate layer 50 of the thin-film transistor on the substrate 10 overlaps with the first overlapping region A1 formed by the orthographic projections of the gate line 20 and the data line 30 on the substrate 10, and the extension direction of the gate layer 50 is parallel to the extension direction of the gate line 20. In this way, the overlapping capacitance of the gate line 20 and the data line 30 and the overlapping capacitance of the gate layer 50 and the drain layer 52 can be reduced to the overlapping capacitance of the gate line 20 and the data line 30, reliably reducing the overlapping area of ​​the gate layer 50 and the drain layer 52, thereby reducing the parasitic capacitance of the gate layer 50 and the drain layer 52. Furthermore, the parallelism between the extension direction of the gate layer 50 and the extension direction of the gate line 20 can also reduce the overlapping area between the pixel electrode 60 and the gate layer 50, avoiding the top gate effect, and thereby reducing the occurrence of thin-film transistor leakage current.

[0074] Furthermore, a void region 54 is formed in the area surrounding the channel region 53 corresponding to the gate layer 50. The void region 54 is located on one side of the drain layer 52. This helps to further reduce the overlap capacitance between the gate layer 50 and the drain layer 52, thereby improving the quality and working efficiency of the array substrate, and further improving the yield and competitiveness of the display products.

[0075] Secondly, embodiments of this application provide a method for fabricating an array substrate according to the first aspect, specifically including the following steps:

[0076] Step S10: Provide substrate 10;

[0077] Step S20: Multiple gate lines 20, multiple data lines 30, and pixel units 40 are formed on the substrate 10. Each pair of adjacent gate lines 20 and each pair of adjacent data lines 30 intersect to define multiple pixel units 40 arranged in an array. Each pixel unit 40 includes a thin film transistor. The thin film transistor includes a gate layer 50. The orthographic projection of the gate layer 50 on the substrate 10 is located at the intersection of the orthographic projections of the gate lines 20 and the data lines 30 on the substrate 10. The length direction of the gate layer 50 is parallel to the length direction of the gate lines 20, and the length of the gate layer 50 is greater than the width of the gate layer 50.

[0078] It is understandable that the gate line 20, data line 30, and thin-film transistors formed on the substrate 10 can all be achieved through material deposition and patterning processes, with the specific processing technology determined based on the actual situation. The gate layer 50 and gate line 20 can be disposed on the same layer, and the data line 30 is generally located on the side of the gate line 20 facing away from the substrate 10.

[0079] In some embodiments, forming the pixel unit 40 includes:

[0080] A portion of the area surrounding the channel region 53 of the gate layer 50 is hollowed out along a direction perpendicular to the substrate 10 to form a void region 54. The void region 54 is located at least on the side close to the drain layer 52.

[0081] Specifically, forming a void in the gate layer 50 can be achieved by creating a via through the area around the channel region 53 of the gate layer 50 along a direction perpendicular to the substrate 10, removing the excess overlapping area between the gate layer 50 and the drain layer 52, and forming a void region 54. Alternatively, the size of the gate layer 50 can be predetermined during the formation of the gate layer 50, and the excess overlapping portion of the drain layer 52 can be omitted from the gate layer 50 formation. After the gate layer 50 is formed, a dielectric layer 55 is formed on the side of the gate layer 50 away from the substrate 10, thereby reducing the overlap capacitance between the gate layer 50 and the drain layer 52. This saves on processing technology, simplifies processing, and helps improve production efficiency.

[0082] Thirdly, embodiments of this application provide an electronic paper display module 200, including the array substrate 100 of the first aspect. It is understood that this electronic paper display module possesses all the features and advantages of the aforementioned array substrate, which will not be repeated here. In summary, this electronic paper display module has high quality and yield, and excellent display performance.

[0083] In some embodiments, the electronic paper display module 200 has an electronic paper display panel. For example... Figure 8As shown, the electronic paper display panel includes an array substrate 100 and an opposing substrate 300 disposed opposite each other, and an electronic ink film layer 400 located between the array substrate 100 and the opposing substrate 300. The array substrate 100 is used to drive the movement of electrophoretic particles within the electronic ink film layer 400 to display an image.

[0084] For example, the electronic ink film layer 400 can be formed by coating electronic ink composed of microcapsules onto a plastic film. The electronic ink consists of millions of microcapsules, each containing negatively charged and positively charged electrophoretic particles suspended in a transparent liquid. An array substrate and a counter substrate are disposed on opposite sides of the electronic ink film layer, providing positive and negative electrodes. Electrophoretic particles with different charges move up and down between the array substrate and the counter substrate according to the applied electric field until they reach a designated position. When ambient light shines on the electrophoretic particles, the particles refract the ambient light of the corresponding color, causing the microcapsule to display the corresponding color. The electrophoretic particles of different colors have opposite charge polarities. For example, each microcapsule contains negatively charged white particles and positively charged black particles suspended in a transparent liquid. When the microcapsule is subjected to a negative electric field, the positively charged white particles move to the top of the microcapsule, displaying white at that position; the negatively charged black particles reach the bottom of the microcapsule under the influence of the electric field, and the user cannot see the black color. If the direction of the electric field is reversed, the display effect is also reversed, i.e., black is displayed and white is hidden. It can be seen that by changing the direction of the electric field, the display can switch between black and white. The white area corresponds to the uninked portion of the paper, while the black corresponds to the printed text and images on the paper. The electronic ink film layers can also be composed of particles such as yellow, cyan, magenta, and red; this application does not limit the material of the electronic ink film layers.

[0085] In some other embodiments, the electronic ink film layer 400 may be replaced with a liquid crystal layer.

[0086] In other embodiments, the common voltage signal line may include a first common voltage signal line and at least one second common voltage signal line. The common electrode includes a first common electrode and a second common electrode. The first common signal line is disposed on the same layer as the first common electrode and electrically connected thereto, and at least part of the first common signal line is located in the display area. At least one second common signal line is disposed on one side of the substrate and located in the non-display area. The first common signal line and each of the second common signal lines are electrically isolated from each other, that is, the first common signal line and each of the second common signal lines are not connected to each other. Thus, by electrically isolating the first common signal line and each of the second common signal lines from each other, when the data line voltage changes, only the voltage of the first common electrode is affected, and the change cannot be transmitted to the second common signal line through the first common signal line. When the second common signal line is used to connect the second common electrode of the electronic paper film, the voltage of the second common electrode will not be affected, thereby avoiding affecting the driving voltage of the electronic ink microcapsules of the electronic paper film. This can prevent crosstalk along the gate line direction in the display screen, ensuring display effect and quality.

[0087] Fourthly, embodiments of this application provide an electronic paper display device, encompassing the electronic paper display module of the third aspect. It is understood that this electronic paper display device possesses all the features and advantages of the aforementioned electronic paper display module, which will not be repeated here. In summary, this electronic paper display device has high quality and yield, and excellent display performance.

[0088] Specifically, the display device includes, but is not limited to, any electronic paper product or component with display function such as ESL (electronic tag), e-book, electronic paper notebook, etc. Those skilled in the art can make the appropriate selection according to the actual use of the display device, which will not be elaborated here.

[0089] It should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., used above to indicate orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the panel or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the invention, unless otherwise stated, "a plurality of" means two or more.

[0090] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. An array substrate, characterized in that, The device includes: a substrate on which multiple gate lines, multiple data lines, and multiple pixel units are disposed; each pair of adjacent gate lines and each pair of adjacent data lines intersects to define the array of pixel units; the orthographic projection of the gate lines on the substrate and the orthographic projection of the data lines on the substrate form a first overlapping region; each pixel unit includes a thin-film transistor; the thin-film transistor includes a gate layer; the orthographic projection of the gate layer on the substrate overlaps with the first overlapping region; the length direction of the gate layer is parallel to the length direction of the gate lines, and the length of the gate layer is greater than the width of the gate layer; wherein, the length direction of the gate layer refers to the direction of current conduction in the thin-film transistor.

2. The array substrate according to claim 1, characterized in that, The gate layer is disposed on the same layer as the gate line.

3. The array substrate according to claim 1, characterized in that, The thin-film transistor further includes a source layer, a drain layer, and an active layer. One end of the source layer is connected to the active layer, and one end of the drain layer is connected to the active layer. The other end of one of the source layer and the drain layer is connected to the data line. The active layer is located on one side of the gate layer and includes a channel region. A vacancy region is formed in a portion of the gate layer corresponding to the periphery of the channel region. The vacancy region is located at least on the side of the gate layer near the drain layer.

4. The array substrate according to claim 3, characterized in that, The vacant area is arranged around the periphery of the channel area.

5. The array substrate according to claim 3, characterized in that, The vacancy region is located at the four corners of the gate layer near the channel region.

6. The array substrate according to claim 3, characterized in that, A dielectric layer is disposed between the active layer and the gate layer, and the vacancy region is filled with the dielectric layer.

7. The array substrate according to any one of claims 1-6, characterized in that, The pixel unit further includes a pixel electrode, and the orthographic projection of the gate layer on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate.

8. The array substrate according to claim 7, characterized in that, The array substrate further includes a common electrode and a common voltage signal line connected to the common electrode, wherein the orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.

9. The array substrate according to claim 7, characterized in that, The orthogonal projection of the pixel electrode on the substrate completely covers the orthogonal projection of the common electrode on the substrate.

10. A method for fabricating an array substrate according to any one of claims 1-9, characterized in that, Specifically, the steps include the following: Provide the substrate, Multiple gate lines, multiple data lines, and pixel units are formed on the substrate. Each pair of adjacent gate lines and each pair of adjacent data lines intersects to define the array of pixel units. Each pixel unit includes a thin-film transistor, and each thin-film transistor includes a gate layer. The orthographic projection of the gate layer on the substrate is located at the intersection of the orthographic projections of the gate lines and the data lines on the substrate. The length direction of the gate layer is parallel to the length direction of the gate lines, and the length of the gate layer is greater than the width of the gate layer.

11. The preparation method according to claim 10, characterized in that, Forming the pixel unit includes: The gate layer is hollowed out along a direction perpendicular to the substrate to form the void region, and the void region is located at least on the side close to the drain layer.

12. An electronic paper display module, characterized in that, Includes the array substrate as described in any one of claims 1-9.

13. An electronic paper display device, characterized in that, Includes the electronic paper display module as described in claim 12.

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