A back contact p-type cell and method of making the same

Abstract

The embodiment of the present application discloses a back junction p-type cell and a preparation method thereof, wherein the back junction p-type cell comprises a p-type silicon substrate, a back surface of the p-type silicon substrate is provided with a pn junction structure, the pn junction structure comprises a tunneling oxide layer and a phosphorus-doped polysilicon layer which are sequentially arranged on the silicon substrate; a front surface of the p-type silicon substrate is provided with a partitioned emitter structure, the partitioned emitter structure comprises: a plurality of p++ doped regions, a low-doped region arranged between adjacent p++ doped regions, and the low-doped region is a p+ doped region or an intrinsic region i; wherein: an activation concentration of the p++ doped region is higher than 1×10 19 cm ‑3 ; and an activation concentration of the p+ doped region is lower than 2×10 18 cm ‑3 . The present application provides a back junction p-type cell, by adopting a gallium-doped P-type silicon wafer and constructing a front surface partitioned emitter and a back surface n-type TOPCon structure, the contact performance is optimized, the recombination is inhibited and the optical gain is combined, the high-performance p-type contact construction problem is avoided, the parasitic absorption and the interface recombination are reduced, and the unity of high efficiency and mass production adaptability is realized.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a back-junction p-type solar cell and its fabrication method. Background Technology

[0002] Driven by the photovoltaic industry's continuous pursuit of higher conversion efficiency and lower levelized cost of electricity (LCOE), battery structures with higher theoretical efficiency ceilings have gradually become a research focus. Among these, back-junction batteries, by placing the PN junction on the back of the cell, offer unique structural advantages: Firstly, compared to traditional front-junction batteries, because the emitter is moved to the back, the front side does not require heavy doping to form the PN junction. This significantly reduces recombination in the front metal contact area and allows for finer, sparser metal grid lines, effectively reducing shading losses and creating favorable conditions for improving short-circuit current (Isc) and fill factor (FF). Secondly, compared to fully back-contact batteries where both the grid lines and junction are located on the back, back-junction TOPCon batteries (TBJ) retain the front main grid lines, significantly simplifying the back electrode pattern and its alignment, reducing interconnection costs and back leakage risks, achieving a better balance between efficiency potential and mass production feasibility. Therefore, TBJ batteries, which combine mainstream tunneling oxide passivation contact technology with a back-junction structure, are considered an important next-generation high-efficiency technology with mass production potential.

[0003] However, despite the significant theoretical advantages of n-type TBJ (n-TBJ), its industrialization process remains relatively slow. Currently, the photovoltaic industry is gradually shifting towards a technology platform based on n-type silicon wafers, but a mature and commercially viable n-TBJ solution has yet to be established. The main obstacle lies in the difficulty of existing mass production processes simultaneously achieving excellent optical and passivation performance on the front side and a highly efficient and low-recombination pn junction structure on the back side of an n-type substrate. This manifests in the following two key contradictions: Firstly, regarding the front structure, TBJ batteries require high-performance passivation capabilities on the front side while also maintaining high light transmittance, but existing technical solutions all have significant shortcomings: (1) If phosphorus-doped polysilicon is used as the passivation contact layer, although it can provide excellent passivation effect, the polysilicon layer itself has strong parasitic absorption. In order to meet the requirements of contact reliability and welding strength of the front metal gate line, the thickness of this layer is usually difficult to be further reduced, which leads to large optical loss and thus affects the short-circuit current (Isc). (2) If conventional phosphorus diffusion is used to form the front surface field in order to reduce absorption, its surface passivation performance (usually characterized by J0 value) is significantly worse than that of the TOPCon structure, which in turn leads to a decrease in open circuit voltage (Voc).

[0004] Secondly, regarding the back-side structure, high-efficiency n-TBJ batteries require the pn junction on the back side to have extremely low recombination current, but existing p-type contact technology still has certain limitations: (1) Recombination in the metal contact region is relatively severe in traditional boron diffused emitters, and its contact recombination parameter (J0e) is usually between 5 and 7 fA / cm. 2 The above factors have become important limiting factors for further increases in open-circuit voltage; (2) Although the p-type TOPCon structure of boron-doped polycrystalline silicon can reduce J0 to 4-6 fA / cm 2 However, it has not yet reached a lower limit, and there are still process challenges in areas such as thin film quality control and doping uniformity, which restricts further improvement in battery efficiency.

[0005] However, all of the above-mentioned technical routes are based on n-type silicon wafers, and their core challenge lies in constructing a p-type contact structure on the back of the cell that combines low recombination loss and low contact resistance. Although existing boron-diffused emitters and boron-doped polycrystalline silicon passivated contact structures can achieve selective carrier transport, their contact recombination current is still relatively high, and there are significant challenges in terms of doping uniformity, thin film quality control, and process stability, thus limiting further improvements in the efficiency of n-type TBJ cells.

[0006] The inventors discovered that the aforementioned problems do not originate from the back junction structure itself, but primarily from the process requirement of constructing high-performance p-type contacts under n-type substrate conditions. If gallium-doped p-type silicon wafers are used as the substrate, the pn junction and electron-selective contacts on the back side can be formed using the industrially mature n-type TOPCon structure, thus avoiding the process complexity associated with constructing high-performance p-type TOPCon contacts. Simultaneously, since a polycrystalline silicon passivation contact layer is not required on the front side, parasitic absorption losses can be further reduced. Therefore, how to construct a back junction solar cell structure based on p-type silicon wafers that retains the advantages of the back junction solar cell structure while also considering process maturity and optical performance has become a pressing technical problem to be solved in this field. Summary of the Invention

[0007] The present invention aims to solve the following technical problems existing in the prior art: In the back junction cell structure, especially in p-type TBJ cells, it is difficult to simultaneously achieve low recombination loss and high optical performance on the front side. Existing solutions either use a highly doped structure, which leads to increased recombination, or use a polycrystalline silicon passivated contact structure, which leads to increased parasitic absorption, thereby limiting the further improvement of open-circuit voltage and short-circuit current.

[0008] This invention also proposes a method for preparing a back-junction P-type battery.

[0009] The technical solution adopted by the present invention is: to provide a back junction p-type battery, including a p-type silicon substrate, wherein the p-type silicon substrate is a gallium-doped p-type silicon wafer, and a pn junction structure is provided on the back side of the p-type silicon substrate, wherein the pn junction structure includes a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer sequentially disposed on the silicon substrate; The p-type silicon substrate has a partitioned emitter structure on its front side, the partitioned emitter structure comprising: Multiple p++ doped regions are disposed in a low-doped region between adjacent p++ doped regions, wherein the low-doped region is a p+ doped region or an intrinsic region i; in: The activation concentration of the p++ doped region is higher than 1×10⁻⁶. 19 cm -3 ; The activation concentration of the p+ doped region is less than 2 × 10⁻⁶. 18 cm -3 .

[0010] Preferably, the area ratio of the p++ doped region in the front side is no more than 40%, and more preferably 10% to 30%. By controlling the area ratio of the p++ doped region, it is mainly distributed in the electrode contact area, thereby ensuring good ohmic contact while avoiding the electrode from falling on the low-doped region or intrinsic region, which is beneficial to improving the process yield; at the same time, reducing the proportion of high-doped region can significantly reduce surface recombination loss.

[0011] This invention does not involve partial improvements to existing n-TBJ structures. Instead, it transforms the difficult-to-achieve back-side p-type TOPCon contact in traditional n-TBJs into a more mature n-type TOPCon contact by using gallium-doped p-type silicon wafers as the substrate, fundamentally circumventing the challenges of constructing high-performance p-type contacts. Through this technical solution, a partitioned emitter structure composed of p++-doped and p+-doped or intrinsic regions is constructed on the front side of the battery. This allows for a highly doped structure in the electrode contact area to reduce contact resistance, while the non-contact area uses a low-doped or intrinsic structure to reduce carrier recombination, thus achieving synergistic optimization of contact performance and recombination suppression. Simultaneously, since no polycrystalline silicon passivation contact layer is introduced on the front side, polycrystalline silicon parasitic absorption is effectively avoided, improving incident light utilization and thus increasing short-circuit current. Furthermore, the combination of a back-side tunneling oxide layer and a phosphorus-doped polycrystalline silicon-based high-efficiency passivation contact structure reduces interface recombination current and improves open-circuit voltage and fill factor.

[0012] Furthermore, this invention employs a P-type back junction structure. Compared to traditional front junction TOPCon cells, its overall process flow is highly compatible with existing n-type cells and TOPCon production lines, allowing full utilization of existing mature equipment such as diffusion, PECVD, and screen printing, thus reducing industrialization costs. Moreover, compared to full back contact (BC) cells, this invention retains the front main grid structure, eliminating the need for complex back cross electrode patterns and high-precision alignment processes. This not only reduces manufacturing difficulty and process costs but also minimizes the risk of back leakage, improving mass production yield. Additionally, the reduced number of back electrodes and relatively simplified metal patterns effectively reduce silver paste consumption, resulting in a better cost advantage; simultaneously, the back junction structure enhances carrier collection capabilities under low-light conditions.

[0013] According to one embodiment of the present invention, the area ratio of the p++ doped region in the front side is ≤40%, preferably 10% to 30%. By controlling this area ratio, the highly doped region is mainly distributed in the electrode contact region, which reduces recombination loss while ensuring contact performance, and avoids the electrode falling into the low-doped region or intrinsic region, thereby improving the battery yield and consistency.

[0014] According to one embodiment of the present invention, the i-region is formed by a patterning process combined with an etching process, wherein the patterning process includes polymer mask patterning or laser patterning. Patterning enables precise division of doped regions, creating a clear interface between the p++ region and the low recombination region, thereby improving the controllability and repeatability of the partitioned structure and further enhancing the stability of device performance.

[0015] According to one embodiment of the present invention, the front side is provided with a composite passivation structure consisting of a SiOx layer, an AlOx layer, and a SiNx layer sequentially from the inside to the outside. Through the synergistic effect of the multilayer passivation films, the interface state density can be effectively reduced and fixed charge can be provided, thereby reducing the surface recombination rate, improving minority carrier lifetime, and further increasing the open-circuit voltage.

[0016] According to one embodiment of the present invention, the back side is provided with a SiOx layer, an AlOx layer, and a SiNx layer sequentially from the inside to the outside, or with a SiOx layer, a carbon-nitrogen polycrystalline silicon layer, an AlOx layer, and a SiNx layer sequentially. By optimizing the back passivation structure, recombination at the tunneling contact interface can be further reduced, and interface stability can be improved, thereby enhancing the overall performance and reliability of the battery.

[0017] According to an embodiment of the present invention, a method for preparing the back-junction p-type battery is provided, comprising the following steps: S1. Provide p-type gallium-doped silicon wafers; S2. Clean and texturize the silicon wafers; S3. Pre-deposit boron source on the front side of the silicon wafer and perform preliminary diffusion to form a borosilicate glass layer; S4. The borosilicate glass layer is patterned to form a retention area and a removal area; S5. Remove the borosilicate glass layer in the removal area; S6. Perform high-temperature diffusion to form a p++ doped region in the retained region and a p+ doped region or i region in the removed region. S7. A tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are formed on the back side of the silicon wafer; S8. Perform passivation structure deposition, electrode preparation and post-processing.

[0018] According to one embodiment of the present invention, in step S4, the patterning process includes using a polymer mask combined with an etching process or using laser patterning combined with a wet etching process. By selecting different patterning methods, a flexible adjustment can be made between structural accuracy and process cost, thereby meeting different production needs.

[0019] According to one embodiment of the present invention, in step S7, the phosphorus-doped polycrystalline silicon layer is formed by LPCVD deposition followed by doping, or by PECVD deposition followed by annealing. By selecting different deposition process routes, both film quality and equipment compatibility can be considered, thus improving process flexibility.

[0020] According to one embodiment of the present invention, in step S6, region i is formed by etching with rich nitric acid for a time of 1–5 min, and / or by secondary texturing for a time of 20–1200 s. Through the isotropic etching characteristics of rich nitric acid etching or the secondary texturing process, effective control over the surface morphology and etching depth can be achieved, thereby optimizing optical performance and reducing recombination losses.

[0021] According to one embodiment of the present invention, after the battery is fabricated, the silicon wafer is cleaved using a laser to divide it into multiple sub-cell units. Preferably, the battery has a cleaved region without a pn junction extending along a predetermined cleaving path. The pn junction structure is not disposed within the cleaved region. Cleaving the silicon wafer in the cleaved region using a laser enables cell miniaturization, thereby reducing series resistance, increasing module output power, and improving module reliability. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the back junction p-type battery in an embodiment of the present invention.

[0024] Figure 2 This is a process flow diagram of the p-type battery with back junction in an embodiment of the present invention. Detailed Implementation

[0025] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0026] Step S1: p-type silicon wafer preparation.

[0027] p-type monocrystalline silicon wafers were selected as the substrate, with the crystal orientation being... <100> The resistivity is controlled within the range of 1 to 10 Ω·cm, the thickness is 100 to 180 μm, and the size can be 166 mm, 182 mm, or 210 mm. The silicon wafer is preferably chamfered before use to reduce the risk of edge chipping, and ultrasonic cleaning is used to remove particulate impurities to ensure uniformity in subsequent processes.

[0028] Step S2: Cleaning and flocking process.

[0029] First, the silicon wafers are pre-cleaned using a mixed solution of NaOH:H₂O₂:H₂O at a temperature controlled at 75–80°C for 100–300 seconds to remove organic contaminants and particles. After cleaning, they are rinsed with deionized water and dried. Then, the silicon wafers are placed in an alkaline solution containing NaOH (1–3 wt%) and texturing additives at 70–85°C for 200–800 seconds to form a uniform pyramidal texturing structure on the wafer surface, reducing surface reflectivity to below 10%.

[0030] Step S3: Boron source pre-deposition and preliminary diffusion.

[0031] The texturized silicon wafer is placed in a diffusion furnace, where boron pre-deposition is performed using a BBr3 gaseous source. The reaction temperature is controlled at 800–950°C, and the time is 5–30 min. This forms a layer of borosilicate glass (BSG) and a shallow p+ doped region on the front side of the silicon wafer. The preferred surface doping concentration of the p+ layer is 1 × 10⁻⁶. 19 ~5×10 19 cm -3 The junction depth is 0.1–0.3 μm. As an alternative, a BSG layer can also be formed by spin-coating with a liquid boron source followed by heat treatment.

[0032] Step S4: Patterning process (printing adhesive and laser windowing).

[0033] A photoresist is applied to the front side of the silicon wafer where the BSG layer is formed using screen printing. The thickness of the photoresist is controlled between 3 and 50 μm, and then cured by drying (temperature 80–300℃, time 0.1–10 min) to form a stable protective layer. Subsequently, patterned windows are created using a laser device. The laser wavelength is preferably 1064 nm or 532 nm, the single pulse energy is 0.1–1 mJ, and the scanning speed is 100–1000 mm / s. The photoresist is removed in the predetermined area, exposing the BSG in the corresponding area, thereby forming a patterned structure.

[0034] Step S5: Remove BSG from the patterned area (removal of adhesive and preparation of p+ / i layer).

[0035] Patterned silicon wafers are selectively etched by immersing them in a hydrofluoric acid (HF) solution with an HF concentration controlled at 1–30 wt% for 30–300 s. This process completely removes the BSG in the exposed areas while retaining the BSG in the areas covered by the resist. The depatterned silicon wafers are then placed in an alkaline solution containing NaOH (1–3 wt%) and secondary texturing additives and treated at 70–85°C for 50–500 s, or cleaned with a mixture of nitric acid, HF, and deionized water for 60–300 s to complete the preparation of the p+ / i regions. After etching, the wafers are cleaned with deionized water, and residual resist is removed using organic solvents or plasma.

[0036] In one embodiment, the region after BSG removal retains the shallow boron diffusion layer formed during the pre-deposition stage, which is then subjected to subsequent heat treatment to form a lightly doped p+ region.

[0037] In another embodiment, after removing the BSG, the surface boron diffusion layer is further removed by rich nitric acid etching, alkaline secondary texturing, or wet etching back process, so that the silicon substrate surface is exposed again in this area, thereby forming the intrinsic region i.

[0038] Step S6: High-temperature propulsion diffusion.

[0039] The treated silicon wafers are then placed back into a high-temperature diffusion furnace for advanced diffusion at 950–1050°C for 20–60 minutes. During this process, the boron source retained in the BSG region continues to diffuse into the silicon, forming a heavily doped p++ region with a surface concentration reaching 1 × 10⁻⁶. 19 cm -3 The junction depth is 0.5–1.0 μm; while the removal of the BSG region only results in limited diffusion, forming a lightly doped p+ region with a surface concentration of approximately 1 × 10⁻⁶. 18 ~5×10 18 cm-3 This allows for the construction of a selective emitter structure.

[0040] Cleaning and polishing of the back side.

[0041] The back side of the silicon wafer undergoes chemical polishing by immersing it in an alkaline solution containing NaOH and an alkaline polishing additive at 70–85°C for 100–300 s to remove the damaged layer and impurities generated during diffusion. After treatment, the wafer is rinsed with deionized water and dried to reduce the back surface roughness Ra to below 10 nm, meeting the requirements for subsequent thin film deposition.

[0042] Step S7: Fabrication of the back TOPCon structure.

[0043] First, a tunneling oxide layer is formed on the back side of the silicon wafer, preferably using a thermal oxidation process to form a 1-2 nm thick SiO2 thin layer at 800-900°C. Subsequently, a phosphorus-doped polycrystalline silicon layer is deposited on top: in one embodiment, intrinsic polycrystalline silicon (100-200 nm thick) is deposited using LPCVD, followed by phosphorus doping via POCl3 diffusion at 850-900°C; in another embodiment, a phosphorus-doped amorphous silicon layer (50-150 nm thick) is directly deposited using PECVD, and then crystallized into a polycrystalline silicon layer by subsequent annealing at 800-900°C. This structure is used to form tunneling oxide passivation contacts.

[0044] Cleaning and removal of plating.

[0045] The edges of the silicon wafer are treated using wet or dry etching to remove the polysilicon or phosphorus diffusion layer formed during the deposition process. The etching width is preferably 1–3 mm to prevent electrical short circuits between the front and back conductive layers. After etching, cleaning and drying are performed.

[0046] Step S8: Deposit an alumina passivation layer.

[0047] An Al2O3 thin film was deposited on the front side of a silicon wafer using atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD), with a thickness controlled in the range of 3–20 nm. This layer can provide a negative fixed charge (approximately 10). 12 cm -2 (on a scale of magnitude), effectively suppressing minority carrier recombination and improving carrier lifetime.

[0048] A silicon nitride layer is deposited on the front side.

[0049] A SiNx antireflective layer with a thickness of 70–90 nm and a refractive index controlled between 1.9 and 2.1 was deposited on an Al2O3 layer via PECVD. This layer not only has antireflective properties but can also form a composite passivation structure with Al2O3, thereby improving battery efficiency.

[0050] A silicon nitride layer is deposited on the back side.

[0051] A SiNx protective layer with a thickness of 50–100 nm is deposited on the back polysilicon layer to prevent polysilicon oxidation and environmental corrosion, while also improving the long-term stability of the device.

[0052] Electrode preparation and post-processing.

[0053] First, a silver electrode is formed on the front side of the silicon wafer via screen printing, and an aluminum electrode or a silver-aluminum composite electrode is formed on the back side. Then, rapid sintering is performed at 700–850°C to ensure good ohmic contact between the metal electrodes and the semiconductor. Following this, light injection (1000 W / m²) is performed. 2 To improve device performance, a process lasting 1–10 min was employed, and laser-induced contact optimization (LECO) technology was used to further reduce contact resistance. Finally, the solar cells were cleaved and sorted for efficiency through electrical performance testing (IV testing).

[0054] Example 1 (P++ / P+ / No secondary fleece processing) S1-S4 are as described above. S5: The patterned silicon wafer is immersed in a hydrofluoric acid (HF) solution for selective etching. The HF concentration is controlled at 1–30 wt%, and the etching time is 30–300 s. This process completely removes the BSG in the exposed areas while retaining the BSG in the areas covered by the resist. After etching, the wafer is rinsed with deionized water, and any residual resist is removed using organic solvents or plasma.

[0055] S6-S8 are as described above. Figure 1 As shown, this embodiment discloses a back-junction p-type battery, the main structural parameters of which are as follows: Gallium-doped P-type single-crystal silicon wafers are used, with a resistivity of 1.5 Ω·cm and a thickness of 130 μm; Front side: Gate line spacing is 1100 μm; a selective emitter structure is set within each 1100 μm period, where the P++ doped region is 250 μm wide and the P+ doped region is 850 μm wide, with the P++ doped region accounting for approximately 22.7% of the area; the surface activation concentration of the P++ doped region is 2 × 10^ 19 cm^ -3 The surface activation concentration of the P+ doped region is 8 × 10^ 18 cm^ -3 The front side adopts a SiOx / AlOx / SiNx composite passivation structure; the J0 of the p++ doped region, p++ is 8.0 fA / cm. 2 The P+ doped region J0,p+ has a strength of 2.6 fA / cm. 2The front-side gate line width is 18 μm, and the gate line contact area composite density is 40 fA / cm. 2 The contact resistivity is 1.5 mΩ·cm. 2 The height difference between the P++ doped region and the P+ doped region is 2.5 μm.

[0056] Back side: Except for the cleaved region, the remaining areas are n-type TOPCon structures; the passivation contact structure consists of a tunneling oxide layer and a phosphorus-doped polysilicon layer, wherein the thickness of the tunneling oxide layer is 1.5 nm and the thickness of the phosphorus-doped polysilicon layer is 120 nm; the J0,r of the back passivation contact region is 1.2 fA / cm. 2 The back-side gate line width is 18 μm, and the composite density in the contact area is 18 fA / cm. 2 The contact resistivity is 0.5 mΩ·cm. 2 .

[0057] The back of the battery features a PN junction-free cracked area with a width of 400 μm. The overall cell efficiency is 26.50%, with Voc = 741.5 mV, Isc = 14.20 mA, and FF = 84.20%.

[0058] Example 2 (P++ / P+ / Secondary flocking 100s) S1-S4 are as described above. S5: The patterned silicon wafer is immersed in a hydrofluoric acid (HF) solution for selective etching. The HF concentration is controlled at 1–30 wt%, and the etching time is 30–300 s. This completely removes the BSG in the exposed areas while retaining the BSG in the areas covered by the resist. The depatched silicon wafer is then placed in an alkaline solution containing NaOH (1–3 wt%) and secondary texturing additives and treated at 70–85°C for 50–100 s to complete the preparation of the p+ region. After etching, the wafer is rinsed with deionized water, and residual resist is removed by organic solvents or plasma.

[0059] S6-S8 as described above This embodiment discloses a back-junction p-type battery, the main structural parameters of which are as follows: Gallium-doped P-type single-crystal silicon wafers are used, with a resistivity of 1.5 Ω·cm and a thickness of 130 μm; Front side: Gate line spacing is 1100 μm; a selective emitter structure is set within each 1100 μm period, where the P++ doped region is 250 μm wide and the P+ doped region is 850 μm wide, with the P++ doped region accounting for approximately 22.7% of the area; the surface activation concentration of the P++ doped region is 1×10^ 20 cm^ -3 The surface activation concentration of the P+ doped region is 8 × 10^18 cm^ -3 In step S5, a secondary texturing process is performed for 100 s; the front side adopts a SiOx / AlOx / SiNx composite passivation structure; the P++ doping region J0,p++ has a density of 8.0 fA / cm. 2 The P+ doped region J0,p+ has a strength of 2.2 fA / cm. 2 The front-side gate line width is 18 μm, and the gate line contact area composite density is 40 fA / cm. 2 The contact resistivity is 1.5 mΩ·cm. 2 The height difference between the P++ doped region and the P+ doped region is 3.0 μm. The back-side structure is the same as in Example 1.

[0060] The back of the battery features a PN junction-free cracked area with a width of 400 μm. The overall cell efficiency is 26.52%, with Voc = 742.6 mV, Isc = 14.19 mA, and FF = 84.17%.

[0061] Example 3 (P++ / P+ / Secondary flocking 200s) S1-S4 are as described above. S5: The patterned silicon wafer is immersed in a hydrofluoric acid (HF) solution for selective etching. The HF concentration is controlled at 1–30 wt%, and the etching time is 30–300 s. This completely removes the BSG in the exposed areas while retaining the BSG in the areas covered by the resist. The depatched silicon wafer is then placed in an alkaline solution containing NaOH (1–3 wt%) and secondary texturing additives and treated at 70–85°C for 100–200 s to complete the preparation of the p+ region. After etching, the wafer is rinsed with deionized water, and residual resist is removed by organic solvents or plasma.

[0062] S6-S8 as described above This embodiment discloses a back-junction p-type solar cell with the following main structural parameters: a gallium-doped p-type single-crystal silicon wafer with a resistivity of 1.5 Ω·cm and a thickness of 130 μm is used; Front side: Gate line spacing is 1100 μm; a selective emitter structure is set within each 1100 μm period, where the P++ doped region is 250 μm wide and the P+ doped region is 850 μm wide, with the P++ doped region accounting for approximately 22.7% of the area; the surface activation concentration of the P++ doped region is 1×10^ 20 cm^ -3 The surface activation concentration of the P+ doped region is 8 × 10^ 18 cm^ -3In step S5, a secondary texturing process is performed for 200 s; the front side adopts a SiOx / AlOx / SiNx composite passivation structure; the P++ doping region J0,p++ has a density of 8.0 fA / cm. 2 The P+ doped region J0,p+ has a strength of 1.8 fA / cm. 2 The front-side gate line width is 18 μm, and the gate line contact area composite density is 40 fA / cm. 2 The contact resistivity is 1.5 mΩ·cm. 2 The height difference between the P++ doped region and the P+ doped region is 3.8 μm.

[0063] The back of the battery features a PN junction-free cracked area with a width of 400 μm. The overall cell efficiency is 26.53%, with Voc = 742.8 mV, Isc = 14.20 mA, and FF = 84.13%.

[0064] Example 4 (P++ / P+ / Enriched Nitric Acid) S1-S4 are as described above. S5: The patterned silicon wafer is immersed in a hydrofluoric acid (HF) solution for selective etching. The HF concentration is controlled at 1–30 wt%, and the etching time is 30–300 s. This completely removes the BSG in the exposed areas while retaining the BSG in the areas covered by the resist. The depatched silicon wafer is then cleaned in a mixed solution of nitric acid, HF, and deionized water for 60–120 s to complete the preparation of the p+ / i region. After etching, the wafer is cleaned with deionized water, and residual resist is removed by organic solvents or plasma.

[0065] S6-S8 as described above This embodiment discloses a back-junction p-type battery, the main structural parameters of which are as follows: Gallium-doped P-type single-crystal silicon wafers are used, with a resistivity of 1.5 Ω·cm and a thickness of 130 μm; Front side: Gate line spacing is 1100 μm; a selective emitter structure is set within each 1100 μm period, where the P++ doped region is 250 μm wide and the P+ doped region is 850 μm wide, with the P++ doped region accounting for approximately 22.7% of the area; the surface activation concentration of the P++ doped region is 1×10^ 20 cm^ -3 The surface activation concentration of the P+ doped region is 8 × 10^ 18 cm^ -3 In step S5, a low recombination region is formed using a rich nitric acid etching process with an etching time of 120 s; the front side employs a SiOx / AlOx / SiNx composite passivation structure; the P++ doped region J0,p++ has a density of 8.0 fA / cm.2 The P+ doped region J0,p+ has a strength of 1.5 fA / cm. 2 The front-side gate line width is 18 μm, and the gate line contact area composite density is 40 fA / cm. 2 The contact resistivity is 1.5 mΩ·cm. 2 The height difference between the P++ doped region and the P+ doped region is 4.2 μm.

[0066] Back side: Except for the cleaved region, the remaining areas are n-type TOPCon structures; the passivation contact structure consists of a tunneling oxide layer and a phosphorus-doped polysilicon layer, wherein the thickness of the tunneling oxide layer is 1.5 nm and the thickness of the phosphorus-doped polysilicon layer is 120 nm; the passivation contact region J0 on the back side has a value of 1.2 fA / cm. 2 The back-side gate line width is 18 μm, and the composite density in the contact area is 18 fA / cm. 2 The contact resistivity is 0.5 mΩ·cm. 2 .

[0067] The back of the battery features a PN junction-free cracked area with a width of 400 μm. The overall cell efficiency is 26.56%, with Voc = 743.0 mV, Isc = 14.22 mA, and FF = 84.09%.

[0068] Example 5 (P++ / i / Secondary flocking 200s) This embodiment discloses a back-junction p-type battery, the main structural parameters of which are as follows: Gallium-doped P-type single-crystal silicon wafers are used, with a resistivity of 1.5 Ω·cm and a thickness of 130 μm; Front side: Gate line spacing is 1100 μm; a selective emitter structure is set within each 1100 μm period, where the P++ doped region is 250 μm wide and the intrinsic region i is 850 μm wide, with the P++ doped region accounting for approximately 22.7% of the area; the surface activation concentration of the P++ doped region is 1×10^ 20 cm^ -3 In step S5, a secondary texturing process is used to form the intrinsic region, with a secondary texturing time of 200 s; the front side adopts a SiOx / AlOx / SiNx composite passivation structure; the P++ doped region J0,p++ has a strength of 8.0 fA / cm. 2 The intrinsic region J0,i is 1.0 fA / cm. 2 The front-side gate line width is 18 μm, and the gate line contact area composite density is 40 fA / cm. 2 The contact resistivity is 1.5 mΩ·cm 2 The height difference between the P++ doped region and the intrinsic region is 5.0 μm.

[0069] Back side: Except for the cleaved region, the remaining areas are n-type TOPCon structures; the passivation contact structure consists of a tunneling oxide layer and a phosphorus-doped polysilicon layer, wherein the thickness of the tunneling oxide layer is 1.5 nm and the thickness of the phosphorus-doped polysilicon layer is 120 nm; the J0,r of the back passivation contact region is 1.2 fA / cm. 2 The back-side gate line width is 18 μm, and the composite density in the contact area is 18 fA / cm. 2 The contact resistivity is 0.5 mΩ·cm. 2 .

[0070] The back of the battery features a PN junction-free cracked area with a width of 400 μm. The overall cell efficiency is 26.52%, with Voc = 742.2 mV, Isc = 14.22 mA, and FF = 84.07%.

[0071] Example 6 (P++ / i / rich nitric acid) S1-S4 are as described above. S5: The patterned silicon wafer is immersed in a hydrofluoric acid (HF) solution for selective etching. The HF concentration is controlled at 1–30 wt%, and the etching time is 30–300 s. This completely removes the BSG in the exposed areas while retaining the BSG in the areas covered by the resist. The depatched silicon wafer is then cleaned in a mixed solution of nitric acid, HF, and deionized water for 120–300 s to complete the preparation of the p+ / i region. After etching, the wafer is cleaned with deionized water, and residual resist is removed by organic solvents or plasma.

[0072] S6-S8 as described above This embodiment discloses a back-junction p-type battery, the main structural parameters of which are as follows: Gallium-doped P-type single-crystal silicon wafers are used, with a resistivity of 1.5 Ω·cm and a thickness of 130 μm; Front side: Gate line spacing is 1100 μm; a selective emitter structure is set within each 1100 μm period, where the P++ doped region is 250 μm wide and the intrinsic region i is 850 μm wide, with the P++ doped region accounting for approximately 22.7% of the area; the surface activation concentration of the P++ doped region is 1×10^ 20 cm^ -3 In step S5, an intrinsic region is formed using a rich nitric acid etching process with an etching time of 300 s; a SiOx / AlOx / SiNx composite passivation structure is adopted on the front side; the P++ doped region J0,p++ has a strength of 8.0 fA / cm. 2 The intrinsic region J0,i is 0.7 fA / cm. 2 The front-side gate line width is 18 μm, and the gate line contact area composite density is 40 fA / cm. 2The contact resistivity is 1.5 mΩ·cm. 2 The height difference between the P++ doped region and the intrinsic region is 5.5 μm.

[0073] Back side: Except for the cleaved region, the remaining areas are n-type TOPCon structures; the passivation contact structure consists of a tunneling oxide layer and a phosphorus-doped polysilicon layer, wherein the thickness of the tunneling oxide layer is 1.5 nm and the thickness of the phosphorus-doped polysilicon layer is 120 nm; the J0,r of the back passivation contact region is 1.2 fA / cm. 2 The back-side gate line width is 18 μm, and the composite density in the contact area is 18 fA / cm. 2 The contact resistivity is 0.5 mΩ·cm. 2 .

[0074] The back of the battery features a PN junction-free cracked area with a width of 400 μm. The overall cell efficiency is 26.53%, with Voc = 742.5 mV, Isc = 14.20 mA, and FF = 84.15%.

[0075] Comparative Example 1 It uses a traditional PERC structure battery.

[0076] Gallium-doped P-type single-crystal silicon wafers are used, with a resistivity of 1.5 Ω·cm and a thickness of 130 μm.

[0077] Front side: Gate line spacing is 1100 μm; the entire front side is an N+ emitter structure formed by phosphorus diffusion, with a surface activation concentration of 1×10^ 20 cm^ -3 The AlOx / SiNx composite passivation structure is adopted; the N+ emitter J0 and n+ are 8.5 fA / cm. 2 The front-side gate line width is 18 μm, and the contact area recombination is 45 fA / cm. 2 The contact resistivity is 1.5 mΩ·cm. 2 .

[0078] Back side: Employs an aluminum back surface structure, with a back surface composite parameter J0,r of 12 fA / cm. 2 .

[0079] The overall cell efficiency is 23.2%, with Voc=694.5 mV, Isc=13.5 mA, and FF=82.5%.

[0080] Comparative Example 2 It adopts a conventional N-type TOPCon structure battery.

[0081] It uses an N-type single-crystal silicon wafer with a resistivity of 1.5 Ω·cm and a thickness of 130 μm.

[0082] Front side: Gate line spacing is 1100 μm; boron diffusion structure is adopted on the front side; the passivated contact area J0,f on the front side is 5.0fA / cm 2 The front-side gate line width is 18 μm, and the contact area recombination is 25 fA / cm. 2 The contact resistivity is 0.8 mΩ·cm. 2 .

[0083] Back side: Employs TOPCon structure, with a passivated contact area J0,r of 1.2 fA / cm. 2 .

[0084] The overall cell efficiency is 26.26%, with Voc=738.7 mV, Isc=14.16 mA, and FF=84.01%.

[0085] Comparative Example 3 A P-type battery with a full-surface P+ structure and a back junction.

[0086] Gallium-doped P-type single-crystal silicon wafers are used, with a resistivity of 1.5 Ω·cm and a thickness of 130 μm.

[0087] Front side: Gate line spacing is 1100 μm; the entire front side is a P+ doped region with a surface activation concentration of 8 × 10^6. 18 cm^-3; employs a SiOx / AlOx / SiNx composite passivation structure; front-side J0,p+ is 3.8 fA / cm 2 The front-side gate line width is 18 μm, and the composite density in the contact area is 40 fA / cm. 2 The contact resistivity is 1.5 mΩ·cm. 2 .

[0088] Back side: Except for the cleavage area, the remaining areas adopt the TOPCon structure; the passivated contact area J0,r on the back side has a value of 1.2fA / cm. 2 The back-side gate line width is 18 μm, and the composite density in the contact area is 18 fA / cm. 2 The contact resistivity is 0.5 mΩ·cm. 2 .

[0089] The overall cell efficiency is 26.33%, with Voc=740.8 mV, Isc=14.15 mA, and FF=83.9%.

[0090] Comparative Example 4 A back-junction P-type cell with a full-surface intrinsic region structure.

[0091] Gallium-doped P-type single-crystal silicon wafers are used, with a resistivity of 1.5 Ω·cm and a thickness of 130 μm.

[0092] Front side: Gate line spacing is 1100 μm; the entire front side is an intrinsic region structure; a SiOx / AlOx / SiNx composite passivation structure is adopted; the intrinsic region J0,i is 0.7 fA / cm 2 The width of the front grid line is 18 μm.

[0093] Since the electrode is in direct contact with the intrinsic region, the recombination rate in the contact region is 95 fA / cm. 2 The contact resistivity is 12 mΩ·cm 2 .

[0094] Back side: Except for the cleavage area, the remaining areas adopt the TOPCon structure; the passivated contact area J0,r on the back side has a value of 1.2fA / cm. 2 The back-side gate line width is 18 μm, and the composite density in the contact area is 18 fA / cm. 2 The contact resistivity is 0.5 mΩ·cm. 2 .

[0095] The back of the battery features a PN junction-free cracked area with a width of 400 μm. The overall cell efficiency is 26.23%, with Voc = 742.9 mV, Isc = 14.19 mA, and FF = 83.10%. The test results of Examples 1-6 and Comparative Examples 1-4 show that the present invention achieves synergistic optimization of contact performance and recombination suppression capability by constructing a back-side PN junction structure formed by a tunneling oxide layer / phosphorus-doped polycrystalline silicon on the back side of a gallium-doped P-type silicon wafer, and constructing a partitioned emitter structure composed of a P++ contact region and a P+ region or intrinsic region on the front side. Compared with Comparative Examples 1 and 2, the embodiments of the present invention all achieve higher open-circuit voltage and conversion efficiency; compared with Comparative Example 3, it shows that confining the highly doped region to the electrode contact position can effectively reduce recombination loss in the non-contact region; compared with Comparative Example 4, it shows that retaining the local P++ contact region is beneficial to reducing contact resistance and improving the fill factor. Furthermore, secondary texturing and nitric acid-rich treatment can reduce recombination in the non-contact region, and the use of the P++ / i structure can further improve the overall performance of the battery. Among them, Example 4 achieved the highest conversion efficiency of 26.56%, indicating that the present invention can effectively balance open-circuit voltage, short-circuit current and fill factor, thereby achieving a high-efficiency back-junction P-type battery.

[0096] In the description of this specification, the use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

Claims

1. A p-type solar cell with a back junction, comprising a p-type silicon substrate, wherein the p-type silicon substrate is a gallium-doped p-type silicon wafer, characterized in that: The p-type silicon substrate has a pn junction structure on its back side, and the pn junction structure includes a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer sequentially disposed on the silicon substrate. The p-type silicon substrate has a partitioned emitter structure on its front side, the partitioned emitter structure comprising: Multiple p++ doped regions are disposed in a low-doped region between adjacent p++ doped regions, wherein the low-doped region is a p+ doped region or an intrinsic region i; in: The activation concentration of the p++ doped region is higher than 1×10⁻⁶. 19 cm -3 ; The activation concentration of the p+ doped region is less than 2 × 10⁻⁶. 18 cm -3 .

2. A p-type battery with a back junction according to claim 1, characterized in that: The area ratio of the p++ doped region in the front side is ≤40%.

3. A p-type battery with a back junction according to claim 1, characterized in that: The i-region is formed by a combination of patterning and etching processes, including polymer mask patterning or laser patterning.

4. A p-type battery with a back junction according to claim 1, characterized in that: The front side is provided with a composite passivation structure consisting of a SiOx layer, an AlOx layer and a SiNx layer from the inside to the outside.

5. A back-junction p-type battery according to claim 1, characterized in that: The back surface is provided with a SiOx layer, an AlOx layer and a SiNx layer in sequence from the inside to the outside, or a SiOx layer, a carbon-nitrogen polycrystalline silicon layer, an AlOx layer and a SiNx layer in sequence.

6. A method for preparing a back-junction p-type battery according to any one of claims 1 to 5, characterized in that, Includes the following steps: S1. Provide p-type gallium-doped silicon wafers; S2. Clean and texturize the silicon wafers; S3. Pre-deposit boron source on the front side of the silicon wafer and perform preliminary diffusion to form a borosilicate glass layer; S4. The borosilicate glass layer is patterned to form a retention area and a removal area; S5. Remove the borosilicate glass layer in the removal area; S6. Perform high-temperature diffusion to form a p++ doped region in the retained region and a p+ doped region or i region in the removed region. S7. A tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are formed on the back side of the silicon wafer; S8. Perform passivation structure deposition, electrode preparation and post-processing.

7. The method for preparing a back-junction p-type battery according to claim 6, characterized in that: In step S4, the patterning process includes using a polymer mask combined with an etching process or using laser patterning combined with a wet etching process.

8. The method for preparing a back-junction p-type battery according to claim 6, characterized in that: In step S7, the phosphorus-doped polycrystalline silicon layer is formed by LPCVD deposition followed by doping, or by PECVD deposition followed by annealing.

9. The method for preparing a back-junction p-type battery according to claim 1, characterized in that: In step S6, region i is formed by etching with rich nitric acid for a time of 1–5 min, and / or The i-region is formed through a secondary texturing process, the secondary texturing time being 20–1200 s.

10. The method for preparing a back-junction p-type battery according to claim 1, characterized in that: After the battery is fabricated, the silicon wafer is split using a laser to divide it into multiple sub-cell units.

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