A flexible gallium arsenide solar cell and a method of manufacturing the same

Abstract

The present application relates to the technical field of semiconductor, in particular to a flexible gallium arsenide solar cell and a manufacturing method thereof. The flexible gallium arsenide solar cell comprises, from top to bottom, a gallium arsenide epitaxial layer, an Al2O3 passivation layer, a first dielectric bonding layer, a second dielectric bonding layer, a Cr transverse connecting layer and a polyimide flexible substrate. The application replaces the high-doped back field layer with the Al2O3 passivation layer, and sets a small-area embedded micro-needle part and a pad part on the back surface. During bonding annealing, Ti and InGaAs react in situ at the opening to form a low-resistance ohmic contact. The back electrode function is realized through the electrical connection among the micro-needle part, the pad part and the Cr transverse connecting layer. The flexible gallium arsenide solar cell provided by the application can realize high-quality back passivation, low-resistance ohmic contact and high-reliability flexible integration under the premise of avoiding the difficulty of high-doped epitaxial growth and not damaging the brittle epitaxial layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a flexible gallium arsenide solar cell and its fabrication method. Background Technology

[0002] Flexible gallium arsenide (GaAs) multi-junction solar cells have significant application value in fields such as space power and wearable energy. Among them, triple-junction GaAs cells employ a flip-chip process, with the P-type InGaAs base region of the bottom cell being the last epitaxial layer grown. An ideal back-side structure requires the continued growth of a highly doped back field layer and a contact layer. However, continuing to grow these layers on the surface of the P-type InGaAs base region faces challenges such as low doping efficiency of the P-type dopant and easy back diffusion of dopants into the base region. Forced growth can introduce defects, leading to a decrease in open-circuit voltage. Replacing the highly doped epitaxial layer with a low-temperature deposited Al2O3 dielectric layer for field-effect passivation can circumvent these growth difficulties, but the Al2O3 dielectric layer itself does not possess ohmic contact functionality. Furthermore, integrating the brittle epitaxial layer with a flexible substrate typically requires high-temperature hot-pressing conditions in existing bonding schemes, which easily leads to epitaxial layer cracking and reduces device fabrication yield. This application aims to provide a flexible gallium arsenide solar cell and its fabrication method, which simultaneously achieves high-quality back-side passivation, ohmic contact and high-reliability flexible integration while avoiding the difficulties of highly doped epitaxial growth and without damaging the brittle epitaxial layer. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to provide a flexible gallium arsenide solar cell and its fabrication method, which can achieve high-quality back-side passivation, ohmic contact, and high-reliability flexible integration without circumventing the difficulties of highly doped epitaxial growth and without damaging the brittle epitaxial layer.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: This invention provides a flexible gallium arsenide solar cell, comprising, from top to bottom, a gallium arsenide epitaxial layer, an Al2O3 passivation layer, a first dielectric bonding layer, a second dielectric bonding layer, a Cr lateral bonding layer, and a polyimide flexible substrate stacked sequentially. The back electrode of the solar cell includes a pad portion and a microneedle portion. The pad portion includes a first pad and a second pad, which are vertically aligned and electrically connected. The microneedle portion includes a first microneedle array and a second microneedle array, which are vertically aligned and electrically connected. The first pad and the first microneedle array both penetrate the first dielectric bonding layer and the Al2O3 passivation layer perpendicularly. The second pad and the second microneedle array both penetrate the second dielectric bonding layer perpendicularly and are electrically connected to the Cr lateral bonding layer. The gallium arsenide epitaxial layer has a stepped etching channel on the sidewall near the pad portion, which is etched from the upper surface of the gallium arsenide epitaxial layer to the upper surface of the pad portion. The first microneedle array has a seed layer and a copper core. The seed layer consists of a Ti layer, a Pt layer, and an Au layer arranged sequentially from the outside to the inside, with the Au layer in close contact with the copper core. The gallium arsenide epitaxial layer adopts a flip-chip grown triple-junction gallium arsenide structure. The triple-junction gallium arsenide structure includes a GaInP top cell, a first tunnel junction, a GaAs middle cell, a second tunnel junction, and an InGaAs bottom cell stacked sequentially from top to bottom. The InGaAs bottom cell includes an N-type AlInP window layer, an N-type InGaAs emitter layer, and a P-type InGaAs base region stacked sequentially from top to bottom. The upper surface of the first microneedle array is in contact with the lower surface of the P-type InGaAs base region, and an ohmic contact is formed through the solid-state reaction between Ti and InGaAs in the seed layer of the first microneedle array.

[0005] Furthermore, the P-type InGaAs base region is subjected to sulfur passivation treatment; the Al2O3 passivation layer has a thickness of 10nm to 30nm, the first dielectric bonding layer has a thickness of 1.5μm to 3μm, and the first microneedle array occupies 2% to 8% of the area of ​​the first dielectric bonding layer.

[0006] Furthermore, the thicknesses of the Ti layer, Pt layer, and Au layer are 20nm–40nm, 40nm–60nm, and 80nm–120nm, respectively; the thickness of the polyimide flexible substrate is 25μm–50μm; and the thickness of the Cr lateral bonding layer is 10nm–50nm.

[0007] This invention also provides a method for fabricating a flexible gallium arsenide solar cell, comprising the following steps: S1. On the surface of an N-type GaAs substrate, an AlGaInP sacrificial layer, a GaAs contact layer, a GaInP top cell, a first tunnel junction, a GaAs middle cell, a second tunnel junction, and an InGaAs bottom cell are grown sequentially by MOCVD, and the epitaxial growth continues until the P-type InGaAs base region of the InGaAs bottom cell is reached. S2. After cleaning the grown wafer, perform sulfur passivation treatment on the surface of the P-type InGaAs base region, and then sequentially fabricate an Al2O3 passivation layer and a first dielectric bonding layer on the surface of the sulfur passivated P-type InGaAs base region. S3. Prepare a first microneedle array and a first pad that penetrate the Al2O3 passivation layer and the first dielectric bonding layer; S4. The surface of the first dielectric bonding layer is subjected to CMP and plasma low-temperature activation treatment in sequence. S5. A polyimide flexible substrate, a Cr lateral bonding layer, and a second dielectric bonding layer are sequentially prepared on the surface of a temporary glass slide. S6. Prepare a second microneedle array and a second pad that penetrate the second dielectric bonding layer; S7. The surface of the second dielectric bonding layer is subjected to CMP and plasma low-temperature activation treatment in sequence. S8. Align the first dielectric bonding layer and the second dielectric bonding layer, and perform pre-bonding under vacuum, room temperature and pressure of 0.01MPa to 0.05MPa. Anneal the pre-bonded wafer under a reducing atmosphere at atmospheric pressure and 300 to 400°C. S9. After bonding is completed, the N-type GaAs substrate and AlGaInP sacrificial layer on the gallium arsenide epitaxial layer are removed to expose the GaAs contact layer. Then, the front electrode and antireflection film are fabricated in sequence. S10. Define the pattern of the back pad by front photolithography, and use Cl-based ICP etching to penetrate the gallium arsenide epitaxial layer from top to bottom until the upper surface of the first pad is fully exposed. S11. Use an excimer laser to uniformly scan and irradiate the back of the temporary glass slide to peel the polyimide flexible substrate off the temporary glass slide. S12. Use a wafer dicing machine to separate the cells into individual battery chips, and then perform photoelectric performance testing and sorting.

[0008] Furthermore, in S2, the sulfur passivation treatment method is to clean the grown wafer, immerse it in a 4% to 10% ammonium sulfate solution for 10 to 15 minutes, and then dry it with nitrogen gas.

[0009] Furthermore, in S2, the Al2O3 passivation layer is prepared by using trimethylaluminum and deionized water as precursors, with a substrate temperature of 240℃~260℃, and depositing Al2O3 on the surface of the sulfur-passivated P-type InGaAs base region by alternating pulses, with the thickness of the prepared Al2O3 passivation layer being 10nm~30nm.

[0010] Furthermore, in S3, the fabrication method of the first microneedle array and the first pad includes the following steps: S31. Spin-coat photoresist onto the surface of the first dielectric bonding layer, use a stepper lithography machine to expose and define the first microneedle array and the first pad pattern, develop and then perform hard film curing. Use an ICP device with a CF4 / O2 mixed gas with a flow ratio of 10:1 as the gas source and a bias power of 150W to rapidly etch the first dielectric bonding layer until the remaining 80nm~120nm is stopped. Reduce the bias power to 50W, adjust the flow ratio of the CF4 / O2 mixed gas to 5:1, and etch to the surface of the Al2O3 passivation layer. Use BCl3 / Ar as the etching gas to etch through the Al2O3 passivation layer to expose the surface of the P-type InGaAs base region. S32. The photoresist is removed by immersion in acetone, the residual photoresist residue is removed by oxygen plasma treatment, the photoresist is immersed in dilute hydrochloric acid for 30 seconds, and the surface is treated in situ by H2 plasma. S33. Ti / Pt / Au are sequentially deposited as a seed layer using electron beam evaporation, and copper is filled to a height above the surface of the first dielectric bonding layer using a pulsed electroplating process, wherein the forward pulse current density is 2A / dm². 2 Reverse pulse current density 0.5 A / dm 2 The duty cycle is 1:10.

[0011] Furthermore, in S6, the fabrication method of the second microneedle array and the second pad includes the following steps: S61. Spin-coat photoresist onto the surface of the second dielectric bonding layer, use a stepper lithography machine to expose and define the second microneedle array and the second pad pattern, develop and then harden the film. Use an ICP device with a CF4 / O2 mixed gas with a flow ratio of 10:1 as the gas source and a bias power of 150W to rapidly etch the second dielectric bonding layer until the remaining 80nm~120nm is reached and then stop. Reduce the bias power to 50W, adjust the flow ratio of the CF4 / O2 mixed gas to 5:1, and etch to expose the surface of the Cr lateral interconnect layer. S62. The photoresist is removed by immersion in acetone, the residual photoresist residue is removed by oxygen plasma treatment, and the surface is treated in situ by H2 plasma. S63. Cr / Cu is sequentially deposited as a seed layer using electron beam evaporation, and copper is then filled to a level above the surface of the second dielectric bonding layer using pulse electroplating. The forward pulse current density is 2 A / dm². 2 Reverse pulse current density 0.5 A / dm 2 The duty cycle is 1:10.

[0012] Furthermore, in S4 and S7, the specific CMP method is as follows: CMP is performed on the back side of the wafer using an alkaline silicon dioxide polishing slurry containing copper corrosion inhibitor. The optical reflectivity endpoint detection system is used for real-time monitoring. When polishing reaches the surface of the first dielectric bonding layer or the second dielectric bonding layer, a sudden change in reflectivity triggers the stop. After polishing, the metal and the first dielectric bonding layer or the second dielectric bonding layer are globally coplanar, with a flatness deviation of less than 50 nm and a surface roughness Ra < 0.5 nm. In S4 and S7, the specific method of plasma low-temperature activation treatment is to remove residual abrasive and metal ions from the surface of the CMP wafer with acid cleaning solution, and to perform Ar / O2 mixed plasma low-temperature activation treatment on the surface of the first dielectric bonding layer or the second dielectric bonding layer.

[0013] Furthermore, in S8, the specific bonding method includes the following steps: S81. When aligning the first dielectric bonding layer and the second dielectric bonding layer, align the first microneedle array with the second microneedle array one by one, align the first pad and the second pad, load the wafer bonding machine, and apply a pressure of 0.01MPa to 0.05MPa for pre-bonding in a vacuum environment and at room temperature. S82. The pre-bonded wafer is placed into an annealing furnace and annealed at 300℃~400℃ in a 95%N2 / 5%H2 mixed atmosphere at a heating rate of 5℃ / min. After holding at this temperature for 30 minutes, the temperature is allowed to drop naturally.

[0014] Compared with the prior art, the beneficial effects of the present invention are: 1. The flexible gallium arsenide solar structure provided in this application replaces the epitaxial highly doped back field layer with an Al2O3 passivation layer. By performing sulfur passivation pretreatment on the surface of the P-type InGaAs base region, the dangling bonds between sulfur atoms and the InGaAs surface reduce the InGaAs interface state density, making the interface between the Al2O3 and InGaAs deposited by ALD cleaner and with better adhesion. The Al2O3 passivation layer deposited by the low-temperature ALD process is used to induce an inversion layer on the base surface by fixing negative charges, which fundamentally avoids the difficulty of growing a highly doped layer at the end of flip-chip epitaxy. The Al2O3 passivation layer and the first dielectric bonding layer have good bonding performance, which can ensure good bonding reliability between the Al2O3 passivation layer and the first dielectric bonding layer. By setting a very small area of ​​embedded microneedles and pads on the back side, Ti and InGaAs react in situ at the opening during bonding annealing to form a low-resistance ohmic contact. The back electrode function is realized through the electrical connection between the microneedles, the pads and the Cr lateral connection layer. The window of the embedded microneedles occupies only a very small proportion of the back side, and most of the area retains the complete Al2O3 passivation layer, while realizing the ohmic contact window, the bonding conductive path and the coplanar plane. The aforementioned back-side bonding structure has a first dielectric bonding layer with a first pad and a first microneedle array on the relatively flat surface of the Al2O3 passivation layer on the epitaxial side, and a second dielectric bonding layer with a second pad and a second microneedle array on the surface of the Cr lateral connection layer on the flexible substrate side. This structure can achieve low-temperature pressureless bonding by relying on SiO2 surface activation and copper atom interdiffusion, avoiding epitaxial layer cracking caused by traditional hot pressing.

[0015] 2. Based on the back-side structure designed in this application, and considering the extremely thin and low mechanical strength of the gallium arsenide epitaxial layer, this application designs a hybrid bonding method combining low-pressure pre-bonding and pressureless annealing. Bonding is achieved through SiO2 surface activation and copper atom interdiffusion, avoiding epitaxial layer cracking caused by traditional hot pressing. The entire annealing process simultaneously completes dielectric bonding, metallic bonding, and ohmic contact formation. Back-side passivation is achieved by replacing the highly doped epitaxial layer with a dielectric layer, large-area passivation is achieved with a very small contact area, and non-destructive integration of the brittle epitaxial layer is achieved through pressureless permanent bonding. The entire process eliminates the need for growing a highly doped epitaxial layer, applying no external mechanical pressure during permanent bonding, and requiring no separate alloying annealing, thus avoiding epitaxial layer cracking caused by traditional hot pressing. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the structure of the gallium arsenide epitaxial side after fabrication of the first pad and the first microneedle array, as shown in some embodiments of this application; Figure 2 for Figure 1 A magnified view of part A in the middle; Figure 3 This is a schematic diagram of the structure of the polyimide flexible substrate side after the fabrication of the second pad and the second microneedle array, as shown in some embodiments of this application; Figure 4 This is a schematic diagram of the battery intermediate structure after bonding is completed, as shown in some embodiments of this application; Figure 5 This is a schematic diagram of the battery intermediate structure after the antireflection film is prepared, as shown in some embodiments of this application; Figure 6 This is a schematic diagram of the battery intermediate structure after removing the temporary glass substrate, as shown in some embodiments of this application; Figure 7 This is a schematic diagram of the structure of a flexible gallium arsenide solar cell product as shown in some embodiments of this application; Figure descriptions: 1. Gallium arsenide epitaxial layer; 11. GaInP top cell; 12. First tunnel junction; 13. GaAs middle cell; 14. Second tunnel junction; 15. InGaAs bottom cell; 151. N-type AlInP window layer; 152. N-type InGaAs emitter layer; 153. P-type InGaAs base region; 2. Al2O3 passivation layer; 3. First dielectric bonding layer; 4. Second dielectric bonding layer; 5. Cr lateral bonding layer; 6. Back electrode; 61. Pad 611, First pad; 612, Second pad; 62, Microneedle section; 621, First microneedle array; 622, Second microneedle array; 7, Polyimide flexible substrate; 8, GaAs contact layer; 9, Front electrode; 10, Anti-reflective coating; 21, Copper core; 22, Ti layer; 23, Pt layer; 24, Au layer; 25, Seed layer; 26, Stepped etching channel; 100, N-type GaAs substrate; 200, AlGaInP sacrificial layer; 300, Temporary glass carrier. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0019] In the description of this application, it should be understood that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application.

[0020] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0021] The following is in conjunction with the accompanying drawings in the instruction manual. Figures 1 to 7 This application will be described in further detail as follows: This invention provides a flexible gallium arsenide solar cell, comprising a gallium arsenide epitaxial layer 1, an Al2O3 passivation layer 2, a first dielectric bonding layer 3, a second dielectric bonding layer 4, a Cr lateral bonding layer 5, and a polyimide flexible substrate 7 stacked sequentially from top to bottom; The back electrode 6 of the solar cell includes a pad portion 61 and a microneedle portion 62. The pad portion 61 includes a first pad 611 and a second pad 612, which are vertically aligned and electrically connected. The microneedle portion 62 includes a first microneedle array 621 and a second microneedle array 622, which are vertically aligned and electrically connected. Both the first pad 611 and the first microneedle array 621 vertically penetrate the first dielectric bonding layer 3 and the Al2O3 passivation layer 2. The upper surface of the first microneedle array 621 is flush with the upper surface of the Al2O3 passivation layer 2. The lower surface of 611 is flush with the lower surface of the first dielectric bonding layer 3; the second pad 612 and the second microneedle array 622 both penetrate the second dielectric bonding layer 4 vertically, the upper surfaces of the second pad 612 and the second microneedle array 622 are flush with the upper surface of the second dielectric bonding layer 4, the lower surfaces of the second pad 612 and the second microneedle array 622 are flush with the lower surface of the second dielectric bonding layer 4, and the second pad 612 and the second microneedle array 622 are electrically connected to the Cr lateral connection layer 5; the sidewall of the gallium arsenide epitaxial layer 1 near the pad portion 61 has a stepped etching channel 26, which is etched from the upper surface of the gallium arsenide epitaxial layer 1 to the upper surface of the pad portion 61; The first microneedle array 621 has a seed layer 25 and a copper core 21. The seed layer 25 consists of a Ti layer 22, a Pt layer 23, and an Au layer 24 arranged sequentially from the outside to the inside. The Au layer 24 is in close contact with the copper core 21. The gallium arsenide epitaxial layer 1 adopts a flip-chip grown triple-junction gallium arsenide structure. The triple-junction gallium arsenide structure includes a GaInP top cell 11, a first tunnel junction 12, a GaAs middle cell 13, a second tunnel junction 14, and an InGaAs bottom cell 15 stacked sequentially from top to bottom. The InGaAs bottom cell 15 includes an N-type AlInP window layer 151, an N-type InGaAs emitter layer 152, and a P-type InGaAs base region 153 stacked sequentially from top to bottom. The upper surface of the first microneedle array 621 is in contact with the lower surface of the P-type InGaAs base region 153, and an ohmic contact is formed through the solid-state reaction between the Ti layer 22 and InGaAs.

[0022] In a preferred embodiment, the P-type InGaAs base region 153 is treated with sulfur passivation; the thickness of the Al2O3 passivation layer 2 is 10nm to 30nm. When the thickness of the Al2O3 passivation layer 2 is less than 10nm, the total amount of fixed negative charge is insufficient, and the field effect passivation effect is weakened. When the thickness of the Al2O3 passivation layer 2 is greater than 30nm, the difficulty of etching and opening windows increases, and the dielectric stress increases. The Al2O3 passivation layer 2 is closely attached to the surface of the P-type InGaAs base region 153, and the fixed negative charge inside it induces the formation of an inversion layer on the surface of the base region, which significantly reduces the surface recombination rate and achieves an equivalent back-side passivation effect without relying on a highly doped epitaxial layer. The thickness of the first dielectric bonding layer 3 is 1.5 μm to 3 μm. When the thickness of the first dielectric bonding layer 3 is less than 1.5 μm, the mechanical strength of the dielectric layer is insufficient, and there is a risk of breakage during CMP. When the thickness of the first dielectric bonding layer 3 is greater than 3 μm, the difficulty of etching and windowing increases significantly. It should be noted that the first microneedle array 621 and the second microneedle array 622 in this application refer to a number of microneedle structures arranged in an array pattern. The area of ​​the first microneedle array 621 (i.e., the total cross-sectional area of ​​the number of microneedles) accounts for 2% to 8% of the area of ​​the first dielectric bonding layer 3. When the area ratio is 2%, the passivation coverage reaches 98%, which is suitable for scenarios with low current density. When the area ratio is 8%, the passivation coverage is 92%, which is suitable for scenarios with higher requirements for current collection capability.

[0023] The flexible gallium arsenide solar structure provided in this application replaces the epitaxial highly doped back field layer with an Al2O3 passivation layer. By performing sulfur passivation pretreatment on the surface of the P-type InGaAs base region, the dangling bonds between sulfur atoms and the InGaAs surface reduce the InGaAs interface state density, making the interface between the Al2O3 and InGaAs deposited by ALD cleaner and with better adhesion. The Al2O3 passivation layer deposited by the low-temperature ALD process is used to induce an inversion layer on the base surface by fixing negative charges, which fundamentally avoids the difficulty of growing a highly doped layer at the end of flip-chip epitaxy. The Al2O3 passivation layer and the first dielectric bonding layer 3 have good bonding performance, which can ensure good bonding reliability between the Al2O3 passivation layer and the first dielectric bonding layer 3. By setting a very small area of ​​embedded microneedles and pads on the back side, Ti and InGaAs react in situ at the opening during bonding annealing to form a low-resistance ohmic contact. The back electrode function is realized through the electrical connection between the microneedles, the pads and the Cr lateral connection layer. The window of the embedded microneedles occupies only a very small proportion of the back side, and most of the area retains the complete Al2O3 passivation layer, while realizing the ohmic contact window, the bonding conductive path and the coplanar plane. The aforementioned back-side bonding structure has a first dielectric bonding layer with a first pad and a first microneedle array on the relatively flat surface of the Al2O3 passivation layer on the epitaxial side, and a second dielectric bonding layer with a second pad and a second microneedle array on the surface of the Cr lateral connection layer on the flexible substrate side. This structure can achieve low-temperature pressureless bonding by relying on SiO2 surface activation and copper atom interdiffusion, avoiding epitaxial layer cracking caused by traditional hot pressing.

[0024] In a preferred embodiment, the thicknesses of Ti layer 22, Pt layer 23 and Au layer 24 in the seed layer 25 are 20nm-40nm, 40nm-60nm and 80nm-120nm respectively; wherein the Ti layer serves as an adhesion layer and ohmic contact reaction material, the Pt layer serves as a diffusion barrier layer and the Au layer serves as an electroplating seed layer. In a preferred embodiment, the thickness of the polyimide flexible substrate 7 is 25 μm to 50 μm; In a preferred embodiment, the thickness of the Cr transverse connecting layer 5 is 10 nm to 50 nm.

[0025] In a preferred embodiment, the light-receiving surface of the solar cell further includes a GaAs contact layer 8, a front electrode 9, and an antireflection film 10; the GaAs contact layer 8 is disposed on the surface of the gallium arsenide epitaxial layer 1 away from the Al2O3 passivation layer 2, and the GaAs contact layer 8 adopts a patterned structure to reduce light absorption; the front electrode 9 is disposed on the surface of the GaAs contact layer 8, and the antireflection film 10 is disposed on the portion of the light-receiving surface of the gallium arsenide epitaxial layer 1 excluding the area covered by the GaAs contact layer 8; the front electrode 9 comprises AuGe / Ni / Ag / Au stacked sequentially from bottom to top; the antireflection film 10 comprises a TiO2 layer and an Al2O3 layer stacked sequentially from bottom to top, with optical thicknesses of 350 nm and 600 nm, respectively.

[0026] According to some preferred embodiments, the first dielectric bonding layer 3 and the second dielectric bonding layer 4 are made of silicon dioxide; according to another preferred embodiment, the first dielectric bonding layer 3 and the second dielectric bonding layer 4 are sequentially deposited SiO2 / SiN x Layering.

[0027] Another embodiment of the present invention provides a method for fabricating a flexible gallium arsenide solar cell, comprising the following steps: S1. On the surface of the N-type GaAs substrate 100, an AlGaInP sacrificial layer 200, a GaAs contact layer 8, a GaInP top cell 11, a first tunnel junction 12, a GaAs middle cell 13, a second tunnel junction 14, and an InGaAs bottom cell 15 are grown sequentially by MOCVD. The epitaxial growth continues until the P-type InGaAs base region 153 of the InGaAs bottom cell 15 is reached. No further growth is made of the overall heavily doped P-type InGaAs back field layer and the heavily doped P-type InGaAs contact layer.

[0028] S2. After cleaning the grown wafer, sulfur passivation treatment is performed on the surface of the P-type InGaAs base region 153. Sulfur passivation treatment can effectively reduce the initial state density of the InGaAs surface and provide a high-quality interface for subsequent alumina deposition. Then, Al2O3 passivation layer 2 and first dielectric bonding layer 3 are sequentially fabricated on the surface of the sulfur passivated P-type InGaAs base region 153. The Al2O3 passivation layer 2 is used to fix the negative charge to achieve field effect passivation, and the first dielectric bonding layer 3 is used as the main medium for mixed bonding.

[0029] In a preferred embodiment, in S2, the sulfur passivation treatment method is to clean the grown wafer, immerse it in an ammonium sulfate solution with a concentration of 4% to 10% for 10 to 15 minutes, and then dry it with nitrogen gas.

[0030] As a preferred embodiment, the method for preparing the ALD field-effect Al2O3 passivation layer 2 is as follows: using trimethylaluminum and deionized water as precursors, the substrate temperature is 250°C, the TMA source bottle temperature is 20°C–40°C, the deionized water source bottle temperature is 20°C–50°C, and the carrier gas is high-purity Ar or N2 with a flow rate of 50 sccm–200 sccm, using alternating pulse deposition. The TMA pulse time is 0.1 s–0.5 s, and the deionized water pulse time is 0.1 s–0.5 s. According to some preferred embodiments, the thickness of the prepared Al2O3 passivation layer 2 is 10 nm–30 nm. When the thickness of the Al2O3 passivation layer 2 is less than 10 nm, the total amount of fixed negative charge is insufficient, and the field-effect passivation effect is weakened; when the thickness of the Al2O3 passivation layer 2 is greater than 30 nm, the difficulty of etching and windowing increases, and the dielectric stress increases. The Al2O3 passivation layer 2 is closely attached to the surface of the P-type InGaAs base region 153. The fixed negative charge inside it induces the formation of an inversion layer on the surface of the base region, which significantly reduces the surface recombination rate and achieves an equivalent back-side passivation effect without relying on a highly doped epitaxial layer.

[0031] In a preferred embodiment, the first dielectric bonding layer 3 is prepared on the surface of the Al2O3 passivation layer 2 by PECVD. According to some preferred embodiments, the thickness of the first dielectric bonding layer 3 is 1.5μm to 3μm. When the thickness of the first dielectric bonding layer 3 is less than 1.5μm, the mechanical strength of the dielectric layer is insufficient, and there is a risk of cracking during CMP. When the thickness of the first dielectric bonding layer 3 is greater than 3μm, the difficulty of etching and opening windows increases significantly.

[0032] S3. Prepare a first microneedle array 621 and a first pad 611 that penetrate the Al2O3 passivation layer 2 and the first dielectric bonding layer 3; In a preferred embodiment, the fabrication method of the first microneedle array 621 and the first pad 611 in step S3 includes the following steps: S31. Photoresist is spin-coated onto the surface of the first dielectric bonding layer 3. A stepper lithography machine is used to expose and define the patterns of the first microneedle array 621 and the first pad 611 (the pattern of the first pad 611 can be set on the opposite side of the front electrode 9, close to the edge of the gallium arsenide epitaxial layer 1, which is beneficial for subsequent wire bonding. The first microneedle array 621 is uniformly distributed on the other areas of the first dielectric bonding layer 3 except for the first pad 611, thereby achieving uniform back-side current conduction). The size of a single microneedle in the first microneedle array 621 can be selected from 30μm×30μm to 80μm×80μm; the total area ratio of the first microneedle array 621 can be selected from 2% to 8%. When the total area ratio is 2%, the passivation coverage reaches 98%, which is suitable for scenarios with low current density; when the total area ratio is 8%, the passivation coverage is 92%, which is suitable for scenarios with higher requirements for current collection capability. The first pad 611 is used for the final external wire bonding. Its size is much larger than that of a single microneedle. In this application, the single-sided size of the first pad 611 is not less than 0.4 mm. After development, hard film curing is performed. ICP equipment is used with a CF4 / O2 mixed gas with a flow ratio of 10:1 as the gas source and a bias power of 150W. The first dielectric bonding layer 3 is rapidly etched until 80nm to 120nm remains. The bias power is then reduced to 50W, and the flow ratio of the CF4 / O2 mixed gas is adjusted to 5:1 to etch to the surface of the Al2O3 passivation layer 2. A BCl3 / Ar with a flow ratio of 3:1 is used as the etching gas to etch through the Al2O3 passivation layer 2 to expose the surface of the P-type InGaAs base region 153. The above step-by-step etching method can effectively avoid plasma damage to the base region surface caused by over-etching. S32. Remove photoresist by immersion in acetone, and remove residual photoresist residue by oxygen plasma treatment. The oxygen plasma treatment power is 50W~100W, the O2 flow rate is 20sccm~50sccm, and the time is 1min~3min. Remove the etched and exposed GaAs surface oxides by immersion in dilute hydrochloric acid for 30s, and perform in-situ surface treatment with H2 plasma. The H2 plasma flow rate is 10sccm~30sccm, the power is 50W~100W, the time is 10s~30s, and the gas pressure is 0.5Pa~1Pa. Then quickly transfer to the coating step. S33. A Ti layer 22, a Pt layer 23, and an Au layer 24 are sequentially deposited using electron beam evaporation as a seed layer 25. Copper is then filled to a depth of 0.3 μm to 1 μm above the surface of the first dielectric bonding layer 3 using a pulse electroplating process as a pre-removal allowance for CMP. The forward pulse current density is 2 A / dm². 2 Reverse pulse current density 0.5 A / dm 2 The duty cycle is 1:10.

[0033] S4. The surface of the first dielectric bonding layer 3 is sequentially subjected to CMP and plasma low-temperature activation treatment; In a preferred embodiment, CMP in S4 uses an alkaline silica polishing slurry containing a copper corrosion inhibitor. The main components of the alkaline silica polishing slurry containing a copper corrosion inhibitor are 5%–15% colloidal silica abrasive particles, 0.1%–0.5% benzotriazole corrosion inhibitor, and 0.5%–2% hydrogen peroxide hydroxide, with a pH value of 10.5–11.0. The polishing pressure is 10 kPa–21 kPa, the polishing disc speed is 60 rpm–100 rpm, the polishing slurry flow rate is 50 mL / min–100 mL / min, and polishing is carried out at room temperature. The process is monitored in real time using an optical reflectivity endpoint detection system. When polishing reaches the surface of the first dielectric bonding layer 3, a sudden change in reflectivity triggers the stop. After polishing, the metal and the first dielectric bonding layer 3 achieve global coplanarity, with a flatness deviation of less than 50 nm and a surface roughness Ra < 0.5 nm. In a preferred embodiment, in S4, the specific method of plasma low-temperature activation treatment is as follows: after CMP, the wafer is cleaned with an acid cleaning solution to remove residual abrasive and metal ions from the surface, and the surface of the first dielectric bonding layer 3 is subjected to Ar / O2 mixed plasma low-temperature activation treatment. In a preferred embodiment, after CMP, residual abrasive and metal ions are removed with a dilute organic acid cleaning solution. The cleaning solution is a mixed aqueous solution of citric acid and hydrogen peroxide, with a citric acid mass fraction of 1% to 5%, a hydrogen peroxide mass fraction of 0.5% to 2%, and the remainder being deionized water. The solution is soaked and cleaned at room temperature for 30 to 60 seconds, followed by rinsing with deionized water and drying with nitrogen. The bonding surface is then subjected to low-temperature activation treatment with Ar / O2 mixed plasma. The process parameters for Ar / O2 mixed plasma low-temperature activation treatment are as follows: Ar flow rate 20 sccm–50 sccm, O2 flow rate 5 sccm–15 sccm, Ar / O2 flow rate ratio 3:1 to 5:1, preferably 4:1; RF power 50 W–150 W, preferably 100 W; chamber pressure 0.5 Pa–2 Pa; treatment time 15 s–60 s, preferably 30 s; treatment temperature below 100℃, which is considered a low-temperature treatment. After activation, a high density of Si-OH dangling bonds is generated on the SiO2 surface, providing reactivity for dehydration condensation covalent bonding during annealing. After activation, the surface should be immediately sent to a bonding machine for pre-bonding, with the interval controlled within 30 minutes to avoid attenuation of surface hydroxyl density.

[0034] S5. A polyimide flexible substrate 7, a Cr lateral bonding layer 5, and a second dielectric bonding layer 4 are sequentially fabricated on the surface of a temporary glass substrate 300. The polyimide flexible substrate 7 has a thickness of 25 μm to 50 μm, providing good temperature resistance and compatibility with the annealing temperature of subsequent hybrid bonding. The Cr lateral bonding layer 5 has a thickness of 10 nm to 50 nm. When the thickness of the Cr lateral bonding layer 5 is less than 10 nm, the lateral conductivity is insufficient. When the thickness of the Cr lateral bonding layer 5 is greater than 50 nm, the film stress increases, posing a risk of peeling off from the PI substrate. The Cr lateral bonding layer 5 electrically connects the microneedle portion 62 to the back lead-out pad portion 61, realizing the lateral current convergence on the flexible substrate side.

[0035] S6. Prepare a second microneedle array 622 and a second pad 612 that penetrate the second dielectric bonding layer 4; In a preferred embodiment, in step S6, the method for fabricating the second microneedle array 622 and the second pad 612 includes the following steps: S61. Spin-coat photoresist onto the surface of the second dielectric bonding layer 4. Use a stepper lithography machine to expose and define the patterns of the second microneedle array 622 and the second pad 612 (the patterns of the second microneedle array 622 and the second pad 612 need to correspond one-to-one with the patterns of the first microneedle array 621 and the first pad 611, respectively, so as to ensure that they can be aligned one-to-one after bonding and achieve electrical connection). After development, perform hard film curing. Use an ICP device with a CF4 / O2 mixed gas with a flow ratio of 10:1 as the gas source and a bias power of 150W to rapidly etch the second dielectric bonding layer 4 until the remaining 80nm~120nm is stopped. Reduce the bias power to 50W and adjust the flow ratio of the CF4 / O2 mixed gas to 5:1 to etch to expose the surface of the Cr lateral connection layer 5. S62. The photoresist is removed by immersion in acetone, the residual photoresist residue is removed by oxygen plasma treatment, and the surface is treated in situ by H2 plasma. S63. Cr / Cu is sequentially deposited as a seed layer 25 using electron beam evaporation, with thicknesses of 80 nm and 100 nm respectively. Copper is then filled to a height above the surface of the second dielectric bonding layer 4 using a pulsed electroplating process, wherein the forward pulse current density is 2 A / dm². 2 Reverse pulse current density 0.5 A / dm 2 The duty cycle is 1:10.

[0036] S7. The surface of the second dielectric bonding layer 4 is subjected to CMP and plasma low-temperature activation treatment in sequence. In a preferred embodiment, CMP in S7 uses an alkaline silica polishing slurry containing a copper corrosion inhibitor. The main components of the alkaline silica polishing slurry containing a copper corrosion inhibitor are 5%–15% colloidal silica abrasive particles, 0.1%–0.5% benzotriazole corrosion inhibitor, and 0.5%–2% hydrogen peroxide hydroxide, with a pH value of 10.5–11.0. The polishing pressure is 10 kPa–21 kPa, the polishing disc speed is 60 rpm–100 rpm, the polishing slurry flow rate is 50 mL / min–100 mL / min, and polishing is carried out at room temperature. The process is monitored in real time using an optical reflectivity endpoint detection system. When polishing reaches the surface of the second dielectric bonding layer 4, a sudden change in reflectivity triggers the stop. After polishing, the metal and the second dielectric bonding layer 4 achieve global coplanarity, with a flatness deviation of less than 50 nm and a surface roughness Ra < 0.5 nm. In a preferred embodiment, in S7, the specific method of plasma low-temperature activation treatment is to remove residual abrasive and metal ions from the surface of the CMP wafer using an acid cleaning solution, and to perform Ar / O2 mixed plasma low-temperature activation treatment on the surface of the second dielectric bonding layer 4.

[0037] In a preferred embodiment, in S7, the specific method of plasma low-temperature activation treatment is as follows: after CMP, the wafer is cleaned with an acid cleaning solution to remove residual abrasive and metal ions from the surface, and the surface of the second dielectric bonding layer 4 is subjected to Ar / O2 mixed plasma low-temperature activation treatment. In a preferred embodiment, after CMP, residual abrasive and metal ions are removed with a dilute organic acid cleaning solution. The cleaning solution is a mixed aqueous solution of citric acid and hydrogen peroxide, with a citric acid mass fraction of 1%–5%, a hydrogen peroxide mass fraction of 0.5%–2%, and the remainder being deionized water. The solution is soaked and cleaned at room temperature for 30–60 seconds, followed by rinsing with deionized water and drying with nitrogen. The bonding surface is then subjected to low-temperature activation treatment with Ar / O2 mixed plasma. The process parameters for Ar / O2 mixed plasma low-temperature activation treatment are as follows: Ar flow rate 20 sccm–50 sccm, O2 flow rate 5 sccm–15 sccm, Ar / O2 flow rate ratio 3:1 to 5:1, preferably 4:1; RF power 50 W–150 W, preferably 100 W; chamber pressure 0.5 Pa–2 Pa; treatment time 15 s–60 s, preferably 30 s; treatment temperature below 100℃, which is considered a low-temperature treatment. After activation, a high density of Si-OH dangling bonds is generated on the SiO2 surface, providing reactivity for dehydration condensation covalent bonding during annealing. After activation, the surface should be immediately sent to a bonding machine for pre-bonding, with the interval controlled within 30 minutes to avoid attenuation of surface hydroxyl density.

[0038] S8. Align the first dielectric bonding layer 3 and the second dielectric bonding layer 4, and perform pre-bonding under vacuum, room temperature and pressure of 0.01MPa to 0.05MPa. Then, anneal and bond the pre-bonded wafer under a reducing atmosphere at atmospheric pressure and 300 to 400°C. In a preferred embodiment, the bonding method in S8 includes the following steps: S81, when the first dielectric bonding layer 3 and the second dielectric bonding layer 4 are aligned, the first pad 611 and the first microneedle array 621 are aligned with the second pad 612 and the second microneedle array 622 one by one, and then loaded into the wafer bonding machine. Under vacuum environment and room temperature, a pressure of 0.01MPa to 0.05MPa is applied for pre-bonding. The pre-bonding uses a lower pressure to overcome the initial unevenness of the wafer, so that the bonding interface reaches the van der Waals force action distance and achieves stable temporary bonding. S82. The pre-bonded wafer is placed in an annealing furnace and annealed at 300℃~400℃ under a 95%N2 / 5%H2 mixed atmosphere at a heating rate of 5℃ / min. After holding at this temperature for 30 minutes, it is allowed to cool naturally. No external mechanical pressure is applied during the entire annealing process. When the annealing temperature is below 300℃, the interdiffusion rate of Cu atoms is insufficient, the bonding strength decreases, and the Ti / InGaAs solid-phase reaction is incomplete. When the temperature is above 400℃, the diffusion barrier ability of the Pt layer begins to degrade. Through the above annealing process, the Si-OH groups on the surface of the first dielectric bonding layer 3 or the second dielectric bonding layer 4 on both sides undergo dehydration condensation to form Si-O-Si covalent bonds, completing the permanent dielectric bonding. The copper cores in the microneedle part 62 and the pad part 61 on both sides form Cu-Cu metallurgical bonding through atomic interdiffusion, establishing vertical electrical conduction. At the same time, Ti in the seed layer 25 reacts with the InGaAs base region to generate intermetallic compounds such as TiAs and TiGa, forming a low-resistance ohmic contact in situ. The Pt layer effectively prevents Cu from diffusing into the semiconductor.

[0039] S9. After bonding is completed, the N-type GaAs substrate 100 and AlGaInP sacrificial layer 200 on the gallium arsenide epitaxial layer 1 are removed to expose the GaAs contact layer 8. Then, the front electrode 9 and the anti-reflection film 10 are prepared in sequence. Preferably, an AuGe / Ni / Ag / Au metal stack is deposited by electron beam evaporation as the front electrode 9. After stripping, it is alloyed to form an N-type GaAs ohmic contact. The GaAs contact material outside the gate line is selectively etched to reduce parasitic absorption of incident light and improve the short-circuit current of the battery. TiO2 / Al2O3 is deposited sequentially by electron beam thermal evaporation to prepare an antireflection film 10 with an optical thickness of 350nm / 600nm.

[0040] S10. Define the pattern of the back pad 61 by front photolithography, and use Cl-based ICP etching to penetrate the gallium arsenide epitaxial layer 1 from top to bottom until the upper surface of the first pad 611 is fully exposed. S11. Use an excimer laser to uniformly scan and irradiate the back of the temporary glass slide 300 to peel the polyimide flexible substrate 7 off the temporary glass slide 300. S12. Use a wafer dicing machine to separate the cells into individual battery chips, and then perform photoelectric performance testing and sorting.

[0041] To address the challenges of extremely thin gallium arsenide epitaxial layers and their low mechanical strength, this application proposes a hybrid bonding method combining low-pressure pre-bonding and pressureless annealing. Bonding is achieved through SiO2 surface activation and copper atom interdiffusion, avoiding epitaxial layer cracking caused by traditional hot pressing. The entire annealing process simultaneously completes dielectric bonding, metal bonding, and ohmic contact formation. A dielectric layer replaces the highly doped epitaxial layer for back-side passivation, a small contact area achieves large-area passivation, and pressureless permanent bonding enables non-destructive integration of the brittle epitaxial layer. The entire process eliminates the need for growing highly doped epitaxial layers, applying external mechanical pressure during permanent bonding, and requiring no separate alloying annealing, thus avoiding key steps that lead to yield losses. This application simultaneously completes dielectric-dielectric covalent bonding, metal-metal diffusion bonding, and in-situ metal-semiconductor ohmic contact formation in a single annealing process, integrating these three steps into one, eliminating the separate alloying annealing step in traditional solutions, shortening the manufacturing cycle, and reducing process complexity.

[0042] The present application will be further described below with reference to specific embodiments: Example 1 This embodiment provides a method for fabricating a flexible triple-junction gallium arsenide solar cell, the specific steps of which are as follows: Step 1: Epitaxial growth Using an MOCVD apparatus and an N-type GaAs substrate, a 200 nm thick AlGaInP sacrificial layer and GaAs contact layer were first grown on the substrate. Then, following a flip-chip sequence, the following cells were grown sequentially: a GaInP top cell (containing an N-type AlInP window layer, an N-type GaInP emitter layer, a P-type GaInP base region, and a P-type GaInP back field layer), a first tunnel junction, a GaAs middle cell (containing an N-type InGaP window layer, an N-type GaAs emitter layer, a P-type GaAs base region, and a P-type GaAs back field layer), a second tunnel junction, and an InGaAs bottom cell (containing an N-type AlInP window layer, an N-type InGaAs emitter layer, and a P-type InGaAs base region). Epitaxial growth terminated at the P-type InGaAs base region of the InGaAs bottom cell; no heavily doped P-type InGaAs back field layer or heavily doped P-type InGaAs contact layer was grown after the base region.

[0043] Step 2: Preparation of hybrid bonding structure on epitaxial wafer side 2.1 Surface Pretreatment: The epitaxially grown wafer is immersed in 5% (v / v) dilute hydrochloric acid for 20 seconds to remove the native oxide layer and adsorbed impurities on the surface of the P-type InGaAs base region. After rinsing with deionized water, it is dried with high-purity nitrogen. Immediately afterwards, it is immersed in 8% (NH4)2S solution for 12 minutes to complete the sulfur passivation treatment on the InGaAs surface. After removal, it is quickly dried with nitrogen and immediately sent to the ALD chamber.

[0044] 2.2. ALD deposition of field-effect Al2O3 passivation layer: Trimethylaluminum and deionized water were used as precursors. The substrate temperature was 250℃, the TMA source bottle temperature was 30℃, the deionized water source bottle temperature was 30℃, the carrier gas was high-purity Ar or N2, the flow rate was 100 sccm, and alternating pulse deposition was performed. The TMA pulse time was 0.3s, the deionized water pulse time was 0.3s, and the deposited Al2O3 thickness was 20nm, thus obtaining the Al2O3 passivation layer.

[0045] 2.3 PECVD Deposition of First Dielectric Bonding Layer: A 2μm SiO2 material was deposited on the surface of the Al2O3 passivation layer using PECVD as the first dielectric bonding layer.

[0046] 2.4 Back Electrode Pattern Fabrication: Spin-coating photoresist, using a stepper lithography machine to expose and define the back electrode first microneedle array and first pad pattern. The size of a single microneedle is 50μm×50μm, accounting for 5% of the total area. The size of the first pad is much larger than that of a single microneedle, measuring 0.5mm×0.5mm, and is used for the final external wire bonding. After development, hard film curing is performed.

[0047] 2.5 Two-step dry etching windowing: First, using an ICP device with a CF4 / O2 mixed gas flow rate ratio of 10:1 as the gas source and a bias power of 150W, the first dielectric bonding layer is rapidly etched until approximately 100nm remains. Second, the bias power is reduced to 50W, and the O2 ratio is increased to a CF4 / O2 flow rate ratio of 5:1. Slow etching is then performed to the Al2O3 passivation layer surface, and the endpoint is detected by monitoring the SiF4 emission peak change using optical emission spectroscopy. Subsequently, the etching gas is switched to a BCl3 / Ar flow rate ratio of 3:1, with the bias power increased to 50W, and etching continues through the Al2O3 passivation layer until the surface of the p-type InGaAs base region is exposed.

[0048] 2.6 Photoresist Removal and Interface Cleaning: Acetone immersion removes photoresist, followed by oxygen plasma treatment to remove residual photoresist residue. The oxygen plasma treatment power is 80W, O2 flow rate is 30sccm, and the time is 2min. A light immersion in 5% dilute hydrochloric acid for 30s removes the oxides on the etched GaAs surface. After etching through, a small amount of H2 plasma is introduced for in-situ surface treatment (H2 flow rate 20sccm, power 80W, time 20s, gas pressure 0.8Pa) to further clean the interface, followed by a rapid transition to the coating step.

[0049] 2.7 Metal Seed Layer Deposition and Pulse Electroplating Filling: Electron beam evaporation was used to sequentially deposit three metal layers (Ti / Pt / Au) on the entire substrate as seed layers. A 30nm Ti layer served as the ohmic contact reaction layer, a 50nm Pt layer as the diffusion barrier layer, and a 100nm Au layer as the electroplating seed layer. Copper filling was then performed using a pulse electroplating process with a forward pulse current density of 2A / dm². 2 Reverse pulse current density 0.5 A / dm 2 With a duty cycle of 1:10, the copper inside the pad window is thickened to 0.5 μm above the surface of the first dielectric bonding layer to allow for removal by CMP, thus obtaining the first pad and the first microneedle array.

[0050] 2.8 Chemical Mechanical Polishing (CMP) Coplanarization: The back side of the wafer was CMPed using an alkaline silica polishing slurry containing copper corrosion inhibitor (main components: 10 wt% colloidal silica abrasive particles, 0.3 wt% benzotriazole corrosion inhibitor, 1 wt% hydrogen peroxide oxidant, pH 10.8). The polishing pressure was 14 kPa, the polishing disk rotation speed was 80 rpm, and the polishing slurry flow rate was 80 mL / min. Polishing was performed at room temperature. Real-time monitoring was conducted using an optical reflectivity endpoint detection system. A sudden change in reflectivity triggered a stop when polishing reached the surface of the first dielectric bonding layer. After polishing, all surfaces of the first bonding pads and the first microneedle array were globally coplanar with the surface of the first dielectric bonding layer, with a flatness deviation of less than 50 nm and a surface roughness Ra < 0.5 nm.

[0051] 2.9 Plasma Activation Before Bonding: After CMP, residual abrasive and metal ions on the surface are removed using a dilute organic acid cleaning solution. The solution contains 3 wt% citric acid, 1 wt% hydrogen peroxide, and the remainder deionized water. The surface is immersed and cleaned at room temperature for 45 seconds, followed by rinsing with deionized water and drying with nitrogen. The bonding surface is then subjected to low-temperature activation treatment with Ar / O2 mixed plasma. The Ar / O2 mixed plasma low-temperature activation treatment parameters are: Ar flow rate 40 sccm, O2 flow rate 10 sccm, RF power 100W, chamber pressure 1 Pa, treatment time 30 seconds, and treatment temperature below 100℃ (low-temperature treatment). After activation, the surface should be immediately sent to the bonding machine for pre-bonding, with the interval controlled within 30 minutes to avoid attenuation of surface hydroxyl density.

[0052] Step 3: Preparation of side-bonding structures on polyimide flexible substrate 3.1 Coating PI and Thermal Imidization: A polyamic acid precursor solution, N-methylpyrrolidone, with a solid content of 18%, was spin-coated onto a clean temporary glass substrate. After spin-coating, thermal imidization was completed in a nitrogen atmosphere with a stepped heating process: 120℃ for 30 min, 200℃ for 30 min, 300℃ for 30 min, and 380℃ for 60 min, with the heating rate controlled at 5℃ / min. After imidization, the substrate was allowed to cool naturally, forming a flexible polyimide substrate firmly bonded to the glass, with a thickness of 30 μm. The flexible polyimide substrate has a temperature resistance exceeding 450℃ and is fully compatible with the subsequent annealing temperature for hybrid bonding.

[0053] 3.2 Preparation of Cr lateral bonding layer: A metal Cr thin film was deposited on the surface of a polyimide flexible substrate by magnetron sputtering as a Cr lateral bonding layer with a thickness of 30 nm.

[0054] 3.3 Deposition of the second dielectric bonding layer: A 2μm thick SiO2 material is deposited on the Cr transverse bonding layer by PECVD to completely encapsulate the Cr metal.

[0055] 3.4 Back Electrode Pattern Fabrication: Spin-coating photoresist, using a stepper lithography machine to expose and define the back electrode second microneedle array and second pad pattern. The size of a single microneedle is 50μm×50μm, accounting for 5% of the total area. The first pad is much larger than a single microneedle, with a size of 0.5mm×0.5mm, and is used for the final external wire bonding. After development, hard film curing is performed.

[0056] 3.5 Two-step dry etching windowing: Step 1: Using an ICP device with a CF4 / O2 mixed gas flow rate ratio of 10:1 as the gas source and a bias power of 150W, rapidly etch the second dielectric bonding layer until approximately 100nm remains. Step 2: Reduce the bias power to 50W, increase the O2 ratio to a CF4 / O2 flow rate ratio of 5:1, and slowly etch to the surface of the Cr lateral bonding layer.

[0057] 3.6 Photoresist Removal and Interface Cleaning: Acetone immersion removes photoresist, followed by oxygen plasma treatment to remove residual photoresist residue. The oxygen plasma treatment power is 80W, O2 flow rate is 30sccm, and the time is 2min. After etching, a small amount of H2 plasma is introduced for in-situ surface treatment. The H2 flow rate is 20sccm, the power is 80W, the time is 20s, and the pressure is 0.8Pa to further clean the interface. Then, the process quickly proceeds to the coating step.

[0058] 3.7 Metal Seed Layer Deposition and Pulse Electroplating Filling: Two metal seed layers, Cr and Cu, were sequentially deposited on the entire substrate using electron beam evaporation, with thicknesses of 80 nm and 100 nm, respectively. Copper filling was then performed using a pulse electroplating process with a forward pulse current density of 2 A / dm². 2 Reverse pulse current density 0.5 A / dm 2 With a duty cycle of 1:10, the copper inside the pad opening is thickened to 0.5 μm above the surface of the second dielectric bonding layer to allow for removal by CMP, thus obtaining the second pad and the second microneedle array.

[0059] 3.8 Chemical Mechanical Polishing (CMP) Coplanarization: CMP was performed using an alkaline silica polishing slurry containing copper corrosion inhibitor (main components: 10 wt% colloidal silica abrasive particles, 0.3 wt% benzotriazole corrosion inhibitor, 1 wt% hydrogen peroxide oxidant, pH 10.8). The polishing pressure was 14 kPa, the polishing disc rotation speed was 80 rpm, and the polishing slurry flow rate was 80 mL / min. Polishing was carried out at room temperature. Real-time monitoring was conducted using an optical reflectivity endpoint detection system. A sudden change in reflectivity triggered a stop when polishing reached the surface of the second dielectric bonding layer. After polishing, all surfaces of the second pads and the second microneedle array were globally coplanar with the surface of the second dielectric bonding layer, with a flatness deviation of less than 50 nm and a surface roughness Ra < 0.5 nm.

[0060] 3.9 Plasma Activation Before Bonding: After CMP, residual abrasive and metal ions on the surface are removed using a dilute organic acid cleaning solution. The solution contains 3 wt% citric acid, 1 wt% hydrogen peroxide, and the remainder deionized water. The surface is immersed and cleaned at room temperature for 45 seconds, followed by rinsing with deionized water and drying with nitrogen. The bonding surface is then subjected to low-temperature activation treatment with Ar / O2 mixed plasma. The Ar / O2 mixed plasma low-temperature activation treatment parameters are: Ar flow rate 40 sccm, O2 flow rate 10 sccm, RF power 100W, chamber pressure 1 Pa, treatment time 30 seconds, and treatment temperature below 100℃ (low-temperature treatment). After activation, the surface should be immediately sent to the bonding machine for pre-bonding, with the interval controlled within 30 minutes to avoid attenuation of surface hydroxyl density.

[0061] Step 4: Mixed bonding and in-situ ohmic contact formation 4.1 High-precision alignment and low-pressure pre-bonding: Align the battery-side epitaxial wafer with the temporary glass substrate with polyimide flexible substrate to ensure that the first microneedle array and the second microneedle array are aligned one by one, and the first pad and the second pad are aligned. Then, load it into the wafer bonding machine and pre-bond it under extremely low pressure of 0.03MPa in a vacuum environment (<1Pa) and at room temperature.

[0062] 4.2 Pressureless permanent bonding and in-situ reactive annealing: The pre-bonded wafer is sent into the annealing furnace. No external mechanical pressure is applied during the entire annealing process. The annealing temperature is 350℃. Under a 95% N2 / 5% H2 mixed atmosphere, the temperature is increased to the target temperature at a rate of 5℃ / min. After holding at this temperature for 30 minutes, the temperature is allowed to drop naturally.

[0063] Step 5: Substrate removal and front electrode fabrication 5.1 Substrate thinning and selective etching: The GaAs substrate was thinned to about 120 μm by mechanical polishing. Then, the residual GaAs was selectively etched to expose the AlGaInP sacrificial layer by using a mixed solution of ammonia and hydrogen peroxide (ammonia:hydrogen peroxide:water volume ratio 1:5:5). Finally, AlGaInP was removed by concentrated hydrochloric acid at room temperature to accurately expose the N-type AlInP window layer of the GaInP top cell.

[0064] 5.2 Front Electrode Fabrication: Photolithography defines the front electrode pattern, including the gate network and large pads located at the edge of the cell. Electron beam evaporation deposits AuGe / Ni / Ag / Au metal stacks with thicknesses of 100nm, 50nm, 4000nm, and 500nm respectively. After lift-off, an N-type GaAs ohmic contact is formed. The GaAs contact layer is heavily doped N-type GaAs with a doping concentration of not less than 1×10⁻⁶. 19 cm -3 The front electrode and the GaAs contact layer have an unalloyed ohmic contact. The GaAs contact layer outside the gate lines is removed by selective etching using a citric acid / hydrogen peroxide mixed solution (citric acid:hydrogen peroxide:water volume ratio of 1:1:2).

[0065] 5.3 Antireflection film deposition: TiO2 / Al2O3 double-layer antireflection film was deposited sequentially by electron beam thermal evaporation, with optical thicknesses of 350nm / 600nm.

[0066] 5.4 Pad Windowing: The front pad area is etched to remove the anti-reflective coating, exposing the front electrode metal and forming a front lead-out pad that can be bonded to external leads.

[0067] Step 6: Back electrode exposure and temporary substrate removal 6.1 Epitaxial Layer Penetration Etching to Form Back Electrode: The front side photolithography defines the pattern of the back electrode pads. Cl-based ICP etching is used to penetrate all gallium arsenide epitaxial layers from top to bottom until the metal of the back electrode pads is fully exposed. The gallium arsenide epitaxial layer above the internal microneedles is completely preserved and not exposed to ensure that the effective light-receiving area of ​​the battery is not affected.

[0068] 6.2 Laser stripping: An excimer laser is used to uniformly scan and irradiate the back of the temporary glass substrate to achieve clean separation of the polyimide / temporary glass substrate, thereby obtaining a complete flexible triple-junction gallium arsenide solar cell film.

[0069] 6.3 Dicing and Testing: A wafer dicing machine is used to separate the thin film into individual battery chips for photoelectric performance testing and sorting.

[0070] Example 2 The method is the same as in Example 1, except that steps 2.3 and 3.3 are different: in step 2.3, a single layer of 2 μm SiO2 replaces the sequentially deposited 1.5 μm SiO2 and 0.5 μm SiN. x The stacked structure, in section 3.3, replaces the single layer of 2μm SiO2 with sequentially deposited 1.5μm SiO2 and 0.5μm SiN. x The stacked structure of SiN. x Located on one side of the bonding surface, the dielectric layer structures on both sides are symmetrical.

[0071] Example 3 The method follows the same procedure as in Example 1, except that in step 3.1, the polyimide flexible substrate is prepared by bonding a pre-made polyimide film to a temporary glass substrate using high-temperature resistant double-sided adhesive. A pre-made polyimide film with a thickness tolerance within ±1 μm and a thickness of 30 μm is selected; the double-sided adhesive is a silicone pressure-sensitive adhesive with a temperature resistance of not less than 350°C and a thickness of 15 μm. During bonding, the double-sided adhesive is first applied to the surface of the temporary glass substrate, and then the pre-made polyimide film is applied to the adhesive layer. A pressure of 0.3 MPa is applied, and the substrate is kept at 80°C for 10 minutes to remove air bubbles. Correspondingly, step 6.2 no longer uses laser peeling but is replaced by thermal peeling: after the process is completed, the temporary glass substrate is heated to 200°C, and after the double-sided adhesive loses its adhesion, the polyimide film and the temporary glass substrate are mechanically separated.

[0072] Example 4 The method is the same as in Example 1, except that the area ratio of the first microneedle array in step 2.4 and the second microneedle array in step 3.4 is 2%, and the passivation coverage reaches 98%.

[0073] Example 5 The method is the same as in Example 1, except that the area ratio of the first microneedle array in step 2.4 and the second microneedle array in step 3.4 is 8%, and the passivation coverage is 92%.

[0074] Test case The flexible solar cells prepared in the above embodiments were subjected to photoelectric performance and reliability tests. The photoelectric performance tests were conducted using a solar simulator under AM0 spectral conditions (AM0, 1000 W / m²). 2The photoelectric parameters of the battery were measured at 25℃. Before testing, the spectral matching of the simulator was calibrated using a standard battery to control the spectral mismatch error within ±2%. During testing, the battery was placed on a temperature-controlled platform, and measurements were taken after the temperature stabilized at 25±0.5℃. The sample was placed in a thermal shock test chamber with a temperature range of -170℃ to +120℃, and held at both high and low temperatures for 20 minutes each, with a switching time not exceeding 1 minute, for a total of 10 cycles. After the test, the sample was removed and allowed to recover at room temperature for 2 hours before retesting the photoelectric performance and calculating the efficiency decay rate. Warpage was measured using a laser scanning rangefinder, and the maximum height difference on the sample surface was used as the measure. Measurements were performed at room temperature, with the sample placed freely without any external force applied. The test results are shown in Table 1. Table 1: Photoelectric performance parameters of each embodiment

[0075] As shown in Table 1, Example 1 exhibits the best overall performance, with an initial photoelectric conversion efficiency of 32.75%, an efficiency decrease of only 1.2% after thermal shock, and a warpage of 1.6 mm. These results indicate that when the microneedle array area ratio is 5%, the optimal balance is achieved between Al2O3 passivation effect, current collection capability, and bonding reliability. Among the embodiments in this application, Example 1 demonstrates the best overall performance and is the preferred embodiment of this invention.

[0076] The efficiency degradation after thermal shock in Example 2 was the same as in Example 1 (1.2%), while the warpage was further reduced to 1.4 mm, demonstrating the performance of SiN. x The laminated structure plays a role in reducing thermal stress at the bonding interface. However, the initial efficiency of 32.66% is slightly lower than that of Example 1, and its overall performance is second only to Example 1.

[0077] Example 3 showed an initial efficiency of 32.55%, the lowest among the examples, with an efficiency decrease of 1.4% after thermal shock and a warpage of 1.8 mm. The structural stability brought about by the uniform thickness of the finished polyimide film resulted in a reliability performance close to that of Example 1, but the presence of the double-sided adhesive layer slightly affected the initial photoelectric properties.

[0078] Example 4 showed the highest initial efficiency (32.86%) because the microneedle array area accounted for only 2%, the passivation coverage reached 98%, and the surface recombination loss was minimal. However, after thermal shock, the efficiency decreased by 2.5%, the warpage was 2.6 mm, and the reliability was the worst among the examples. This indicates that the small pad area leads to localized stress concentration, and the total Cu-Cu bonding area is insufficient to withstand the mechanical stress during thermal shock.

[0079] Example 5 exhibited the highest initial short-circuit current density (17.15 mA / cm²), thanks to its enhanced current collection capability due to an 8% area ratio. However, the passivation coverage decreased to 92%, and surface recombination in the non-passivated area increased after thermal shock, resulting in a 2.0% efficiency decrease, a 2.4 mm warpage, and significantly lower reliability compared to Examples 1-3.

[0080] For any content not described in this embodiment, please refer to the relevant descriptions in the rest of this application.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them; although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of this application or equivalent substitutions can be made to some technical features, all of which should be covered within the scope of the technical solutions claimed in this application.

Claims

1. A flexible gallium arsenide solar cell, characterized in that, It includes a gallium arsenide epitaxial layer, an Al2O3 passivation layer, a first dielectric bonding layer, a second dielectric bonding layer, a Cr lateral bonding layer, and a polyimide flexible substrate, which are stacked sequentially from top to bottom; The back electrode of the solar cell includes a pad portion and a microneedle portion. The pad portion includes a first pad and a second pad, which are vertically aligned and electrically connected. The microneedle portion includes a first microneedle array and a second microneedle array, which are vertically aligned and electrically connected. The first pad and the first microneedle array both penetrate the first dielectric bonding layer and the Al2O3 passivation layer perpendicularly. The second pad and the second microneedle array both penetrate the second dielectric bonding layer perpendicularly and are electrically connected to the Cr lateral bonding layer. The gallium arsenide epitaxial layer has a stepped etching channel on the sidewall near the pad portion, which is etched from the upper surface of the gallium arsenide epitaxial layer to the upper surface of the pad portion. The first microneedle array has a seed layer and a copper core. The seed layer consists of a Ti layer, a Pt layer, and an Au layer arranged sequentially from the outside to the inside, with the Au layer in close contact with the copper core. The gallium arsenide epitaxial layer adopts a flip-chip grown triple-junction gallium arsenide structure. The triple-junction gallium arsenide structure includes a GaInP top cell, a first tunnel junction, a GaAs middle cell, a second tunnel junction, and an InGaAs bottom cell stacked sequentially from top to bottom. The InGaAs bottom cell includes an N-type AlInP window layer, an N-type InGaAs emitter layer, and a P-type InGaAs base region stacked sequentially from top to bottom. The upper surface of the first microneedle array is in contact with the lower surface of the P-type InGaAs base region, and an ohmic contact is formed through the solid-state reaction between Ti and InGaAs in the seed layer of the first microneedle array.

2. The flexible gallium arsenide solar cell according to claim 1, characterized in that, The P-type InGaAs base region is treated with sulfur passivation; the Al2O3 passivation layer has a thickness of 10nm to 30nm, the first dielectric bonding layer has a thickness of 1.5μm to 3μm, and the first microneedle array occupies 2% to 8% of the area of ​​the first dielectric bonding layer.

3. A flexible gallium arsenide solar cell according to claim 1, characterized in that, The thicknesses of the Ti layer, Pt layer, and Au layer are 20nm–40nm, 40nm–60nm, and 80nm–120nm, respectively; the thickness of the polyimide flexible substrate is 25μm–50μm; and the thickness of the Cr lateral bonding layer is 10nm–50nm.

4. A method for fabricating a flexible gallium arsenide solar cell, used to fabricate the flexible gallium arsenide solar cell as described in any one of claims 1 to 3, characterized in that, Includes the following steps: S1. On the surface of an N-type GaAs substrate, an AlGaInP sacrificial layer, a GaAs contact layer, a GaInP top cell, a first tunnel junction, a GaAs middle cell, a second tunnel junction, and an InGaAs bottom cell are grown sequentially by MOCVD, and the epitaxial growth continues until the P-type InGaAs base region of the InGaAs bottom cell is reached. S2. After cleaning the grown wafer, perform sulfur passivation treatment on the surface of the P-type InGaAs base region, and then sequentially fabricate an Al2O3 passivation layer and a first dielectric bonding layer on the surface of the sulfur passivated P-type InGaAs base region. S3. Prepare a first microneedle array and a first pad that penetrate the Al2O3 passivation layer and the first dielectric bonding layer; S4. The surface of the first dielectric bonding layer is subjected to CMP and plasma low-temperature activation treatment in sequence. S5. A polyimide flexible substrate, a Cr lateral bonding layer, and a second dielectric bonding layer are sequentially prepared on the surface of a temporary glass slide. S6. Prepare a second microneedle array and a second pad that penetrate the second dielectric bonding layer; S7. The surface of the second dielectric bonding layer is subjected to CMP and plasma low-temperature activation treatment in sequence. S8. Align the first dielectric bonding layer and the second dielectric bonding layer, and perform pre-bonding under vacuum, room temperature and pressure of 0.01MPa to 0.05MPa. Anneal the pre-bonded wafer under a reducing atmosphere at atmospheric pressure and 300 to 400°C. S9. After bonding is completed, the N-type GaAs substrate and AlGaInP sacrificial layer on the gallium arsenide epitaxial layer are removed to expose the GaAs contact layer. Then, the front electrode and antireflection film are fabricated in sequence. S10. Define the pattern of the back pad by front photolithography, and use Cl-based ICP etching to penetrate the gallium arsenide epitaxial layer from top to bottom until the upper surface of the first pad is fully exposed. S11. Use an excimer laser to uniformly scan and irradiate the back of the temporary glass slide to peel the polyimide flexible substrate off the temporary glass slide. S12. Use a wafer dicing machine to separate the cells into individual battery chips, and then perform photoelectric performance testing and sorting.

5. The method for fabricating a flexible gallium arsenide solar cell according to claim 4, characterized in that, In S2, the sulfur passivation treatment method is to clean the grown wafer, immerse it in a 4% to 10% ammonium sulfate solution for 10 to 15 minutes, and then dry it with nitrogen gas.

6. The method for fabricating a flexible gallium arsenide solar cell according to claim 4, characterized in that, In S2, the Al2O3 passivation layer is prepared by using trimethylaluminum and deionized water as precursors, with a substrate temperature of 240℃~260℃, and Al2O3 is deposited on the surface of the sulfur-passivated P-type InGaAs base region by alternating pulses. The thickness of the prepared Al2O3 passivation layer is 10nm~30nm.

7. The method for fabricating a flexible gallium arsenide solar cell according to claim 4, characterized in that, In S3, the fabrication method of the first microneedle array and the first pad includes the following steps: S31. Spin-coat photoresist onto the surface of the first dielectric bonding layer, use a stepper lithography machine to expose and define the first microneedle array and the first pad pattern, develop and then perform hard film curing. Use an ICP device with a CF4 / O2 mixed gas with a flow ratio of 10:1 as the gas source and a bias power of 150W to rapidly etch the first dielectric bonding layer until the remaining 80nm~120nm is stopped. Reduce the bias power to 50W, adjust the flow ratio of the CF4 / O2 mixed gas to 5:1, and etch to the surface of the Al2O3 passivation layer. Use BCl3 / Ar as the etching gas to etch through the Al2O3 passivation layer to expose the surface of the P-type InGaAs base region. S32. The photoresist is removed by immersion in acetone, the residual photoresist residue is removed by oxygen plasma treatment, the photoresist is immersed in dilute hydrochloric acid for 30 seconds, and the surface is treated in situ by H2 plasma. S33. Ti / Pt / Au are sequentially deposited as a seed layer using electron beam evaporation, and copper is filled to a height above the surface of the first dielectric bonding layer using a pulsed electroplating process, wherein the forward pulse current density is 2A / dm². 2 Reverse pulse current density 0.5 A / dm 2 The duty cycle is 1:

10.

8. The method for fabricating a flexible gallium arsenide solar cell according to claim 4, characterized in that, In S6, the fabrication method of the second microneedle array and the second pad includes the following steps: S61. Spin-coat photoresist onto the surface of the second dielectric bonding layer, use a stepper lithography machine to expose and define the second microneedle array and the second pad pattern, develop and then harden the film. Use an ICP device with a CF4 / O2 mixed gas with a flow ratio of 10:1 as the gas source and a bias power of 150W to rapidly etch the second dielectric bonding layer until the remaining 80nm~120nm is reached and then stop. Reduce the bias power to 50W, adjust the flow ratio of the CF4 / O2 mixed gas to 5:1, and etch to expose the surface of the Cr lateral interconnect layer. S62. The photoresist is removed by immersion in acetone, the residual photoresist residue is removed by oxygen plasma treatment, and the surface is treated in situ by H2 plasma. S63. Cr / Cu is sequentially deposited as a seed layer using electron beam evaporation, and copper is then filled to a level above the surface of the second dielectric bonding layer using pulse electroplating. The forward pulse current density is 2 A / dm². 2 Reverse pulse current density 0.5 A / dm 2 The duty cycle is 1:

10.

9. The method for fabricating a flexible gallium arsenide solar cell according to claim 4, characterized in that, In S4 and S7, the specific CMP method is as follows: CMP is performed on the back side of the wafer using an alkaline silicon dioxide polishing slurry containing copper corrosion inhibitor. The optical reflectivity endpoint detection system is used for real-time monitoring. When polishing reaches the surface of the first dielectric bonding layer or the second dielectric bonding layer, a sudden change in reflectivity triggers the stop. After polishing, the metal and the first dielectric bonding layer or the second dielectric bonding layer are globally coplanar, with a flatness deviation of less than 50nm and a surface roughness Ra < 0.5nm. In S4 and S7, the specific method of plasma low-temperature activation treatment is to remove residual abrasive and metal ions from the surface of the CMP wafer with acid cleaning solution, and to perform Ar / O2 mixed plasma low-temperature activation treatment on the surface of the first dielectric bonding layer or the second dielectric bonding layer.

10. A method for fabricating a flexible gallium arsenide solar cell according to claim 4, characterized in that, In S8, the specific bonding method includes the following steps: S81. When aligning the first dielectric bonding layer and the second dielectric bonding layer, align the first microneedle array with the second microneedle array one by one, align the first pad and the second pad, load the wafer bonding machine, and apply a pressure of 0.01MPa to 0.05MPa for pre-bonding in a vacuum environment and at room temperature. S82. The pre-bonded wafer is placed into an annealing furnace and annealed at 300℃~400℃ in a 95%N2 / 5%H2 mixed atmosphere at a heating rate of 5℃ / min. After holding at this temperature for 30 minutes, the temperature is allowed to drop naturally.

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