Flat panel detector, method of manufacturing the same, and detection device

Abstract

The embodiment of the application provides a flat panel detector, a preparation method thereof and a detection device. The flat panel detector comprises a substrate, a plurality of pixel units, a metal wiring layer, a first passivation layer and a first electrode layer. The metal wiring layer is arranged on a side of the pixel unit away from the substrate and comprises a first bias line and a second bias line electrically connected. The first passivation layer is defined with a first via hole in a display area. The first electrode layer is arranged on a side of the first passivation layer away from the substrate and is electrically connected with the second bias line through the first via hole. According to the technology of the application, the first electrode layer and the second bias line are connected through the first via hole in the display area, so that the first via hole and the edge of the scintillator layer prone to water absorption and deliquescence are staggered, thereby avoiding the edge of the scintillator layer from water absorption and deliquescence and the corrosion of the metal wiring layer through the via hole connected with the first electrode layer and the metal wiring layer, and the phenomenon of corrosion of the metal wiring layer is avoided.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a flat panel detector and its preparation method and detection device. Background Technology

[0002] In related technologies, flat panel detectors include a substrate, multiple pixel units, a metal wiring layer, a passivation layer, and an electrode layer.

[0003] After the electrode layer is fabricated, a scintillator needs to be placed on the side of the electrode layer facing away from the substrate. Since the scintillator is made of cesium iodide, it is prone to moisture absorption and deliquescence. For narrow-bezel products, the aluminum film used in the bonding process cannot meet the product requirements. Therefore, a perylin encapsulation film needs to be placed on the side of the scintillator facing away from the substrate to protect it, thus enabling the narrow-bezel product functionality. However, after the perylin process (CVD deposition for the entire flat panel detector), the perylin in the bonding electrode area of ​​the non-display area needs to be removed. During the removal of the perylin in the bonding electrode area, the edge of the perylin encapsulation film will experience edge grinding, leading to problems with the bonding of the aluminum film and ultimately increasing the risk of deliquescence of the scintillator. In related technologies, the edge of the perylin encapsulation film needs to be placed inside the scintillator. This means that the edge of the scintillator is not protected by the perylin encapsulation film. Once the edge of the scintillator absorbs moisture and deliquulates, it easily generates free iodide ions. These iodide ions corrode the metal trace layer in the non-display area through the apertures, thus affecting the image quality of the flat panel detector. Summary of the Invention

[0004] This application provides a flat panel detector and its preparation method and detection device to solve or alleviate one or more technical problems in the prior art.

[0005] As one aspect of the embodiments of this application, this application provides a flat panel detector having a display area and a non-display area, the flat panel detector comprising:

[0006] Substrate;

[0007] Multiple pixel units are disposed on one side of a substrate and located within the display area; each pixel unit includes an electrically connected photoelectric converter and a thin-film transistor;

[0008] A metal trace layer is disposed on the side of the pixel unit away from the substrate, including a first bias line and a second bias line electrically connected. The first bias line is located in the non-display area, and the second bias line is located in the display area and electrically connected to the photoelectric converter.

[0009] A first passivation layer is disposed on the side of the metal trace layer away from the substrate. A plurality of first vias corresponding to a plurality of pixel units are defined on the first passivation layer. The plurality of first vias are located within the display area.

[0010] The first electrode layer is disposed on the side of the first passivation layer away from the substrate, and the first electrode layer is electrically connected to the second bias line through the first via.

[0011] In some embodiments, the first electrode layer is located within the display area.

[0012] In some embodiments, the first electrode layer includes a plurality of first electrodes corresponding to a plurality of pixel units, the plurality of first electrodes being electrically connected to each other, and each first electrode being electrically connected to a second bias line through a corresponding first via.

[0013] In some embodiments, the orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of the corresponding photoelectric converter on the substrate.

[0014] In some embodiments, the first electrode includes at least a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion, and the photoelectric converter includes at least a first edge, a second edge, a third edge, and a fourth edge. The orthographic projection of the first conductive portion on the substrate at least partially overlaps with the orthographic projection of the first edge of the corresponding photoelectric converter on the substrate. The orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the second edge of the corresponding photoelectric converter on the substrate. The orthographic projection of the third conductive portion on the substrate at least partially overlaps with the orthographic projection of the third edge of the corresponding photoelectric converter on the substrate. The orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the fourth edge of the corresponding photoelectric converter on the substrate.

[0015] In some embodiments, the photoelectric converter includes a second electrode, a photoelectric conversion layer, and a third electrode sequentially stacked on one side of a substrate, and the thin-film transistor includes a gate, a source, and a drain, with the second electrode electrically connected to the drain.

[0016] In some embodiments, the device further includes a scintillator layer, a paraffin encapsulation film, and an aluminum film. The scintillator layer is disposed on the side of the first electrode layer away from the substrate, the paraffin encapsulation film is disposed on the side of the scintillator layer away from the substrate, and the aluminum film is disposed on the side of the paraffin encapsulation film away from the substrate.

[0017] In some embodiments, the orthographic projection of the Parylene encapsulation film on the substrate is within the orthographic projection range of the scintillator layer on the substrate, and the orthographic projection of the scintillator layer on the substrate is within the orthographic projection of the aluminum film on the substrate; the edges of the Parylene encapsulation film, the scintillator layer, and the aluminum film are located within the non-display area.

[0018] In some embodiments, a reading module is also included, which is electrically connected to the first bias line.

[0019] In another aspect, this application also provides a method for fabricating a flat panel detector, the flat panel detector including a display area and a non-display area, the fabrication method comprising:

[0020] Provide substrates;

[0021] Multiple pixel units are formed on one side of the substrate, and the multiple pixel units are disposed on one side of the substrate and located within the display area; the pixel unit includes a photoelectric converter and a thin film transistor; the thin film transistor is disposed on one side of the substrate; the photoelectric converter is disposed on the side of the thin film transistor opposite to the substrate.

[0022] A metal trace layer is formed on the side of the photoelectric conversion layer away from the substrate. The metal trace layer includes a first bias line and a second bias line that are electrically connected. The first bias line is located in the non-display area, and the second bias line is located in the display area and is electrically connected to the photoelectric converter.

[0023] A first passivation layer is formed on the side of the metal trace layer away from the substrate. A plurality of first vias corresponding to a plurality of pixel units are defined on the first passivation layer. The plurality of first vias are located in the display area.

[0024] A first electrode layer is formed on the side of the first passivation layer away from the substrate, and the first electrode layer is electrically connected to the second bias line through a first via.

[0025] In some embodiments, the first electrode layer includes a plurality of first electrodes corresponding to a plurality of pixel units, the plurality of first electrodes being electrically connected to each other, and each first electrode being electrically connected to a second bias line through a corresponding first via.

[0026] As another aspect of this application, a detection device is also provided, comprising a flat panel detector as described in any of the preceding claims or a flat panel detector manufactured by any of the preceding claims.

[0027] The embodiments of this application have the following beneficial effects:

[0028] According to the technology of this application, by eliminating the vias in the non-display area of ​​the passivation layer in related technologies, multiple first vias are provided on the first passivation layer and located within the display area. This allows the first electrode layer and the second bias line to make contact and connect within the display area through the first vias, thereby achieving electrical connection between the first electrode layer and the second bias line. This arrangement, on the one hand, ensures that the first vias and the scintillator layer, which are prone to moisture absorption and deliquescence, are staggered at the edge of the non-display area. This prevents moisture absorption and deliquescence at the edge of the scintillator layer, which could then corrode the metal trace layer through the vias connecting the first electrode layer and the metal trace layer, thus avoiding corrosion of the metal trace layer. On the other hand, in related technologies, a break in the metal trace layer and electrode layer can cause the metal trace layer to be unable to load signals. However, in this application, the number of first vias corresponds one-to-one with the number of pixel units. The metal trace layer passes through the first via corresponding to each pixel unit and contacts the first electrode layer. Therefore, pixel units can be connected through the metal trace layer and the first electrode layer. When a break occurs in the metal trace layer and the first electrode layer in one of the first vias, causing the first electrode layer and the metal trace layer at that location to disconnect, the metal trace layer at the failure location can be loaded with signals through the surrounding first electrode layers. This solves the technical problem in related technologies where a break in the metal trace layer and electrode layer can cause the metal trace layer to be unable to load signals.

[0029] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0030] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0031] Figure 1 A cross-sectional view of a flat panel detector in the related art is shown;

[0032] Figure 2 A cross-sectional view of a flat panel detector in the related art is shown;

[0033] Figure 3 A top view of a flat panel detector according to an embodiment of this application is shown;

[0034] Figure 4 Show Figure 3 Sectional view of AA;

[0035] Figure 5 Show Figure 3 Sectional view of BB;

[0036] Figure 6 A top view of a flat panel detector according to an embodiment of this application is shown;

[0037] Figure 7 Show Figure 6 Sectional view of CC;

[0038] Figure 8 This diagram illustrates the positional relationship between the scintillator and the first via according to an embodiment of this application.

[0039] Figure 9 A schematic flowchart of the preparation method according to an embodiment of this application is shown.

[0040] Explanation of reference numerals in the attached figures:

[0041] Related technologies

[0042] 10', Electrode layer;

[0043] 20', Metallic trace layer;

[0044] 30', passivation layer; 31', hole location;

[0045] 40', scintillator;

[0046] 50', Perelin encapsulation film;

[0047] 60', aluminum foil.

[0048] This application

[0049] 1. Flat panel detector;

[0050] 10. Aluminum foil;

[0051] 20. Reading module;

[0052] 30. Substrate;

[0053] 40. Pixel unit; 41. Photoelectric converter; 411. Second electrode; 412. Photoelectric conversion layer; 413. Third electrode; 414. First edge; 415. Second edge; 416. Third edge; 417. Fourth edge; 42. Thin film transistor; 421. Gate; 422. Source; 423. Drain; 424. Active layer;

[0054] 50. Metallic trace layer; 51. First bias line; 52. Second bias line;

[0055] 60. First passivation layer; 61. First via;

[0056] 70. First electrode layer; 71. First electrode;

[0057] 80. Scintillator layer;

[0058] 90. Perylene encapsulation film. Detailed Implementation

[0059] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0060] Figure 1 This shows a cross-sectional view of a flat panel detector in the related art. Figure 2 A cross-sectional view of a flat panel detector in the related art is shown; see [link / reference]. Figure 1 and Figure 2 ,

[0061] In related technologies, a flat panel detector includes a substrate, multiple pixel units, a metal wiring layer 20', a passivation layer 30', and an electrode layer 10'.

[0062] After the electrode layer 10' is fabricated, a scintillator 40' needs to be set on the side of the electrode layer 10' away from the substrate. Since the scintillator 40' is made of cesium iodide, it is prone to moisture absorption and deliquescence. For narrow bezel products, the aluminum film 60' of the bonding process cannot meet the product requirements. Therefore, a paraffin encapsulation film 50' needs to be set on the side of the scintillator 40' away from the substrate to protect the scintillator 40', thereby realizing the function of the narrow bezel product. However, after the paraffin process (CVD deposition for the entire flat panel detector), the paraffin in the bonding electrode area in the non-display area needs to be removed. During the removal of the paraffin in the bonding electrode area, the edge of the paraffin film layer will have a grinding problem, which will lead to problems in the bonding of the aluminum film 60', ultimately increasing the risk of deliquescence of the scintillator 40'. In related technologies, the edge of the Parylene encapsulation film 50' needs to be placed inside the scintillator 40'. This results in the edge of the scintillator 40' not being protected by the Parylene encapsulation film 50'. Once the edge of the scintillator 40' absorbs water and deliquesces, it is easy to generate free iodine ions. The iodine ions corrode the metal trace layer 20' located in the non-display area through the aperture 31', thereby affecting the image quality of the flat panel detector.

[0063] Figure 3 A top view of a flat panel detector according to an embodiment of this application is shown. Figure 4 Show Figure 3 Sectional view of AA, Figure 5 Show Figure 3 Sectional view of BB, Figure 6 A top view of a flat panel detector according to an embodiment of this application is shown. Figure 7 Show Figure 6 Sectional view of CC, Figure 8 A schematic diagram showing the positional relationship between the scintillator and the first via according to an embodiment of this application is provided. See also: Figures 3 to 8 This application provides a flat panel detector 1, which has a display area and a non-display area. The flat panel detector 1 includes a substrate 30, a plurality of pixel units 40, a metal wiring layer 50, a first passivation layer 60 and a first electrode layer 70.

[0064] In some examples, the substrate 30 may be a flexible substrate 30, such as a plastic substrate made of materials with excellent heat resistance and durability, such as polyvinyl ether phthalate, polyethylene naphthalate, polycarbonate, polyaryl compounds, polyetherimide, polyethersulfone or polyimide; or it may be a rigid substrate 30, such as a glass substrate, without limitation.

[0065] In the embodiments of this application, see Figure 4 and Figure 5 Multiple pixel units 40 are disposed on one side of the substrate 30 and located within the display area. Each pixel unit 40 includes a photoelectric converter 41 and a thin film transistor 42, which are electrically connected.

[0066] It should be noted that the thin-film transistor 42 is used to control the switching of each pixel unit 40 in the flat panel detector 1. This application does not limit the specific type of thin-film transistor 42. For example, bottom-gate or top-gate thin-film transistors 42 can be selected.

[0067] In some examples, the thin-film transistor 42 is disposed on one side of the substrate 30, and the photoelectric converter 41 is disposed on the side of the thin-film transistor 42 opposite to the substrate 30.

[0068] See Figure 4 and Figure 5 The metal wiring layer 50 is disposed on the side of the pixel unit 40 away from the substrate 30. The metal wiring layer 50 includes a first bias line 51 and a second bias line 52. The first bias line 51 and the second bias line 52 are electrically connected. The first bias line 51 is located in the non-display area, and the second bias line 52 is located in the display area and is electrically connected to the photoelectric converter 41.

[0069] See Figure 5 and Figure 7 The first passivation layer 60 is disposed on the side of the metal trace layer 50 away from the substrate 30. The first passivation layer 60 is provided with a plurality of first vias 61 corresponding to the plurality of pixel units 40. The plurality of first vias 61 are located in the display area.

[0070] It should be noted that the passivation layer mentioned in the embodiments of this application may be made of at least one of the following materials: inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride, organic insulating materials such as organic resin, or other insulating materials. This application does not limit the specific material of the passivation layer.

[0071] In the embodiments of this application, see Figure 5 The first electrode layer 70 is disposed on the side of the first passivation layer 60 away from the substrate 30, and the first electrode layer 70 is electrically connected to the second bias line 52 through the first via 61.

[0072] In some examples, the material of the first electrode layer 70 is a metal oxide. Exemplarily, the material of the first electrode layer 70 includes, but is not limited to, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc gallium oxide (GZO), and indium gallium zinc oxide (IGZO).

[0073] According to the embodiments of this application, this application eliminates the via 31' located in the non-display area of ​​the passivation layer 30' in related technologies, and provides a plurality of first vias 61 on the first passivation layer 60 at positions within the display area. This allows the first electrode layer 70 and the second bias line 52 to make contact and connection within the display area through the first vias 61, thereby achieving electrical connection between the first electrode layer 70 and the second bias line 52. This arrangement, on the one hand, ensures that the first vias 61 and the scintillator layer 80, which are prone to moisture absorption and deliquescence, are offset from the edges of the non-display area. This prevents moisture absorption and deliquescence at the edges of the scintillator layer 80, which could then corrode the metal trace layer 50 through the vias connecting the first electrode layer 70 and the metal trace layer 50, thus avoiding corrosion of the metal trace layer 50. On the other hand, in related technologies, a break in the metal trace layer 20' and electrode layer 10' can cause the metal trace layer 20' to be unable to load a signal. However, in this application, the number of first vias 61 corresponds one-to-one with the number of pixel units 40. The metal trace layer 50 passes through the first vias 61 corresponding to each pixel unit 40 and contacts the first electrode layer 70. Therefore, the pixel units 40 can be connected through the metal trace layer 50 and the first electrode layer 70. When a break occurs in the metal trace layer 50 and the first electrode layer 70 in one of the first vias 61, causing the first electrode layer 70 and the metal trace layer 50 at that location to disconnect, the metal trace layer 50 at the failed location can load a signal through the surrounding first electrode layers 70. This solves the technical problem in related technologies where a break in the metal trace layer 20' and electrode layer 10' can cause the metal trace layer 20' to be unable to load a signal.

[0074] It should be noted that the first electrode layer 70 and the metal trace layer 50 can achieve bidirectional signal transmission. If the first electrode layer 70 or the metal trace layer 50 corresponding to a pixel unit 40 is broken, the signal will be loaded through the first electrode layer 70 or the metal trace layer 50 of another pixel unit 40, thereby ensuring the normal operation of the flat panel detector 1.

[0075] In some embodiments, see Figure 6 The first bias line 51 is in the shape of a ring, and the ring-shaped first bias line 51 is arranged around the display area.

[0076] In some embodiments, see Figure 6 There are multiple second bias lines 52, each extending laterally and connected at both ends to a first bias line 51. These multiple second bias lines 52 are spaced apart longitudinally, allowing them to sequentially connect to multiple pixel units 40 spaced apart laterally. In other embodiments, the multiple second bias lines 52 extend longitudinally and are connected at both ends to a first bias line 51. These multiple second bias lines 52 are spaced apart laterally, allowing them to sequentially connect to multiple pixel units 40 spaced apart longitudinally.

[0077] In some embodiments, see Figure 7 The first electrode layer 70 is located within the display area.

[0078] For example, the first electrode layer 70 is connected to the metal trace layer 50 through a plurality of first vias 61 in the display area. Therefore, even if the first electrode layer 70 is completely disposed in the display area, the signal transmission between the first electrode layer 70 and the metal trace layer 50 can still be realized. With this configuration, when the edge of the scintillator layer 80 is not protected by the pyrene encapsulation film 90 and absorbs water and deliquesces, the first electrode layer 70 will not be corroded. This allows the present application to realize the signal transmission between the first electrode layer 70 and the metal trace layer 50 while effectively protecting the first electrode layer 70 and the metal trace layer 50 from corrosion caused by the water and deliquescence of the scintillator layer 80.

[0079] In some embodiments, see Figure 7 The first electrode layer 70 includes a plurality of first electrodes 71 corresponding to a plurality of pixel units 40, the plurality of first electrodes 71 are electrically connected to each other, and each first electrode 71 is electrically connected to a second bias line 52 through a corresponding first via 61.

[0080] In this embodiment, the first electrodes 71 between each pixel unit 40 are bridged to electrically connect the first electrodes 71 between each pixel unit 40. This configuration enables the first electrodes 71 between each pixel unit 40 to transmit signals to each other. When a break occurs in the metal trace layer 50 and the first electrode layer 70 in one of the first vias 61, causing the first electrode layer 70 and the metal trace layer 50 to disconnect at that location, the metal trace layer 50 at the failure location can be loaded with signals through the surrounding first electrode layers 70. This solves the technical problem in the related art where a break in the metal trace layer 20' and the electrode layer 10' would prevent the metal trace layer 20' from loading signals.

[0081] In some embodiments, see Figure 7 The orthographic projection of the first electrode 71 on the substrate 30 at least partially overlaps with the orthographic projection of the corresponding photoelectric converter 41 on the substrate 30.

[0082] In some embodiments, the first bias line 51 and the second bias line 52 can be made of transparent conductive materials. Since the first bias line 51 and the second bias line 52 are made of transparent conductive materials, they will not block the photoelectric converter 41, thus preventing a reduction in the effective area of ​​the photoelectric converter 41. This can improve the pixel fill rate, which is beneficial for noise reduction and sensitivity improvement.

[0083] Optionally, the transparent conductive material can be ITO. Of course, in specific implementations, the transparent conductive material is not limited to ITO and can also be other transparent conductive materials.

[0084] In some embodiments, the first electrode 71 includes at least a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion, and the photoelectric converter 41 includes at least a first edge, a second edge, a third edge, and a fourth edge. The orthographic projection of the first conductive portion on the substrate 30 at least partially overlaps with the orthographic projection of the first edge of the corresponding photoelectric converter 41 on the substrate 30. The orthographic projection of the second conductive portion on the substrate 30 at least partially overlaps with the orthographic projection of the second edge of the corresponding photoelectric converter 41 on the substrate 30. The orthographic projection of the third conductive portion on the substrate 30 at least partially overlaps with the orthographic projection of the third edge of the corresponding photoelectric converter 41 on the substrate 30. The orthographic projection of the fourth conductive portion on the substrate 30 at least partially overlaps with the orthographic projection of the fourth edge of the corresponding photoelectric converter 41 on the substrate 30.

[0085] In some examples, the first electrode 71 is ring-shaped, and the orthographic projection of the first electrode 71 on the substrate 30 overlaps with the orthographic projection of the edge of the photoelectric converter 41 on the substrate 30.

[0086] According to the embodiments of this application, by having the first conductive part cover the first edge, the second conductive part cover the second edge, the third conductive part cover the third edge, and the fourth conductive part cover the fourth edge, the first electrode 71 can shield the first edge, the second edge, the third edge and the fourth edge of the photoelectric converter 41 from static electricity, which is beneficial to reduce the static electricity generated in the flat panel detector 1 during the manufacturing process.

[0087] In some embodiments, see Figure 4 and Figure 5 The photoelectric converter 41 includes a second electrode 411, a photoelectric conversion layer 412 and a third electrode 413 stacked sequentially on one side of the substrate 30. The thin film transistor 42 includes a gate 421, a source 422, a drain 423 and an active layer 424. The second electrode 411 is electrically connected to the drain 423.

[0088] In this embodiment, the thin-film transistor 42 is electrically connected to the photoelectric converter 41, thereby controlling the conduction state of the thin-film transistor 42 to enable the thin-film transistor 42 to detect the optical signal collected by the photoelectric converter 41.

[0089] In some embodiments, see Figure 8 The embodiments of this application also include a scintillator layer 80, a paraffin encapsulation film 90, and an aluminum film 10. The scintillator layer 80 is disposed on the side of the first electrode layer 70 away from the substrate 30, the paraffin encapsulation film 90 is disposed on the side of the scintillator layer 80 away from the substrate 30, and the aluminum film 10 is disposed on the side of the paraffin encapsulation film 90 away from the substrate 30.

[0090] In this embodiment, the scintillator layer 80 is used to convert X-ray photons into visible light. The material in the scintillator layer 80 interacts with the X-ray photons, thereby increasing the energy of the atoms in the scintillator layer 80. When the energy-activated atoms in the scintillator layer 80 return to the ground state, they emit visible light, which is detected by the photoelectric converter 41 and the thin-film transistor 42. Secondly, since the scintillator layer 80 is made of cesium iodide, the cesium iodide scintillator layer 80 is prone to water absorption and deliquescence. Therefore, a pyrene encapsulation film 90 needs to be provided on the side of the scintillator layer 80 away from the substrate 30 to protect the scintillator layer 80. After the pyrene encapsulation film 90 is provided, an aluminum film 10 is provided on the side of the pyrene encapsulation film 90 away from the substrate 30.

[0091] In some embodiments, the orthographic projection of the Parylene encapsulation film 90 onto the substrate 30 lies within the orthographic projection range of the scintillator layer 80 onto the substrate 30, and the orthographic projection of the scintillator layer 80 onto the substrate 30 lies within the orthographic projection of the aluminum film 10 onto the substrate 30. The edges of the Parylene encapsulation film 90, the scintillator layer 80, and the aluminum film 10 are located within the non-display area, thereby ensuring that the integrity and functionality of the display area are not affected and maintaining high-quality image output.

[0092] According to the embodiments of this application, the edge of the scintillator layer 80 is located within the non-display area, so that the scintillator layer 80 can completely cover the display area of ​​the flat panel detector 1, thereby enabling the scintillator layer 80 to completely cover the pixel unit 40 within the display area. This allows the scintillator layer 80 to convert X-ray photons into visible light, which can then be detected by the photoelectric converter 41 and the thin-film transistor 42. Secondly, since the pyrene encapsulation film 90 is prone to burrs, it can cause the aluminum film 10 to not fully adhere during the application process. Based on this, the embodiments of this application set the orthographic projection of the pyrene encapsulation film 90 on the substrate 30 within the orthographic projection range of the scintillator layer 80 on the substrate 30. This allows the pyrene encapsulation film 90 to protect the scintillator layer 80 and reduce the susceptibility of the scintillator layer 80 to absorb moisture and deliquescence. On the other hand, it solves the problem of the aluminum film 10 not fully adhering during the application process due to burrs on the pyrene encapsulation film 90.

[0093] In this embodiment, the scintillator layer 80 may include a plurality of cesium iodide columnar crystals arranged in an array. The diameter of each cesium iodide columnar crystal must be suitable for the pixel unit 40. If the cesium iodide columnar crystals are too thick, crosstalk will easily increase; if they are too thin, the light conversion efficiency of the columnar crystals will decrease and the spacing between the columnar crystals will increase, resulting in sparse pixels in the image generated by the flat panel detector 1.

[0094] In some examples, embodiments of this application use a physical vapor deposition process to form an aluminum film 10 on a Parylene encapsulation film 90. The aluminum film 10 and the Parylene encapsulation film 90 allow X-rays to pass through while reflecting visible light generated by the cesium iodide scintillator layer 80, thereby avoiding visible light loss and improving the performance of the flat panel detector 1. Of course, the material of the aluminum film 10 is not limited to this.

[0095] It should be noted that the aluminum film 10 serves two purposes: waterproofing and metal reflection. After X-ray irradiation is converted into visible light through the scintillator layer 80, the visible light enters the substrate and is reflected. The reflected light is then reflected and refracted again after reaching the aluminum film 10, thus improving the utilization rate of visible light.

[0096] In some embodiments, this application further includes a reading module 20, which is electrically connected to the first bias line 51. The reading module 20 can be used to read pixel data (or image data) of a plurality of pixel units 40, so that the subsequent processor can process the pixel data.

[0097] In some examples, the read module 20 can be a read-out integrated circuit (ROIC).

[0098] Figure 9 A schematic flowchart of the preparation method according to an embodiment of this application is shown. See also: Figure 9 As another aspect of this application, embodiments of this application also provide a method for manufacturing a flat panel detector 1, the flat panel detector 1 including a display area and a non-display area, the manufacturing method including:

[0099] S1. Provide a substrate 30.

[0100] S2. A plurality of pixel units 40 are formed on one side of the substrate 30. The plurality of pixel units 40 are disposed on one side of the substrate 30 and located in the display area. The pixel unit 40 includes a photoelectric converter 41 and a thin film transistor 42. The thin film transistor 42 is disposed on one side of the substrate 30. The photoelectric converter 41 is disposed on the side of the thin film transistor 42 away from the substrate 30.

[0101] S3. A metal trace layer 50 is formed on the side of the photoelectric conversion layer 412 away from the substrate 30. The metal trace layer 50 includes a first bias line 51 and a second bias line 52 that are electrically connected. The first bias line 51 is located in the non-display area, and the second bias line 52 is located in the display area and is electrically connected to the photoelectric converter 41.

[0102] S4. A first passivation layer 60 is formed on the side of the metal trace layer 50 away from the substrate 30. A plurality of first vias 61 are defined on the first passivation layer 60, corresponding to the plurality of pixel units 40. The plurality of first vias 61 are located in the display area.

[0103] S5. A first electrode layer 70 is formed on the side of the first passivation layer 60 away from the substrate 30. The first electrode layer 70 is electrically connected to the second bias line 52 through the first via 61.

[0104] In some embodiments, the first electrode layer 70 includes a plurality of first electrodes 71 corresponding to a plurality of pixel units 40, the plurality of first electrodes 71 being electrically connected to each other, and each first electrode 71 being electrically connected to a second bias line 52 through a corresponding first via 61.

[0105] As another aspect of this application, embodiments of this application also provide a detection device, which includes a flat panel detector 1 as described in any of the preceding embodiments or a flat panel detector 1 manufactured by the preparation method described in any of the preceding embodiments. Thus, this detection device possesses all the features and advantages of the aforementioned flat panel detector 1, which will not be repeated here.

[0106] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0107] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0108] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0109] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0110] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0111] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A flat panel detector, characterized in that, The flat panel detector includes a display area and a non-display area. Substrate; Multiple pixel units are disposed on one side of the substrate and located within the display area; each pixel unit includes an electrically connected photoelectric converter and a thin-film transistor; A metal trace layer is disposed on the side of the pixel unit away from the substrate, and includes a first bias line and a second bias line electrically connected. The first bias line is located in the non-display area, and the second bias line is located in the display area and electrically connected to the photoelectric converter. A first passivation layer is disposed on the side of the metal trace layer away from the substrate. A plurality of first vias corresponding to the plurality of pixel units are defined on the first passivation layer, and the plurality of first vias are located within the display area. A first electrode layer is disposed on the side of the first passivation layer opposite to the substrate, and the first electrode layer is electrically connected to the second bias line through the first via.

2. The flat panel detector according to claim 1, characterized in that, The first electrode layer is located within the display area.

3. The flat panel detector according to claim 1, characterized in that, The first electrode layer includes a plurality of first electrodes corresponding to the plurality of pixel units, the plurality of first electrodes are electrically connected to each other, and each first electrode is electrically connected to the second bias line through a corresponding first via.

4. The flat panel detector according to claim 1, characterized in that, The orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of the corresponding photoelectric converter on the substrate.

5. The flat panel detector according to claim 4, characterized in that, The first electrode includes at least a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion. The photoelectric converter includes at least a first edge, a second edge, a third edge, and a fourth edge. The orthographic projection of the first conductive portion on the substrate at least partially overlaps with the orthographic projection of the first edge of the corresponding photoelectric converter on the substrate. The orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the second edge of the corresponding photoelectric converter on the substrate. The orthographic projection of the third conductive portion on the substrate at least partially overlaps with the orthographic projection of the third edge of the corresponding photoelectric converter on the substrate. The orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the fourth edge of the corresponding photoelectric converter on the substrate.

6. The flat panel detector according to claim 1, characterized in that, The photoelectric converter includes a second electrode, a photoelectric conversion layer, and a third electrode stacked sequentially on one side of the substrate. The thin-film transistor includes a gate, a source, and a drain, and the second electrode is electrically connected to the drain.

7. The flat panel detector according to claim 1, characterized in that, It also includes a scintillator layer, a paraffin encapsulation film, and an aluminum film. The scintillator layer is disposed on the side of the first electrode layer away from the substrate. The paraffin encapsulation film is disposed on the side of the scintillator layer away from the substrate. The aluminum film is disposed on the side of the paraffin encapsulation film away from the substrate.

8. The flat panel detector according to claim 7, characterized in that, The orthographic projection of the Parylene encapsulation film on the substrate is within the orthographic projection range of the scintillator layer on the substrate, and the orthographic projection of the scintillator layer on the substrate is within the orthographic projection of the aluminum film on the substrate; the edges of the Parylene encapsulation film, the scintillator layer, and the aluminum film are located within the non-display area.

9. The flat panel detector according to claim 1, characterized in that, It also includes a reading module, which is electrically connected to the first bias line.

10. A method for fabricating a flat panel detector, characterized in that, The flat panel detector includes a display area and a non-display area, and the fabrication method includes: Provide substrates; A plurality of pixel units are formed on one side of a substrate, the plurality of pixel units being disposed on one side of the substrate and located within the display area; each pixel unit includes a photoelectric converter and a thin-film transistor; the thin-film transistor is disposed on one side of the substrate; the photoelectric converter is disposed on the side of the thin-film transistor opposite to the substrate. A metal trace layer is formed on the side of the photoelectric conversion layer away from the substrate; the metal trace layer includes a first bias line and a second bias line that are electrically connected, the first bias line being located in the non-display area, and the second bias line being located in the display area and electrically connected to the photoelectric converter; A first passivation layer is formed on the side of the metal trace layer away from the substrate. A plurality of first vias corresponding to the plurality of pixel units are defined on the first passivation layer. The plurality of first vias are located within the display area. A first electrode layer is formed on the side of the first passivation layer away from the substrate, and the first electrode layer is electrically connected to the second bias line through the first via.

11. The preparation method according to claim 10, characterized in that, The first electrode layer includes a plurality of first electrodes corresponding to the plurality of pixel units, the plurality of first electrodes are electrically connected to each other, and each first electrode is electrically connected to the second bias line through a corresponding first via.

12. A detection device, characterized in that, This includes a flat panel detector as described in any one of claims 1 to 9, or a flat panel detector manufactured using the method described in claim 10 or 11.

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