Topcon cell integrated rca degumming etching micro-texturing process

Abstract

The application discloses a TOPCon cell integrated RCA degumming etching micro-texturing process, and aims at the process status of the existing RCA without texturing, RCA direct ALD of the photolithography patterned cell for mass production of TOPCon selective passivation, and embeds an integrated selective micro-texturing section after the completion of the internal, back Poly-Si patterned positive etching and two-stage water washing of the slot-type RCA, so that the whole RCA continuous wet process synchronously completes photoresist removal, front side around-plating Poly-Si etching, back side excess Poly-Si patterning, back side exposed silicon substrate micro-texturing surface preparation, and direct ALD after drying, without the need of adding external independent texturing equipment; the whole RCA wet process completely abandons the ammonia water cleaning formula, adopts a low-concentration KOH / NaOH inorganic alkali-hydrogen peroxide system to realize photoresist removal, eliminates ALD film defects induced by ammonia gas volatilization pollution and ammonium salt residues, and the degumming alkali source is homologous to the micro-texturing KOH system in the back end, so that waste liquid treatment is simplified.

Description

Technical Field

[0001] This invention relates to the field of TOPCon battery technology, and in particular to an integrated RCA texturing process for TOPCon batteries. Background Technology

[0002] TOPCon selective passivation (Poly-finger) bifacial cells are the mainstream technology route for current N-type high-efficiency photovoltaic cells. Its core architecture is: only the metal grid contact area on the back retains an ultra-thin tunnel oxide layer and a doped polycrystalline silicon (Poly-Si) structure, while the rest of the area exposes the silicon substrate, and is combined with atomic layer deposition (ALD) aluminum oxide film to achieve full back-side passivation.

[0003] The standard process flow for mass-produced TOPCon selective passivation cells is as follows: N-type silicon wafer boron diffusion → tunnel oxide layer + intrinsic Poly-Si deposition → in-situ phosphorus diffusion to form the front PSG layer → back screen printing photoresist patterning (only the area corresponding to the grid line is covered with a photoresist protective layer) → UV curing photoresist → PSG chain machine processing (etching to remove the oxide layer in the area on the back without photoresist coverage, and simultaneously removing excess Poly-Si around the front) → traditional tank RCA process → water washing, acid washing, slow pull-out drying → ALD deposition of aluminum oxide passivation layer → PECVD silicon nitride coating, metal screen printing, and high-temperature sintering.

[0004] Among them, the tank-type RCA is the core wet process for achieving back-side patterning. Traditional RCA in the industry only involves alkaline hydrogen peroxide removal, water washing, Poly-Si positive etching, water washing, acid pickling and neutralization, and multi-stage water washing and drying. The entire process lacks silicon surface morphology control, and the process goal is only to remove photoresist residue and selectively etch the non-gate area Poly-Si thin film on the back side. After uniform thin etching, the exposed silicon substrate on the back side forms a highly smooth polished mirror surface without any microtexture morphology.

[0005] The alumina film is uniformly spread on the polished silicon surface, and the contact area between silicon and the passivation film is equal to the geometric area of ​​the silicon wafer. The back of the bifacial cell relies on ambient diffuse reflection light to generate electricity. The high reflectivity of the polished mirror surface greatly reduces the effective light absorption on the back. At the same time, the passivation effect of alumina is positively correlated with the specific surface area of ​​the silicon film. The flat interface has a large number of minority carrier recombination centers, which limits the passivation performance of the cell.

[0006] Currently, there is no mature solution in the industry: No native texturing process: There is no independent texturing section between RCA and ALD on existing mass production lines. The coating is applied directly, and the back side is always polished. The shortcomings of passivation and double-sided ratio cannot be improved by the existing process. The new external texturing solution has significant drawbacks: if an independent alkaline texturing tank is added after RCA, an additional set of temperature control, chemical circulation, and transfer equipment must be purchased, increasing the production line footprint and equipment investment; silicon wafers require an additional loading and unloading transfer, increasing the breakage rate; the strong alkaline texturing solution will laterally erode the ultra-thin Poly-Si tunneling layer in the gate area, damaging the selective passivation contact and deteriorating the electrical performance. Thickening the alumina film only slightly optimizes the passivation charge density, cannot increase the silicon film contact interface, and has limited passivation gain. Excessive alumina thickness will increase back-side optical reflection, further reducing the bifaciality. Global front-side silicon texturing completely etches the entire Poly-Si thin film on the back side, making it impossible to achieve local selective passivation and unsuitable for photolithographic patterned Poly-finger architectures.

[0007] Existing technologies cannot simultaneously complete cleaning and etching and selective microtexturing on the back side within the original RCA continuous wet process, resulting in multiple shortcomings such as insufficient passivation, low double-sided ratio, high cost of improvement and modification, and poor compatibility.

[0008] The core drawbacks of traditional non-flush RCA process Single process function: Traditional RCA only achieves resist removal and backside Poly-Si patterning etching, without the ability to control the micro-morphology of silicon surface. After RCA is discharged, the non-gate contact area on the backside is polished mirror. Shortcomings in passivation performance: The small contact area at the polished silicon / alumina interface leads to severe minority carrier recombination on the silicon surface, limiting the potential for increasing the open-circuit voltage of the battery, and resulting in significant passivation degradation after damp heat aging. Poor bifacial power generation performance: The visible light mirror reflectivity of the polished back surface exceeds 32%, resulting in low back-reflected light capture efficiency. The bifaciality of mass-produced batteries is generally below 72%. The improved solution has poor compatibility and high cost: If the back microtextured surface is to be prepared, an independent texturing section must be added between RCA and ALD, which will increase equipment investment, chemical consumption and silicon wafer transport fragmentation rate simultaneously; and the strong alkaline texturing solution is easy to corrode the gate line region and tunnel through Poly-Si, destroying the selective passivation contact structure. The process is complicated and the cleanliness is reduced: the addition of external texturing will increase the number of water washing and buffer transfer stations, and the silicon wafer surface is prone to adsorption of particles and metal impurities, which will induce pinhole defects in the ALD aluminum oxide film and reduce the yield of the battery.

[0009] Therefore, it is necessary to develop a TOPCon battery integrated RCA resist removal etching microtexturing process to solve the above problems. Summary of the Invention

[0010] The purpose of this invention is to design a TOPCon battery integrated RCA resist removal etching microtexturing process to solve the above problems.

[0011] The present invention achieves the above objectives through the following technical solutions: TOPCon's integrated RCA texturing process for battery assembly includes: S1. Photoresist removal process: The silicon wafer is immersed in an ammonia-free inorganic alkali-hydrogen peroxide solution in an alkaline hydrogen peroxide removal tank to remove photoresist residue and organic impurities from the surface of the silicon wafer. S2, First-level water washing step: Send the silicon wafer into the first-level water washing tank and use room temperature ultrapure water overflow to wash away the residual alkaline adhesive remover on the surface of the silicon wafer. S3. Polysilicon patterning etching steps: The silicon wafer is sent into the back polysilicon positive etching tank, and the silicon wafer is immersed in the acidic etching solution buffered by dilute nitric acid-hydrofluoric acid to remove the polysilicon in the back area without photoresist protection, leaving only the tunneling polysilicon layer at the corresponding position of the gate line; the front side of the silicon wafer is isolated from the etching solution by the PSG oxide layer, and there is no over-etching damage to the front silicon substrate. S4, Secondary water washing step: Send the silicon wafer into the secondary water washing tank and rinse it with room temperature ultrapure water overflow to thoroughly remove acidic etching residue from the surface of the silicon wafer; S5. Selective texturing step: The silicon wafer is placed in a selective texturing tank and immersed in an alkaline texturing solution containing potassium hydroxide, isopropanol, and silicon crystal surface orientation buffer. Relying on the double barrier effect of photoresist and tunneling polysilicon in the back gate area, the texturing solution only contacts the exposed silicon substrate where the back polysilicon has been completely etched away, and directional etching is performed to generate pyramidal microtexture on the back non-gate area silicon substrate. The front side of the silicon wafer is isolated from the alkaline solution by the PSG oxide layer, and the front morphology is not roughened. S6, Neutralization and pickling step: The silicon wafer is sent into the pickling and neutralization tank and immersed in dilute HF aqueous solution at room temperature to neutralize the strong alkali residue on the surface of the silicon wafer, terminate the silicon substrate etching reaction, peel off the surface natural oxide layer and remove trace metal impurities. S7. Multi-stage rinsing steps: The silicon wafer is sent into a multi-stage overflow water washing tank, and ultrapure water overflow cleaning is performed in multiple stages to remove acid and alkali ion residues on the surface of the silicon wafer step by step. S8. Drying step: The silicon wafer is sent into the slow-lift drying tank and dried by gradient hot air slow lifting.

[0012] As a preferred embodiment, in step S1, the mass fraction ratio of the ammonia-free inorganic alkali-hydrogen peroxide solution is: 0.08%-0.15% potassium hydroxide, 1.8%-2.5% 30% hydrogen peroxide, 0.05%-0.1% nonionic surfactant, and the remainder is ultrapure water; in the degumming step, the temperature is 60-70℃, the soaking time is 3-5 minutes, and nitrogen gas is gently bubbled and stirred at the bottom.

[0013] As another preferred option, in step S1, the ammonia-free inorganic alkali-hydrogen peroxide solution is replaced with a NaOH system solution. The mass fraction of the NaOH system solution is: 0.05%-0.12% sodium hydroxide, 1.8%-2.5% 30% hydrogen peroxide, 0.05%-0.1% nonionic surfactant, and the remainder is ultrapure water.

[0014] Preferably, in step S3, the treatment temperature is 25-30℃, and the soaking time is 90-150 seconds.

[0015] Preferably, in step S2, the overflow cleaning time of the primary water washing tank is 2 minutes; in step S4, the overflow cleaning time of the secondary water washing tank is 1.5-2.5 minutes.

[0016] Preferably, in step S5, the mass fraction of the alkaline texturing solution is: 2%-4% potassium hydroxide, 0.8%-1.5% isopropanol, 0.02%-0.04% silicon crystal surface orientation buffer, and the remainder is ultrapure water; in the selective microtexturing step: the temperature is independently controlled at 78-85℃, soaking for 90-180s, low-flow nitrogen bubbling, and etching to generate 2-5μm pyramidal microtexture.

[0017] Preferably, in step S6, the mass fraction of the dilute HF aqueous solution is 0.5%-1%, and it is soaked at room temperature for 1.5-2.5 minutes.

[0018] Preferably, in step S7, the multi-stage rinsing step consists of three stages of sequential cleaning, with a total rinsing time of 3-4 minutes.

[0019] Preferably, in step S8, the drying temperature in the slow-pulling drying tank is 80-90℃, and the silicon wafer pulling rate is 0.8-1.2cm / s.

[0020] Preferably, the alkaline hydrogen peroxide desizing tank, the back polycrystalline silicon positive etching tank, and the selective microtexturing tank are each equipped with a 50nm circulating filter for filtering silicon microparticles.

[0021] The beneficial effects of this invention are as follows: To address the current state of mass-produced TOPCon selective passivation photolithography patterned cells, where RCA (Rice Anode Material) is not texturized and ALD is performed directly after RCA, an integrated selective micro-texturing process is embedded inside the grooved RCA, after the back Poly-Si patterning and secondary water washing are completed. The entire RCA continuous wet process simultaneously completes photoresist removal, front Poly-Si etching, back excess Poly-Si patterning, and back exposed silicon substrate micro-texturing preparation. After drying, it is directly sent to ALD without the need for additional external independent texturing equipment. The entire RCA wet process abandons the ammonia cleaning formula and uses a low-concentration KOH / NaOH inorganic alkali-hydrogen peroxide system to remove photoresist, eliminating ALD film defects induced by ammonia volatilization pollution and ammonium salt residue. Moreover, the photoresist removal alkali source can be the same as the downstream microtexturing KOH system, simplifying waste liquid treatment. A dual-layer selective barrier protection mechanism of photoresist in the back gate area and Poly-Si in the bottom layer is adopted. The micro-texturing alkaline solution only etches the bare silicon substrate on the back without the protective layer to generate micron-textured material, without etching the Poly-Si thin film tunneling through the gate contact area, thus fully preserving the TOPCon local selective passivation contact core structure. A specific alkaline solution system for embedded microtexturing of RCA (2%-4% KOH, 0.8%-1.5% IPA, 0.02%-0.04% silicon crystal surface orientation buffer) and a matching etching process window of 78-85℃ and 90-180s are used to precisely control the microtexture size of 2-5μm, and simultaneously achieve passivation gain and back-side light absorption enhancement. A complete, integrated RCA process sequence is constructed: alkaline hydrogen peroxide desizing tank → primary water wash → Poly-Si positive etching tank → secondary water wash → embedded microtexturing tank → acid pickling and neutralization tank → multi-stage water wash and drying. The chemical solutions, temperatures, and soaking times of each stage are coordinated and matched to avoid cross-contamination of chemical solutions and loss of control over etching and texturing morphology. The micro-textured structure increases the contact surface area between the silicon substrate and the ALD alumina passivation film, and the coupling achieves improved back-side passivation performance and enhanced back-side reflected light capture, while simultaneously improving the cell's open-circuit voltage, bifaciality, and photoelectric conversion efficiency. Attached Figure Description

[0022] Figure 1 A schematic diagram of the overall process flow for TOPCon selective passivation batteries; Figure 2 This is a schematic diagram of the process of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0025] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0026] In the description of this invention, it should be understood that the terms "upper," "lower," "inner," "outer," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this invention and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0027] Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0028] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, terms such as "set" and "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0029] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0030] like Figure 2 As shown, the TOPCon battery integrated RCA resist removal etching microtexturing process includes: S1. Photoresist removal process: The silicon wafer is immersed in an ammonia-free inorganic alkali-hydrogen peroxide solution in an alkaline hydrogen peroxide removal tank to remove photoresist residue and organic impurities from the surface of the silicon wafer. As a preferred embodiment, in step S1, the mass fraction ratio of the ammonia-free inorganic alkali-hydrogen peroxide solution is: 0.08%-0.15% potassium hydroxide, 1.8%-2.5% 30% hydrogen peroxide, 0.05%-0.1% nonionic surfactant, and the balance being ultrapure water. In the photoresist removal step, the temperature is 60-70℃, and the soaking time is 3-5 minutes, with gentle bubbling and stirring at the bottom using nitrogen. Function: Utilizing low-concentration KOH alkaline hydrolysis of the photoresist crosslinking resin, combined with the strong oxidizing properties of hydrogen peroxide, thoroughly oxidizes and decomposes photoresist residues, organic contaminants, and silicon particle impurities introduced by the PSG chain process on the silicon wafer surface; the UV-curable photoresist in the back gate area is resistant to dilute alkali immersion, preventing lateral corrosion and thinning of the underlying Poly-Si film, and completely preserving the selective passivation contact protection layer.

[0031] As another preferred option, in step S1, the ammonia-free inorganic alkali-hydrogen peroxide solution is replaced with a NaOH system solution. The mass fraction of the NaOH system solution is: 0.05%-0.12% sodium hydroxide, 1.8%-2.5% 30% hydrogen peroxide, 0.05%-0.1% nonionic surfactant, and the balance is ultrapure water. Function: The low-alkali NaOH system efficiently removes organic residues from the photoresist, while hydrogen peroxide simultaneously removes surface particles and carbonaceous contaminants. Strict control of the low alkali concentration avoids etching the gate area to cure the photoresist and the underlying Poly-Si, removing only surface impurities in the non-adhesive areas without damaging the back-side patterned protective structure.

[0032] S2, First-level water washing step: The silicon wafer is sent into the first-level water washing tank and cleaned with room temperature ultrapure water overflow to remove residual alkaline adhesive remover on the surface of the silicon wafer and avoid the alkaline solution being carried into the subsequent positive etching tank and interfering with the etching rate; the overflow cleaning time of the first-level water washing tank is 2 minutes. S3. Polysilicon Patterning Etching Step: The silicon wafer is placed into the back polysilicon positive etching tank and immersed in a dilute nitric acid-hydrofluoric acid buffered acidic etching solution at a temperature of 25-30℃ for 90-150 seconds. The polysilicon in the back area without photoresist protection is selectively etched, leaving only the tunneling polysilicon layer at the corresponding positions of the gate lines, thus completing the selective passivation pattern construction on the back side. The front silicon substrate is protected by a complete PSG oxide layer, and there is no over-etching damage to the front silicon substrate. S4, Secondary water washing step: Send the silicon wafer into the secondary water washing tank and rinse with room temperature ultrapure water overflow for 1.5-2.5 minutes to thoroughly remove acidic etching residue from the surface of the silicon wafer; isolate the acidic positive etching solution from the subsequent alkaline microtexturing system to prevent the solution from neutralizing and failing, and to prevent uneven texturing morphology; S5. Selective Microtexturing Step: The silicon wafer is placed in a selective microtexturing bath and immersed in an alkaline texturing solution containing potassium hydroxide, isopropanol, and silicon crystal surface orientation buffer. The double barrier effect of the upper layer of alkali-resistant photoresist and the lower layer of tunneling polysilicon in the back gate area prevents the alkaline texturing solution from contacting the silicon substrate. The texturing solution only contacts the exposed silicon substrate where the back polysilicon has been completely etched away, generating 2-5μm pyramidal microtexture on the non-gate area of ​​the back silicon substrate. The front side of the silicon wafer is isolated from the alkaline solution by a PSG oxide layer, preventing roughening of the front morphology. The mass fraction of the alkaline texturing solution is: 2%-4% potassium hydroxide, 0.8%-1.5% isopropanol, 0.02%-0.04% silicon crystal surface orientation buffer, with the remainder being ultrapure water. In the selective microtexturing step: independent temperature control at 78-85℃, immersion for 90-180 seconds, and low-flow nitrogen bubbling.

[0033] S6, Neutralization and Pickling Step: The silicon wafer is placed in the pickling and neutralization tank and immersed in a dilute HF aqueous solution at room temperature for 1.5-2.5 minutes. The mass fraction of the dilute HF aqueous solution is 0.5%-1%. This neutralizes the residual strong alkali on the surface of the silicon wafer, terminates the etching reaction of the silicon substrate, peels off the surface natural oxide layer and removes trace metal impurities, and locks the micro-texture morphology size. S7. Three-stage rinsing step: The silicon wafer is sent into the three-stage overflow water rinsing tank. The three-stage ultrapure water overflow rinsing is carried out in series for a total water rinsing time of 3-4 minutes. The residual acid and alkali ions on the surface of the silicon wafer are removed step by step to improve the cleanliness of the micro-fiber gaps. S8. Drying Step: The silicon wafer is fed into a slow-lift drying tank and dried slowly with gradient hot air. The drying temperature in the slow-lift drying tank is 80-90℃, and the silicon wafer lifting rate is 0.8-1.2cm / s. This avoids watermark defects caused by residual water stains in the microtextured gaps. After drying, the silicon wafer is directly transferred to the ALD process without an intermediate texturing step.

[0034] Supporting collaborative control scheme: Precision filtration of the solution: The alkaline hydrogen peroxide degumming tank, the back polycrystalline silicon positive etching tank, and the selective microtexturing tank are each equipped with a 50nm circulating filter to filter silicon microparticles and prevent point defects from forming on the microtextured surface. Transmission interlock control: The silicon wafer basket transmission speed is linked to the immersion time of each tank, and the uniformity deviation of the micro-texture size on the back of batch silicon wafers is ≤5%; Photoresist matching requirements: Select a weak alkali resistant UV curing photoresist to prevent swelling and peeling during resist removal and microtexturing processes, and continuously protect the Poly-Si gate area; Physical isolation of the tank: The micro texturing tank is equipped with an independent heat-insulating cavity, which is heat-insulated from the previous room temperature positive etching tank to avoid heat crosstalk causing fluctuations in etching and texturing parameters; Unified optimization of alkali source: KOH system is preferred in the degumming section, which is consistent with the alkali source of the micro-texturing tank. The waste liquid has a single component, which simplifies the neutralization process and eliminates the need for ammonia water waste gas treatment.

[0035] like Figure 1 As shown, the complete process flow (TOPCon overall fabrication process) of this application is as follows: N-type silicon wafer boron diffusion → tunneling oxide layer + intrinsic Poly-Si deposition → phosphorus diffusion to form front PSG layer → back photoresist printing patterning (gate area covered with photoresist protective layer) → UV curing photoresist → PSG chain machine (removing oxide layer in the back uncoated area and etching off the front Poly-Si coating) → integrated microtexturing and RCA process of this invention → slow pull-out drying → direct transport to ALD equipment to deposit alumina passivation layer → subsequent silicon nitride coating, metallization printing, and sintering.

[0036] This application sets up a control group: the existing mass-produced conventional RCA process (without built-in microtexturing, using ammonia-based cleaning solution, direct ALD after RCA, and back-side polishing to a mirror finish); the experimental group uses the integrated embedded microtexturing RCA process of this invention (inorganic alkali removal, ammonia-free, built-in microtexturing); the silicon substrate, diffusion, Poly-Si deposition, ALD, metallization, and sintering parameters are completely identical for both groups, and the batch production test data are as follows: 1. Backside morphology and optical properties Control group (traditional polished substrate + ammonia cleaning): Silicon-alumina contact surface area = 1 times geometric area; average back reflectance at 550nm visible light 32.8%; trace amounts of ammonium salt impurities present on the silicon wafer surface; pinhole defect rate of ALD film 0.87%; Experimental group (microtextured substrate of this invention + inorganic alkali cleaning): The specific surface area of ​​silicon-alumina contact increased by 2.5-3.3 times; the average back surface reflectance at 550nm decreased to 14.6%-16.8%; no ammonium salt residue; and the pinhole defect rate of ALD film decreased to 0.12%. 2. Backside passivation performance Backside minority carrier lifetime: 1260 μs in control group; 1740-1910 μs in experimental group, with a significant reduction in surface carrier recombination. Battery open-circuit voltage Uoc: control group 712.1mV; experimental group 717.9-722.0mV, an increase of 5.8-9.9mV; 3. Battery photoelectric output performance (182mm bifacial TOPCon battery) Double-sidedness: Control group 71.1%; Experimental group 79.4%-81.5%; Photoelectric conversion efficiency: control group 25.30%; experimental group 25.70%-25.90%, single-chip efficiency improved by 0.40-0.60 percentage points; Fill factor FF: 83.38% in the control group and 83.53%-83.71% in the experimental group, with no deterioration in series resistance caused by Poly-Si lateral corrosion; 4. Advantages of production line in terms of mass production cost, environmental protection, and capacity. There is no need to add an external independent texturing tank, temperature control, and chemical circulation equipment between RCA and ALD, saving approximately RMB 1.15 million in new equipment investment for a single 10,000 pieces / hour mass production line; at the same time, the ammonia waste gas collection and treatment device is eliminated, reducing investment in environmental protection equipment. By eliminating the two transfer and buffer stations before and after the external texturing section, the total processing time for a single piece of wet processing is reduced by 85-140 seconds, and the effective production line capacity is increased by 13%. The integrated process centrally utilizes the texturing solution, reducing the total consumption of KOH and IPA by 66%; the waste liquid contains only a single alkaline ion, reducing the amount of neutralizing agent used by 40%, and significantly reducing chemical operating costs; Without additional silicon wafer loading and unloading transfer steps, the silicon wafer breakage rate decreased from 0.43% to 0.20%, improving mass production yield; the workshop is free of the irritating odor of ammonia, improving the production environment; Long-term reliability testing Comparison of performance degradation after 400h of 85℃ / 85RH damp heat aging: The passivation performance of the control group decreased by 2.8%; the experimental group of this invention decreased by only 1.0%, the interface bonding of the micro-velvet structure alumina film is more stable, there is no ammonium salt impurity to induce local failure, and the battery’s resistance to damp heat aging is significantly optimized.

[0037] This application provides the following embodiments and comparative examples: Example 1 (Optimal Solution for Mass Production Standards) This embodiment is adapted to a standard 182mm N-type silicon wafer with a thickness of 155μm, and uses a KOH resist removal system. The specific process steps are as follows: Pre-processing: The N-type 182 silicon wafer undergoes boron diffusion, tunnel oxide layer and intrinsic Poly-Si deposition, and phosphorus diffusion to form the front PSG layer. The back side is patterned with photoresist printing, and the area corresponding to the gate line is covered with a photoresist protective layer. After UV curing, it is sent to the PSG chain machine for processing to remove the oxide layer in the non-resin area on the back side and to etch away the Poly-Si around the front side.

[0038] Integrated RCA Wet Processing: ① Alkaline Hydrogen Peroxide Removal: A KOH system is used, with a solution ratio of 0.12wt% KOH + 2.2wt% 30% hydrogen peroxide + 0.07wt% nonionic surfactant, and the remainder being ultrapure water; the process temperature is 68℃, soaking for 4 minutes, with gentle bubbling and stirring at the bottom using nitrogen. ② First-Stage Water Rinse: Overflow rinsing with ultrapure water at room temperature for 2 minutes. ③ Poly-Si Positive Etching: Using a dilute nitric acid-hydrofluoric acid buffered etching solution, soaking at 28℃ for 120 seconds, selectively etching excess Poly-Si in the unprotected areas on the back side. ④ Second-Stage Water Rinse: Overflow rinsing with ultrapure water at room temperature for 2 minutes. ⑤ Embedded Microtexturing: The solution ratio is 3wt% KOH + 1.2wt% IPA + 0.03wt% silicon crystal surface orientation buffer, with the remainder being ultrapure water; soaking at 82℃ for 135 seconds, generating uniform 3-4μm pyramidal microtexture on the back side. ⑥ Acid pickling and neutralization: Immerse in 0.8wt% dilute HF aqueous solution at room temperature for 2 minutes. ⑦ Three-stage overflow water rinse: Total water rinse time 3.5 minutes. ⑧ Slow lifting and drying: Gradient hot air drying at 85℃, lifting speed 1.0 cm / s.

[0039] Subsequent processes: After drying, the silicon wafer is directly fed into the ALD equipment to deposit an 8nm alumina passivation layer, followed by silicon nitride coating, screen printing of metal grid lines, and high-temperature sintering at 820℃.

[0040] The test results of the finished product in this embodiment are as follows: the specific surface area of ​​the silicon-alumina contact is 2.95 times that of the silicon-alumina contact, the average back reflectance at 550nm wavelength is 15.5%, the back minority carrier lifetime is 1860μs, the open circuit voltage Uoc is 720.8mV, the bifaciality is 80.9%, the photoelectric conversion efficiency is 25.87%, the silicon wafer fragmentation rate is 0.19%, and the pinhole defect rate of the ALD thin film is 0.11%.

[0041] Example 2 (Low-Cost Solution for Ultrathin Silicon Wafers) This embodiment is adapted for 140-150μm ultrathin silicon wafers, using a NaOH resist removal system and a low-temperature, short-time texturing process to control the wafer thinning amount. Specific parameters are as follows: The preceding steps are the same as in Example 1.

[0042] Integrated RCA wet processing: ① Alkaline hydrogen peroxide desmearing: Using a NaOH system, the solution ratio is 0.09wt% NaOH + 2.0wt% 30% hydrogen peroxide + 0.06wt% nonionic surfactant, with the remainder being ultrapure water; soaking at 65℃ for 3.5 min. ② First-stage water wash: overflow rinsing at room temperature for 2 min. ③ Poly-Si positive etching: Same as Example 1. ④ Second-stage water wash: overflow rinsing at room temperature for 2 min. ⑤ Embedded microtexturing: The solution ratio is 2wt% KOH + 0.8wt% IPA + 0.03wt% buffer; soaking at 78℃ for 95 s to generate 2-3μm microtexture, with an overall silicon substrate thinning of ≤7μm. ⑥ Acid washing and neutralization, water washing, and drying parameters are the same as in Example 1.

[0043] Subsequent procedures are the same as in Example 1.

[0044] The test results of the finished product in this embodiment are as follows: double-sidedness 79.4%, photoelectric conversion efficiency 25.70%, and ultra-thin silicon wafer fragmentation rate 0.22%.

[0045] Example 3 (Customized Solution for High Duplexity) This embodiment is adapted for ground-based high-reflectivity scene components, employing a high-temperature long texturing process to maximize backside light absorption and bifaciality. Specific parameters are as follows: The preceding steps are the same as in Example 1.

[0046] Integrated RCA wet treatment: ① Alkaline hydrogen peroxide degumming: Using a KOH system, the solution ratio is 0.15wt% KOH + 2.5wt% 30% hydrogen peroxide + 0.1wt% nonionic surfactant, soaked at 70℃ for 5 min. ② First-stage water washing, Poly-Si positive etching, and second-stage water washing are the same as in Example 1. ③ Embedded microtexturing: The solution ratio is 4wt% KOH + 1.5wt% IPA + 0.03wt% buffer, soaked at 85℃ for 175 s, generating 4-5μm microtexture with a contact surface area of ​​3.3 times. ④ Acid washing and neutralization, water washing, and drying parameters are the same as in Example 1.

[0047] Subsequent procedures are the same as in Example 1.

[0048] The test results of the finished product in this embodiment are as follows: back reflectivity at 550nm wavelength is 14.6%, double-sidedness is 81.5%, and photoelectric conversion efficiency is 25.90%.

[0049] Comparative example (existing traditional process) The existing mass-produced conventional ammonia-based RCA process is adopted, without an embedded micro-texturing section: the RCA resist removal uses an ammonia-based SC1 cleaning solution, and the process is resist removal → water washing → Poly-Si positive etching → water washing → acid washing → water washing and drying, without an embedded micro-texturing section; the remaining diffusion, coating, metallization, and sintering parameters are completely consistent with those in Example 1.

[0050] Test results: The back surface is a polished mirror with a reflectivity of 32.8% at 550nm wavelength; the minority carrier lifetime on the back surface is 1260μs; the open-circuit voltage Uoc = 712.1mV; the bifaciality is 71.1%; the conversion efficiency is 25.30%; the silicon wafer fragmentation rate is 0.43%; and the pinhole defect rate of the ALD thin film is 0.87%.

[0051] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. The TOPCon battery integrated RCA resist removal etching microtexturing process, characterized in that, include: S1. Photoresist removal process: The silicon wafer is immersed in an ammonia-free inorganic alkali-hydrogen peroxide solution in an alkaline hydrogen peroxide removal tank to remove photoresist residue and organic impurities from the surface of the silicon wafer. S2, First-level water washing step: Send the silicon wafer into the first-level water washing tank and use room temperature ultrapure water overflow to wash away the residual alkaline adhesive remover on the surface of the silicon wafer. S3. Polysilicon patterning etching steps: The silicon wafer is sent into the back polysilicon positive etching tank, and the silicon wafer is immersed in the acidic etching solution buffered by dilute nitric acid-hydrofluoric acid to remove the polysilicon in the back area without photoresist protection, leaving only the tunneling polysilicon layer at the corresponding position of the gate line; the front side of the silicon wafer is isolated from the etching solution by the PSG oxide layer, and there is no over-etching damage to the front silicon substrate. S4, Secondary water washing step: Send the silicon wafer into the secondary water washing tank and rinse it with room temperature ultrapure water overflow to thoroughly remove acidic etching residue from the surface of the silicon wafer; S5. Selective texturing step: The silicon wafer is placed into a selective texturing tank and immersed in an alkaline texturing solution containing potassium hydroxide, isopropanol, and silicon crystal surface orientation buffer. Relying on the double barrier effect of photoresist and tunneling polysilicon in the back gate area, the texturing solution only contacts the exposed silicon substrate where the back polysilicon has been completely etched away, and directional etching is performed to generate pyramidal microtexture on the back non-gate area silicon substrate. The front side of the silicon wafer is isolated from the alkaline solution by the PSG oxide layer, and the front morphology is not roughened. S6, Neutralization and pickling step: The silicon wafer is sent into the pickling and neutralization tank and immersed in dilute HF aqueous solution at room temperature to neutralize the strong alkali residue on the surface of the silicon wafer, terminate the silicon substrate etching reaction, peel off the surface natural oxide layer and remove trace metal impurities. S7. Multi-stage rinsing steps: The silicon wafer is sent into a multi-stage overflow water washing tank, and ultrapure water overflow cleaning is performed in multiple stages to remove acid and alkali ion residues on the surface of the silicon wafer step by step. S8. Drying step: The silicon wafer is sent into the slow-lift drying tank and slowly lifted and dried with gradient hot air.

2. The TOPCon battery integrated RCA resist removal etching microtexturing process according to claim 1, characterized in that, In step S1, the mass fraction ratio of the ammonia-free inorganic alkali-hydrogen peroxide solution is: 0.08%-0.15% potassium hydroxide, 1.8%-2.5% 30% hydrogen peroxide, 0.05%-0.1% nonionic surfactant, and the remainder is ultrapure water; in the degumming step, the temperature is 60-70℃, the soaking time is 3-5 minutes, and nitrogen gas is gently bubbled and stirred at the bottom.

3. The TOPCon battery integrated RCA resist removal etching microtexturing process according to claim 1, characterized in that, In step S1, the ammonia-free inorganic alkali-hydrogen peroxide solution is replaced with a NaOH system solution. The mass fraction of the NaOH system solution is: 0.05%-0.12% sodium hydroxide, 1.8%-2.5% 30% hydrogen peroxide, 0.05%-0.1% nonionic surfactant, and the remainder is ultrapure water.

4. The TOPCon battery integrated RCA resist removal etching microtexturing process according to claim 1, characterized in that, In step S3, the temperature is 25-30℃ and the soaking time is 90-150 seconds.

5. The TOPCon battery integrated RCA resist removal etching microtexturing process according to claim 1, characterized in that, In step S2, the overflow cleaning time of the primary water washing tank is 2 minutes; In S4, the overflow cleaning time of the secondary water washing tank is 1.5-2.5 minutes.

6. The TOPCon battery integrated RCA resist removal etching microtexturing process according to claim 1, characterized in that, In step S5, the mass fraction of the alkaline texturing solution is: 2%-4% potassium hydroxide, 0.8%-1.5% isopropanol, 0.02%-0.04% silicon crystal surface orientation buffer, and the balance is ultrapure water; in the selective microtexturing step: the temperature is independently controlled at 78-85℃, soaking for 90-180s, low-flow nitrogen bubbling, and etching to generate 2-5μm pyramid microtexture.

7. The TOPCon battery integrated RCA resist removal etching microtexturing process according to claim 1, characterized in that, In step S6, the mass fraction of the dilute HF aqueous solution is 0.5%-1%, and it is soaked at room temperature for 1.5-2.5 minutes.

8. The TOPCon battery integrated RCA resist removal etching microtexturing process according to claim 1, characterized in that, In step S7, the multi-stage rinsing step consists of three stages of cascading cleaning, with a total rinsing time of 3-4 minutes.

9. The TOPCon battery integrated RCA resist removal etching microtexturing process according to claim 1, characterized in that, In step S8, the drying temperature in the slow-pulling drying tank is 80-90℃, and the silicon wafer pulling rate is 0.8-1.2cm / s.

10. The TOPCon battery integrated RCA resist removal etching microtexturing process according to claim 1, characterized in that, The alkaline hydrogen peroxide desmearing tank, the back polycrystalline silicon positive etching tank, and the selective microtexturing tank are each equipped with a 50nm circulating filter for filtering silicon microparticles.

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