A solar cell and a method for improving laser residues thereof

Abstract

The application discloses a solar cell and a method for improving laser residues of the solar cell, and belongs to the technical field of solar cells. The method comprises the following steps: performing acid pickling on a silicon wafer after boron diffusion treatment, so as to remove a BSG layer formed by boron diffusion, and obtaining a first silicon wafer; depositing a low-boron BSG layer on the back surface of the first silicon wafer, and then performing first patterning treatment, so as to form a first patterned groove; removing BSG around the front surface; removing a doped polysilicon layer and a tunneling oxide layer corresponding to the position of the first patterned groove through alkali throwing, and deepening the depth of the first patterned groove. The method can reduce a boron-rich layer (BRL) formed by laser-induced impurity redistribution, reduce the blocking ability of chemical etching and various physical and chemical effects such as the melting and recombination of materials, and improve the generation of residues after laser treatment. The solar cell obtained through the method has relatively high photoelectric conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a solar cell and a method for improving its laser residue. Background Technology

[0002] In existing technologies, the boron diffusion process for TBC batteries requires a high p-poly doping concentration. The BSG grown under the high-temperature conditions of the boron source deposition and propagation process means it contains an extremely high concentration of boron atoms. When irradiated by a high-energy-density laser, the localized high temperature generated by the laser disrupts the original impurity balance of the doped polycrystalline silicon layer, causing boron atoms to migrate and accumulate on the surface of the laser-affected area, forming a region with a sharp increase in impurities. Ultimately, a "boron-rich layer" with an extremely high boron concentration is formed on the surface of the polycrystalline silicon layer. This boron-rich layer has strong resistance to chemical erosion by alkaline solutions, making wet etching ineffective and resulting in residues that are difficult to remove. Furthermore, the thermal effect of the laser causes the BSG and polycrystalline silicon layer to melt and then rapidly solidify. Through the melting and recrystallization process, the density and crystal structure of the material are physically altered. The reconstituted material becomes even denser, making it difficult for conventional wet cleaning to penetrate and peel off, thus becoming another type of residue that is difficult to remove.

[0003] In view of this, the present invention is proposed. Summary of the Invention

[0004] The purpose of this invention is to provide a solar cell and a method for improving its laser residue, so as to solve or improve the above-mentioned technical problems.

[0005] This invention can be implemented as follows: In a first aspect, the present invention provides a method for improving laser residue in solar cells, comprising the following steps: acid washing of a silicon wafer after boron diffusion treatment to remove the BSG layer formed by boron diffusion, obtaining a first silicon wafer; depositing a low-boron BSG layer on the back side of the first silicon wafer, followed by a first patterning treatment to form a first patterned groove in the area where the removed low-boron BSG layer is located; subsequently removing the BSG wrapping on the front side; and removing the doped polycrystalline silicon layer and the first tunneling oxide layer corresponding to the position of the first patterned groove by alkaline polishing, thereby increasing the depth of the first patterned groove.

[0006] In an optional embodiment, the pickling solution used for pickling includes 40L~60L of HF, 35L~55L of HCl and 360L~400L of H2O. And / or, the pickling time is 90s~120s.

[0007] In an optional embodiment, depositing a low-boron BSG layer includes sequentially performing high-temperature deposition, low-temperature deposition, and annealing on the back side of a first silicon wafer.

[0008] In an optional embodiment, the conditions for high-temperature deposition include: an O2 flow rate of 20 slm to 40 slm, an N2 flow rate of 500 sccm to 1500 sccm, a pressure of 700 mbar to 900 mbar, a deposition temperature of 920°C to 940°C, and a deposition time of 40 min to 60 min.

[0009] In an optional embodiment, the conditions for low-temperature deposition include: an O2 flow rate of 20 slm to 40 slm, an N2 flow rate of 500 sccm to 1500 sccm, a pressure of 700 mbar to 900 mbar, a deposition temperature of 900°C to 920°C, and a deposition time of 20 min to 40 min.

[0010] In an optional embodiment, the annealing temperature is 700℃~730℃, and the annealing time is 10min~20min.

[0011] In an optional embodiment, the thickness of the low-boron BSG layer is 30 nm to 80 nm; And / or, the B content in the low-boron BSG layer is 1.8 × 10⁻⁶. 19 / cm 3 ~2.3×10 19 / cm 3 .

[0012] In an optional embodiment, the depth of the first patterned groove is 30nm~80nm and the width is 400μm~600μm; And / or, the depth of the first patterned groove is increased to 2μm~3μm after alkali polishing.

[0013] In an optional embodiment, after alkaline polishing, the process further includes: depositing a second tunneling oxide layer and a second intrinsic polysilicon layer on the front and back sides of the second silicon wafer obtained after alkaline polishing, followed by phosphorus diffusion treatment; performing a second patterning treatment on the back side of the phosphorus-diffused silicon wafer to remove the PSG layer corresponding to the regions other than the N-region; then texturing the regions other than the doped polysilicon layer and tunneling oxide layer corresponding to the N-region and P-region to obtain a third silicon wafer; and passivating the surface of the third silicon wafer, followed by electrode fabrication.

[0014] Secondly, the present invention provides a solar cell prepared by any of the methods described in the foregoing embodiments.

[0015] The beneficial effects of this invention include: This invention, by adding acid washing and low-boron BSG deposition processes after boron diffusion, can reduce the boron-rich layer (BRL) formed by laser-induced impurity redistribution, decrease the barrier to chemical etching, and reduce various physicochemical effects such as initiating material melting and recombination, thus improving the formation of residues after laser treatment. Solar cells obtained through this method exhibit superior photoelectric conversion efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the product structure corresponding to step S0 of the present invention; Figure 2 This is a schematic diagram of the product structure corresponding to step S1 of the present invention; Figure 3 This is a schematic diagram of the product structure corresponding to step S2 of the present invention; Figure 4 This is a schematic diagram of the product structure corresponding to step S3 of the present invention; Figure 5 This is a schematic diagram of the product structure corresponding to step S5 of the present invention; Figure 6 This is a schematic diagram of the product structure corresponding to step S7 of the present invention; Figure 7 This is a schematic diagram of the product structure corresponding to step S8 of the present invention; Figure 8 This is a schematic diagram of the product structure corresponding to step S9 of the present invention.

[0018] Icons: 10-N-type crystalline silicon substrate; 11-First tunneling oxide layer; 12-First intrinsic polycrystalline silicon layer; 13-BSG layer; 20-First silicon wafer; 21-Low boron BSG layer; 22-First patterned groove; 30-Second silicon wafer; 31-Second tunneling oxide layer; 32-Second intrinsic polycrystalline silicon layer; 33-PSG layer; 40-Third silicon wafer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0020] The following is a detailed description of the solar cell provided by the present invention and the method for improving its laser residue.

[0021] This invention provides a method for improving laser residue in solar cells, comprising the following steps: S0: such as Figure 1 As shown, a silicon wafer with a first tunneling oxide layer 11 and a first intrinsic polysilicon layer 12 deposited on the back side is subjected to boron diffusion treatment.

[0022] The silicon wafers mentioned above are N-type crystalline silicon substrates 10 that have been polished on both sides.

[0023] Both the first tunneling oxide layer 11 and the first intrinsic polycrystalline silicon layer 12 were deposited using LPCVD.

[0024] In some alternative embodiments, the thickness of the first tunneling oxide layer 11 can be 1.0 nm to 2.5 nm (e.g., 1.0 nm, 1.5 nm, 2.0 nm or 2.5 nm), the deposition temperature can be 500 °C to 650 °C (e.g., 500 °C, 550 °C, 600 °C or 650 °C), and the deposition time can be 20 min to 80 min (e.g., 20 min, 40 min, 60 min or 80 min).

[0025] In some optional embodiments, the thickness of the first intrinsic polysilicon layer 12 can be 200nm~400nm (e.g., 200nm, 250nm, 300nm, 350nm or 400nm, etc.), the deposition temperature can be 500℃~650℃ (e.g., 500℃, 550℃, 600℃ or 650℃, etc.), and the deposition time can be 50min~100min (e.g., 50min, 60min, 70min, 80min, 90min or 100min, etc.).

[0026] In some optional embodiments, the conditions for boron diffusion treatment include: during the deposition process, BCl3, O2, and N2 gases are introduced. The flow rate of BCl3 can be 200 sccm to 400 sccm (e.g., 200 sccm, 250 sccm, 300 sccm, 350 sccm, or 400 sccm), the flow rate of O2 can be 700 sccm to 1000 sccm (e.g., 700 sccm, 750 sccm, 800 sccm, 850 sccm, 900 sccm, 950 sccm, or 1000 sccm), and the flow rate of N2 can be 2500 sccm to 3000 sccm (e.g., 2500 sccm, 2600 sccm, 2700 sccm, 2800 sccm, 2900 sccm, or 3000 sccm). The temperature for boron diffusion treatment can be 800℃~1000℃ (e.g., 800℃, 850℃, 900℃, 950℃ or 1000℃), and the treatment time can be 1h~2h (e.g., 1h, 1.5h or 2h).

[0027] In some alternative embodiments, the sheet resistance of the silicon wafer obtained after the above boron diffusion treatment can be 100Ω~200Ω.

[0028] In some alternative embodiments, the thickness of the BSG layer 13 formed after boron expansion can be 30nm~80nm, such as 30nm, 40nm, 50nm, 60nm, 70nm or 80nm, or other values ​​in the range of 30nm~80nm.

[0029] S1: As Figure 2 As shown, the silicon wafer after boron diffusion is acid-washed to remove the BSG layer 13 formed by boron diffusion, and a first silicon wafer 20 is obtained.

[0030] In some optional embodiments, the pickling solution used for pickling may include 40L~60L (e.g., 40L, 45L, 50L, 55L or 60L, etc.) of HF, 35L~55L (e.g., 35L, 40L, 45L, 50L or 55L, etc.) of HCl and 360L~400L (e.g., 360L, 370L, 380L, 390L or 400L, etc.) of H2O.

[0031] In some alternative implementations, the pickling time can be 90s to 120s, such as 90s, 100s, 110s or 120s, or other values ​​within the range of 90s to 120s.

[0032] S2: As Figure 3 As shown, a low-boron BSG layer 21 is deposited on the back side of the first silicon wafer 20.

[0033] In some alternative embodiments, depositing the low-boron BSG layer 21 includes sequentially performing high-temperature deposition, low-temperature deposition, and annealing on the back side of the first silicon wafer 20.

[0034] The conditions for high-temperature deposition may include: an O2 flow rate of 20 slm to 40 slm (e.g., 20 slm, 25 slm, 30 slm, 35 slm, or 40 slm), an N2 flow rate of 500 sccm to 1500 sccm (e.g., 500 sccm, 800 sccm, 1000 sccm, 1200 sccm, or 1500 sccm), a pressure of 700 mbar to 900 mbar (e.g., 700 mbar, 750 mbar, 800 mbar, 850 mbar, or 900 mbar), a deposition temperature of 920℃ to 940℃ (e.g., 920℃, 925℃, 930℃, 935℃, or 940℃), and a deposition time of 40 min to 60 min (e.g., 40 min, 45 min, 50 min, 55 min, or 60 min).

[0035] Conditions for low-temperature deposition may include: an O2 flow rate of 20 slm to 40 slm (e.g., 20 slm, 25 slm, 30 slm, 35 slm, or 40 slm), an N2 flow rate of 500 sccm to 1500 sccm (e.g., 500 sccm, 800 sccm, 1000 sccm, 1200 sccm, or 1500 sccm), a pressure of 700 mbar to 900 mbar (e.g., 700 mbar, 750 mbar, 800 mbar, 850 mbar, or 900 mbar), a deposition temperature of 900℃ to 920℃ (e.g., 900℃, 905℃, 910℃, 915℃, or 920℃), and a deposition time of 20 min to 40 min (e.g., 20 min, 25 min, 30 min, 35 min, or 40 min).

[0036] The annealing temperature can be 700℃~730℃ (such as 700℃, 705℃, 710℃, 715℃, 720℃, 725℃ or 730℃, etc.), and the annealing time is 10min~20min (such as 10min, 15min or 20min, etc.).

[0037] It should be noted that some shallowly diffused boron remains on the surface of the first silicon wafer 20, therefore no additional boron source is needed when depositing the low-boron BSG layer 21. This invention achieves the low-boron BSG layer 21 by first performing high-temperature deposition to grow a high-quality, dense oxide layer; then performing low-temperature deposition to grow a highly uniform oxide layer; and finally performing annealing to significantly reduce the interface defect state density between the oxide layer and the silicon substrate, while simultaneously activating the boron doped on the silicon substrate surface to promote element diffusion between different layers.

[0038] If the high-temperature deposition temperature is below 920℃, it is not conducive to obtaining a high-quality, dense oxide layer; if the high-temperature deposition temperature is above 940℃, thermal stress may not be released in time, leading to cracks, delamination, or even peeling of the oxide layer, severely affecting its integrity and stability. If the high-temperature deposition time is less than 40 minutes, it is not conducive to growing an oxide layer of the required thickness; if the high-temperature deposition time is longer than 60 minutes, it may lead to an excessively thick oxide layer and deterioration of interface properties.

[0039] If the low-temperature deposition temperature is below 900℃, the oxide layer is more likely to contain more defects and pinholes, leading to increased leakage current and decreased breakdown voltage. If the low-temperature deposition temperature is above 920℃, the oxide layer uniformity is likely to deteriorate. If the low-temperature deposition time is less than 20 minutes, it is not conducive to improving the oxide layer uniformity; if the low-temperature deposition time is more than 40 minutes, it is likely to result in an excessively thick oxide layer.

[0040] If the annealing temperature is below 700℃, it is not conducive to completely repairing damage or dangling bonds inside the oxide layer; if the annealing temperature is above 730℃, it is easy to cause the boron concentration in the oxide layer to be too high. If the annealing time is less than 10 minutes, it is not conducive to the dopant atoms having enough time to diffuse; if the annealing time is longer than 20 minutes, it is easy to cause the originally improved electrical properties to deteriorate again.

[0041] In some alternative embodiments, the thickness of the low-boron BSG layer 21 can be 30nm to 80nm, such as 30nm, 40nm, 50nm, 60nm, 70nm or 80nm, or other values ​​in the range of 30nm to 80nm.

[0042] In some alternative embodiments, the boron content in the low-boron BSG layer 21 is 1.8 × 10⁻⁶. 19 / cm 3 ~2.3×10 19 / cm 3 Compared to the B content in conventional BSG layer 13 (approximately 3 × 10⁻⁶), the content of B in this layer is significantly higher. 19 / cm 3 () significantly reduced.

[0043] S3: As Figure 4 As shown, a first patterning process is performed to form a first patterned groove 22 in the region where the partially removed low-boron BSG layer 21 is located.

[0044] In some alternative implementations, a picosecond laser can be used to remove part of the low-boron BSG layer 21 (the subsequent PSG layer 33 in the gap region + N region) to form the first patterned groove 22.

[0045] In some optional embodiments, the depth of the first patterned groove 22 is 30nm to 80nm, such as 30nm, 40nm, 50nm, 60nm, 70nm, or 80nm, or other values ​​within the range of 30nm to 80nm. The width of the first patterned groove 22 is 400μm to 600μm, such as 400μm, 450μm, 500μm, 550μm, or 600μm, or other values ​​within the range of 400μm to 600μm.

[0046] S4: Remove the BSG coating on the front side.

[0047] In some alternative implementations, conventional chain wet processes can be used to remove the BSG wrap-around plating on the front side.

[0048] S5: As Figure 5 As shown, the doped polysilicon layer and the first tunneling oxide layer 11 corresponding to the position of the first patterned groove 22 are removed by alkaline polishing, and the depth of the first patterned groove 22 is increased to obtain the second silicon wafer 30.

[0049] In some alternative implementations, trench polishing can be used to remove residual plating on the front side and the doped polysilicon layer and the first tunneling oxide layer 11 in the first patterned groove 22 region on the back side.

[0050] In some alternative embodiments, the depth of the first patterned groove 22 after alkaline polishing is increased to 2μm~3μm, such as 2μm, 2.5μm or 3μm, or other values ​​in the range of 2μm~3μm.

[0051] S6: A second tunneling oxide layer 31 and a second intrinsic polysilicon layer 32 (which can be combined) are deposited on the front and back sides of the second silicon wafer 30 obtained after alkaline polishing. Figure 6 (As shown).

[0052] The second tunneling oxide layer 31 and the second intrinsic polycrystalline silicon layer 32 were both deposited using LPCVD.

[0053] In some alternative embodiments, the thickness of the second tunneling oxide layer 31 can be 1.0 nm to 2.5 nm (e.g., 1.0 nm, 1.5 nm, 2.0 nm or 2.5 nm), the deposition temperature can be 500 °C to 650 °C (e.g., 500 °C, 550 °C, 600 °C or 650 °C), and the deposition time can be 20 min to 80 min (e.g., 20 min, 40 min, 60 min or 80 min).

[0054] In some optional embodiments, the thickness of the second intrinsic polysilicon layer 32 can be 100nm~300nm (e.g., 100nm, 150nm, 200nm, 250nm or 300nm, etc.), the deposition temperature can be 500℃~650℃ (e.g., 500℃, 550℃, 600℃ or 650℃, etc.), and the deposition time can be 50min~100min (e.g., 50min, 60min, 70min, 80min, 90min or 100min, etc.).

[0055] S7: Phosphorus diffusion treatment.

[0056] In some optional embodiments, the conditions for phosphorus diffusion treatment include: during the deposition process, POCl3, O2, and N2 gases are introduced. The flow rate of POCl3 can be 1000 sccm to 2000 sccm (e.g., 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm, or 2000 sccm), the flow rate of O2 can be 500 sccm to 1000 sccm (e.g., 500 sccm, 550 sccm, 600 sccm, 650 sccm, 700 sccm, 750 sccm, 800 sccm, 850 sccm, 900 sccm, 950 sccm, or 1000 sccm), and the flow rate of N2 can be 500 sccm to 1500 sccm (e.g., 500 sccm, 800 sccm, 1000 sccm, 1200 sccm, or 1500 sccm). The temperature for phosphorus diffusion treatment can be 800℃~1000℃ (e.g., 800℃, 850℃, 900℃, 950℃ or 1000℃), and the treatment time can be 1h~3h (e.g., 1h, 1.5h, 2h, 2.5h or 3h).

[0057] In some alternative embodiments, the sheet resistance of the silicon wafer obtained after the above phosphorus diffusion treatment can be 20Ω to 80Ω.

[0058] In some alternative embodiments, the PSG layer 33 formed after phosphorus diffusion (e.g.) Figure 6As shown, the thickness can be 30nm~80nm, such as 30nm, 40nm, 50nm, 60nm, 70nm or 80nm, or other values ​​within the range of 30nm~80nm.

[0059] S8: As Figure 7 As shown, a second patterning process is performed on the back side of the silicon wafer after phosphorus diffusion to remove the PSG layer 33 corresponding to the areas other than the N region.

[0060] In some alternative implementations, the PSG layer 33 in the N-region on the back side of the silicon wafer is retained, and the PSG layer 33 in the remaining area is removed using a picosecond laser.

[0061] S9: As Figure 8 As shown, texturing is performed on the areas outside the doped polysilicon layer and tunnel oxide layer corresponding to the N and P regions on the back side to obtain the third silicon wafer 40.

[0062] S10: Passivate the surface of the third silicon wafer 40.

[0063] In some alternative embodiments, the passivation process includes depositing aluminum oxide passivation layers on the front and back sides of the third silicon wafer 40, followed by depositing a silicon nitride passivation layer on the back side, and depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front side.

[0064] S11: Electrode preparation.

[0065] In some alternative implementations, electrodes can be fabricated using a printing method.

[0066] Accordingly, the present invention also provides a solar cell prepared by the above method.

[0067] The battery can be, for example, a TBC battery.

[0068] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0069] Example 1 This embodiment provides a TBC battery, the preparation method of which includes: S0: The N-type crystalline silicon substrate 10 is polished on both sides, and a first tunneling oxide layer 11 and a first intrinsic polycrystalline silicon layer 12 are deposited on the back side of the silicon substrate using LPCVD, followed by boron diffusion treatment.

[0070] The first tunneling oxide layer 11 has a thickness of 2 nm, a deposition temperature of 600 °C, and a deposition time of 50 min. The first intrinsic polycrystalline silicon layer 12 has a thickness of 300 nm, a deposition temperature of 600 °C, and a deposition time of 80 min.

[0071] The conditions for boron diffusion treatment included: during the deposition process, BCl3, O2, and N2 gases were introduced. The flow rates of BCl3 were 300 sccm, O2 was 850 sccm, and N2 was 2800 sccm. The boron diffusion treatment temperature was 900℃, and the treatment time was 1.5 h.

[0072] The sheet resistance of the silicon wafer obtained after the above boron expansion treatment is 150Ω. The thickness of the BSG layer 13 formed after boron expansion is 50nm.

[0073] S1: The silicon wafer after boron diffusion is acid-washed to remove the BSG layer 13 formed by boron diffusion, and the first silicon wafer 20 is obtained.

[0074] The pickling solution used included 50L of HF, 45L of HCl, and 380L of H2O. The pickling time was 105 seconds.

[0075] S2: Deposit a low-boron BSG layer 21 on the back side of the first silicon wafer 20.

[0076] The deposition of the low-boron BSG layer 21 includes sequentially performing high-temperature deposition, low-temperature deposition, and annealing on the back side of the first silicon wafer 20. The high-temperature deposition conditions include: an O2 flow rate of 30 slm, an N2 flow rate of 1000 sccm, a pressure of 800 mbar, a deposition temperature of 930℃, and a deposition time of 50 min. The low-temperature deposition conditions include: an O2 flow rate of 30 slm, an N2 flow rate of 1000 sccm, a pressure of 800 mbar, a deposition temperature of 910℃, and a deposition time of 30 min. The annealing temperature is 715℃, and the annealing time is 15 min.

[0077] The thickness of the low-boron BSG layer 21 is 50 nm, and the boron content in the low-boron BSG layer 21 is 2 × 10⁻⁶. 19 / cm 3 .

[0078] S3: A picosecond laser is used for the first patterning process to form a first patterned groove 22 in the area where the removed low boron BSG layer 21 is located.

[0079] The first patterned groove 22 has a depth of 50nm and a width of 500μm.

[0080] S4: The BSG wrap-around plating on the front side is removed using a conventional chain wet process.

[0081] S5: The residual plating on the front side and the doped polysilicon layer and the first tunneling oxide layer 11 in the first patterned groove 22 area on the back side are removed by trough polishing (alkaline polishing), and the depth of the first patterned groove 22 is increased to obtain the second silicon wafer 30. After alkaline polishing, the depth of the first patterned groove 22 is increased to 2.5μm.

[0082] S6: Using LPCVD, a second tunneling oxide layer 31 and a second intrinsic polysilicon layer 32 are deposited on the front and back sides of the second silicon wafer 30 obtained after alkaline polishing.

[0083] The second tunneling oxide layer 31 has a thickness of 2 nm, a deposition temperature of 600 °C, and a deposition time of 50 min. The second intrinsic polycrystalline silicon layer 32 has a thickness of 200 nm, a deposition temperature of 580 °C, and a deposition time of 80 min.

[0084] S7: Phosphorus diffusion treatment.

[0085] The conditions for phosphorus diffusion treatment included: during the deposition process, POCl3, O2, and N2 gases were introduced. The flow rates of POCl3 were 1500 sccm, O2 was 800 sccm, and N2 was 1000 sccm. The phosphorus diffusion treatment temperature was 900℃, and the treatment time was 2 hours.

[0086] The sheet resistance of the silicon wafer obtained after the above phosphorus diffusion treatment is 50Ω. The thickness of the PSG layer 33 formed after phosphorus diffusion is 50nm.

[0087] S8: The PSG layer 33 in the N region on the back of the silicon wafer is retained. A picosecond laser is used to perform a second patterning process on the back of the silicon wafer after phosphorus diffusion to remove the PSG layer 33 corresponding to the areas other than the N region.

[0088] S9: Texturing is performed on the areas outside the doped polysilicon layer and tunnel oxide layer corresponding to the N and P regions on the back side to obtain the third silicon wafer 40.

[0089] S10: Passivate the surface of the third silicon wafer 40.

[0090] The passivation process includes: depositing aluminum oxide passivation layers on the front and back sides of the third silicon wafer 40, followed by depositing a silicon nitride passivation layer on the back side, and depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front side.

[0091] S11: Electrode preparation.

[0092] Example 2 This embodiment provides a TBC battery, the preparation method of which includes: S0: The N-type crystalline silicon substrate 10 is polished on both sides, and a first tunneling oxide layer 11 and a first intrinsic polycrystalline silicon layer 12 are deposited on the back side of the silicon substrate using LPCVD, followed by boron diffusion treatment.

[0093] The first tunneling oxide layer 11 has a thickness of 1.0 nm, a deposition temperature of 500 °C, and a deposition time of 20 min. The first intrinsic polycrystalline silicon layer 12 has a thickness of 200 nm, a deposition temperature of 500 °C, and a deposition time of 50 min.

[0094] The conditions for boron diffusion treatment included: during the deposition process, BCl3, O2, and N2 gases were introduced. The flow rates of BCl3 were 200 sccm, O2 was 700 sccm, and N2 was 2500 sccm. The boron diffusion treatment temperature was 800℃, and the treatment time was 1 hour.

[0095] The sheet resistance of the silicon wafer obtained after the above boron diffusion process is 100Ω. The thickness of the BSG layer 13 formed after boron diffusion is 30nm.

[0096] S1: The silicon wafer after boron diffusion is acid-washed to remove the BSG layer 13 formed by boron diffusion, and the first silicon wafer 20 is obtained.

[0097] The pickling solution used included 40L of HF, 35L of HCl, and 360L of H2O. The pickling time was 90 seconds.

[0098] S2: Deposit a low-boron BSG layer 21 on the back side of the first silicon wafer 20.

[0099] The deposition of the low-boron BSG layer 21 includes sequentially performing high-temperature deposition, low-temperature deposition, and annealing on the back side of the first silicon wafer 20. The high-temperature deposition conditions are: O2 flow rate of 20 slm, N2 flow rate of 500 sccm, pressure of 700 mbar, deposition temperature of 920℃, and deposition time of 40 min. The low-temperature deposition conditions are: O2 flow rate of 20 slm, N2 flow rate of 500 sccm, pressure of 700 mbar, deposition temperature of 900℃, and deposition time of 20 min. The annealing temperature is 700℃, and the annealing time is 10 min.

[0100] The thickness of the low-boron BSG layer 21 is 30 nm, and the boron content in the low-boron BSG layer 21 is 1.8 × 10⁻⁶. 19 / cm 3 .

[0101] S3: A picosecond laser is used for the first patterning process to form a first patterned groove 22 in the area where the removed low boron BSG layer 21 is located.

[0102] The first patterned groove 22 has a depth of 30nm and a width of 400μm.

[0103] S4: The BSG wrap-around plating on the front side is removed using a conventional chain wet process.

[0104] S5: The residual plating on the front side and the doped polysilicon layer and the first tunneling oxide layer 11 in the first patterned groove 22 area on the back side are removed by trough polishing (alkaline polishing), and the depth of the first patterned groove 22 is increased to obtain the second silicon wafer 30. After alkaline polishing, the depth of the first patterned groove 22 is increased to 2μm.

[0105] S6: Using LPCVD, a second tunneling oxide layer 31 and a second intrinsic polysilicon layer 32 are deposited on the front and back sides of the second silicon wafer 30 obtained after alkaline polishing.

[0106] The second tunneling oxide layer 31 has a thickness of 1.0 nm, a deposition temperature of 500 °C, and a deposition time of 20 min. The second intrinsic polycrystalline silicon layer 32 has a thickness of 100 nm, a deposition temperature of 500 °C, and a deposition time of 50 min.

[0107] S7: Phosphorus diffusion treatment.

[0108] The conditions for phosphorus diffusion treatment included: during the deposition process, POCl3, O2, and N2 gases were introduced. The flow rates of POCl3 and N2 were 1000 sccm, 500 sccm, and 500 sccm, respectively. The phosphorus diffusion treatment temperature was 800℃, and the treatment time was 1 hour.

[0109] The sheet resistance of the silicon wafer obtained after the above phosphorus diffusion treatment is 20Ω. The thickness of the PSG layer 33 formed after phosphorus diffusion is 30nm.

[0110] S8: The PSG layer 33 in the N region on the back of the silicon wafer is retained. A picosecond laser is used to perform a second patterning process on the back of the silicon wafer after phosphorus diffusion to remove the PSG layer 33 corresponding to the areas other than the N region.

[0111] S9: Texturing is performed on the areas outside the doped polysilicon layer and tunnel oxide layer corresponding to the N and P regions on the back side to obtain the third silicon wafer 40.

[0112] S10: Passivate the surface of the third silicon wafer 40.

[0113] The passivation process includes: depositing aluminum oxide passivation layers on the front and back sides of the third silicon wafer 40, followed by depositing a silicon nitride passivation layer on the back side, and depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front side.

[0114] S11: Electrode preparation.

[0115] Example 3 This embodiment provides a TBC battery, the preparation method of which includes: S0: The N-type crystalline silicon substrate 10 is polished on both sides, and a first tunneling oxide layer 11 and a first intrinsic polycrystalline silicon layer 12 are deposited on the back side of the silicon substrate using LPCVD, followed by boron diffusion treatment.

[0116] The first tunneling oxide layer 11 has a thickness of 2.5 nm, a deposition temperature of 650 °C, and a deposition time of 80 min. The first intrinsic polycrystalline silicon layer 12 has a thickness of 400 nm, a deposition temperature of 650 °C, and a deposition time of 100 min.

[0117] The conditions for boron diffusion treatment included: during the deposition process, BCl3, O2, and N2 gases were introduced. The flow rates of BCl3 were 400 sccm, O2 was 1000 sccm, and N2 was 3000 sccm. The boron diffusion treatment temperature was 1000℃, and the treatment time was 2 hours.

[0118] The sheet resistance of the silicon wafer obtained after the above boron expansion treatment is 200Ω. The thickness of the BSG layer 13 formed after boron expansion is 80nm.

[0119] S1: The silicon wafer after boron diffusion is acid-washed to remove the BSG layer 13 formed by boron diffusion, and the first silicon wafer 20 is obtained.

[0120] The pickling solution used included 60L of HF, 55L of HCl, and 400L of H2O. The pickling time was 120 seconds.

[0121] S2: Deposit a low-boron BSG layer 21 on the back side of the first silicon wafer 20.

[0122] The deposition of the low-boron BSG layer 21 includes sequentially performing high-temperature deposition, low-temperature deposition, and annealing on the back side of the first silicon wafer 20. The high-temperature deposition conditions are: O2 flow rate of 40 slm, N2 flow rate of 1500 sccm, pressure of 900 mbar, deposition temperature of 940℃, and deposition time of 60 min. The low-temperature deposition conditions are: O2 flow rate of 40 slm, N2 flow rate of 1500 sccm, pressure of 900 mbar, deposition temperature of 920℃, and deposition time of 40 min. The annealing temperature is 730℃, and the annealing time is 20 min.

[0123] The thickness of the low-boron BSG layer 21 is 80 nm, and the boron content in the low-boron BSG layer 21 is 2.3 × 10⁻⁶. 19 / cm 3 .

[0124] S3: A picosecond laser is used for the first patterning process to form a first patterned groove 22 in the area where the removed low boron BSG layer 21 is located.

[0125] The first patterned groove 22 has a depth of 80nm and a width of 600μm.

[0126] S4: The BSG wrap-around plating on the front side is removed using a conventional chain wet process.

[0127] S5: The residual plating on the front side and the doped polysilicon layer and the first tunneling oxide layer 11 in the first patterned groove 22 area on the back side are removed by trough polishing (alkaline polishing), and the depth of the first patterned groove 22 is increased to obtain the second silicon wafer 30. After alkaline polishing, the depth of the first patterned groove 22 is increased to 3μm.

[0128] S6: Using LPCVD, a second tunneling oxide layer 31 and a second intrinsic polysilicon layer 32 are deposited on the front and back sides of the second silicon wafer 30 obtained after alkaline polishing.

[0129] The second tunneling oxide layer 31 has a thickness of 2.5 nm, a deposition temperature of 650 °C, and a deposition time of 80 min. The second intrinsic polycrystalline silicon layer 32 has a thickness of 300 nm, a deposition temperature of 650 °C, and a deposition time of 100 min.

[0130] S7: Phosphorus diffusion treatment.

[0131] The conditions for phosphorus diffusion treatment included: during the deposition process, POCl3, O2, and N2 gases were introduced. The flow rates of POCl3 were 2000 sccm, O2 was 1000 sccm, and N2 was 1500 sccm. The phosphorus diffusion treatment temperature was 1000℃, and the treatment time was 3 hours.

[0132] The sheet resistance of the silicon wafer obtained after the above phosphorus diffusion treatment is 80Ω. The thickness of the PSG layer 33 formed after phosphorus diffusion is 80nm.

[0133] S8: The PSG layer 33 in the N region on the back of the silicon wafer is retained. A picosecond laser is used to perform a second patterning process on the back of the silicon wafer after phosphorus diffusion to remove the PSG layer 33 corresponding to the areas other than the N region.

[0134] S9: Texturing is performed on the areas outside the doped polysilicon layer and tunnel oxide layer corresponding to the N and P regions on the back side to obtain the third silicon wafer 40.

[0135] S10: Passivate the surface of the third silicon wafer 40.

[0136] The passivation process includes: depositing aluminum oxide passivation layers on the front and back sides of the third silicon wafer 40, followed by depositing a silicon nitride passivation layer on the back side, and depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front side.

[0137] S11: Electrode preparation.

[0138] Comparative Example 1 The difference between this comparative example and Example 1 is that S1 and S2 processes were not performed. Instead, the silicon wafer obtained from S0 was directly subjected to the first patterning process S3. All other steps and conditions were the same as in Example 1.

[0139] Comparative Example 2 The difference between this comparative example and Example 1 is that in S2, the high-temperature deposition is followed by direct annealing, without a low-temperature deposition process.

[0140] Comparative Example 3 The difference between this comparative example and Example 1 is that in S2, the material is directly annealed after low-temperature deposition, without a high-temperature deposition process.

[0141] Comparative Example 4 The difference between this comparative example and Example 1 is that in S2, the high-temperature deposition temperature is 900°C.

[0142] Comparative Example 5 The difference between this comparative example and Example 1 is that in S2, the high-temperature deposition temperature is 950°C.

[0143] Comparative Example 6 The difference between this comparative example and Example 1 is that in S2, the low-temperature deposition temperature is 880°C.

[0144] Comparative Example 7 The difference between this comparative example and Example 1 is that in S2, the low-temperature deposition temperature is 930°C.

[0145] Test case The TBC batteries prepared in Examples 1-3 and Comparative Examples 1-7 were subjected to IV testing, and the results are shown in Table 1.

[0146] Table 1 Test Results

[0147] As can be seen from Table 1, the TBC cells prepared in Examples 1-3 of this invention have better photoelectric conversion efficiency and higher fill factor than the TBC cells prepared in Comparative Examples 1-7.

[0148] In summary, the method provided by this invention, by adding acid washing and low-boron BSG deposition processes after boron diffusion, can reduce the formation of a boron-rich layer (BRL) induced by laser-induced impurity redistribution, decrease the barrier to chemical etching, and reduce various physicochemical effects such as initiating material melting and reorganization, thereby improving the generation of residues after laser treatment. The solar cells obtained by this method exhibit superior photoelectric conversion efficiency.

[0149] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for improving laser residue in solar cells, characterized in that, Includes the following steps: The silicon wafer after boron diffusion is acid-washed to remove the BSG layer formed by boron diffusion, and the first silicon wafer is obtained. A low-boron BSG layer is deposited on the back side of the first silicon wafer, followed by a first patterning process to form a first patterned groove in the area where the removed portion of the low-boron BSG layer is located; then the BSG wrap-around plating on the front side is removed. The doped polysilicon layer and the first tunneling oxide layer corresponding to the first patterned groove position are removed by alkaline polishing, thereby increasing the depth of the first patterned groove.

2. The method according to claim 1, characterized in that, The pickling solution used for pickling includes 40L~60L of HF, 35L~55L of HCl and 360L~400L of H2O; And / or, the pickling time is 90s~120s.

3. The method according to claim 1, characterized in that, The deposition of the low-boron BSG layer includes: performing high-temperature deposition, low-temperature deposition, and annealing treatment sequentially on the back side of the first silicon wafer.

4. The method according to claim 3, characterized in that, The conditions for high-temperature deposition include: an O2 flow rate of 20 slm to 40 slm, an N2 flow rate of 500 sccm to 1500 sccm, a pressure of 700 mbar to 900 mbar, a deposition temperature of 920℃ to 940℃, and a deposition time of 40 min to 60 min.

5. The method according to claim 3, characterized in that, The conditions for low-temperature deposition include: O2 flow rate of 20 slm to 40 slm, N2 flow rate of 500 sccm to 1500 sccm, pressure of 700 mbar to 900 mbar, deposition temperature of 900℃ to 920℃, and deposition time of 20 min to 40 min.

6. The method according to claim 3, characterized in that, The annealing temperature is 700℃~730℃, and the annealing time is 10min~20min.

7. The method according to claim 3, characterized in that, The thickness of the low-boron BSG layer is 30nm~80nm; And / or, the B content in the low-boron BSG layer is 1.8 × 10⁻⁶. 19 / cm 3 ~2.3×10 19 / cm 3 .

8. The method according to claim 1, characterized in that, The depth of the first patterned groove is 30nm~80nm, and the width is 400μm~600μm; And / or, after alkaline polishing, the depth of the first patterned groove is increased to 2μm~3μm.

9. The method according to any one of claims 1 to 8, characterized in that, The alkaline polishing process further includes: depositing a second tunneling oxide layer and a second intrinsic polysilicon layer on the front and back sides of the second silicon wafer obtained after alkaline polishing, followed by phosphorus diffusion treatment; performing a second patterning treatment on the back side of the phosphorus-diffused silicon wafer to remove the PSG layer corresponding to the regions other than the N-region; then texturing the regions other than the doped polysilicon layer and tunneling oxide layer corresponding to the N-region and P-region to obtain a third silicon wafer; and passivating the surface of the third silicon wafer, followed by electrode fabrication.

10. A solar cell, characterized in that, It is prepared by the method described in any one of claims 1 to 9.

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