Solar cell and method of manufacturing the same

Abstract

The application provides a solar cell and a preparation method thereof. In the application, a substrate is provided, the substrate comprising opposite first and second surfaces; a first passivation layer is formed on the first surface, and a second passivation layer is formed on the second surface; a polysilicon layer is formed on the side of the first passivation layer away from the substrate; a silicon-based semiconductor layer is formed on the side of the second passivation layer away from the substrate, and the silicon-based semiconductor layer plated on the surface of the polysilicon layer, the sidewall region of the first passivation layer and the sidewall region of the second passivation layer during the formation of the silicon-based semiconductor layer is removed. The application solves the problem that the edge passivation quality of a high-efficiency crystalline silicon cell is much lower than the front surface / back surface, which leads to serious minority carrier recombination and low reverse bias breakdown voltage.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and more specifically, to a solar cell and a method for its fabrication. Background Technology

[0002] With the rapid development of high-efficiency crystalline silicon cell technologies such as heterojunction with intrinsic thin-layer (HJT) solar cells and tunnel oxide passivated contact (TOPCon) solar cells, the passivation quality of the front and back surfaces has approached the theoretical limit, significantly improving minority carrier lifetime and driving continuous breakthroughs in cell efficiency.

[0003] However, in existing processes, edge passivation relies on the plating of passivation films on the front / back sides. When the subsequent etching step removes the plating layer, the passivation film at the edge is also peeled off, resulting in missing edge passivation and increased recombination. This has become a key bottleneck limiting the improvement of open-circuit voltage and reverse-bias breakdown voltage. Current technology has not yet achieved independent, in-situ, and stable passivation of the edge region. Summary of the Invention

[0004] The main objective of this application is to provide a silicon solar cell and its fabrication method, so as to at least solve the problem that the edge passivation quality of high-efficiency crystalline silicon cells in the prior art is much lower than that of the front / back side, resulting in severe minority carrier recombination and low reverse-bias breakdown voltage.

[0005] To achieve the above objectives, according to one aspect of this application, a method for fabricating a solar cell is provided, comprising: providing a substrate, the substrate including a first surface and a second surface opposite to each other; forming a first passivation layer on the first surface and a second passivation layer on the second surface; forming a polycrystalline silicon layer on a side of the first passivation layer away from the substrate; forming a silicon-based semiconductor layer on a side of the second passivation layer away from the substrate, and removing the silicon-based semiconductor layer deposited around the surface of the polycrystalline silicon layer, the sidewall region of the first passivation layer, and the sidewall region of the second passivation layer during the formation of the silicon-based semiconductor layer.

[0006] Optionally, forming a polycrystalline silicon layer on the side of the first passivation layer away from the substrate includes: forming an amorphous silicon layer on the side of the first passivation layer away from the substrate, wherein the doping type of the amorphous silicon layer is different from the doping type of the silicon-based semiconductor layer; forming a silicon oxide thin film layer on the side of the amorphous silicon layer away from the substrate, while crystallizing the amorphous silicon layer into a polycrystalline silicon layer.

[0007] Optionally, forming a silicon oxide thin film layer on the side of the amorphous silicon layer away from the substrate, while simultaneously crystallizing the amorphous silicon layer into a polycrystalline silicon layer, includes: performing a first high-temperature annealing treatment on the amorphous silicon layer, causing the amorphous silicon layer to be oxidized in situ on its surface to form the silicon oxide thin film layer, while the amorphous silicon layer itself crystallizes into the polycrystalline silicon layer; wherein the first high-temperature annealing treatment includes: performing a first annealing treatment for a first preset time in a first atmosphere; and performing a second annealing treatment for a second preset time in a second atmosphere, wherein the first atmosphere is nitrogen, and the second atmosphere is nitrogen and oxygen.

[0008] Optionally, the temperature of the first annealing treatment is 800-980℃, the process gas pressure is 800Pa, and the first preset time is 2500s. The volume flow ratio of nitrogen to oxygen in the second annealing treatment is 5:1 to 1:1, the temperature is 800-980℃, the process gas pressure is 800Pa, and the second preset time is 50s-500s.

[0009] Optionally, a silicon oxide thin film layer is formed on the side of the amorphous silicon layer away from the substrate, while the amorphous silicon layer is crystallized into a polycrystalline silicon layer. This includes: performing a second high-temperature annealing treatment on the amorphous silicon layer, so that the amorphous silicon layer is oxidized in situ on the surface to form the silicon oxide thin film layer, while the amorphous silicon layer itself crystallizes into the polycrystalline silicon layer, wherein the second high-temperature annealing treatment is performed in a pure nitrogen atmosphere.

[0010] Optionally, before forming a silicon oxide thin film layer on the amorphous silicon layer and crystallizing the amorphous silicon layer into a polycrystalline silicon layer, the method further includes: using an alkaline solution to etch and remove the amorphous silicon layer that was deposited around the second passivation layer during the formation of the amorphous silicon layer, wherein the etching rate of the alkaline solution on the amorphous silicon layer is greater than the etching rate on the silicon oxide.

[0011] Optionally, forming a first passivation layer on the first surface and a second passivation layer on the second surface includes: placing the substrate in a vacuum chamber of a tubular quartz furnace, exposing both the first and second surfaces to a reaction atmosphere; introducing a mixed gas composed of nitrogen and oxygen into the vacuum chamber for reaction, controlling the reaction temperature in the vacuum chamber to be 650-1000℃ and the process gas pressure to be 100-500Pa, and controlling the volume flow ratio of nitrogen to oxygen to be 1:1-1:10, so as to simultaneously form silicon oxide thin films as the first passivation layer and the second passivation layer on the first and second surfaces.

[0012] Optionally, forming a silicon-based semiconductor layer on the side of the second passivation layer away from the substrate includes: placing the substrate on which the second passivation layer has been formed into the vacuum chamber of a plasma-enhanced chemical vapor deposition (PECVD) apparatus; introducing H2, SiH4, and B2H6 as reaction gases into the vacuum chamber of the PECVD apparatus, and controlling the reaction temperature to be 150-220°C and the deposition pressure to be 200-350 Pa, so as to form the silicon-based semiconductor layer on the side of the second passivation layer away from the substrate, wherein the volumetric flow rate ratio of H2, SiH4, and B2H6 is: H2 / SiH4 = 100-700:1, and SiH4 / B2H6 = 20-200:1.

[0013] Optionally, after forming a silicon-based semiconductor layer on the second passivation layer and removing the silicon-based semiconductor layer deposited around the surface of the polycrystalline silicon layer, the sidewall region of the first passivation layer, and the sidewall region of the second passivation layer during the formation of the silicon-based semiconductor layer, the method further includes: removing the silicon oxide thin film layer, depositing a first transparent conductive oxide layer on the polycrystalline silicon layer, and depositing a second transparent conductive oxide layer on the silicon-based semiconductor layer; fabricating a first electrode on the first transparent conductive oxide layer, and fabricating a second electrode on the second transparent conductive oxide layer.

[0014] According to another aspect of this application, a solar cell is provided, which is prepared using any of the solar cell preparation methods described above.

[0015] The present application provides a substrate comprising a first side and a second side opposite to each other. A first passivation layer is formed on the first side, and a second passivation layer is formed on the second side. A polycrystalline silicon layer is formed on the side of the first passivation layer away from the substrate. A silicon-based semiconductor layer is formed on the side of the second passivation layer away from the substrate. The silicon-based semiconductor layer deposited around the surface of the polycrystalline silicon layer, the sidewall region of the first passivation layer, and the sidewall region of the second passivation layer during the formation of the silicon-based semiconductor layer is removed. In this solution, by first forming a first passivation layer and a second passivation layer as a passivation interface on both sides of the substrate, then forming a polycrystalline silicon layer on the first passivation layer and a silicon-based semiconductor layer on the second passivation layer, and selectively removing the portion of the silicon-based semiconductor layer deposited around the surface of the polycrystalline silicon layer, the sidewall region of the first passivation layer, and the sidewall region of the second passivation layer after deposition, excess semiconductor material in the target area is eliminated without damaging the functional structure of the front polycrystalline silicon layer and the back silicon-based semiconductor layer. This solves the problem that the edge passivation quality of high-efficiency crystalline silicon cells is much lower than that of the front / back sides, resulting in severe minority carrier recombination and low reverse-bias breakdown voltage. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A schematic flowchart of a method for fabricating a solar cell according to an embodiment of this application is shown;

[0018] Figure 2 A schematic diagram of a first fabrication process of a specific method for fabricating a solar cell according to an embodiment of this application is shown;

[0019] Figure 3 A schematic diagram of a second fabrication process of a specific solar cell fabrication method according to an embodiment of this application is shown;

[0020] Figure 4 A schematic diagram of a third fabrication process of a specific solar cell fabrication method according to an embodiment of this application is shown;

[0021] Figure 5 A schematic diagram of a fourth fabrication process of a specific solar cell fabrication method according to an embodiment of this application is shown;

[0022] Figure 6 An embodiment of a specific method for fabricating a solar cell according to an embodiment of this application is shown, along with a comparative example of the cell's reverse bias IV curve.

[0023] The above figures include the following reference numerals:

[0024] 01. Monocrystalline silicon substrate; 10. First passivation layer; 20. Second passivation layer; 30. Amorphous silicon layer; 40. Silicon oxide thin film layer; 50. Silicon-based semiconductor layer; 60. First transparent conductive oxide layer; 70. Second transparent conductive oxide layer; 80. First electrode; 90. Second electrode; 110. Polycrystalline silicon layer. Detailed Implementation

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] As described in the background section, in the prior art, edge passivation relies on the wrap-around plating of the front / back passivation film. When the subsequent etching step removes the wrap-around plating, the passivation film at the edge is also peeled off, resulting in missing edge passivation and aggravated recombination. In order to solve the problem that the edge passivation quality of high-efficiency crystalline silicon cells in the prior art is much lower than that of the front / back side, resulting in severe minority carrier recombination and low reverse bias breakdown voltage, the embodiments of this application provide a solar cell and its fabrication method.

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0030] Figure 1 This is a schematic flowchart illustrating a method for fabricating a solar cell according to an embodiment of this application. Figure 1 As shown, the method includes the following steps:

[0031] Step S101: Provide a substrate, the substrate including opposing first and second surfaces;

[0032] Specifically, a silicon substrate with two opposing surfaces is required, where the first and second surfaces correspond to the front and back sides of the cell, respectively. This substrate can be an N-type or P-type monocrystalline silicon or polycrystalline silicon material, serving as the basis for the subsequent growth of all functional layers.

[0033] Step S102: A first passivation layer is formed on the first surface, and a second passivation layer is formed on the second surface.

[0034] Specifically, a first passivation layer is formed on the first side of the substrate, and a second passivation layer is formed on the second side of the substrate. The main function of these two oxide layers is to serve as a passivation interface between the silicon surface of the substrate and the subsequent semiconductor layer, which can effectively reduce the recombination loss of charge carriers at the interface and provide a good adhesion foundation for the subsequent polycrystalline silicon layer and silicon-based semiconductor layer.

[0035] Step S103: A polysilicon layer is formed on the side of the first passivation layer away from the substrate.

[0036] Specifically, forming a polysilicon layer on the side of the first passivation layer away from the substrate means growing a semiconductor thin film with polysilicon as the main component on the surface above the first passivation layer already located on the first surface of the substrate, i.e., on the other side that is not in direct contact with the substrate. This polysilicon layer is attached to the top surface of the first passivation layer and does not directly contact the substrate. Its function is to serve as a channel for subsequent electron transport. It is formed only at this specific location and is limited to the area above the first passivation layer, without involving any changes to other layers or structures.

[0037] Step S104: A silicon-based semiconductor layer is formed on the side of the second passivation layer away from the substrate, and the silicon-based semiconductor layer deposited around the surface of the polysilicon layer, the sidewall region of the first passivation layer, and the sidewall region of the second passivation layer during the formation of the silicon-based semiconductor layer is removed.

[0038] Specifically, to ensure the electrical integrity of the battery structure, a selective etching process is required after deposition to remove only the excess silicon-based semiconductor layers attached to the surface of the polycrystalline silicon layer, the sidewall regions of the first and second passivation layers (using an alkaline solution as the etchant for selective removal). The silicon-based semiconductor layer directly above the second passivation layer, which serves as the effective functional layer, and the front-side polycrystalline silicon layer and two oxide layers remain unaffected. This step achieves precise cleaning of non-target areas around the plating layer in the battery structure, thereby avoiding potential edge short circuits and localized recombination.

[0039] In this embodiment, by first forming a first passivation layer and a second passivation layer on both sides of the substrate as a passivation interface, then forming a polycrystalline silicon layer on the first passivation layer and a silicon-based semiconductor layer on the second passivation layer, and selectively removing the portion of the silicon-based semiconductor layer that is deposited around the surface of the polycrystalline silicon layer, the sidewall region of the first passivation layer, and the sidewall region of the second passivation layer after depositing the silicon-based semiconductor layer, excess semiconductor material in non-target areas is eliminated without damaging the functional structure of the front polycrystalline silicon layer and the back silicon-based semiconductor layer. This solves the problem that the passivation quality at the edge of high-efficiency crystalline silicon cells is much lower than that on the front / back side, resulting in severe minority carrier recombination and low reverse-bias breakdown voltage.

[0040] In the specific implementation process, a polycrystalline silicon layer is formed on the side of the first passivation layer away from the substrate, including: forming an amorphous silicon layer on the side of the first passivation layer away from the substrate, wherein the doping type of the amorphous silicon layer is different from the doping type of the silicon-based semiconductor layer; forming a silicon oxide thin film layer on the side of the amorphous silicon layer away from the substrate, and simultaneously crystallizing the amorphous silicon layer into a polycrystalline silicon layer.

[0041] Specifically, firstly, an amorphous silicon thin film is deposited on the side of the first passivation layer away from the substrate to form an amorphous silicon layer. The doping type of this amorphous silicon layer is different from that of the silicon-based semiconductor layer subsequently formed on the second passivation layer. The silicon-based semiconductor layer is p-type, while the amorphous silicon layer is n-type, to achieve functional complementarity. Subsequently, a silicon oxide thin film is deposited on the side of the amorphous silicon layer away from the substrate to form a silicon oxide thin film layer. At the same time, the underlying amorphous silicon layer is crystallized through heat treatment and transformed into a polycrystalline silicon layer. The newly added silicon oxide thin film is then used as a capping layer to cover the polycrystalline silicon layer.

[0042] By first depositing an amorphous silicon layer with a doping type opposite to that of the back silicon-based semiconductor layer above the first passivation layer, and then forming a silicon oxide thin film layer on top of it to achieve crystallization of the amorphous silicon layer, the polycrystalline silicon layer is generated in situ under the protection of the silicon oxide thin film. This process promotes the crystallization of amorphous silicon by utilizing the formation process of the silicon oxide thin film without adding an additional crystallization step. This ensures the crystal quality of the polycrystalline silicon layer and avoids etching the polycrystalline silicon layer below the silicon oxide layer in the subsequent de-coating step through the masking effect of the silicon oxide layer.

[0043] In some embodiments of this application, a silicon oxide thin film layer is formed on the side of the amorphous silicon layer away from the substrate, while the amorphous silicon layer is crystallized into a polycrystalline silicon layer. This includes: performing a first high-temperature annealing treatment on the amorphous silicon layer, causing the amorphous silicon layer to be oxidized in situ on its surface to form the silicon oxide thin film layer, while the amorphous silicon layer itself crystallizes into the polycrystalline silicon layer; wherein the first high-temperature annealing treatment includes: performing a first annealing treatment for a first preset time in a first atmosphere; and performing a second annealing treatment for a second preset time in a second atmosphere, wherein the first atmosphere is nitrogen, and the second atmosphere is nitrogen and oxygen.

[0044] In some specific embodiments of this application, the temperature of the first annealing treatment is 800-980℃, the process gas pressure is 800Pa, and the first preset time is 2500s. The volume flow ratio of nitrogen to oxygen in the second annealing treatment is 5:1 to 1:1, the temperature is 800-980℃, the process gas pressure is 800Pa, and the second preset time is 50s-500s.

[0045] Specifically, the above process involves a first high-temperature annealing treatment, which is divided into two stages. The first stage involves a first annealing treatment of the amorphous silicon layer in a pure nitrogen atmosphere, and the second stage involves a second annealing treatment of the amorphous silicon layer in a mixed atmosphere of nitrogen and oxygen. In the first annealing treatment, under pure nitrogen, the amorphous silicon layer primarily undergoes a crystallization process, transforming into a polycrystalline silicon layer. Due to the lack of oxygen in the environment, this stage focuses on grain growth and perfection, avoiding premature oxidation. The first annealing treatment lasts for a first preset time to ensure sufficient internal restructuring of the amorphous silicon layer, forming a well-crystallized polycrystalline silicon layer. For the first annealing treatment, the preferred process conditions are: annealing temperature controlled between 800℃ and 980℃, process pressure maintained at 800 Pa, and annealing time (first preset time) set to 2500 seconds. Under these conditions, the amorphous silicon layer obtains sufficient crystallization energy and time, forming a polycrystalline silicon layer with complete crystal structure and low defect state density.

[0046] Subsequently, a second annealing treatment is performed in a second atmosphere, which is a mixture of nitrogen and oxygen. Under this oxygen-containing atmosphere, an in-situ oxidation reaction occurs on the surface of the already crystallized polycrystalline silicon layer, generating a dense silicon oxide film (i.e., a silicon oxide film layer). This process achieves simultaneous crystallization and oxidation; that is, while the amorphous silicon layer is transformed into a polycrystalline silicon layer, its surface is oxidized to form a passivation layer. The second annealing treatment lasts for a second preset time to control the thickness and quality of the silicon oxide film. For the second annealing treatment, the preferred process conditions are: the annealing temperature is also controlled between 800°C and 980°C, and the process gas pressure is maintained at 800 Pa. The volumetric flow rate ratio of nitrogen to oxygen in the mixed gas is controlled between 5:1 and 1:1, and the annealing time (second preset time) is set to 50 seconds to 500 seconds. The shorter second annealing time, combined with a specific gas flow rate ratio, aims to prevent the oxide layer from becoming too thick, ensuring that the formed silicon oxide film has sufficient passivation capability without introducing excessive interface defects or increasing series resistance. This achieves optimal edge and surface passivation effects while ensuring the crystallization quality of the polycrystalline silicon layer.

[0047] By employing a staged annealing process, the amorphous silicon layer is first annealed for a long time in a pure nitrogen atmosphere to ensure that it is fully crystallized into a polycrystalline silicon layer, avoiding premature oxidation that could affect the crystallization quality. Subsequently, a short-time annealing is performed in a nitrogen-oxygen mixed atmosphere to allow in-situ oxidation of the polycrystalline silicon layer surface, forming a silicon oxide film. This process achieves synergistic crystallization and oxidation, ensuring high-quality surface passivation while maintaining the crystallization quality of the polycrystalline silicon layer.

[0048] In some other embodiments of this application, a silicon oxide thin film layer is formed on the side of the amorphous silicon layer away from the substrate, and the amorphous silicon layer is crystallized into a polycrystalline silicon layer. This includes: performing a second high-temperature annealing treatment on the amorphous silicon layer, so that the amorphous silicon layer is oxidized in situ on the surface to form the silicon oxide thin film layer, while the amorphous silicon layer itself crystallizes into the polycrystalline silicon layer. The second high-temperature annealing treatment is performed in a pure nitrogen atmosphere.

[0049] Specifically, this embodiment represents another approach to forming a silicon oxide thin film layer on the side of the amorphous silicon layer away from the substrate and simultaneously crystallizing it into a polycrystalline silicon layer. This method also involves high-temperature annealing to generate a silicon oxide thin film in situ on the surface of the amorphous silicon layer, thereby promoting the transformation of the amorphous silicon layer into a polycrystalline silicon layer. The difference lies in the annealing environment being a pure nitrogen atmosphere. Under pure nitrogen conditions, the formation of the silicon oxide thin film does not rely on the direct participation of an external oxygen source. Instead, it relies on the oxygen impurities inherent in the amorphous silicon layer or the trace amounts of oxygen diffused upwards from the first passivation layer, which undergo a slow oxidation reaction with the amorphous silicon surface under high temperature, thus forming a thin layer of silicon oxide in situ on the surface. Simultaneously, the high-temperature environment still provides sufficient heat energy to promote the rearrangement of amorphous silicon atoms, completing the crystallization process into polycrystalline silicon. This approach, by using a pure nitrogen atmosphere, avoids the risk of additional oxidation and thickening of the second passivation layer on the back side due to external oxygen, achieving simultaneous construction of the polycrystalline silicon layer and the silicon oxide layer on the front side, while maintaining the stability of the original thickness of the oxide layer on the back side.

[0050] By performing high-temperature annealing on the amorphous silicon layer in a pure nitrogen atmosphere, a silicon oxide film is generated in situ on its surface using trace amounts of oxygen diffused from the amorphous silicon layer itself or from the first passivation layer without introducing external oxygen. This simultaneously achieves the crystallization of amorphous silicon into polycrystalline silicon. This method effectively avoids the additional oxidation effect of oxygen on the second passivation layer on the back side while completing the construction of the front passivation contact layer. Thus, the synergistic formation of the front polycrystalline silicon layer and the silicon oxide layer is achieved without changing the thickness and integrity of the back structure.

[0051] In some embodiments of this application, before forming a silicon oxide thin film layer on the amorphous silicon layer and crystallizing the amorphous silicon layer into a polycrystalline silicon layer, the method further includes: using an alkaline solution to etch and remove the amorphous silicon layer that was deposited around the second passivation layer during the formation of the amorphous silicon layer, wherein the etching rate of the alkaline solution on the amorphous silicon layer is greater than the etching rate on the silicon oxide.

[0052] Specifically, after forming the front amorphous silicon layer and before crystallization, selective etching is required.

[0053] The silicon wafer is cleaned using an alkaline solution (which can be potassium hydroxide solution (KOH solution), sodium hydroxide solution (NaOH solution), or other alkaline solutions) to remove excess amorphous silicon material (i.e., the wrap-around coating) deposited on the surface and sidewalls of the second passivation layer during the deposition of the amorphous silicon layer. The concentration of the alkaline solution is 0.5%wt-10%wt. This step utilizes the chemical selectivity of KOH solution, which has a high etching rate for amorphous silicon but an extremely low etching rate for silicon oxide (including the first and second passivation layers), to remove only the amorphous silicon in non-target areas without damaging any formed silicon oxide layer structure. This etching process occurs after the front amorphous silicon layer deposition is completed and before crystallization treatment. Its function is limited to cleaning the wrap-around amorphous silicon on the back and sides, ensuring that the back electrical structure is not disturbed in subsequent processes.

[0054] By selectively etching away the amorphous silicon layer around the surface and sidewalls of the second passivation layer during deposition using KOH solution before the silicon oxide film is formed and the amorphous silicon crystallizes, the significant difference between the high etching rate of KOH on amorphous silicon and the extremely low etching rate on silicon oxide is utilized to achieve precise removal of the plating defects. This completely avoids the risks of leakage, short circuit or passivation failure caused by back-side plating of amorphous silicon, and fully protects the integrity of the second passivation layer. Thus, without introducing additional processes or damaging the functional layer, the passivation quality and electrical stability of the battery edge are improved.

[0055] In some embodiments of this application, forming a first passivation layer on the first surface and a second passivation layer on the second surface includes: placing the substrate in a vacuum chamber of a tubular quartz furnace, exposing both the first and second surfaces to a reaction atmosphere; introducing a mixed gas composed of nitrogen and oxygen into the vacuum chamber for reaction, controlling the reaction temperature in the vacuum chamber to be 650-1000°C and the process gas pressure to be 100-500 Pa, and controlling the volume flow ratio of nitrogen to oxygen to be 1:1-1:10, so as to simultaneously form a silicon oxide thin film as the first passivation layer and the second passivation layer on both the first and second surfaces.

[0056] Specifically, a vacuum chamber in a tubular quartz furnace is used to simultaneously expose both sides of a silicon wafer to a mixed reaction atmosphere of nitrogen and oxygen, allowing for the simultaneous growth of silicon oxide thin films on both sides through a thermal oxidation reaction. Key parameters for this process include: a reaction temperature controlled between 650-1000℃, a process pressure maintained between 100-500 Pa, and a nitrogen to oxygen volumetric flow rate ratio set at 1:1-1:10. This parameter range ensures a slow, uniform, and high-quality thermal oxidation process under low temperature, low pressure, and low oxygen partial pressure conditions, guaranteeing the growth of the silicon oxide thin film (SiO₂). xThe uniformity and density of thickness on both sides effectively suppress interface defects or stress accumulation caused by excessively rapid oxidation. This embodiment achieves the construction of the first and second passivation layers through a single, double-sided simultaneous thermal oxidation process, improving production efficiency and providing a high-quality, uniform, and damage-free interface foundation for the subsequent formation of double-sided passivation contact structures (such as a front polycrystalline silicon layer and a back silicon-based semiconductor layer).

[0057] By simultaneously thermally oxidizing both sides of a silicon wafer in a nitrogen-oxygen mixed atmosphere at 650-1000℃, 100-500Pa, and a nitrogen-oxygen volume flow ratio of 1:1-1:10, uniform and symmetrical growth of the first and second passivation layers is achieved. This improves the quality consistency and process efficiency of the double-sided passivation layers without the need for masks or step-by-step processing, providing a stable interface foundation for efficient passivation contact structures.

[0058] In some embodiments of this application, forming a silicon-based semiconductor layer on the side of the second passivation layer away from the substrate includes: placing the substrate on which the second passivation layer has been formed into the vacuum chamber of a plasma-enhanced chemical vapor deposition (PECVD) apparatus; introducing H2, SiH4, and B2H6 as reaction gases into the vacuum chamber of the PECVD apparatus, and controlling the reaction temperature to be 150-220°C and the deposition pressure to be 200-350 Pa, so as to form the silicon-based semiconductor layer on the side of the second passivation layer away from the substrate, wherein the volumetric flow rate ratio of H2, SiH4, and B2H6 is: H2 / SiH4 = 100-700:1, and SiH4 / B2H6 = 20-200:1.

[0059] Specifically, hydrogen (H2), silane (SiH4), and diborane (B2H6) are used as reactant gases in a plasma-enhanced chemical vapor deposition (PECVD) system at low temperature and low pressure conditions of 150-220℃ and 200-350Pa. Deposition is performed with a precise volumetric flow rate ratio of H2 / SiH4 of 100-700:1 and SiH4 / B2H6 of 20-200:1 to achieve uniform deposition of boron-doped p-type silicon thin films. This process reduces the silane decomposition rate through high-ratio H2 dilution, suppressing amorphous silicon particle coarsening and promoting microcrystalline structure growth. Simultaneously, the ultra-low concentration of B2H6 ensures effective doping without introducing excessive defects, and the low temperature conditions prevent thermal damage or thickness increase to the underlying thermally oxidized second passivation layer. This parameter combination enables the precise deposition of high-quality, low-defect, and high-conductivity p-type silicon-based semiconductor layers without damaging the back-side silicon oxide passivation layer.

[0060] By using precise gas ratios of 100-700:1 for H2 / SiH4 and 20-200:1 for SiH4 / B2H6 under low-temperature and low-pressure PECVD conditions of 150-220℃ and 200-350Pa, a p-type silicon-based semiconductor layer was deposited. This enabled the efficient formation of p-type microcrystalline / amorphous silicon layers with low defects, high doping uniformity, and high conductivity without damaging the underlying thermally oxidized silicon layer, effectively reducing contact resistance and recombination loss.

[0061] In some embodiments of this application, after forming a silicon-based semiconductor layer on the second passivation layer and removing the silicon-based semiconductor layer deposited around the surface of the polycrystalline silicon layer, the sidewall region of the first passivation layer, and the sidewall region of the second passivation layer during the formation of the silicon-based semiconductor layer, the method further includes: removing the silicon oxide thin film layer; depositing a first transparent conductive oxide layer on the polycrystalline silicon layer; depositing a second transparent conductive oxide layer on the silicon-based semiconductor layer; fabricating a first electrode on the first transparent conductive oxide layer; and fabricating a second electrode on the second transparent conductive oxide layer.

[0062] Specifically, the silicon oxide thin film layer formed during crystallization is first removed. This silicon oxide thin film layer acts as a mask, preventing the underlying polycrystalline silicon layer from being etched during the de-coating process. After the de-coating is completed, the protective function of the silicon oxide thin film layer is achieved, and it is no longer necessary to retain it. Therefore, it needs to be removed before forming the transparent conductive oxide (TCO) layer. Subsequently, efficient lateral conduction of charge carriers on both sides is achieved through simultaneous or stepwise deposition of the TCO on both sides. Finally, metal electrodes are formed by screen printing, evaporation, or sputtering to complete the charge collection structure.

[0063] By removing the silicon-based semiconductor layer after the winding plating, the surface silicon oxide thin film layer formed during the crystallization process is removed first, and then transparent conductive oxide layers are deposited on the surfaces of the polycrystalline silicon layer and the silicon-based semiconductor layer respectively to prepare electrodes. This effectively solves the problems of poor TCO contact and increased series resistance caused by silicon oxide residue, realizes a carrier collection interface with low resistance and high conductivity on both the front and back sides, improves the fill factor and battery efficiency, and ensures the stable integration of the electrode and the passivation contact structure.

[0064] In some embodiments of this application, before forming a first passivation layer on the first surface and a second passivation layer on the second surface, the method further includes cleaning and texturing the substrate.

[0065] Specifically, before forming the first and second passivation layers, the silicon wafer substrate undergoes a cleaning and texturing process. This is a fundamental pretreatment step to ensure the quality of the subsequent passivation layers and the performance of the battery. Cleaning aims to remove organic contaminants, metal ions, and the natural oxide layer from the silicon wafer surface, preventing them from interfering with the uniform nucleation and interfacial bonding of silicon oxide. Texturing, on the other hand, forms a micro-nano pyramid structure through chemical anisotropic etching (such as alkaline etching of single-crystal silicon), significantly reducing surface reflectivity and improving light absorption.

[0066] By performing cleaning and texturing before the deposition of the first and second passivation layers, surface contaminants are effectively removed and a micro / nano texturing structure is constructed, improving the interface quality and optical coupling efficiency between the silicon oxide layer and the silicon substrate. This provides a clean, low-reflection substrate for the subsequent formation of a high-integrity passivation layer, thereby ensuring the passivation effect, reducing recombination losses, and improving the battery short-circuit current and overall conversion efficiency.

[0067] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the solar cell fabrication method of this application will be described in detail below with reference to specific embodiments.

[0068] This embodiment relates to a specific method for fabricating a solar cell, including:

[0069] 1) See Figure 2 A single-crystal silicon substrate 01 is provided. The single-crystal silicon substrate (silicon wafer) is placed in the vacuum chamber of a tube furnace, and a mixture of nitrogen and oxygen is introduced for reaction. The volumetric flow rate ratio of nitrogen to oxygen is 1:1-1:10, the process gas pressure is 100-500 Pa, and the reaction temperature is 650-1000℃. A first passivation layer L1 and a second passivation layer L2 (i.e., first passivation layer 10 and second passivation layer 20) are formed on both sides of the single-crystal silicon substrate. The single-crystal silicon substrate can be N-type or P-type single-crystal silicon, preferably N-type single-crystal silicon. The first passivation layer L1 and the second passivation layer L2 can be SiOx. After the silicon wafer is cleaned and texturized, a SiOx thin film, the first passivation layer L1 and the second passivation layer L2, is grown on both sides of the silicon wafer. The thickness of the SiOx is 0.5-2 nm.

[0070] 2) such as Figure 2 As shown, an N-type amorphous silicon layer L3 (i.e., amorphous silicon layer 30) is formed on the first passivation layer L1 (i.e., the first passivation layer 10). The N-type amorphous silicon layer L3 is grown on the first passivation layer L1 film, and the thickness of L3 is 5-50 nm.

[0071] 3) When removing the N-type amorphous silicon layer L3 film during growth, the amorphous silicon film is deposited around the second passivation layer L2 film.

[0072] 4) A high-temperature process is used to promote the crystallization of the N-type amorphous silicon layer L3. The high-temperature annealing process involves introducing a mixture of nitrogen and oxygen gas to oxidize the surface of the N-type amorphous silicon layer L3 (i.e., amorphous silicon layer 30) to form a silicon oxide film L4 (i.e., silicon oxide film layer 40). After the formation of silicon oxide film layer 40, the amorphous silicon layer 30 is transformed into a polycrystalline silicon layer 110, such as... Figure 3 As shown;

[0073] Alternatively, a silicon oxide film L4 can be grown on the N-type amorphous silicon layer L3, with a thickness of 20-150 nm. High-temperature annealing with pure nitrogen (to avoid thickening the second passivation layer L2 silicon oxide layer) can be used to promote the crystallization of the N-type amorphous silicon layer L3.

[0074] 5) See Figure 4 p-type microcrystalline silicon or amorphous silicon L5 (i.e. silicon-based semiconductor layer 50) is grown on the second passivation layer L2 (i.e., the second passivation layer), and the thickness of the p-type microcrystalline silicon or amorphous silicon L5 film is 10-30 nm.

[0075] 6) When removing the p-type microcrystalline silicon or amorphous silicon L5 film grown on the back and sides of the silicon wafer, the p-type microcrystalline silicon or amorphous silicon is coated around it.

[0076] 7) Use a chain cleaning machine to remove the silicon oxide film L4 and then dry it.

[0077] 8) For example Figure 5 As shown, a first TCO thin film (i.e., a first transparent conductive oxide layer 60) is prepared on the surface of the polycrystalline silicon layer 110, a second TCO thin film (i.e., a second transparent conductive oxide layer 70) is prepared on the surface of the p-type microcrystalline silicon or amorphous silicon L5 thin film (i.e., a silicon-based semiconductor layer 50), a first electrode 80 is prepared on the first transparent conductive oxide layer 60, and a second electrode 90 is prepared on the second transparent conductive oxide layer 70.

[0078] The following are several specific embodiments and comparative examples of this application.

[0079] Example 1:

[0080] 1) After the silicon wafer is cleaned and texturized, SiOx thin films L1 and L2 (i.e., the first passivation layer and the second passivation layer) are grown on both sides of the silicon wafer by thermal oxidation. The thickness of L1 and L2 is 2nm.

[0081] 2) An n-type amorphous silicon thin film L3 (i.e., an amorphous silicon layer) is grown on the L1 film, and the thickness of L3 is 35 nm.

[0082] 3) A chain-type floating process is used to remove the amorphous silicon film that is coated on the L2 film during the growth of the L3 film. The removal mechanism is to use KOH solution to etch the amorphous silicon film, while the etching rate of silicon oxide film in KOH is very low.

[0083] 4) High-temperature process is used to promote the crystallization of L3 film. During the high-temperature annealing process, a mixture of nitrogen and oxygen gas is introduced to oxidize the surface of L3 film to produce a silicon oxide film L4 (i.e. silicon oxide film layer). The thickness of L4 is about 25nm, while the thickness of L3 is 10nm.

[0084] 5) Grow p-type microcrystalline silicon L5 (i.e., silicon-based semiconductor layer) on the L2 thin film. The thickness of the L5 thin film is 30 nm.

[0085] 6) When removing the p-type microcrystalline silicon or amorphous silicon coated on the back and sides of the silicon wafer during L5 film growth, the removal mechanism is the same as above.

[0086] 7) Use a chain cleaning machine to remove the L4 film and dry it.

[0087] 8) A first TCO film (i.e., a first transparent conductive oxide layer) is prepared on the surface of the L3 film, a second TCO film (i.e., a second transparent conductive oxide layer) is prepared on the surface of the L5 film, a first electrode is prepared on the first TCO film, and a second electrode is prepared on the second TCO film.

[0088] Example 2:

[0089] 1) After the silicon wafer is cleaned and texturized, SiOx thin films L1 and L2 (i.e., the first passivation layer and the second passivation layer) are grown on both sides of the silicon wafer by thermal oxidation. The thickness of L1 and L2 is 2nm.

[0090] 2) An n-type amorphous silicon thin film L3 (i.e., an amorphous silicon layer) is grown on the L1 thin film, and the thickness of L3 is 10 nm.

[0091] 3) A chain-type floating process is used to remove the amorphous silicon film that is coated on the L2 film during the growth of the L3 film. The removal mechanism is to use KOH solution to etch the amorphous silicon film, while the etching rate of silicon oxide film in KOH is very low.

[0092] 4) A SiOx thin film L4 (i.e., silicon oxide thin film layer) with a thickness of 30 nm was grown on the L3 thin film. High-temperature annealing with pure nitrogen was used to promote the crystallization of the L3 thin film.

[0093] 5) Grow p-type microcrystalline silicon L5 (i.e., silicon-based semiconductor layer) on the L2 thin film. The thickness of the L5 thin film is 30 nm.

[0094] 6) When removing the p-type microcrystalline silicon or amorphous silicon coated on the back and sides of the silicon wafer during L5 film growth, the removal mechanism is the same as above.

[0095] 7) Use a tank cleaning machine to remove the L4 film and dry it.

[0096] 8) A first TCO film (i.e., a first transparent conductive oxide layer) is prepared on the surface of the L3 film, a second TCO film (i.e., a second transparent conductive oxide layer) is prepared on the surface of the L5 film, a first electrode is prepared on the first TCO film, and a second electrode is prepared on the second TCO film.

[0097] Example 3:

[0098] 1) After the silicon wafer is cleaned and texturized, SiOx thin films L1 and L2 (i.e., the first passivation layer and the second passivation layer) are grown on both sides of the silicon wafer by thermal oxidation. The thickness of L1 and L2 is 2nm.

[0099] 2) An n-type amorphous silicon thin film L3 (i.e., an amorphous silicon layer) is grown on the L1 thin film, and the thickness of L3 is 10 nm.

[0100] 3) A chain-type floating process is used to remove the amorphous silicon film that is coated on the L2 film during the growth of the L3 film. The removal mechanism is to use KOH solution to etch the amorphous silicon film, while the etching rate of silicon oxide film in KOH is very low.

[0101] 4) A SiOx thin film L4 (i.e., silicon oxide thin film layer) with a thickness of 30 nm was grown on the L3 thin film. High-temperature annealing with pure nitrogen was used to promote the crystallization of the L3 thin film.

[0102] 5) Grow p-amorphous silicon L5 (i.e., silicon-based semiconductor layer) on the L2 thin film. The thickness of the L5 thin film is 15nm.

[0103] 6) When removing the p-type microcrystalline silicon or amorphous silicon coated on the back and sides of the silicon wafer during L5 film growth, the removal mechanism is the same as above.

[0104] 7) Use a chain cleaning machine to remove the L4 film and dry it.

[0105] 8) A first TCO film (i.e., a first transparent conductive oxide layer) is prepared on the surface of the L3 film, a second TCO film (i.e., a second transparent conductive oxide layer) is prepared on the surface of the L5 film, a first electrode is prepared on the first TCO film, and a second electrode is prepared on the second TCO film.

[0106] Comparative Example 1: Traditional heterojunction solar cell.

[0107] 1) After the silicon wafer is cleaned and texturized, intrinsic amorphous silicon thin films L1 and L2 are deposited on both sides. The thicknesses of L1 and L2 are 8nm and 10nm, respectively.

[0108] 2) n-type microcrystalline silicon L3 and p-type microcrystalline silicon L4 are deposited on the surfaces of L1 and L2 films, respectively, with thicknesses of 20 nm and 30 nm, respectively.

[0109] 3) TCO films and electrodes were prepared on the surfaces of L3 and L4 films, respectively.

[0110] Comparative Example 2: Traditional TOPCon battery.

[0111] 1) After the silicon wafer is cleaned and texturized, boron diffusion is performed, and the sheet resistance is 110Ω / □.

[0112] 2) Remove the BSG and the wrapping layer generated on the back side during boron diffusion.

[0113] 3) Intrinsic silicon oxide and n-type amorphous silicon are grown on the back side of the silicon wafer.

[0114] 4) High-temperature annealing forms n-poly with a sheet resistance of 40Ω / □.

[0115] 5) Remove the PSG layer on the front.

[0116] 6) Remove n-poly from the front and sides.

[0117] 7) AlOx and SiNx are grown on the front side.

[0118] 8) Screen printing and sintering on both sides.

[0119] The battery IV data tables for the three embodiments and two comparative examples are shown in Table 1, obtained using a solar simulator under standard test conditions.

[0120] Table 1 Battery IV Data Sheet

[0121]

[0122] Wherein, Voc is the open-circuit voltage, Jsc is the short-circuit current density, FF is the fill factor, and Eta is the energy conversion efficiency. Table 1 shows that, while maintaining high Jsc and FF, Examples 1, 2, and 3 exhibit significantly higher Voc than traditional TOPCon batteries (Comparative Example 2), and slightly higher than or equal to HJT batteries (Comparative Example 1), achieving an efficiency of 25.53%~25.64%, surpassing Comparative Example 1 (25.03%) and Comparative Example 2 (25.49%). This demonstrates that this application effectively improves the open-circuit voltage and overall efficiency of the battery through optimized edge passivation and process flow, especially achieving a breakthrough in open-circuit voltage without sacrificing current.

[0123] The reverse bias IV curves of the batteries in the three embodiments and two comparative examples are shown below. Figure 6As shown, the horizontal axis represents reverse voltage, and the vertical axis represents reverse current. The curves are used to evaluate the battery's breakdown characteristics under reverse voltage, a key indicator of edge passivation quality. Under reverse bias, if the battery edge passivation is poor (e.g., there are unremoved silicon-on-wall coatings, oxide layer fractures, or interface defects), a low-resistance leakage path will form in the edge region, causing the reverse leakage current to rise sharply at a lower voltage, thus significantly reducing the reverse-bias breakdown voltage. Conversely, if the edge is well-encapsulated by a complete, uniform, and high-quality silicon oxide passivation layer, it can effectively suppress carrier tunneling and recombination leakage at the edge, causing the reverse current to rise rapidly only at a higher voltage, resulting in a higher reverse-bias breakdown voltage. Examples 1, 2, and 3 all exhibit higher reverse-bias breakdown voltages (significantly higher than Comparative Examples 1 and 2), indicating that their edge SiOx passivation layers are complete, defect-free, and free of silicon-on-wall coating residues, effectively blocking the edge leakage path.

[0124] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0126] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for preparing a solar cell, characterized in that, include: A substrate is provided, the substrate including opposing first and second surfaces; A first passivation layer is formed on the first surface, and a second passivation layer is formed on the second surface; A polycrystalline silicon layer is formed on the side of the first passivation layer away from the substrate; A silicon-based semiconductor layer is formed on the side of the second passivation layer away from the substrate, and the silicon-based semiconductor layer deposited around the surface of the polysilicon layer, the sidewall region of the first passivation layer, and the sidewall region of the second passivation layer during the formation of the silicon-based semiconductor layer is removed.

2. The method for preparing a solar cell according to claim 1, characterized in that, A polycrystalline silicon layer is formed on the side of the first passivation layer away from the substrate, comprising: An amorphous silicon layer is formed on the side of the first passivation layer away from the substrate, and the doping type of the amorphous silicon layer is different from the doping type of the silicon-based semiconductor layer; A silicon oxide thin film layer is formed on the side of the amorphous silicon layer away from the substrate, while the amorphous silicon layer is crystallized into a polycrystalline silicon layer.

3. The method for preparing a solar cell according to claim 2, characterized in that, A silicon oxide thin film layer is formed on the side of the amorphous silicon layer away from the substrate, while the amorphous silicon layer is crystallized into a polycrystalline silicon layer, including: The amorphous silicon layer is subjected to a first high-temperature annealing treatment, which causes the amorphous silicon layer to be oxidized in situ on the surface to form the silicon oxide thin film layer, while the amorphous silicon layer itself crystallizes into the polycrystalline silicon layer. The first type of high-temperature annealing treatment includes: a first annealing treatment for a first preset time in a first atmosphere; and a second annealing treatment for a second preset time in a second atmosphere, wherein the first atmosphere is nitrogen and the second atmosphere is nitrogen and oxygen.

4. The method for preparing a solar cell according to claim 3, characterized in that, The temperature of the first annealing treatment is 800-980℃, the process gas pressure is 800Pa, and the first preset time is 2500s. The volume flow ratio of nitrogen and oxygen in the second annealing treatment is 5:1 to 1:1, the temperature is 800-980℃, the process gas pressure is 800Pa, and the second preset time is 50s-500s.

5. The method for preparing a solar cell according to claim 2, characterized in that, A silicon oxide thin film layer is formed on the side of the amorphous silicon layer away from the substrate, while the amorphous silicon layer is crystallized into a polycrystalline silicon layer, including: The amorphous silicon layer is subjected to a second high-temperature annealing treatment, which causes the amorphous silicon layer to be oxidized in situ on the surface to form the silicon oxide thin film layer, while the amorphous silicon layer itself crystallizes into the polycrystalline silicon layer. The second high-temperature annealing treatment is carried out in a pure nitrogen atmosphere.

6. The method for preparing a solar cell according to claim 2, characterized in that, Before forming a silicon oxide thin film layer on the amorphous silicon layer and crystallizing the amorphous silicon layer into a polycrystalline silicon layer, the method further includes: The amorphous silicon layer deposited around the second passivation layer during the formation of the amorphous silicon layer is removed by etching with an alkaline solution, wherein the etching rate of the alkaline solution on the amorphous silicon layer is greater than the etching rate on silicon oxide.

7. The method for preparing a solar cell according to claim 1, characterized in that, A first passivation layer is formed on the first surface, and a second passivation layer is formed on the second surface, including: The substrate is placed in the vacuum chamber of a tubular quartz furnace, so that both the first and second surfaces are exposed to the reaction atmosphere; A mixture of nitrogen and oxygen is introduced into the vacuum chamber for reaction. The reaction temperature in the vacuum chamber is controlled at 650-1000℃, the process gas pressure is controlled at 100-500Pa, and the volume flow ratio of nitrogen to oxygen is controlled at 1:1-1:10, so as to simultaneously form silicon oxide thin films as the first passivation layer and the second passivation layer on the first and second surfaces.

8. The method for preparing a solar cell according to claim 1, characterized in that, A silicon-based semiconductor layer is formed on the side of the second passivation layer away from the substrate, comprising: The substrate with the second passivation layer formed is placed in the vacuum chamber of a plasma-enhanced chemical vapor deposition apparatus; H2, SiH4, and B2H6 are introduced as reaction gases into the vacuum chamber of the plasma-enhanced chemical vapor deposition apparatus, and the reaction temperature is controlled at 150-220°C and the deposition pressure is controlled at 200-350 Pa, so as to form the silicon-based semiconductor layer on the side of the second passivation layer away from the substrate. The volume flow rate ratio of H2, SiH4, and B2H6 is: H2 / SiH4 is 100-700:1, and SiH4 / B2H6 is 20-200:

1.

9. The method for preparing a solar cell according to claim 2, characterized in that, After forming a silicon-based semiconductor layer on the second passivation layer and removing the silicon-based semiconductor layer deposited around the surface of the polysilicon layer, the sidewall region of the first passivation layer, and the sidewall region of the second passivation layer during the formation of the silicon-based semiconductor layer, the method further includes: Remove the silicon oxide thin film layer, deposit a first transparent conductive oxide layer on the polycrystalline silicon layer, and deposit a second transparent conductive oxide layer on the silicon-based semiconductor layer; A first electrode is fabricated on the first transparent conductive oxide layer, and a second electrode is fabricated on the second transparent conductive oxide layer.

10. A solar cell, characterized in that, The solar cell is prepared using the solar cell preparation method described in any one of claims 1 to 9.

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