Solar cell and method of manufacturing the same

Abstract

The present disclosure provides a solar cell and a preparation method thereof, and belongs to the technical field of semiconductors. The preparation method comprises: sequentially forming a back field layer, a base region, an emission region, a window layer and a cover layer, wherein the base region is a GaInP layer; forming a dielectric layer on the surface of the cover layer; annealing the solar cell containing the dielectric layer; and removing the dielectric layer. The present disclosure can improve the photoelectric conversion efficiency of the solar cell.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor technology, and specifically relates to a solar cell and its fabrication method. Background Technology

[0002] Triple-junction solar cells are one of the most efficient power generation technologies currently available and have been used in space stations and various satellites. A triple-junction solar cell consists of a top cell, a middle cell, and a bottom cell connected in series.

[0003] In related technologies, the top-mounted solar cell comprises a back field layer, a base region, an emitter region, a window layer, and a capping layer stacked sequentially. The base region is a GaInP layer. During the formation of the base region, Sb doping is often used to induce a transition from ordered to disordered arrangement of gallium (Ga) and indium (In) atoms to increase the band gap.

[0004] However, the introduction of Sb inevitably brings about impurity effects, which not only exacerbate the absorption of free carriers but also destroy the integrity of the crystal lattice, resulting in a significant decrease in crystal quality and loss of optical performance. Summary of the Invention

[0005] This disclosure provides a solar cell and its fabrication method, which can improve the optical performance of the solar cell. The technical solution is as follows: In a first aspect, embodiments of this disclosure provide a method for preparing a solar cell, the method comprising: A back surface layer, a base region, an emitter region, a window layer, and a capping layer are formed sequentially, wherein the base region is a GaInP layer; a dielectric layer is formed on the surface of the capping layer; the solar cell containing the dielectric layer is annealed; and the dielectric layer is removed.

[0006] In another implementation of this disclosure, the thickness of the dielectric layer is 200 nm to 600 nm.

[0007] In another implementation of this disclosure, the dielectric layer is a silicon oxide layer or a silicon nitride layer.

[0008] In another implementation of this disclosure, the annealing temperature is 800℃~950℃.

[0009] In another implementation of this disclosure, the annealing time is 20s to 200s.

[0010] In another implementation of this disclosure, forming a dielectric layer on the surface of the capping layer includes: forming the dielectric layer on the surface of the capping layer using an epitaxial process within a process temperature range of 25°C to 300°C.

[0011] In another implementation of this disclosure, the base region is a p-type doped GaInP layer.

[0012] In another implementation of this disclosure, the band gap of the base region is 1.85 eV to 1.95 eV.

[0013] In another implementation of this disclosure, the photoluminescence wavelength of the base region is 635 nm to 670 nm.

[0014] On the other hand, this disclosure also provides a solar cell prepared according to the preparation method described above.

[0015] The beneficial effects of the technical solutions provided in this disclosure are: In the fabrication method provided in this disclosure, a back field layer, a base region, an emitter region, a window layer, and a capping layer are first formed. Then, a dielectric layer is formed on the surface of the capping layer, and the solar cell containing the dielectric layer is annealed. This allows Ga and In atoms in the base region to diffuse into the dielectric layer. Therefore, when the base region is a GaInP layer, without introducing foreign impurities, Ga and In atoms in the GaInP base region are induced to diffuse outward, achieving atomic rearrangement and bandgap modulation, thereby increasing the band gap. This fabrication method avoids lattice defects and optical losses caused by impurity doping, and while ensuring crystal quality, it increases the band gap of the GaInP base region, thereby improving the photoelectric conversion efficiency of the solar cell. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a method for fabricating a solar cell according to an embodiment of this disclosure; Figure 2 A flowchart illustrating another method for fabricating a solar cell according to an embodiment of this disclosure; Figure 3 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this disclosure.

[0018] The symbols in the diagram represent the following meanings: 1. Back field layer; 2. Base region; 3. Emission region; 4. Window layer; 5. Cap layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0020] Triple-junction solar cells overcome the efficiency limits of single-junction cells by stacking three sub-cells with different bandgapes to capture high-, medium-, and low-energy photons from the solar spectrum. A typical structure consists of a top cell, a middle cell, and a bottom cell connected in series. The top cell absorbs high-energy ultraviolet light, the middle cell absorbs mid-range visible light, and the bottom cell absorbs near-infrared light that penetrates the top and middle cells.

[0021] The top cell comprises a back surface layer, a base region, an emitter region, a window layer, and a capping layer stacked sequentially. The base region is a GaInP layer.

[0022] To improve the band gap of the base region of a top-mounted solar cell and achieve better current matching, antimony (Sb) doping is often used during base region growth to induce atomic disorder in the GaInP material, thereby widening the band gap. Specifically, when setting up the GaInP base region via metal-organic chemical vapor deposition, in addition to the Ga, In, and P sources introduced into the anti-cavity, an additional antimony source (such as triethylantimony) is introduced as a surfactant source. During surface migration, Ga and In atoms tend to arrange themselves in a regular alternating pattern to reduce energy, forming a CuPt-type ordered structure. This ordered structure introduces additional energy levels, narrowing the band gap. The presence of Sb atoms disrupts the arrangement of Ga and In atoms during diffusion, causing In and Ga atoms to become randomly distributed when they settle, forming an atomically disordered solid solution. When the Ga and In atoms change from ordered to disordered arrangement, the energy bands that were originally folded due to the ordered structure return to their normal structure. This increases the energy required for electrons to transition from the valence band to the conduction band, which macroscopically manifests as a significant increase in the band gap (Eg) and a blue shift in wavelength.

[0023] However, the introduction of Sb inevitably brings about impurity effects, which not only exacerbate free carrier absorption but also disrupt lattice integrity, resulting in a significant decrease in crystal quality and loss of optical performance. To address these problems, this disclosure provides a method for fabricating a solar cell.

[0024] Figure 1 A flowchart illustrating a method for fabricating a solar cell according to an embodiment of this disclosure is shown below. Figure 1 As shown, the preparation method includes: S101: The back field layer, base region, emitter region, window layer and cap layer are formed sequentially.

[0025] The base region is a GaInP layer.

[0026] S102: A medium layer is formed on the surface of the capping layer.

[0027] S103: Annealing the solar cell containing the dielectric layer.

[0028] Annealing causes Ga and In atoms in the base region to diffuse into the dielectric layer, thereby creating Ga and In vacancies in the base region.

[0029] S104: Remove the dielectric layer.

[0030] In the preparation method provided in this embodiment, a back field layer, a base region, an emitter region, a window layer, and a capping layer are first formed, and then a dielectric layer is formed on the surface of the capping layer. The solar cell containing the dielectric layer is then annealed, which allows Ga and In atoms in the base region to diffuse into the dielectric layer. Thus, when the base region is a GaInP layer, without introducing foreign impurities (such as antimony), Ga and In atoms in the GaInP base region are induced to diffuse outward, thereby achieving atomic rearrangement and bandgap modulation, and thus improving the bandgap.

[0031] This preparation method can avoid lattice defects and optical losses caused by impurity doping, and improve the band gap of the GaInP base region while ensuring crystal quality, thereby improving the photoelectric conversion efficiency of solar cells.

[0032] Furthermore, this fabrication method removes the dielectric layer at the end, thus completely eliminating its influence on the light path and ensuring that incident light can enter the cell without obstruction. It also avoids the stress or interface state effects that might result from a residual dielectric layer. In this way, the band structure of the solar cell is controlled while maintaining its clean and intact surface, allowing the photovoltaic performance advantages of the solar cell to be fully realized.

[0033] In this preparation method, during the high-temperature annealing process, the dielectric layer acts as an "atom collector" due to its natural affinity for gallium (Ga) and indium (In) atoms, continuously "extracting" Ga and In atoms from the base region 2. In other words, annealing provides Ga and In atoms with sufficient energy to break free from the lattice constraints, causing them to migrate from the base region 2 and eventually become trapped in the dielectric layer. This atom migration process leaves a large number of vacancies in the GaInP base region, resulting in a decrease in the concentration of Ga or In atoms in the base region. Consequently, the material composition and atomic arrangement shift from order to disorder, thereby achieving band gap widening. The essence of this technical solution is to achieve the directional migration of base region atoms at the microscopic level through annealing, in order to achieve the purpose of bandgap modulation.

[0034] In other words, the entire process described above utilizes the Impurity Free Vacancy Disorder (IFVD) method to improve the bandgap of the base region 2 of the top cell.

[0035] Using IFVD can promote atomic diffusion by utilizing the lattice vacancies of the material itself without introducing any foreign impurities, thereby increasing the band gap of the top cell material. This does not increase free carrier absorption or lattice defects, nor does it reduce the quality of the epitaxial layer.

[0036] This disclosure also provides another method for preparing a solar cell, such as... Figure 2 As shown, the preparation method includes: S201: The back field layer, base region, emitter region, window layer and cap layer are formed sequentially.

[0037] In this embodiment, the back surface layer, base region, emitter region, window layer, and capping layer mentioned above refer to the various film layer structures of the top cell in a solar cell. In other examples, they may also refer to other sub-cells.

[0038] The back surface field (SFR) layer is the bottom layer of the top cell. It is usually the first layer epitaxially grown on the surface of the substrate (or the tunnel junction of the lower cell) and is a material layer with the same conductivity type (p-type) as the subsequent base region but with a higher doping concentration. Its function is to create a built-in electric field at the bottom of the base region, reflecting photogenerated minority carriers (electrons) back to the base region, reducing their recombination at the back surface interface, thereby improving the cell's collection efficiency.

[0039] For example, the back field layer is a p-type doped AlGaInP layer.

[0040] The back field layer 1 can be formed in the following manner: The substrate was placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber. Under an H2 carrier gas atmosphere, trimethylaluminum (TMAl), trimethylgallium (TMGa), and trimethylindium (TMIn) were introduced as group III sources, phosphine (PH3) as a group V source, and diethylzinc (DEZn) or dimethylzinc (DMZn) as p-type dopant.

[0041] The temperature of the reaction chamber was controlled at 600℃~700℃, and the flow rate and introduction time of each gas source were controlled. A layer with a thickness of 15nm~35nm and a carrier concentration of 0.5×10⁻⁶ was epitaxially grown on the substrate surface. 18 ~5×10 18 cm -3 The p-type AlGaInP layer forms the back field layer 1.

[0042] By adjusting the flow ratio of TMAl to TMGa / TMIn, the Al composition can be controlled to achieve the desired wide bandgap characteristics.

[0043] The base region is the core absorption layer of the top cell.

[0044] For example, the base region is a p-type doped GaInP layer.

[0045] The base region can be formed in the following way: After the back field layer is epitaxially grown, the growth temperature and pressure in the MOCVD reaction chamber are maintained, the group III source is switched to TMGa and TMIn, the group V source remains phosphine (PH3), and the p-type dopant diethyl zinc (DEZn) or dimethyl zinc (DMZn) is continued to be introduced.

[0046] By controlling the flow rate and introduction time of each gas source, an epitaxial layer with a thickness of 500 nm to 750 nm and a carrier concentration of 0.5 × 10⁻⁶ is grown on top of the back field layer. 17 ~5×10 17 cm -3 The p-type GaInP layer is used to obtain the base region.

[0047] The Ga composition is controlled by adjusting the flux ratio of TMGa to TMIn. This layer serves as the main absorption region of the top cell, responsible for absorbing high-energy photons and generating photogenerated carriers.

[0048] The emitter layer grows immediately after the base layer, but with the opposite doping type, being n-type. It together with the underlying p-type base layer forms a pn junction.

[0049] During growth, the doping source needs to be switched (either silane (Si₂H₆) or diethyltelluride (DETe)) for n-type doping, and epitaxial growth continues on the base region. The emitter region 3 is usually thinner to ensure that photogenerated carriers can effectively diffuse into the pn junction.

[0050] For example, the emitter region is an n-type doped GaInP layer.

[0051] The launch area can be formed in the following manner: After the epitaxial growth of the base region is completed, the growth temperature and pressure in the MOCVD reaction chamber are maintained, the dopant type is switched, the p-type dopant is stopped and the n-type dopant (such as Si2H6 or DETe) is introduced instead, the group III source is still TMGa and TMIn, and the group V source is still PH3.

[0052] By controlling the flow rate and inlet time of each gas source, an epitaxial layer with a thickness of 50 nm to 150 nm and a carrier concentration of 1 × 10⁻⁶ is grown on top of the base region. 18 ~6×10 18 cm -3 The n-type GaInP layer is used to obtain the emitter region.

[0053] The Ga composition is controlled by adjusting the flux ratio of TMGa to TMIn. This layer, together with the underlying p-type base region, forms a pn junction, which is the core structure of the photovoltaic effect.

[0054] Window layer 4 grows immediately following the emitter region. Window layer 4 reduces recombination losses of photogenerated carriers at the top surface of the cell. Furthermore, the bandgap width of window layer 4 is significantly wider than that of the emitter region 3 below. This wide bandgap allows high-energy photons to smoothly enter the emitter and base regions without absorption, enhancing light transmittance. Simultaneously, its band structure can also reflect photogenerated minority carriers (electrons) back to the emitter and base regions, improving collection efficiency.

[0055] In actual growth, after the epitaxial growth in the emitter region is completed, the growth temperature (600~700℃) and pressure in the MOCVD reaction chamber are maintained, the group III source is switched to TMAl and TMIn, the group V source remains PH3, and n-type dopant (such as Si2H6 or DETe) is continued to be introduced.

[0056] By controlling the flux ratio of TMA1 to TMAIn, a layer with a thickness of 25 nm to 40 nm and a carrier concentration of 1 × 10⁻⁶ was epitaxially grown on the emitter region. 18 ~6×10 18 cm - ³ n-type AlInP layers are used to obtain window layers.

[0057] After the window layer has finished growing, a capping layer continues to form on the window layer.

[0058] For example, the capping layer is an n-type InGaAs layer.

[0059] The cap layer can be formed in the following manner: Maintaining the growth temperature (600~700℃) and pressure within the MOCVD reactor, switch the group III source to TMGa and TMIn, and the group V source to AsH3, while continuing to introduce an n-type dopant (such as Si2H6 or DETe). By controlling the TMGa to TMIn flow ratio, an n-type InGaAs layer with a thickness of 300nm~600nm is epitaxially grown on top of the window layer, with a doping concentration typically of 0.1×10⁻⁶. 19 ~1×10 19 cm -3 This layer is the cap layer.

[0060] As a "protective cover" for the top battery, the capping layer can prevent the underlying window layer from being contaminated, oxidized, or mechanically damaged during subsequent high-temperature annealing, photolithography, etching, and other processes.

[0061] S202: A dielectric layer is formed on the surface of the capping layer.

[0062] An epitaxial process is used to form a dielectric layer on the surface of the capping layer within a process temperature range of 25°C to 300°C.

[0063] For example, the thickness of the dielectric layer is 200nm~600nm.

[0064] In the above implementation, the thickness is sufficient to continuously and fully absorb Ga / In atoms diffused from the base region during high-temperature annealing, effectively controlling the band structure of the top cell and improving the band gap. Moreover, the appropriate film thickness is conducive to subsequent removal by wet etching (such as diluted hydrofluoric acid), avoiding removal difficulties or residue problems caused by excessive thickness, while preventing premature consumption or pinhole defects during annealing due to excessive thinness. Thus, while ensuring the process effect, manufacturability and device yield are also taken into account.

[0065] For example, the thickness of the dielectric layer is 300 nm, 400 nm or 500 nm.

[0066] In one implementation, the dielectric layer is a silicon oxide layer or a silicon nitride layer.

[0067] In the above implementation, the dielectric layer uses silicon oxide or silicon nitride, which possesses good high-temperature stability and affinity for gallium / indium atoms, enabling effective adsorption and extraction of Ga / In atoms from the base region during annealing. Furthermore, both materials are mature dielectric materials used in semiconductor processes, and high-quality deposition can be achieved through low-temperature plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD), offering strong process compatibility. Both materials can also be selectively removed subsequently using diluted hydrofluoric acid (DHF), demonstrating good operability and process window.

[0068] In this embodiment, the dielectric layer can be prepared in the following manner: The wafer with the completed epitaxial structure (including the capping layer) of the top cell is placed in the deposition reaction chamber, using high-purity nitrogen (N2) or argon (Ar) as the carrier gas and purge gas. Precursor sources required for the dielectric layer are introduced into the reaction chamber at a growth temperature of 25℃~300℃.

[0069] When depositing silicon nitride (Si3N4), silane (SiH4) and ammonia (NH3) or nitrogen (N2) are usually used to carry out the reaction under the assistance of radio frequency plasma.

[0070] When depositing silica (SiO2), silane (SiH4) and nitrous oxide (N2O) or oxygen (O2) are usually used, and the reaction is carried out under plasma.

[0071] With the assistance of plasma, the precursor decomposes and undergoes a chemical reaction at low temperature, uniformly depositing a dielectric film with a thickness of 200nm~600nm on the capping layer surface.

[0072] During the deposition process, it is necessary to control the chamber pressure, radio frequency power, gas flow rate and substrate temperature to ensure the uniformity of the dielectric film thickness, density and good step coverage.

[0073] After deposition, turn off the RF power supply and gas supply, cool to room temperature in N2 or Ar atmosphere, and remove the top cell.

[0074] S203: Annealing a solar cell containing a dielectric layer allows Ga and In atoms in the base region to diffuse into the dielectric layer.

[0075] After depositing the dielectric layer on the capping layer surface, the entire epitaxial structure of the battery needs to be subjected to high-temperature rapid thermal annealing to induce Ga atoms and In atoms in the base region to diffuse into the dielectric layer, thereby achieving bandgap modulation.

[0076] Optionally, the annealing temperature is 800℃~950℃.

[0077] The annealing temperature is controlled between 800℃ and 950℃ to provide sufficient thermal energy for Ga and In atoms, enabling them to effectively break free from the lattice and diffuse into the dielectric layer, thereby achieving the migration of base region atoms and widening of the band gap. At the same time, this temperature range is lower than the decomposition threshold of GaInP material, which can prevent the epitaxial structure from undergoing thermal decomposition or performance degradation at high temperatures.

[0078] For example, the annealing temperature is 850°C or 900°C.

[0079] In one implementation, the annealing time is 20s to 200s.

[0080] Annealing time is controlled between 20s and 200s. This ensures that Ga / In atoms have sufficient time to complete directional diffusion and bandgap widening, while effectively avoiding insufficient atom migration due to too short a time, or excessive diffusion, lattice defect proliferation, and epitaxial layer thermal degradation due to too long a time. Thus, crystal quality is protected while achieving bandgap control.

[0081] For example, the annealing time is 100 seconds.

[0082] Optionally, step S203 can be implemented in the following manner: The top cell with the deposited dielectric layer is placed on a quartz base inside the rapid thermal annealing furnace. After evacuation, high-purity nitrogen (N2) or argon (Ar) is introduced as a protective atmosphere to prevent oxidation or decomposition of the epitaxial layer at high temperatures.

[0083] Under a protective atmosphere, the temperature is rapidly increased to the target annealing temperature of 800℃~950℃ at a heating rate of 50~100℃ / second, and held at this temperature for 20s~200s. At this high temperature, the dielectric layer (SiO2 or Si3N4) continuously adsorbs Ga and In atoms from the top cell due to its affinity for Ga and In atoms, causing them to break free from the lattice and diffuse into the dielectric layer. At the same time, a large number of vacancies are left in the GaInP base region, driving Ga and In atoms in the base region to continuously migrate outward through the vacancy relay mechanism. This reduces the atomic concentration in the base region and transforms the atomic arrangement from ordered to disordered, ultimately achieving the effect of widening the band gap.

[0084] After the constant temperature period ends, the heating power is quickly cut off, and a large amount of N2 or Ar is introduced for forced cooling, rapidly reducing the temperature to below 600°C at a cooling rate of 20~40°C / second. Then, the temperature is allowed to cool naturally to room temperature, and the wafer is removed.

[0085] After annealing, the dielectric layer has fulfilled its role as an "atom collector" and can be completely removed by diluting hydrofluoric acid (DHF) to eliminate its influence on the optical path. The entire annealing process requires careful control of the heating rate, isothermal temperature, isothermal time, and cooling rate to achieve effective atomic diffusion while avoiding thermal damage to the top cell crystal or the introduction of additional defects due to high temperatures.

[0086] The resulting dielectric layer will play a crucial role in the subsequent high-temperature annealing process, acting as an atom collector to induce the outward diffusion of Ga / In atoms in the base region, thereby achieving bandgap tuning. After annealing, this dielectric layer can be completely removed by selective etching methods such as DHF without damaging the underlying capping material.

[0087] S204: Remove the dielectric layer.

[0088] Optionally, step S204 can be implemented as follows: In one implementation, when the dielectric layer is a silicon oxide (SiO2) layer, wet etching is performed at room temperature using DHF.

[0089] DHF reacts only with SiO2 and has an extremely slow corrosion rate on the InGaAs capping layer, enabling highly selective removal.

[0090] During the operation, the wafer is immersed in DHF solution. After the dielectric layer is completely dissolved, it is immediately rinsed with plenty of deionized water and then spun dry.

[0091] In one implementation, the concentration of DHF is 0.5% to 2%, or HF:H2O = 1:50 to 1:100.

[0092] By controlling the hydrofluoric acid concentration in the low range of 0.5% to 2%, the etching rate of the underlying n-type InGaAs capping layer and other epitaxial layers of the top cell can be significantly reduced while ensuring sufficient and uniform removal of the silicon oxide or silicon nitride dielectric layer. This improves the etching selectivity and avoids problems such as over-etching, surface roughness, or material damage caused by excessive concentration. At the same time, the reaction is mild and controllable within this concentration range, which is beneficial to improving process repeatability, batch consistency, and yield.

[0093] In one implementation, when the dielectric layer is a silicon nitride (Si3N4) layer, dry etching (reactive ion etching (RIE) or inductively coupled plasma (ICP)) is employed. For example, plasma etching is performed using CF4 / O2 or SF6 gas, and endpoint detection is used to control the etching to stop at the capping layer surface, avoiding over-etching and damage to the underlying material.

[0094] After removal, only the original n-type InGaAs capping layer remains on the surface of the top battery, providing a clean and complete operating interface for subsequent chip processes.

[0095] S205: Fabrication of electrodes.

[0096] Before fabricating the electrodes, the dimensions of individual battery chips are defined through photolithography and etching, and the chips are electrically isolated to prevent leakage.

[0097] Then, grid-like or mesh-like metal electrodes (such as Au / Ge / Ni / Au or Ti / Pt / Au) are fabricated on the capping layer surface using photolithography, metal deposition (such as electron beam evaporation or magnetron sputtering), and lift-off processes to collect photocurrent. Simultaneously, metal (such as Au / Ge / Ni / Au) is deposited on the back side of the substrate after thinning to form the bottom electrode.

[0098] The top cell with fabricated electrodes is annealed at a low temperature (e.g., 300℃~450℃) to form an ohmic contact between the metal electrode and the semiconductor layer, thereby reducing the series resistance.

[0099] Next, dicing cuts the wafer into individual cell chips, followed by sorting, testing, and packaging to ultimately form a solar cell module that can be installed and used.

[0100] In this embodiment of the disclosure, a solar cell is also provided, which is prepared according to the preparation method described above.

[0101] Figure 3 This is a schematic diagram of the structure of a solar cell provided in an embodiment of the present disclosure, such as... Figure 3 As shown, the solar cell includes a bottom cell, a middle cell, and a top cell, with the middle cell located between the bottom and top cells. The top, middle, and bottom cells are connected in series. The top cell includes a back field layer 1, a base region 2, an emitter region 3, a window layer 4, and a capping layer 5, which are sequentially stacked on a substrate, wherein the base region 2 is a GaInP layer.

[0102] The above methods have the same beneficial effects as the aforementioned preparation methods, and will not be repeated here.

[0103] In this embodiment, base region 2 is a p-type doped GaInP layer. The band gap of base region 2 is 1.85 eV to 1.95 eV.

[0104] Increasing the bandgap of base region 2 from 1.8 eV to greater than 1.85 eV is beneficial for optimizing the current matching between the top cell, middle cell, and bottom cell. This is because the wider bandgap top cell can reduce the absorption of low-energy photons, allowing more photons to penetrate to the lower cells, thereby improving the photoelectric conversion efficiency of the entire triple-junction solar cell.

[0105] Optionally, the photoluminescence wavelength of the base region 2 is 635nm~670nm.

[0106] Blue-shifting the photoluminescence (PL) wavelength of base region 2 from the original 690nm to 635nm~670nm means a reduction in wavelength compared to the original. The absorption of shorter wavelengths means that the top cell can utilize high-energy photons more efficiently, while reducing the excessive absorption of long-wavelength photons, allowing more low-energy photons to penetrate to the middle and bottom cells, thereby optimizing the current matching of the triple-junction cell and improving the overall photoelectric conversion efficiency.

[0107] In the epitaxially grown GaInP base region of the top-cell battery, Ga and In atoms spontaneously form an ordered CuPt arrangement, which results in a low bandgap. However, in this embodiment, a dielectric layer is deposited on the capping layer surface of the top-cell battery using a vacancy-free disordered deposition method, followed by high-temperature annealing. This causes the Ga and In atoms in the base region to extend into the dielectric layer, generating group III vacancies on the base surface that diffuse into the material. These lattice vacancies disrupt the originally ordered CuPt structure, resulting in a disordered state, which in turn increases the bandgap and causes a blue shift in wavelength.

[0108] The spontaneous formation of CuPt structure by Ga and In atoms in the GaInP base region refers to the Ga and In atomic layers being aligned along a certain crystal orientation. <111> The directions are stacked alternately in atomic layers, forming a superlattice of infinitely repeating GaP and InP monolayers; along the... <111> In terms of direction, the stacking order of the atomic layers is: ...-P-Ga-P-In-P-Ga-P-In-....

[0109] The band gap of the ordered GaInP base region is 1.80 eV, and the photoluminescence (PL) wavelength is 690 nm. In this embodiment, after IFVD, the band gap of the GaInP base region can be increased by about 80 meV, from the original 1.8 eV to 1.88 eV, and the photoluminescence (PL) wavelength changes from the original 690 nm to 658 nm, which is basically consistent with the PL wavelength (655 nm) of Sb-doped GaInP base regions in related technologies.

[0110] Photoluminescence (PL) spectroscopy is the most direct and conventional method for obtaining the band gap and atomic ordering state of GaInP base regions. By comparing the changes in the PL peak wavelength (PL wavelength) before and after treatment (e.g., 690 nm → 655 nm), the degree of order disruption and band gap modulation effect can be quantitatively characterized. The PL wavelength is obtained through photoluminescence spectroscopy.

[0111] During testing, the sample is irradiated with a laser of energy higher than the band gap of the GaInP substrate (e.g., 532nm green light) to excite electron transitions. The fluorescence emitted after the electrons return is collected by a spectrometer to obtain the photoluminescence (PL) spectrum. The peak wavelength of the PL spectrum is the PL wavelength (λ). The band gap value can then be obtained using the formula Eg = 1240 / λ.

[0112] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0113] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for preparing a solar cell, characterized in that, The preparation method includes: A back field layer (1), a base region (2), an emitter region (3), a window layer (4), and a capping layer (5) are formed sequentially, wherein the base region (2) is a GaInP layer; A medium layer is formed on the surface of the cover layer (5); The solar cell containing the dielectric layer is annealed; Remove the dielectric layer.

2. The preparation method according to claim 1, characterized in that, The thickness of the dielectric layer is 200nm~600nm.

3. The preparation method according to claim 1, characterized in that, The dielectric layer is a silicon oxide layer or a silicon nitride layer.

4. The preparation method according to claim 1, characterized in that, The annealing temperature is 800℃~950℃.

5. The preparation method according to claim 1, characterized in that, The annealing time is 20s~200s.

6. The preparation method according to claim 1, characterized in that, The formation of a dielectric layer on the surface of the capping layer (5) includes: The dielectric layer is formed on the surface of the capping layer (5) by using an epitaxial process within a process temperature range of 25°C to 300°C.

7. The preparation method according to claim 1, characterized in that, The base region (2) is a p-type doped GaInP layer.

8. The preparation method according to claim 1, characterized in that, The band gap of the base region (2) is 1.85eV~1.95eV.

9. The preparation method according to claim 1, characterized in that, The photoluminescence wavelength of the base region (2) is 635nm~670nm.

10. A solar cell, characterized in that, The solar cell is prepared according to the preparation method of any one of claims 1 to 9.

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