Method for preparing a silicon wafer texturing, silicon wafer and solar cell

Abstract

The application discloses a preparation method of a silicon wafer texturing structure, a silicon wafer and a solar cell, and belongs to the technical field of solar cells. The method comprises the following steps: providing a silicon wafer to be textured, wherein the silicon wafer has a first surface and a second surface arranged oppositely; performing double-side phosphorus diffusion on the silicon wafer to form phosphorus diffusion layers located on the first surface and the second surface; removing the phosphorus diffusion layer on the first surface; placing the silicon wafer in a texturing tank, and using a texturing reagent to perform texturing on the silicon wafer to form a texturing structure located on the first surface and the second surface, wherein the size of the texturing structure on the first surface is larger than the size of the texturing structure on the second surface. The method can simplify the texturing process, reduce the manufacturing cost, and significantly optimize the contact performance of the obtained texturing structure.

Description

Technical Field

[0001] This application belongs to the field of solar cell technology, and particularly relates to a method for preparing a textured silicon wafer, a silicon wafer, and a solar cell. Background Technology

[0002] Solar cells convert light energy into electrical energy through the photoelectric conversion effect. Texturing the front side of a solar cell, i.e., the light-receiving side, can create microstructures to increase the optical path and improve light trapping effect. In structures such as heterojunction cells and passivated emitter-backside cells, textured surfaces can be formed on both the front and back sides of the solar cell. The textured back side can receive back-incident light reflected or scattered from the environment and reflect long-wavelength light that is not absorbed by the front side back to the solar cell, enhancing light absorption and thus improving the photoelectric performance of the solar cell. Current texturing processes are complex and costly to manufacture. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a method for preparing a textured silicon wafer structure, a silicon wafer, and a solar cell, which can simplify the texturing process, reduce manufacturing costs, and significantly optimize the contact performance of the resulting textured structure.

[0004] In a first aspect, this application provides a method for fabricating a textured silicon wafer structure, the method comprising: A silicon wafer to be texturized is provided, the silicon wafer having a first surface and a second surface disposed opposite to each other; The silicon wafer is subjected to double-sided phosphorus diffusion to form a phosphorus diffusion layer located on the first surface and the second surface; Remove the phosphorus diffusion layer from the first surface; The silicon wafer is placed in a texturing tank, and a texturing reagent is used to texturize the silicon wafer to form a texturized structure on the first surface and the second surface, wherein the size of the texturized structure on the first surface is larger than the size of the texturized structure on the second surface.

[0005] According to the method for preparing a textured silicon wafer structure provided in this application, after performing double-sided phosphorus diffusion on the silicon wafer, the phosphorus diffusion layer on the first surface is removed, and the phosphorus diffusion layer on the remaining second surface is used as a mask to texture the silicon wafer, thereby forming a differentiated textured surface on the first and second surfaces. The first surface with a larger textured structure can serve as a backlight surface, forming a higher quality contact and passivation effect with the electrode, while the second surface with a smaller textured structure can serve as a light-receiving surface, increasing the silicon wafer's ability to capture and absorb incident light. This method simplifies the silicon wafer texturing process, reduces manufacturing costs, significantly optimizes the contact performance of the obtained textured structure, and helps improve the photoelectric performance of the battery prepared from the silicon wafer.

[0006] According to one embodiment of this application, placing the silicon wafer in a texturing tank and texturing the silicon wafer using a texturing reagent includes: The silicon wafer is placed in a texturing tank, and the silicon wafer is texturized for the first time using a first texturing reagent to form an intermediate texturing structure on the first surface. After the first texturing is completed, the phosphorus diffusion layer on the second surface is removed; The silicon wafer is placed in a texturing tank, and a second texturing agent is used to perform a second texturing process on the silicon wafer to form a texturized structure on the first surface and the second surface.

[0007] According to one embodiment of this application, both the first texturing reagent and the second texturing reagent include an alkaline solution and a texturing additive, wherein the alkaline concentration of the second texturing reagent is less than the alkaline concentration of the first texturing reagent.

[0008] According to one embodiment of this application, the intermediate velvet structure includes a pyramid structure, wherein the base size of the intermediate velvet structure is less than 4 μm.

[0009] According to one embodiment of this application, the alkali concentration of the first texturing reagent is 0.05%-0.01%; And / or, the processing time for the first texturing step is 300s-500s; And / or, the reagent temperature for the first texturing process is 70℃-80℃.

[0010] According to one embodiment of this application, the alkali concentration of the second texturing reagent is 0.009%-0.03%; And / or, the processing time for the second texturing is 150s-300s; And / or, the reagent temperature for the second texturing process is 60℃-80℃.

[0011] According to one embodiment of this application, the textured structure of the first surface includes a pyramid structure, and the base size of the textured structure of the first surface is 4μm-5μm; The textured structure of the second surface includes a pyramid structure, and the base size of the textured structure of the second surface is 1μm-3μm.

[0012] According to one embodiment of this application, the thickness of the silicon wafer to be texturized is 80μm-120μm.

[0013] According to one embodiment of this application, the phosphorus diffusion layer includes a heavily doped layer close to the silicon wafer and a phosphorus silicate glass layer located on the side of the heavily doped layer away from the silicon wafer, wherein the thickness of the phosphorus silicate glass layer is 50nm-100nm.

[0014] Secondly, this application provides a silicon wafer having a first surface and a second surface disposed opposite to each other, wherein the textured structure size of the first surface is larger than the textured structure size of the second surface; The textured surface of the first and second surfaces is formed through the following steps: The silicon wafer to be texturized is subjected to double-sided phosphorus diffusion to form a phosphorus diffusion layer located on the first surface and the second surface; Remove the phosphorus diffusion layer from the first surface; The silicon wafer is placed in a texturing tank, and a texturing reagent is used to texturize the silicon wafer to form a texturized structure on the first surface and the second surface.

[0015] Thirdly, this application provides a solar cell comprising a silicon wafer as described in the second aspect above.

[0016] According to one embodiment of this application, a first transparent conductive film layer is further located on one side of the first surface; The textured structure of the first surface includes a pyramid structure, the base size of the textured structure of the first surface is 4μm-5μm, and the thickness of the first transparent conductive film layer is 100nm-110nm.

[0017] According to one embodiment of this application, the first surface is sequentially stacked with a first intrinsic amorphous silicon layer, a first doped crystalline silicon layer and a first transparent conductive film layer along a direction away from the silicon wafer; The second surface is sequentially stacked with a second intrinsic amorphous silicon layer, a second doped crystalline silicon layer, and a second transparent conductive film layer along a direction away from the silicon wafer.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is one of the flowcharts illustrating the method for fabricating a textured silicon wafer structure according to an embodiment of this application; Figure 2 This is a second schematic flowchart of the method for preparing the textured silicon wafer structure provided in the embodiments of this application; Figure 3 This is the third schematic flowchart of the method for preparing the textured silicon wafer structure provided in the embodiments of this application; Figure 4 This is the fourth flowchart illustrating the method for preparing the textured silicon wafer structure provided in this application embodiment; Figure 5 This is the fifth schematic flowchart of the method for preparing the textured silicon wafer structure provided in the embodiments of this application; Figure 6 This is one of the microscopic morphological diagrams of the textured silicon wafer structure provided in the embodiments of this application; Figure 7 This is the second schematic diagram of the microstructure of the textured silicon wafer provided in the embodiments of this application; Figure 8 This is the third of the microscopic morphological diagrams of the textured silicon wafer structure provided in the embodiments of this application; Figure 9 This is the fourth of the microscopic morphological diagrams of the textured silicon wafer structure provided in the embodiments of this application; Figure 10 This is the fifth of the microscopic morphological diagrams of the textured silicon wafer structure provided in the embodiments of this application; Figure 11 This is the sixth of the microscopic morphological diagrams of the textured silicon wafer structure provided in the embodiments of this application; Figure 12 This is a schematic diagram of the microstructure of the velvet structure in the relevant technology; Figure 13 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application.

[0020] Figure label: Silicon wafer 210, phosphorus diffusion layer 220; The first intrinsic amorphous silicon layer 310, the first doped crystalline silicon layer 320, and the first transparent conductive film layer 330; The second intrinsic amorphous silicon layer 410, the second doped crystalline silicon layer 420, and the second transparent conductive film layer 430. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0022] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0023] The following description, in conjunction with the accompanying drawings, details the fabrication method of the textured silicon wafer structure, the silicon wafer, and the solar cell provided in this application through specific embodiments and application scenarios.

[0024] like Figure 1 As shown, the method for preparing the textured silicon wafer structure includes steps 110, 120, 130, and 140.

[0025] Step 110: Provide a silicon wafer 210 to be texturized.

[0026] The silicon wafer 210 has a first surface S1 and a second surface S2 that are disposed opposite to each other.

[0027] In practice, silicon wafer 210 is used to fabricate solar cells, including but not limited to monocrystalline silicon wafers and polycrystalline silicon wafers, which can be determined according to actual needs.

[0028] In some embodiments, silicon wafer 210 can be used to fabricate heterojunction cells (HJT), passivated emitter-back cell (PERC) structures, or other solar cells with a double-sided textured structure.

[0029] It is understood that the first surface S1 and the second surface S2 are two surfaces that are arranged opposite to each other on the silicon wafer 210. For example, the first surface S1 can be the back surface of the solar cell, and the second surface S2 can be the light-receiving surface of the solar cell.

[0030] In some embodiments, the thickness of the silicon wafer 210 to be texturized is 80μm-120μm.

[0031] For example, the thickness of the silicon wafer 210 to be texturized can be 80μm, 90μm, 100μm, 110μm or 120μm.

[0032] In this embodiment, a silicon wafer 210 with a thickness of 80μm-120μm is selected, which is beneficial for the subsequent texturing process. It should be noted that the silicon wafer 210 to be texturized has had its surface organic matter, metal impurities, and surface damage layer removed, achieving a polished state for the first surface S1 and the second surface S2.

[0033] Step 120: Perform double-sided phosphorus diffusion on silicon wafer 210 to form a phosphorus diffusion layer 220 located on the first surface S1 and the second surface S2.

[0034] In this embodiment, double-sided phosphorus diffusion is performed on silicon wafer 210 to precipitate and enrich impurity atoms from inside silicon wafer 210, which can improve the photoelectric performance of silicon wafer 210.

[0035] In practice, silicon wafer 210 can be placed in a tube diffusion furnace, and the temperature of the tube diffusion furnace can be raised to about 900℃-1000℃. An oxygen source (such as oxygen) and a phosphorus source (such as phosphorus oxychloride) can be introduced into the tube diffusion furnace to perform double-sided phosphorus diffusion on silicon wafer 210. The diffusion time can be controlled to about 30 minutes (starting from the moment the gas source is introduced). Impurities in silicon wafer 210 move from the inside to the surface and form a phosphorus diffusion layer 220 on the surface of silicon wafer 210.

[0036] It is understandable that by using double-sided phosphorus diffusion, impurities in silicon wafer 210 can be moved from the inside to the surface, making it easier to remove impurities through subsequent cleaning, which is beneficial to improving the photoelectric performance of silicon wafer 210.

[0037] In this embodiment, after the double-sided phosphorus diffusion is completed, the phosphorus diffusion layer 220 refers to the layered structure in which the phosphorus diffusion layer 220 is formed on both the first surface S1 and the second surface S2 of the silicon wafer 210.

[0038] In some embodiments, the phosphorus diffusion layer 220 includes a heavily doped layer close to the silicon wafer and a phosphosilicate glass (PSG) layer located on the side of the heavily doped layer away from the silicon wafer 210.

[0039] The thickness of the phosphosilicate glass layer is 50nm-100nm.

[0040] For example, the thickness of the phosphosilicate glass layer can be 50nm, 60nm, 70nm, 80nm, 90nm or 100nm.

[0041] In practice, the thickness of the phosphosilicate glass layer can be controlled by adjusting the parameters of the diffusion process, such as diffusion temperature, diffusion time, and gas flow rate.

[0042] Understandably, the heavily doped layer is formed by phosphorus atoms entering the lattice of silicon wafer 210, belonging to the silicon substrate modification region, and can also be called n. ++The silicon layer is a heavy phosphorus-doped layer; the phosphorus-silicon glass layer is an amorphous silicon oxide glass phase formed on the surface of silicon wafer 210, which contains phosphorus atoms.

[0043] Step 130: Remove the phosphorus diffusion layer 220 located on the first surface S1.

[0044] In this step, the phosphorus diffusion layer 220 located on the first surface S1 is removed to expose the first surface S1, while the phosphorus diffusion layer 220 located on the second surface S2 is retained.

[0045] In practice, the phosphorus diffusion layer 220 on the first surface S1 can be removed by chemical etching, mechanical grinding or chemical mechanical polishing, or by using an etching slurry for single-sided treatment, which can remove the phosphorus diffusion layer 220 on the first surface S1 without damaging (or excessively damaging) the phosphorus diffusion layer 220 on the second surface S2.

[0046] For example, a standard wet chemical cleaning process (RCA) is used, with hydrofluoric acid (HF) and a chain cleaning machine to remove the phosphorus diffusion layer 220 on the first surface S1. At the same time, a water film is covered on the side of the silicon wafer 210 where the second surface S1 is located to protect the phosphorus diffusion layer 220 on the second surface S1.

[0047] Step 140: Place the silicon wafer 210 in a texturing tank and use a texturing reagent to texturize the silicon wafer 210 to form a textured structure on the first surface S1 and the second surface S2.

[0048] The textured surface of the first surface S1 has a larger textured surface size than that of the second surface S2.

[0049] It is understandable that texturing refers to the process of treating the surface of silicon wafer 210 to form a light-trapping structure with a specific microstructure on the surface of silicon wafer 210. The texturing structure refers to the microstructure with anti-reflection and light-trapping functions formed on the first surface S1 and the second surface S2 after texturing. The texturing of the first surface S1 and the second surface S2 can cause the incident light to be reflected and refracted multiple times on the surface, increasing the optical path of the light in silicon wafer 210, thereby improving the light absorption efficiency and photoelectric conversion efficiency of silicon wafer 210.

[0050] Among them, the textured surface structure size is a parameter used to characterize the geometric size of the textured surface microstructure unit.

[0051] In practice, microscopic images of the textured surface are obtained using methods such as scanning electron microscopy (SEM), and the dimensions of the textured surface are measured.

[0052] In some embodiments, the suede structure includes a pyramid structure, and the dimensions of the suede structure include the base dimensions of the pyramid structure.

[0053] It should be noted that the larger the base size, the greater the surface roughness; the smaller the base size, the denser the pyramid arrangement, and the more significant the reflection and refraction effects on incident light.

[0054] In practice, one or more pyramid structural units can be selected from the microscopic image (top view), and the diagonal length of the base of the selected pyramid can be measured as the base dimension of the pyramid structure.

[0055] In some embodiments, the flocking process is carried out using a wet trough process.

[0056] In this embodiment, the wet tank process involves immersing the silicon wafer 210 in a texturing tank containing a texturing reagent. By utilizing the chemical reaction between the texturing reagent and the silicon wafer 210, a textured surface can be formed on the surface of the silicon wafer 210. The wet tank process has low equipment cost, high production capacity, and good process uniformity.

[0057] In practice, different texturing reagents can be selected for the wet cell process depending on the material of the silicon wafer 210.

[0058] For example, for monocrystalline silicon wafers, an alkaline solution containing potassium hydroxide or sodium hydroxide can be used, along with texturing additives, to control the nucleation and growth of pyramidal morphology.

[0059] For example, for polycrystalline silicon wafers, isotropic etching can be performed using an acid solution containing hydrofluoric acid and nitric acid.

[0060] Understandably, in the alkaline texturing process, different crystal orientations on the surface of silicon wafer 210 are etched at different rates, exposing specific crystal faces and naturally forming a regular square pyramid shape composed of four bevels, that is, a pyramid structure.

[0061] It is understandable that the specific numerical range of the textured structure size of the first surface S1 and the textured structure size of the second surface S2 can be determined according to the optical and electrical design requirements of the silicon wafer 210, as long as the condition that the textured structure size of the first surface S1 is greater than the textured structure size of the second surface S2 is met.

[0062] In this step, after removing the phosphorus diffusion layer 220 from the first surface S1, texturing is performed on both the first and second surfaces S2. With the phosphorus diffusion layer 220 removed, the texturing agent reacts directly with the first surface S1, forming a textured surface structure. The second surface S2 is still covered by the phosphorus diffusion layer 220, which only reacts with the second surface S2 after being removed in a subsequent process. In other words, texturing is performed on both the first and second surfaces S1 while the phosphorus diffusion layer 220 is removed, resulting in differentiated textures on the first and second surfaces S1. The first surface S1 has a larger textured structure size and a larger surface area. When the larger textured surface S1 is used as the backlight surface of the solar cell, it can achieve higher quality contact and passivation with the electrodes. Conversely, the smaller textured surface S2 has lower reflectivity, providing better light trapping when used as the light-receiving surface of the solar cell, thus increasing the solar cell's ability to capture and absorb incident light.

[0063] The following is a specific example.

[0064] The silicon wafer 210 is an N-type monocrystalline silicon wafer with a thickness of 80μm-120μm. It is polished to remove organic matter, metal impurities and surface damage layers from the silicon wafer surface, achieving a polished state on both sides of the silicon wafer 210.

[0065] A phosphorus diffusion process is performed on silicon wafer 210 using a tube diffusion furnace, thereby forming a phosphorus diffusion layer 220 on both sides (first surface S1 and second surface S2) of silicon wafer 210, resulting in... Figure 2 The structure shown.

[0066] A chain cleaning process is used to remove the phosphorus diffusion layer 220 on the first surface S1 of the silicon wafer 210 using hydrofluoric acid. A water film on the second surface S2 protects the phosphorus diffusion layer 220 from damage, resulting in the desired product. Figure 3 The structure shown.

[0067] The silicon wafer 210 is placed in a texturing tank for texturing, thereby forming differentiated textured surfaces on the first surface S1 and the second surface S2. The texturing reagent can react immediately with the first surface S1, while the second surface S2 is still covered by the phosphorus diffusion layer 220. After texturing is completed, the desired texture is obtained as shown below. Figure 5 In the structure shown, R1 represents the textured structure dimension of the first surface S1, and R2 represents the textured structure dimension of the second surface S2. The microstructure of the textured structure on the first surface S1 and the second surface S2 of silicon wafer 210 is shown below. Figure 6-7 As shown, where, Figure 6 The first surface S1 has a larger velvet structure size. Figure 7 The second surface S2 has a smaller size than the velvety structure.

[0068] In related technologies, silicon wafers are first texturized once, then a mask is prepared on one side as a protective layer, and then a second texturization is performed to achieve differentiated texturized surfaces on the front and back sides. This process is costly and complex.

[0069] In this embodiment, the silicon wafer 210 is first subjected to double-sided phosphorus diffusion to form a phosphorus diffusion layer 220 on the first surface S1 and the second surface S2 of the silicon wafer 210. After the phosphorus diffusion layer 220 on the first surface S1 is removed on one side, the remaining phosphorus diffusion layer 220 on the second surface S2 can be directly used as a mask for the second surface S2 in the texturing process, without the need to prepare a separate mask. When texturing the first surface S1 and the second surface S2, the phosphorus diffusion layer 220 on the first surface S1 is removed, and the texturing reagent can react with the first surface S1 immediately. However, the second surface S2 is still covered by the phosphorus diffusion layer 220, and the texturing reagent will react with the phosphorus diffusion layer 220 first. It will only react with the second surface S2 after the phosphorus diffusion layer 220 is removed by subsequent processes, thereby forming a differentiated textured surface on the first surface S1 and the second surface S2.

[0070] After texturing, the first surface S1 has a larger textured structure size and surface area compared to the second surface S2. This allows it to serve as the back surface of the solar cell, achieving higher quality contact and passivation with the electrodes. Furthermore, the larger textured structure size provides better growth space for the transparent conductive film layer, resulting in high carrier mobility and transmittance in the transparent conductive film layer formed on the second surface S2. Conversely, the smaller textured structure of the second surface S2 results in lower reflectivity, making it suitable as the light-receiving surface of the solar cell. This provides better light-trapping performance, increasing the solar cell's ability to capture and absorb incident light. The resulting solar cell exhibits a differentiated double-sided textured structure, high electrode contact quality, and excellent photoelectric performance. Moreover, by using the phosphorus diffusion layer 220 formed on the silicon wafer 210 after double-sided phosphorus diffusion as a mask, the differentiated double-sided textured surface can be obtained without the need for a separate mask, resulting in low manufacturing costs and a simple process.

[0071] According to the method for preparing a textured silicon wafer structure provided in this application, after performing double-sided phosphorus diffusion on the silicon wafer 210, the phosphorus diffusion layer 220 on the first surface S1 is removed, and the phosphorus diffusion layer 220 on the remaining second surface S2 is used as a mask to texture the silicon wafer 210, thereby forming a differentiated textured surface on the first surface S1 and the second surface S2. The first surface S1, with a larger textured surface size, can serve as a backlight surface, forming a higher quality contact and passivation effect with the electrode. The second surface S2, with a smaller textured surface size, can serve as a light-receiving surface, increasing the solar cell's ability to capture and absorb incident light. This method simplifies the texturing process of the silicon wafer 210, reduces manufacturing costs, significantly optimizes the contact performance of the obtained textured surface structure, and helps to improve the photoelectric performance of the cell prepared from the silicon wafer 210.

[0072] In some embodiments, step 140, placing the silicon wafer 210 in a texturing tank and texturing the silicon wafer 210 using a texturing reagent, may include: The silicon wafer 210 is placed in the texturing tank, and the silicon wafer 210 is texturized for the first time using the first texturing reagent to form an intermediate texturing structure on the first surface S1. After the first texturing is completed, the phosphorus diffusion layer 220 on the second surface S2 is removed; The silicon wafer 210 is placed in a texturing tank, and the silicon wafer 210 is texturized a second time using a second texturing reagent to form a textured surface structure located on the first surface S1 and the second surface S2.

[0073] In this embodiment, texturing the first surface S1 and the second surface S2 can be performed using a step-by-step texturing process. That is, the first surface S1 is first texturized (single-sided texturing) using a first texturing reagent, and after removing the phosphorus diffusion layer 220 of the second surface S2, the first surface S1 and the second surface S2 are then texturized (double-sided texturing) using a second texturing reagent.

[0074] In the first texturing process, the phosphorus diffusion layer 220 on the first surface S1 has been removed, and the texturing reagent will react directly with the first surface S1, thereby forming an intermediate texturing structure on the first surface S1. The second surface S2 is covered with the phosphorus diffusion layer 220. Under the action of the phosphorus diffusion layer 220, the second surface S2 is not corroded or damaged by the first texturing reagent, and a texturing structure will not be formed on the second surface S2.

[0075] After the first texturing is completed, hydrofluoric acid (HF) can be used to remove the phosphorus diffusion layer 220 on the second surface S2 without damaging the intermediate texturing structure of the first surface S1.

[0076] During the second texturing process, the first surface S1 continues to be etched by the second texturing reagent on top of the existing intermediate texturing structure, and the size of the texturing structure continues to increase. Meanwhile, the phosphorus diffusion layer 220 of the second surface S2 is completely removed. The second surface S2 reacts with the second texturing reagent to form a texturing surface. The size of the texturing structure formed by the second surface S2 is smaller than that of the texturing structure of the first surface S1, resulting in the following... Figure 5 The structure shown enables the preparation of a differentiated textured surface on the first surface S1 and the second surface S2.

[0077] In actual implementation, when silicon wafer 210 is placed in the texturing tank for texturing, silicon wafer 210 is completely immersed in the texturing reagent. The second texturing can be carried out in the same texturing tank as the first texturing, or it can be carried out in a new texturing tank. The specific method can be determined according to the production line configuration and process requirements.

[0078] In this embodiment, by dividing the texturing process into two stages, namely the first texturing and the second texturing, the differential morphology of the first surface S1 and the second surface S2 can be controlled more precisely, thereby improving the texture quality of the first surface S1 and the second surface S2, and thus improving the light absorption efficiency of the solar cell and the contact quality with the electrode.

[0079] In some embodiments, both the first texturing reagent and the second texturing reagent include an alkaline solution and a texturing additive, wherein the alkaline concentration of the second texturing reagent is less than that of the first texturing reagent.

[0080] In this embodiment, the first texturing operation is performed using a first texturing reagent with a high alkali concentration. This high corrosion rate quickly forms a large-sized pyramid shape (i.e., a textured surface structure in the middle) on the first surface S1, which helps to shorten the overall process time. The second texturing operation is performed using a second texturing reagent with a lower alkali concentration. This reduces the corrosion rate, thereby modifying and refining the textured surface of the first surface S1. This makes the pyramid shape of the first surface S1 more uniform and larger. Furthermore, the lower corrosion rate also helps to form a smaller, more uniform, and denser pyramid structure on the second surface S2.

[0081] In some embodiments, the intermediate velvet structure includes a pyramid structure, wherein the base size of the intermediate velvet structure is less than 4 μm.

[0082] In this embodiment, the size of the tower base of the intermediate flocked structure is controlled below 4μm after the first flocking, which can effectively limit the structural splitting on the original tower base during the subsequent second flocking and significantly improve the flocking effect.

[0083] In some embodiments, the alkali concentration of the first texturing reagent is 0.05%-0.1%; And / or, the processing time for the first fabrication is 300s-500s; And / or, the reagent temperature for the first texturing is 70℃-80℃.

[0084] In this embodiment, the alkali concentration of the first texturing reagent can be any value between 0.05% and 0.1%, the processing time of the first texturing can be any value between 300s and 500s, and the reagent temperature of the first texturing can be any value between 70℃ and 80℃.

[0085] For example, the alkali concentration of the first texturing reagent is 0.05%, 0.075%, or 0.1%, the processing time of the first texturing is 300s, 350s, 400s, 450s, or 500s, and the reagent temperature of the first texturing is 70℃, 75℃, or 80℃.

[0086] In this embodiment, by adjusting parameters such as alkali concentration, texturing process time, and texturing process temperature, the morphology and size of the intermediate texturing structure formed on the first surface S1 can be precisely controlled, and the base size of the intermediate texturing structure can be controlled to below 4μm.

[0087] In some embodiments, the alkali concentration of the second texturing reagent is 0.01%-0.03%; And / or, the second texturing process takes 150s-300s; And / or, the reagent temperature for the second texturing is 60℃-80℃.

[0088] In this embodiment, the alkali concentration of the second texturing reagent can be any value between 0.01% and 0.03%, the processing time of the second texturing can be any value between 150s and 300s, and the reagent temperature of the second texturing can be any value between 60℃ and 80℃.

[0089] For example, the alkali concentration of the second texturing reagent is 0.01%, 0.02%, or 0.03%, the processing time of the second texturing is 150s, 200s, 250s, or 300s, and the reagent temperature of the first texturing is 60℃, 70℃, or 80℃.

[0090] In this embodiment, by adjusting parameters such as alkali concentration, texturing process time, and texturing process temperature, the morphology and size of the texturing structure formed by the first surface S1 and the second surface S2 can be precisely controlled.

[0091] In practice, while reducing the alkali concentration, the second texturing process can be extended to allow the second surface S2 to form a more complete texturing structure.

[0092] It should be noted that the alkali concentration of the texturing reagent can refer to the mass ratio of alkali in the texturing reagent. For example, a 0.1% concentration corresponds to 1g of alkali in 1000g of texturing solvent. For example, a texturing surface morphology obtained with an alkali concentration of 0.05% is as follows: Figure 8 As shown, the morphology of the napped surface obtained with an alkali concentration of 0.01% is as follows. Figure 9 As shown, the corrosion rate is fast at higher alkali concentrations, resulting in larger pyramid sizes. Using a higher alkali concentration in the first texturing process can provide a higher corrosion rate, quickly forming a large pyramid shape on the first surface S1 and thinning the phosphorus diffusion layer 220 on the second surface S2.

[0093] In practice, the concentration of additives in the texturing reagent can be adjusted to optimize the morphology and size of the texturing structure.

[0094] In some embodiments, the additive concentration of the second texturing agent is greater than the additive concentration of the first texturing agent.

[0095] Among them, the additives can be auxiliary components in the texturing reagent used to control the micromorphology of the textured surface. The additives can be selectively adsorbed on specific crystal faces on the surface of silicon wafer 210, changing the relative corrosion rate of each crystal face, thereby affecting the nucleation density, growth rate, morphology and size of the textured pyramid.

[0096] In practice, a higher additive concentration results in a suede morphology such as... Figure 10 As shown, the morphology of the napped surface obtained with a lower additive concentration is as follows: Figure 11 As shown, an appropriate concentration of additives can promote nucleation and make the pyramid more uniform.

[0097] In this embodiment, the additive concentration of the second texturing reagent used in the second texturing process is greater than the additive concentration of the first texturing reagent used in the first texturing process. This can improve the uniformity and density of the textured surface of the second surface S2, thereby enhancing the light-trapping capability of the solar cell's light-receiving surface.

[0098] In some embodiments, the textured structure of the first surface S1 includes a pyramid structure, wherein the base size of the textured structure of the first surface S1 is 4μm-5μm. The textured structure of the second surface S2 includes a pyramid structure, and the base size of the textured structure of the second surface S2 is 1μm-3μm.

[0099] In this embodiment, the base size of the first surface S1 is 4μm-5μm, and the large pyramid structure of the textured surface allows the first surface S1 to have a larger surface area. When the first surface S1 is used as the backlight surface of the solar cell, the larger surface area can effectively reduce the contact resistance between the first surface S1 and the electrode, and provide more passivation points, which can effectively improve the contact quality and passivation effect.

[0100] The base size of the second surface S2 is 1μm-3μm. The small pyramid structure of the textured surface allows the incident light to undergo more reflections and refractions between the pyramids, reducing the surface's light reflectivity. When the second surface S2 serves as the light-receiving surface of the solar cell, it can effectively improve the light absorption efficiency and short-circuit current of the solar cell.

[0101] It should be noted that the base size of the first surface S1 is 4μm-5μm and the base size of the second surface S2 is 1μm-3μm. This means that the statistical average or typical value of the base size of the first surface S1 and the second surface S2 falls within the corresponding range. In actual measurement, the base size of a single pyramid may be affected by factors such as crystal defects and differences in local reaction rates, and there may be a certain distribution range. It may be outside the corresponding range. As long as the average base size of the first surface S1 and the second surface S2 is within the corresponding range, it is acceptable.

[0102] The technical effects achievable by the method for preparing the textured silicon wafer structure in this application will be described below through specific embodiments and comparative examples. It should be noted that these embodiments and comparative examples are for illustrative purposes only and do not constitute any limitation on the scope of protection of this application.

[0103] The comparative preparation process is as follows: S1.1 Select an N-type single crystal silicon wafer with a thickness of 80μm-120μm, and remove organic matter, metal impurities and surface damage layer from the silicon wafer surface by polishing to achieve a double-sided polished state.

[0104] S1.2. The silicon wafer is placed in a texturing tank for texturing. The texturing reagent includes KOH solution and texturing additives. The texturing temperature is 70℃-80℃, the texturing time is 350s-500s, the alkali concentration is 0.05%-0.1%, and the additive dosage is 1L-1.5L. This forms a texturing layer on both sides of the silicon wafer. Figure 12 The velvet surface shown.

[0105] S1.3. The amorphous silicon layer and the doped microcrystalline silicon thin film layer on both sides of the silicon wafer are grown by plasma enhanced chemical vapor deposition (PECVD) process, and the transparent conductive film (TCO) on both sides is fabricated by atmospheric pressure chemical vapor deposition (APCVD) magnetron sputtering process.

[0106] S1.4. Screen printing is performed on both transparent conductive film layers, and low-temperature curing is completed at around 200℃ to finally form electrode contacts.

[0107] In this comparative example, the size difference between the two textured surfaces of the silicon wafer is small. The solar cell prepared from this silicon wafer has a photoelectric conversion efficiency of 27.23%, an open-circuit voltage of 750.5mV, a short-circuit current of 8.120mA, and a sheet resistance of 1.48mΩ.

[0108] The preparation process for the example is as follows: S2.1. Select an N-type monocrystalline silicon wafer as silicon wafer 210 with a thickness of 80μm-120μm, and remove organic matter, metal impurities and surface damage layer from the silicon wafer surface by polishing to achieve a polished state on both sides of silicon wafer 210.

[0109] S2.2, The silicon wafer 210 is subjected to double-sided phosphorus diffusion in a tube diffusion furnace, thereby forming a phosphorus diffusion layer 220 on both sides (first surface S1 and second surface S2) of the silicon wafer 210, resulting in the following: Figure 2 In the structure shown, the thickness of the PSG layer in the phosphorus diffusion layer 220 is controlled between 50 nm and 100 nm.

[0110] S2.3. A chain cleaning machine is used to remove the phosphorus diffusion layer 220 on the first surface S1 of the silicon wafer 210 using hydrofluoric acid. A water film on the second surface S2 protects the phosphorus diffusion layer 220 from damage, resulting in the following... Figure 3 The structure shown.

[0111] S2.4. The silicon wafer 210 is placed in a texturing tank for the first texturing process. The texturing reagent includes KOH solution and texturing additives. The texturing temperature is 70℃-80℃, the texturing time is 300s-500s, the alkali concentration is 0.05%-0.1%, and the additive dosage is 0.5L-1L. Under the action of the texturing reagent, the first surface S1 of the silicon wafer 210 forms an intermediate texturized structure, while the second surface S2 is protected from alkali corrosion by the phosphorus diffusion layer 220, resulting in the following... Figure 4 The structure shown is such that, after texturing, the remaining phosphorus diffusion layer 220 on the second surface S2 is removed by hydrofluoric acid.

[0112] S2.5. The silicon wafer 210 is placed in a texturing tank for a second texturing process. The texturing reagent includes KOH solution and texturing additives. The temperature is 60℃-80℃, the texturing time is 150s-300s, the alkali concentration is 0.01%-0.03%, and the additive dosage is 1L-3L. The first surface S1 of the silicon wafer 210 is further enlarged, resulting in the following... Figure 5 The differentiated morphological structure shown has the following microstructure: the microstructure of the first surface S1 is as follows. Figure 6 As shown, the microstructure of the second surface S2 is as follows Figure 7 As shown.

[0113] S2.6. The amorphous silicon layer and the doped microcrystalline silicon thin film layer on both sides of the silicon wafer 210 are grown by plasma enhanced chemical vapor deposition (PECVD) process, and the transparent conductive film layer on both sides is fabricated by atmospheric pressure chemical vapor deposition (APCVD) magnetron sputtering process.

[0114] S2.7. Screen printing is performed on both transparent conductive film layers, and low-temperature curing is completed at around 200℃ to finally form electrode contacts.

[0115] In this embodiment, the silicon wafer 210 has a differentiated textured surface structure on both sides. The solar cell prepared from the silicon wafer 210 has a photoelectric conversion efficiency of 27.37%, an open circuit voltage of 750.8mV, a short circuit current of 8.145mA, and a sheet resistance of 1.00mΩ.

[0116] In this embodiment, the battery efficiency of the embodiment is improved by 0.14% compared with the comparative example. Compared with the reflectivity of conventional symmetrical textured surfaces of 11%-12%, the reflectivity of both the front and back sides of the differentiated structure is less than 11%, which can improve the short-circuit current of the solar cell.

[0117] Furthermore, the large textured surface structure of the solar cell back surface, with a size of 4μm-5μm, provides better contact than the approximately 2μm structure in related technologies. It also has a larger contact area with the passivation layer, transparent conductive film layer, and electrodes formed by subsequent processes, resulting in a more significant advantage in contact.

[0118] In addition, the back surface of the solar cell, i.e. the first surface S1, adopts a step-by-step texturing process, which increases the nucleation density of the pyramids, making the pyramid structure more dense and the size more uniform, with a low carrier recombination rate, which is superior to the texturing structure formed by the one-step texturing method.

[0119] This application also provides a silicon wafer 210.

[0120] The silicon wafer 210 has a first surface S1 and a second surface S2 disposed opposite to each other, wherein the textured structure size of the first surface S1 is larger than the textured structure size of the second surface S2. The textured surface structure of the first surface S1 and the second surface S2 is formed through the following steps: Double-sided phosphorus diffusion is performed on the silicon wafer 210 to be texturized to form a phosphorus diffusion layer 220 located on the first surface S1 and the second surface S2. Remove the phosphorus diffusion layer 220 from the first surface S1; The silicon wafer 210 is placed in a texturing tank, and a texturing reagent is used to texturize the silicon wafer 210 to form a textured surface structure on the first surface S1 and the second surface S2.

[0121] It should be noted that the silicon wafer 210 in this application embodiment includes, but is not limited to, half wafers obtained by dicing, three-part wafers obtained by dicing, and whole wafers that are not diced.

[0122] According to the silicon wafer 210 provided in this application, after performing double-sided phosphorus diffusion on the silicon wafer 210, the phosphorus diffusion layer 220 on the first surface S1 is removed, and the phosphorus diffusion layer 220 on the remaining second surface S2 is used as a mask to texturize the silicon wafer 210, thereby forming differentiated textured surfaces on the first surface S1 and the second surface S2. The first surface S1 with a larger textured surface structure can serve as a backlight surface, forming a higher quality contact and passivation effect with the electrode. The second surface S2 with a smaller textured surface structure can serve as a light-receiving surface, increasing the solar cell's ability to capture and absorb incident light. This simplifies the texturing process of the silicon wafer 210, reduces manufacturing costs, significantly optimizes the contact performance of the obtained textured surface structure, and helps to improve the photoelectric performance of the cell prepared from the silicon wafer 210.

[0123] It should be noted that the silicon wafer 210 with a differentiated textured surface provided in this application embodiment can be prepared by the above-described method for preparing a textured silicon wafer.

[0124] This application also provides a solar cell, including the silicon wafer 210 as described above.

[0125] According to the solar cell provided in this application, after performing double-sided phosphorus diffusion on the silicon wafer 210, the phosphorus diffusion layer 220 on the first surface S1 is removed, and the phosphorus diffusion layer 220 on the remaining second surface S2 is used as a mask to texturize the silicon wafer 210, thereby forming differentiated textured surfaces on the first surface S1 and the second surface S2. The first surface S1, with a larger textured surface structure size, can serve as a backlight surface, forming a higher quality contact and passivation effect with the electrode. The second surface S2, with a smaller textured surface structure size, can serve as a light-receiving surface, increasing the solar cell's ability to capture and absorb incident light. This simplifies the texturing process of the silicon wafer 210, reduces manufacturing costs, significantly optimizes the contact performance of the obtained textured surface structure, and helps to improve the photoelectric performance of the solar cell.

[0126] In some embodiments, the textured structure of the first surface S1 includes a pyramid structure, and the base size of the textured structure of the first surface S1 is 4μm-5μm; the textured structure of the second surface S2 includes a pyramid structure, and the base size of the textured structure of the second surface S2 is 1μm-3μm.

[0127] In this embodiment, the base size of the first surface S1 is 4μm-5μm, and the large pyramid structure of the textured surface allows the first surface S1 to have a larger surface area. When the first surface S1 is used as the backlight surface of the solar cell, the larger surface area can effectively reduce the contact resistance between the first surface S1 and the electrode, and provide more passivation points, which can effectively improve the contact quality and passivation effect.

[0128] The base size of the second surface S2 is 1μm-3μm. The small pyramid structure of the textured surface allows the incident light to undergo more reflections and refractions between the pyramids, reducing the surface's light reflectivity. When the second surface S2 serves as the light-receiving surface of the solar cell, it can effectively improve the light absorption efficiency and short-circuit current of the solar cell.

[0129] It should be noted that the base size of the first surface S1 is 4μm-5μm and the base size of the second surface S2 is 1μm-3μm. This means that the statistical average or typical value of the base size of the first surface S1 and the second surface S2 falls within the corresponding range. In actual measurement, the base size of a single pyramid may be affected by factors such as crystal defects and differences in local reaction rates, and there may be a certain distribution range. It may be outside the corresponding range. As long as the average base size of the first surface S1 and the second surface S2 is within the corresponding range, it is acceptable.

[0130] In some embodiments, the solar cell further includes a first transparent conductive film layer 330 located on one side of the first surface S1, the thickness of the first transparent conductive film layer 330 being 100nm-110nm.

[0131] For example, the thickness of the first transparent conductive film layer 330 can be 100 nm, 105 nm or 110 nm.

[0132] In related technologies, the thickness of the transparent conductive film layer on the backlight surface is 110nm-120nm, the sheet resistance is 30Ω / sq-35Ω / sq, and the mobility is 50cm. 2 V -1 s -1 -65cm 2 V -1 s -1 In this embodiment, the thickness of the first transparent conductive film layer 330 grown on the textured surface of the first surface S1 is 100nm-110nm (thinned by about 10nm), the sheet resistance is 28Ω / sq-32Ω / sq, and the mobility is 55cm. 2 V - 1 s -1 -65cm 2 V -1 s -1 .

[0133] The first transparent conductive film layer 330 is a transparent conductive film layer grown on the textured surface of the first surface S1. The grain mobility and light transmittance are significantly improved, which is conducive to reducing the thickness of the transparent conductive film layer. The thickness of the first transparent conductive film layer 330 can be controlled between 100nm and 110nm. Without affecting the battery efficiency, the consumption of target materials is reduced, thus reducing manufacturing costs.

[0134] In some embodiments, the solar cell is a heterojunction cell or a passivated emitter-back cell.

[0135] In this embodiment, the solar cell is suitable for heterojunction cells (HJT), passivated emitter back cells (PERC), or other cells with double-sided textured surfaces. The large textured surface of the first surface S1, i.e. the backlight surface, can form a higher quality contact and passivation effect with the electrode. The small textured surface of the second surface S2, i.e. the light-receiving surface, can increase the solar cell's ability to capture and absorb incident light.

[0136] In some embodiments, a first intrinsic amorphous silicon layer 310, a first doped crystalline silicon layer 320 and a first transparent conductive film layer 330 are sequentially stacked on the first surface S1 along the direction away from the silicon wafer; a second intrinsic amorphous silicon layer 410, a second doped crystalline silicon layer 420 and a second transparent conductive film layer 430 are sequentially stacked on the second surface S2 along the direction away from the silicon wafer.

[0137] like Figure 13 As shown, the solar cell includes a silicon wafer 210, a first intrinsic amorphous silicon layer 310, a first doped crystalline silicon layer 320, a first transparent conductive film layer 330, a second intrinsic amorphous silicon layer 410, a second doped crystalline silicon layer 420, and a second transparent conductive film layer 430. The first surface S1 is stacked sequentially with the first intrinsic amorphous silicon layer 310, the first doped crystalline silicon layer 320 (e.g., doped amorphous silicon layer or doped microcrystalline silicon layer) and the first transparent conductive film layer 330 along the direction away from the silicon wafer. The second surface S2 of the silicon wafer 210 is stacked sequentially with the second intrinsic amorphous silicon layer 410, the second doped crystalline silicon layer 420 (e.g., doped amorphous silicon layer or doped microcrystalline silicon layer) and the second transparent conductive film layer 430 along the direction away from the silicon wafer. The solar cell is a heterojunction cell.

[0138] Understandably, the first intrinsic amorphous silicon layer 310 and the second intrinsic amorphous silicon layer 410 can be used to passivate the surface of the silicon wafer 210, the first doped crystalline silicon layer 320 and the second doped crystalline silicon layer 420 can be used to form the emitter or back field, and the first transparent conductive film layer 330 and the second transparent conductive film layer 430 can be used to collect and transport charge carriers. The specific materials, thicknesses and doping concentrations of these layered structures can be selected and adjusted according to the battery performance requirements.

[0139] It should be noted that after removing the phosphorus diffusion layer 220 on the first surface S1 of the silicon wafer 210 by double-sided phosphorus diffusion, the silicon wafer 210 is placed in a texturing tank for the first texturing to form an intermediate texturized structure. Then, the phosphorus diffusion layer 220 on the second surface S2 is removed, and the silicon wafer 210 is placed in a texturing tank for the second texturing. The temperature of the two texturing processes is controlled below 80°C to meet the requirements of heterojunction solar cell fabrication with a lower process temperature.

[0140] This application also provides a photovoltaic module, which includes at least one solar cell as described above.

[0141] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular often have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0142] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0143] In the description of this application, it should be understood that the terms "length", "width", "thickness", "upper", "lower", "horizontal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0144] In the description of this application, "first feature" and "second feature" may include one or more of the features.

[0145] In the description of this application, "multiple" means two or more.

[0146] In the description of this application, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or it may include the first and second features not being in direct contact but being in contact through another feature between them.

[0147] In the description of this application, the terms "above," "over," and "on top" for the first feature and the second feature include the first feature being directly above or diagonally above the second feature, or simply indicate that the first feature is at a higher horizontal level than the second feature.

[0148] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0149] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0150] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0151] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0152] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for preparing a textured silicon wafer structure, characterized in that, include: A silicon wafer to be texturized is provided, the silicon wafer having a first surface and a second surface disposed opposite to each other; The silicon wafer is subjected to double-sided phosphorus diffusion to form a phosphorus diffusion layer located on the first surface and the second surface; Remove the phosphorus diffusion layer from the first surface; The silicon wafer is placed in a texturing tank, and a texturing reagent is used to texturize the silicon wafer to form a texturized structure on the first surface and the second surface, wherein the size of the texturized structure on the first surface is larger than the size of the texturized structure on the second surface.

2. The method for preparing a textured silicon wafer structure according to claim 1, characterized in that, The step of placing the silicon wafer in a texturing tank and texturing the silicon wafer using a texturing reagent includes: The silicon wafer is placed in a texturing tank, and the silicon wafer is texturized for the first time using a first texturing reagent to form an intermediate texturing structure on the first surface. After the first texturing is completed, the phosphorus diffusion layer on the second surface is removed; The silicon wafer is placed in a texturing tank, and a second texturing agent is used to perform a second texturing process on the silicon wafer to form a texturized structure on the first surface and the second surface.

3. The method for preparing a textured silicon wafer structure according to claim 2, characterized in that, Both the first texturing reagent and the second texturing reagent include an alkaline solution and a texturing additive, and the alkaline concentration of the second texturing reagent is less than that of the first texturing reagent.

4. The method for preparing a textured silicon wafer structure according to claim 3, characterized in that, The intermediate velvet structure includes a pyramid structure, and the base size of the intermediate velvet structure is less than 4μm.

5. The method for preparing a textured silicon wafer structure according to claim 4, characterized in that, The alkali concentration of the first texturing reagent is 0.05%-0.01%; And / or, the processing time for the first texturing step is 300s-500s; And / or, the reagent temperature for the first texturing process is 70℃-80℃.

6. The method for preparing a textured silicon wafer structure according to claim 4, characterized in that, The alkali concentration of the second texturing reagent is 0.009%-0.03%; And / or, the processing time for the second texturing is 150s-300s; And / or, the reagent temperature for the second texturing process is 60℃-80℃.

7. The method for preparing a textured silicon wafer structure according to any one of claims 1-6, characterized in that, The textured structure of the first surface includes a pyramid structure, and the base size of the textured structure of the first surface is 4μm-5μm; The textured structure of the second surface includes a pyramid structure, and the base size of the textured structure of the second surface is 1μm-3μm.

8. The method for preparing a textured silicon wafer structure according to any one of claims 1-6, characterized in that, The thickness of the silicon wafer to be texturized is 80μm-120μm.

9. The method for preparing a textured silicon wafer structure according to any one of claims 1-6, characterized in that, The phosphorus diffusion layer includes a heavily doped layer close to the silicon wafer and a phosphorus-silicon glass layer located on the side of the heavily doped layer away from the silicon wafer, wherein the thickness of the phosphorus-silicon glass layer is 50nm-100nm.

10. A silicon wafer, characterized in that, The silicon wafer has a first surface and a second surface disposed opposite to each other, wherein the textured structure size of the first surface is larger than the textured structure size of the second surface; The textured surface of the first and second surfaces is formed through the following steps: The silicon wafer to be texturized is subjected to double-sided phosphorus diffusion to form a phosphorus diffusion layer located on the first surface and the second surface; Remove the phosphorus diffusion layer from the first surface; The silicon wafer is placed in a texturing tank, and a texturing reagent is used to texturize the silicon wafer to form a texturized structure on the first surface and the second surface.

11. A solar cell, characterized in that, Including the silicon wafer as described in claim 10.

12. The solar cell according to claim 11, characterized in that, It also includes a first transparent conductive film layer located on one side of the first surface; The textured structure of the first surface includes a pyramid structure, the base size of the textured structure of the first surface is 4μm-5μm, and the thickness of the first transparent conductive film layer is 100nm-110nm.

13. The solar cell according to claim 12, characterized in that, The first surface is sequentially stacked with a first intrinsic amorphous silicon layer, a first doped crystalline silicon layer and a first transparent conductive film layer along a direction away from the silicon wafer; The second surface is sequentially stacked with a second intrinsic amorphous silicon layer, a second doped crystalline silicon layer, and a second transparent conductive film layer along a direction away from the silicon wafer.

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