Solar cell and method of manufacturing the same, photovoltaic module

Abstract

The application relates to the photovoltaic field, and provides a solar cell, a preparation method thereof and a photovoltaic module, and at least the photoelectric conversion efficiency of the solar cell can be improved. The solar cell comprises a substrate, a tunneling layer located on the surface of the substrate, a doped polysilicon layer located on the surface of the tunneling layer, and a P-type doping element is doped in the doped polysilicon layer, the grain size of the doped polysilicon layer ranges from 200 nm to 1000 nm, and an electrode is located on the doped polysilicon layer and is electrically connected with the doped polysilicon layer.

Description

Technical Field

[0001] This application relates to the photovoltaic field, and in particular to a solar cell, its preparation method, and a photovoltaic module. Background Technology

[0002] Currently, with the gradual depletion of fossil fuels, solar cells are becoming increasingly widely used as a new energy alternative. A solar cell is a device that converts solar energy into electrical energy. Solar cells utilize the photovoltaic principle to generate charge carriers, and then use electrodes to extract these carriers, thus facilitating the efficient use of electrical energy.

[0003] Current solar cells mainly include IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and rear cell), and heterojunction cells. Different film layer configurations and functional limitations are used to reduce optical losses and decrease photogenerated carrier recombination on and within the silicon substrate, thereby improving the photoelectric conversion efficiency of solar cells.

[0004] However, current solar cells have some problems that result in poor photoelectric conversion efficiency, such as the contact resistance between the film and the electrode paste or the integrity of the passivation layer. Summary of the Invention

[0005] This application provides a solar cell and its preparation method, as well as a photovoltaic module, which at least helps to improve the photoelectric conversion efficiency of the solar cell.

[0006] According to some embodiments of this application, one aspect of this application provides a solar cell, comprising: a substrate; a tunneling layer located on the surface of the substrate; a doped polycrystalline silicon layer located on the surface of the tunneling layer, wherein the doped polycrystalline silicon layer is doped with a p-type dopant element; the grain size of the doped polycrystalline silicon layer is in the range of 200 nm to 1000 nm; and an electrode located on the doped polycrystalline silicon layer and electrically connected to the doped polycrystalline silicon layer.

[0007] In some embodiments, the doping concentration of the doped polysilicon layer is 8E19 atoms / cm². 3 ~8E20atoms / cm 3 .

[0008] In some embodiments, the thickness of the doped polycrystalline silicon layer is 50 nm to 500 nm.

[0009] In some embodiments, the tunneling layer has pores, and the pore density is 10. 8 cm -2 ~10 10 cm -2 .

[0010] In some embodiments, the size of the hole ranges from 6 nm to 10 nm.

[0011] According to some embodiments of this application, another aspect of this application provides a method for fabricating a solar cell, comprising: providing a substrate; forming an initial tunneling layer and an initial semiconductor layer, wherein the initial tunneling layer is located on the surface of the substrate and the initial semiconductor layer is located on the surface of the initial tunneling layer; pre-treating the initial tunneling layer and the initial semiconductor layer, wherein the pre-treating transforms the initial semiconductor layer into an initial polycrystalline silicon layer, and the grain size of the initial polycrystalline silicon layer is in the range of 200 nm to 1000 nm; the pre-treating further transforms the initial tunneling layer into a tunneling layer; performing doping and annealing treatment on the initial polycrystalline silicon layer, wherein the initial polycrystalline silicon layer is transformed into a doped polycrystalline silicon layer, wherein the doped polycrystalline silicon layer is doped with a p-type dopant element; forming an electrode, wherein the electrode is located on the doped polycrystalline silicon layer and the electrode is electrically connected to the doped polycrystalline silicon layer.

[0012] In some embodiments, the preprocessing is a chain annealing process.

[0013] In some embodiments, the chain annealing process takes 5 to 60 minutes and the chain annealing process takes 850°C to 1050°C.

[0014] In some embodiments, the heating rate of the chain annealing process is greater than 50°C / min; the cooling rate of the chain annealing process is greater than 50°C / min.

[0015] In some embodiments, the second temperature of the annealing process is lower than the first temperature of the chain annealing process.

[0016] According to some embodiments of this application, another aspect of this application provides a photovoltaic module, including: a battery string, which is formed by connecting multiple solar cells as described in any one of the above embodiments, or formed by connecting multiple solar cells prepared by the method described in any one of the above embodiments; ; an encapsulating film for covering the surface of the battery string; a cover plate for covering the surface of the encapsulating film facing away from the battery string.

[0017] The technical solution provided in this application has at least the following advantages: The solar cell provided in this application includes a doped polycrystalline silicon layer, which contains P-type dopant and has a grain size ranging from 200 nm to 1000 nm, meaning its grain boundary density is significantly lower than that of microcrystalline or nanocrystalline silicon (<100 nm). Larger grains reduce dangling bonds and defect states at grain boundaries, thereby lowering the carrier recombination rate. Simultaneously, the P-type dopant can form a built-in electric field within the doped polycrystalline silicon layer, enhancing the field passivation effect, reducing interfacial recombination, and thus increasing the open-circuit voltage. Furthermore, the 200 nm to 1000 nm grain size gives the doped polycrystalline silicon layer near-single-crystal transport characteristics. Combined with the sufficient hole concentration provided by the P-type dopant, this reduces the bulk resistance of the layer, facilitating rapid lateral transport of photogenerated holes to the electrodes, reducing series resistance, and improving the fill factor.

[0018] When the grain size of polycrystalline silicon is between 200 nm and 1000 nm, its surface roughness is moderate and the number of grain boundaries is relatively small. When electrodes (such as silver, aluminum, titanium, etc.) come into contact with it, metal atoms are less likely to diffuse excessively into the tunneling layer or substrate along the grain boundaries. At the same time, larger grain surfaces can form uniform metal silicides, providing low-barrier ohmic contact paths, thereby significantly reducing contact resistance. Large grains also represent better stability, making abnormal grain growth or surface bulging less likely. During sintering, the electrode material can form a continuous and dense contact interface, avoiding electrode peeling or voids caused by excessive grain boundaries, which can improve the mechanical adhesion and long-term reliability of the electrode. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the drawings in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a solar cell provided in an embodiment of this application; Figures 2-6 This is a schematic diagram of the structure of a solar cell corresponding to each step in a method for preparing a solar cell according to another embodiment of this application; Figure 7 This is a schematic diagram of a photovoltaic module provided in another embodiment of this application. Detailed Implementation

[0021] As can be seen from the background technology, the photoelectric conversion efficiency of current solar cells is not good.

[0022] This application provides a solar cell and its preparation method, as well as a photovoltaic module. By controlling the grain size of polycrystalline silicon in the doped polycrystalline silicon layer, the contact resistivity between the polycrystalline silicon and the silver paste of the electrode is reduced, thereby reducing electrical losses and improving the photoelectric conversion efficiency of the solar cell.

[0023] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0026] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0027] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0028] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0029] In the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0030] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Moreover, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0031] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "part" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0032] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] According to some embodiments of this application, one aspect of this application provides a solar cell that improves the passivation performance of the passivation layer deposited thereon by improving the morphology of the textured structure on the substrate surface, thereby improving the photoelectric conversion efficiency of the solar cell.

[0034] refer to Figure 1 The solar cell includes: a substrate 100; a tunneling layer 111 located on the surface of the substrate 100; a doped polycrystalline silicon layer 112 located on the surface of the tunneling layer 111, the doped polycrystalline silicon layer 112 being doped with a P-type dopant element; the grain size of the doped polycrystalline silicon layer 112 being in the range of 200 nm to 1000 nm; and an electrode 110 located on the doped polycrystalline silicon layer 112, the electrode 110 being electrically connected to the doped polycrystalline silicon layer 112.

[0035] The technical solution provided in this application includes a doped polycrystalline silicon layer 112, which contains P-type dopant and has a grain size ranging from 200 nm to 1000 nm, meaning its grain boundary density is significantly lower than that of microcrystals or nanocrystals (<100 nm). Larger grains reduce dangling bonds and defect states at grain boundaries, thereby reducing carrier recombination rates. Simultaneously, P-type doping can create a built-in electric field within the polycrystalline silicon layer, enhancing the field passivation effect, reducing interfacial recombination, and thus increasing the open-circuit voltage. Furthermore, the 200 nm to 1000 nm grain size gives the polycrystalline silicon layer near-single-crystal transport characteristics. Combined with the sufficient hole concentration provided by P-type doping, this reduces the layer's bulk resistance, facilitating rapid lateral transport of photogenerated holes to the electrode 110, reducing series resistance, and improving the fill factor.

[0036] When the polycrystalline silicon grain size is 200nm~1000nm, its surface roughness is moderate and the number of grain boundaries is relatively small. When the electrode 110 (such as silver, aluminum, titanium, etc.) comes into contact with it, metal atoms are less likely to diffuse excessively into the tunneling layer 111 or the substrate along the grain boundaries. At the same time, a uniform metal silicide can be formed on the surface of larger grains, providing a low-barrier ohmic contact path, thereby significantly reducing contact resistance. Large grains also represent better stability, and are less prone to abnormal grain growth or surface bulging. The electrode 110 material can form a continuous and dense contact interface during sintering, avoiding electrode 110 peeling or voids caused by excessive grain boundaries, which can improve the mechanical adhesion and long-term reliability of the electrode 110.

[0037] The above features and the effects achieved will be described in detail below with reference to the accompanying drawings.

[0038] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material may be monocrystalline, polycrystalline, amorphous, or microcrystalline (a state simultaneously possessing both monocrystalline and amorphous states is called microcrystalline). For example, silicon may be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0039] In some embodiments, the substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium dihydrogen phosphate, perovskite, cadmium telluride, and copper indium selenide. The substrate 100 may also be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

[0040] In some embodiments, substrate 100 may be an N-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type dopant element, which may be any one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). Substrate 100 may also be a P-type semiconductor substrate. The P-type semiconductor substrate is doped with a P-type dopant element, which may be any one of group III elements such as boron (B), indium (In), or gallium (Ga).

[0041] In some embodiments, the substrate 100 includes a first surface 101 and a second surface 102.

[0042] In some embodiments, the cells used in single-glass photovoltaic modules are considered single-sided cells, in which case the first side 101 can serve as the light-receiving surface for receiving sunlight, and the second side 102 serves as the backlighting surface. In some embodiments, the cells used in double-glass or bifacial modules are considered bifacial cells, in which case both the first side 101 and the second side 102 can serve as light-receiving surfaces and can both be used to receive sunlight. It is understood that the backlighting surface referred to in the embodiments of this application can also receive sunlight, but the degree of sunlight reception is weaker than that of the light-receiving surface, and therefore it is defined as a backlighting surface.

[0043] It should be noted that, Figure 1 The side facing the top is the illuminated side, and the side facing the bottom is the shaded side. Taking the first side as the illuminated side and the second side as the shaded side as an example.

[0044] The first surface 101 of the substrate 100 has a textured surface (not shown). The textured surface can improve the internal reflectivity of incident light, thereby improving the photoelectric conversion efficiency. The textured surface may include multiple protrusions, which may be arranged adjacently or spaced apart, or stacked or partially overlapped. This application does not limit the number, arrangement, or shape of the protrusions.

[0045] In other embodiments, the second surface 102 is a polished surface. A polished surface refers to a surface that has been smoothed or has low roughness by removing the textured surface, rough layer, damaged layer, or oxide layer of the material surface through methods such as mechanical grinding, chemical polishing (e.g., acid / alkali solution etching), or chemical-mechanical polishing (CMP). Polished surfaces can optimize optical and electrical properties by improving surface smoothness.

[0046] The solar cell includes an emitter 103 located within the substrate 100 adjacent to the first surface 101.

[0047] Emitter 103 is used to generate a built-in electric field and selectively collect charge carriers. The built-in electric field drives the separation of photogenerated electron-hole pairs, with electrons moving towards the n-region (emitter 103 or base region) and holes moving towards the p-region, forming a photocurrent.

[0048] The emitter 103 is doped with a first dopant element, the doping type of which differs from that of the dopant element in the substrate 100. In one example, the substrate 100 is doped with an N-type dopant element, and the emitter 103 is doped with a P-type dopant element. In another example, the substrate 100 is doped with a P-type dopant element, and the emitter 103 is doped with an N-type dopant element.

[0049] It should be noted that the emitter 103 can be a part of the substrate 100. An original substrate is subjected to doping or diffusion treatment to convert a portion of the substrate 100 into the emitter 103, and the first surface 101 of the substrate 100 can be the surface of the emitter 103. In other embodiments, the emitter 103 can be a separate film layer, with the undoped or undiffused substrate serving as the substrate, and the emitter located on the substrate.

[0050] The tunneling layer 111 and the doped polysilicon layer 112 form a passivation contact structure. Due to the special band structure of the passivation contact structure, the doped polysilicon layer 112 and the substrate 100 are in electrical contact, causing the energy band of the substrate 100 to bend downward, which reduces the electron transport barrier. Therefore, the ultrathin tunneling layer 111 can allow majority carriers to tunnel through while blocking minority carriers from passing through, thereby separating electrons and holes, reducing recombination, and lowering the recombination rate.

[0051] In some embodiments, the thickness of the tunneling layer 111 is 0.5 nm to 2 nm. The thickness of the tunneling layer 111 can be 0.5 nm, 0.7 nm, 0.9 nm, 1.1 nm, 1.6 nm, or 2 nm. When the thickness of the tunneling layer 111 is within any of these ranges, the thickness of the tunneling layer 111 is relatively thin, allowing majority carriers to easily tunnel through the tunneling layer 111, while minority carriers have difficulty passing through it, thus achieving selective carrier transport.

[0052] In some embodiments, the material of the tunneling layer 111 includes at least one of silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0053] In some embodiments, the tunneling layer 111 has pores with a pore density of 10. 8 cm -2 ~10 10 cm -2 Thus, the number of pores in the tunneling layer 111 is moderate, allowing holes to be transported through these pores without a potential barrier, avoiding the resistance contribution of the tunneling barrier; and the density range of these pores will not have a significant impact on the integrity and passivation of the tunneling layer 111 itself, thus exhibiting good passivation properties.

[0054] The pore density of the holes can be 1×10⁻⁶. 8 cm -2 2×10 8 cm -2 5×10 8 cm -2 8×10 8 cm -2 1×10 9 cm -2 3×10 9 cm -2 5×10 9 cm -2 7×10 9 cm -2 9×10 9 cm -2 Or 10 10 cm -2 .

[0055] In some embodiments, the size of the holes ranges from 6 nm to 10 nm. The small hole size does not affect the insulation and passivation properties of the tunneling layer 111; that is, the lateral transport capability of the tunneling layer 111 is weak, and it does not form a leakage path. The hole size is smaller than the size of metal ions in the subsequent electrode 110 paste, thereby blocking metal ions from the electrode 110 paste. The hole size can be 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, or 10 nm.

[0056] It should be noted that the holes in the tunnel layer 111 can be through holes or surface-opening, internally closed / semi-connected blind holes / sponge-like holes, that is, not through holes that penetrate the entire tunnel layer 111. The lateral dimensions of the holes are not uniform and are scattered, and the depth of the holes along the vertical direction is also not uniform. That is, the embodiments of this application do not limit the size, depth, shape and distribution of the holes.

[0057] Among them, the pore size / size testing methods can include gas adsorption, mercury porosimetry, bubble pressure, scanning electron microscopy, etc.; and can be carried out using fully automated surface area and porosity analyzers or scanning electron microscopes.

[0058] In some embodiments, the dopant elements in the polysilicon layer 112 have the same conductivity type as the dopant elements in the substrate 100. For example, the substrate 100 has N-type dopant elements, and the polysilicon layer 112 has N-type dopant elements; or the substrate 100 has P-type dopant elements, and the polysilicon layer 112 has P-type dopant elements. In this way, the polysilicon layer 112 and the substrate 100 have dopant elements of the same conductivity type. By setting the concentration of dopant elements in the polysilicon layer 112 to be greater than the concentration of dopant elements in the substrate 100, a high-low junction is formed between the substrate 100 and the polysilicon layer 112. Under the action of the built-in electric field constructed by the high-low junction, charge carriers can quickly migrate from the substrate 100 to the polysilicon layer 112 and be collected by the electrode 110.

[0059] In some embodiments, the doping concentration of the doped polysilicon layer 112 is 8E19 atoms / cm². 3 ~8E20atoms / cm 3 The doping concentration of the polycrystalline silicon layer 112 is 8E19 atoms / cm². 3 9E19atoms / cm 3 1E20atoms / cm 3 2E20atoms / cm 3 3E20atoms / cm 3 4E20atoms / cm 35E20atoms / cm 3 6E20atoms / cm 3 7E20atoms / cm 3 Or 8E20atoms / cm 3 .

[0060] In some embodiments, the thickness of the doped polysilicon layer 112 is 50 nm to 500 nm. The thickness of the doped polysilicon layer 112 can be 50 nm, 52 nm, 57 nm, 63 nm, 90 nm, 110 nm, 130 nm, 180 nm, 210 nm, 260 nm, 310 nm, 350 nm, 390 nm, 410 nm, 460 nm, 480 nm, or 500 nm. The thickness range of the doped polysilicon layer 112 allows it to act as a barrier layer to prevent the electrode 110 paste from burning through the passivation layer.

[0061] In some embodiments, when the polycrystalline silicon grain size of the doped polycrystalline silicon layer 112 is 200 nm to 1000 nm, its surface roughness is moderate and the number of grain boundaries is small. When electrodes (such as silver, aluminum, titanium, etc.) come into contact with it, metal atoms are less likely to diffuse excessively into the tunneling layer or substrate along the grain boundaries. At the same time, the larger grain surface can form a uniform metal silicide, providing a low-barrier ohmic contact path, thereby significantly reducing contact resistance. Large grains also represent better stability, and are less prone to abnormal grain growth or surface bulging. The electrode material can form a continuous and dense contact interface during sintering, avoiding electrode peeling or voids caused by excessive grain boundaries, which can improve the mechanical adhesion and long-term reliability of the electrode.

[0062] In some embodiments, the polysilicon grain size of the doped polysilicon layer 112 can be any value or a range between any two of 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 950nm, or 1000nm.

[0063] In some embodiments, the polycrystalline silicon grain size of the doped polycrystalline silicon layer 112 can be 500 nm to 900 nm, for example, any value or a range between any two of 500 nm, 550 nm, 600 nm, 700 nm, 750 nm, 800 nm, 850 nm, or 900 nm. With a polycrystalline silicon grain size within this range, the polycrystalline silicon has fewer lattice defects, resulting in better passivation of the doped polycrystalline silicon layer 112 and improved photoelectric conversion efficiency of the solar cell. Secondly, the polycrystalline silicon grain size is not too large, and the roughness of the doped polycrystalline silicon layer 112 is moderate, thus not affecting the uniformity and density of the tunneling layer, thereby ensuring the tunneling performance of the tunneling layer and improving the passivation performance of the solar cell. Thirdly, the moderate grain size of the polycrystalline silicon results in better contact performance between the doped polycrystalline silicon layer 112 and the electrode, thereby reducing electrical losses.

[0064] In some embodiments, the polycrystalline silicon layer 112 is doped with a P-type dopant. When the polycrystalline silicon size of the doped polycrystalline silicon layer 112 is 200 nm to 1000 nm, the polycrystalline silicon size of the doped polycrystalline silicon layer 112 increases, the grain boundaries between polycrystalline silicon particles in the doped polycrystalline silicon layer 112 decrease, and the diffusion of the P-type dopant slows down appropriately. This can prevent the P-type dopant from failing to diffuse into the tunneling layer and the substrate during high-temperature annealing, thus avoiding defects in the tunneling layer 111 (e.g., the combination of oxygen and boron dopant elements in the tunneling layer to form boron-oxygen recombination centers), which would affect the photoelectric conversion efficiency of the solar cell. The polycrystalline silicon size of the doped polycrystalline silicon layer 112 being 200 nm to 1000 nm is beneficial for suppressing excessive diffusion of the P-type dopant, thereby reducing the interface state density and reducing recombination losses.

[0065] Secondly, the polysilicon size of the doped polysilicon layer 112 is 200nm~1000nm. The grain boundaries of the doped polysilicon layer 112 are small, which can block the migration of metal ions in the electrode 110, thereby reducing the metal recombination problem of the substrate 100 and improving the passivation effect.

[0066] It should be noted that the grain size of the doped polycrystalline silicon layer 112 refers to the average size of the tiny silicon crystals (grains) constituting the polycrystalline silicon thin film. The grain size of the polycrystalline silicon thin film can be obtained directly or indirectly by X-ray diffraction (XRD), transmission electron microscopy (TEM), scanning electron microscopy (SEM), electron backscatter diffraction (EBSD), or Raman spectroscopy (Raman), and then the average value can be calculated.

[0067] The solar cell includes: a front passivation layer 107, which is located on the surface of the emitter 103 and on the first surface 101 of the substrate 100.

[0068] In some embodiments, the front passivation layer 107 can be a single-layer structure or a stacked structure, and the material of the front passivation layer 107 can be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0069] The solar cell includes a passivation layer 108, which is located on the surface of a doped polycrystalline silicon layer 112.

[0070] In some embodiments, the passivation layer 108 can be a single-layer structure or a stacked structure, and the material of the passivation layer 108 can be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0071] The solar cell includes: a first electrode 109, which is located on the front passivation layer 107 and is electrically connected to the emitter 103.

[0072] In some embodiments, the first electrode 109 may be sintered from a burn-through metal paste or from a LECO (Laser-enhanced contact optimization) paste, wherein the metal paste and the LECO paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel.

[0073] The solar cell includes an electrode 110 located on a passivation layer 108 and electrically connected to a doped polycrystalline silicon layer 112.

[0074] In some embodiments, the electrode 110 may be sintered from a burn-through metal paste or a LECO paste, wherein the metal paste and the LECO paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel.

[0075] The technical solution provided in this application includes a doped polycrystalline silicon layer 112, which contains P-type dopant and has a grain size ranging from 200 nm to 1000 nm, meaning its grain boundary density is significantly lower than that of microcrystals or nanocrystals (<100 nm). Larger grains reduce dangling bonds and defect states at grain boundaries, thereby reducing carrier recombination rates. Simultaneously, P-type doping can create a built-in electric field within the polycrystalline silicon layer, enhancing the field passivation effect, reducing interfacial recombination, and thus increasing the open-circuit voltage. Furthermore, the 200 nm to 1000 nm grain size gives the polycrystalline silicon layer near-single-crystal transport characteristics. Combined with the sufficient hole concentration provided by P-type doping, this reduces the layer's bulk resistance, facilitating rapid lateral transport of photogenerated holes to the electrode 110, reducing series resistance, and improving the fill factor.

[0076] When the polycrystalline silicon crystal size is between 200nm and 1000nm, its surface roughness is moderate and the number of grain boundaries is relatively small. When the electrode 110 (such as silver, aluminum, titanium, etc.) comes into contact with it, metal atoms are less likely to diffuse excessively into the tunneling layer 111 or the substrate along the grain boundaries. At the same time, a uniform metal silicide can be formed on the surface of larger grains, providing a low-barrier ohmic contact path, thereby significantly reducing contact resistance. Large grains also represent better stability, making it less prone to abnormal grain growth or surface bulging. During sintering, the electrode 110 material can form a continuous and dense contact interface, avoiding electrode 110 peeling or voids caused by excessive grain boundaries, which can improve the mechanical adhesion and long-term reliability of the electrode 110.

[0077] Accordingly, another embodiment of this application provides a method for preparing a solar cell, which is used to prepare the solar cell provided in the above embodiment. The same or corresponding technical features as those in the above embodiment will not be described in detail here.

[0078] Figures 2-6 This is a schematic diagram of the structure of a solar cell corresponding to each step in a method for preparing a solar cell according to another embodiment of this application.

[0079] According to some embodiments of this application, another aspect of this application provides a method for fabricating a solar cell, comprising: providing a substrate 100; forming an initial tunneling layer 104 and an initial semiconductor layer 105, wherein the initial tunneling layer 104 is located on the surface of the substrate 100 and the initial semiconductor layer 105 is located on the surface of the initial tunneling layer 104; pre-treating the initial tunneling layer 104 and the initial semiconductor layer 105, wherein the pre-treating transforms the initial semiconductor layer 105 into an initial polycrystalline silicon layer 106, and the grain size of the initial polycrystalline silicon layer 106 is in the range of 200 nm to 1000 nm; the pre-treating further transforms the initial tunneling layer 104 into a tunneling layer 111; performing a doping treatment and an annealing treatment on the initial polycrystalline silicon layer 106, wherein the initial polycrystalline silicon layer 106 is transformed into a doped polycrystalline silicon layer 112, wherein the doped polycrystalline silicon layer 112 is doped with a p-type dopant element; forming an electrode 110, wherein the electrode 110 is located on the doped polycrystalline silicon layer 112 and the electrode 110 is electrically connected to the doped polycrystalline silicon layer 112.

[0080] refer to Figure 2 The preparation method includes: providing a substrate 100.

[0081] The substrate 100 is made of elemental semiconductor material or compound semiconductor material.

[0082] Continue to refer to Figure 2 The preparation method includes: forming a pile-forming process to form a pile surface structure.

[0083] In some embodiments, the texturing process may include conventionally selected methods such as solution texturing, laser texturing, and ion texturing.

[0084] refer to Figure 2 The preparation method includes: doping the substrate 100 to form an emitter 103, the surface of which has doped silicon glass.

[0085] In some embodiments, doping can be performed by tubular diffusion. BCl3 or BBr3 is used as the boron diffusion source, with a flow rate of 100 sccm to 1000 sccm, and the oxygen flow rate is 300 sccm to 1000 sccm, with the temperature controlled at 900℃ to 1100℃.

[0086] The resulting emitter has a sheet resistance of 50 ohms / sq to 400 ohms / sq. The emitter surface is covered with doped silicon glass, specifically borosilicate glass (BSG), with a thickness of 30 nm to 150 nm. The surface concentration of the emitter is 1E¹⁸ atoms / cm². 3 ~1E20atoms / cm 3 The junction depth of the emitter is 0.3μm~2μm.

[0087] refer to Figure 2 Remove doped silicon glass.

[0088] The preparation method includes: preparing HF with a concentration of 5% to 10%, processing time of 100 to 1000 seconds, at room temperature, and removing BSG.

[0089] refer to Figure 3 An initial tunneling layer 104 and an initial semiconductor layer 105 are formed, wherein the initial tunneling layer 104 is located on the surface of the substrate 100 and the initial semiconductor layer 105 is located on the surface of the initial tunneling layer 104.

[0090] In some embodiments, the initial tunneling layer 104 and the initial semiconductor layer 105 are formed using an LPCVD (Low Pressure Chemical Vapor Deposition) process.

[0091] refer to Figure 4 The initial tunneling layer 104 and the initial semiconductor layer 105 are pre-processed to transform the initial semiconductor layer 105 into an initial polysilicon layer 106, and the grain size of the initial polysilicon layer 106 is in the range of 200nm~1000nm; the pre-processing also transforms the initial tunneling layer 104 into a tunneling layer 111.

[0092] In some embodiments, the pretreatment is a chain annealing process. Chain annealing enables rapid heating (tens to hundreds of °C / second) and controlled cooling, precisely controlling the thermal budget, which helps maintain a grain size of 200 nm to 1000 nm in the P-type doped polycrystalline silicon layer, avoiding excessive grain growth or stress defects. Secondly, the heating time is short, and the high-temperature exposure time of the silicon wafer is much shorter than that of tubular annealing, which can reduce warpage, reduce bulk recombination, and improve mechanical yield.

[0093] In some embodiments, the chain annealing time is 5 min to 60 min; the chain annealing temperature is 850℃ to 1050℃.

[0094] In some embodiments, the heating rate of the chain annealing process is greater than 50°C / min; the cooling rate of the chain annealing process is greater than 50°C / min.

[0095] In some embodiments, the initial tunneling layer 104 has a thickness of 1 nm to 2 nm and a pore density of 102. 6 cm -2 ~10 8 cm -2 The pore size ranges from 2nm to 5nm. After pretreatment, the porosity of the tunneling layer is 10. 8 cm -2 ~10 10 cm-2 The size of the holes ranges from 6nm to 10nm.

[0096] In some embodiments, the thickness of the initial semiconductor layer 105 is 50 nm to 500 nm, and the grain size within the initial semiconductor layer 105 ranges from 0 to 200 nm. After pretreatment, the grain size of the initial polycrystalline silicon layer 106 ranges from 200 nm to 1000 nm.

[0097] As can be seen, the size and density of the pores in the tunneling layer are improved after pretreatment, which is beneficial for hole transport without affecting the passivation layer itself. For the doped polycrystalline silicon layer, the larger grains reduce dangling bonds and defect states at the grain boundaries, thereby reducing the carrier recombination rate.

[0098] In some embodiments, the grain size of the polysilicon in the final doped polysilicon layer can be changed by controlling the temperature and time of the chain annealing process. For example, controlling the chain annealing temperature to 850°C~1050°C and the time to 30 min results in a polysilicon grain size of 200 nm~1000 nm in the final doped polysilicon layer. This allows for a more suitable grain size in the doped polysilicon layer, which can reduce the contact resistance between the electrode and the doped polysilicon layer and improve the passivation performance of the doped polysilicon layer.

[0099] For example, by controlling the chain annealing temperature to be 1030℃~1050℃ and the time to be 30min, the grain size of the polysilicon in the final doped polysilicon layer is 500nm~900nm. This reduces the contact resistance between the electrode and the doped polysilicon layer, improves the passivation performance of the doped polysilicon layer, and the grain size is also suitable. It will not damage the tunneling layer and can ensure the passivation performance of the tunneling layer and the doped polysilicon layer.

[0100] refer to Figure 5 The initial polysilicon layer 106 is subjected to doping and annealing treatment, and the initial polysilicon layer 106 is transformed into a doped polysilicon layer 112, which is doped with P-type doping elements.

[0101] In some embodiments, the second temperature of the annealing process is lower than the first temperature of the chain annealing process.

[0102] refer to Figure 1 The preparation method includes: forming a front passivation layer 107, wherein the front passivation layer 107 is located on the emitter 103.

[0103] refer to Figure 1 The preparation method includes: forming a passivation layer 108, wherein the passivation layer 108 is located on the surface of the doped polycrystalline silicon layer 112.

[0104] In some embodiments, a passivation layer 108 is formed simultaneously with the formation of the front passivation layer 107.

[0105] refer to Figure 1 A first electrode 109 and an electrode 110 are formed. Electrode 110 is located on the doped polysilicon layer 112 and is electrically connected to the doped polysilicon layer 112. The first electrode 109 is located on the front passivation layer 107 and is electrically connected to the emitter 103.

[0106] Accordingly, according to some embodiments of this application, another aspect of this application provides a photovoltaic module, including the solar cell provided in the above embodiments and the solar cell prepared by the preparation method of the solar cell provided in the above embodiments, with the same or corresponding technical features as the above embodiments, which will not be described in detail here.

[0107] Figure 7 This is a schematic diagram of a photovoltaic module provided in another embodiment of this application.

[0108] refer to Figure 7 The photovoltaic module includes: a battery string, which is formed by connecting multiple solar cells 30 as described in any of the above embodiments; an encapsulating film 31 for covering the surface of the battery string; and a cover plate 32 for covering the surface of the encapsulating film away from the battery string.

[0109] Specifically, in some embodiments, multiple solar cells 30 can be electrically connected to each other via a connecting member 318, which is welded to a main grid on the solar cell. The main grid includes a main electrode electrically connected to electrode 110 and a main electrode electrically connected to a first electrode 109.

[0110] In some embodiments, there is no spacing between the solar cells, meaning that the solar cells overlap each other.

[0111] In some embodiments, the connecting member 318 is welded to a sub-grid on the battery cell, the sub-grid including an electrode 110 and a first electrode 109.

[0112] In some embodiments, the encapsulating film 31 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the solar cell, and the second encapsulating layer covers the other of the front or back sides of the solar cell. Specifically, at least one of the first encapsulating layer or the second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, or polyethylene terephthalate (PET) film.

[0113] It is worth noting that the first encapsulation layer and the second encapsulation layer still have a dividing line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 31.

[0114] In some embodiments, the cover plate 32 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 32 facing the encapsulating film 31 can be an uneven surface, thereby increasing the utilization rate of incident light. The cover plate 32 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer and the second cover plate being opposite to the second encapsulation layer; or the first cover plate being opposite to one side of the solar cell and the second cover plate being opposite to the other side of the solar cell.

[0115] The solar cells provided above will be described in detail below with reference to relevant embodiments.

[0116] Example 1: (1) N-type single crystal silicon wafers are selected as the substrate. The resistivity of N-type single crystal silicon wafers is 10 ohm mm and the thickness is 130 μm.

[0117] (2) The texturing process, doping treatment, and polishing process are used to form a material such as... Figure 2 The precursor shown.

[0118] (3) An initial tunneling layer (1.5 nm) and an initial semiconductor layer are prepared on the surface of a silicon wafer using LPCVD process. The initial semiconductor layer is an intrinsic polycrystalline silicon layer (300 nm) or an intrinsic amorphous silicon layer (300 nm). The reaction temperature is 565 °C. The grain size of the intrinsic polycrystalline silicon layer is 100 nm. The pore density of the initial tunneling layer is 10. 7 cm -2 The size is 3nm.

[0119] (4) The initial semiconductor layer is pre-annealed using a chain annealing equipment at a temperature of 1045℃ for 30 minutes. The gas atmosphere is nitrogen or argon. The resulting initial polycrystalline silicon layer has a grain size of 600 nm and a tunneling layer porosity of 10. 9 cm -2 The size is 8nm.

[0120] (5) High-temperature boron diffusion was performed on the back side of the silicon wafer using a tubular diffusion apparatus to achieve doping of the initial semiconductor layer. The doping concentration of the polycrystalline silicon layer after diffusion was 6E19 atoms / cm. 3 The high-temperature boron diffusion temperature is 950℃.

[0121] (6) The subsequent steps are to complete the battery preparation according to the existing process, which will not be elaborated here.

[0122] Examples 2 to 4: The difference between Examples 2 and 4 lies in the different chain annealing temperatures, as detailed in Table 1.

[0123] Comparative Example 1: The difference in Comparative Example 1 is that step (4) of Example 1 is replaced by using a tubular annealing apparatus to pre-anneal the initial semiconductor layer. The tubular annealing temperature is 1045℃, the time is 30min, the gas atmosphere is nitrogen or argon, the grain size of the formed initial polycrystalline silicon layer is 300nm, and the pore density of the tunneling layer is 10. 9 cm -2 The size is 8nm.

[0124] The annealed wafers were then acid-washed with HF solution at a concentration of 6% for 300 seconds.

[0125] Comparative Example 2: The difference in Comparative Example 2 is that step (4) of Example 1 is omitted.

[0126] Electrical tests were performed on Examples 1 to 4, as well as Comparative Examples 1 and 2, and the results are shown in Table 1 below.

[0127] Table 1

[0128] Note: VOC represents open-circuit voltage, Isc represents short-circuit current, FF represents fill factor, and EFF represents conversion efficiency.

[0129] Based on the experimental results, Example 1, which uses the chain annealing of the present invention, shows a significant and uniform increase in open-circuit voltage and fill factor, and an overall efficiency increase of 0.17%. Comparative Example 1, which uses tubular annealing, also shows a significant efficiency improvement, but the comparative example has an additional pickling step compared to the present invention, which increases the process time and cost. In comparison, the present invention has a higher cost-performance ratio.

[0130] In particular, tubular annealing can cause the battery surface to react with the furnace atmosphere, forming a dense oxide layer that hinders subsequent PN junction formation, coating (such as SiNx antireflection film), and electrode contact. This oxide layer must be thoroughly removed. In addition, during the annealing process, the quartz boat and furnace tube may release metallic impurities such as Fe, Cu, and Cr, which are adsorbed on the silicon wafer surface. These impurities become "recombination centers," reducing the minority carrier lifetime of the silicon wafer (directly affecting photoelectric conversion efficiency). Acid washing can dissolve and remove these impurities, but it will affect the final photoelectric conversion efficiency.

[0131] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A solar cell, characterized in that, include: Base; A tunneling layer located on the surface of the substrate; A doped polycrystalline silicon layer is located on the surface of the tunneling layer, and the doped polycrystalline silicon layer is doped with a P-type dopant element; the grain size of the doped polycrystalline silicon layer ranges from 200 nm to 1000 nm. An electrode is located on the doped polysilicon layer and is electrically connected to the doped polysilicon layer.

2. The solar cell according to claim 1, characterized in that, The doping concentration of the doped polycrystalline silicon layer is 8E19 atoms / cm². 3 ~8E20atoms / cm 3 .

3. The solar cell according to claim 1, characterized in that, The thickness of the doped polycrystalline silicon layer is 50 nm to 500 nm.

4. The solar cell according to claim 1, characterized in that, The tunneling layer has pores, and the pore density is 10. 8 cm -2 ~10 10 cm -2 .

5. The solar cell according to claim 4, characterized in that, The size of the hole ranges from 6 nm to 10 nm.

6. A method for preparing a solar cell, characterized in that, include: Provide a base; An initial tunneling layer and an initial semiconductor layer are formed, wherein the initial tunneling layer is located on the surface of the substrate and the initial semiconductor layer is located on the surface of the initial tunneling layer; The initial tunneling layer and the initial semiconductor layer are pre-processed, wherein the pre-processing transforms the initial semiconductor layer into an initial polysilicon layer, and the grain size of the initial polysilicon layer is in the range of 200nm~1000nm; the pre-processing also transforms the initial tunneling layer into a tunneling layer. The initial polycrystalline silicon layer is subjected to doping and annealing treatment, and the initial polycrystalline silicon layer is transformed into a doped polycrystalline silicon layer, wherein the doped polycrystalline silicon layer is doped with a P-type dopant element. An electrode is formed on the doped polysilicon layer and is electrically connected to the doped polysilicon layer.

7. The method for preparing a solar cell according to claim 6, characterized in that, The pretreatment is a chain annealing process.

8. The method for preparing a solar cell according to claim 7, characterized in that, The chain annealing process takes 5 to 60 minutes and is carried out at a temperature of 850°C to 1050°C.

9. The method for preparing a solar cell according to claim 6, characterized in that, The heating rate of the chain annealing process is greater than 50℃ / min; the cooling rate of the chain annealing process is greater than 50℃ / min.

10. The method for preparing a solar cell according to claim 7, characterized in that, The second temperature of the annealing process is lower than the first temperature of the chain annealing process.

11. A photovoltaic module, characterized in that, include: A battery string is formed by connecting multiple solar cells as described in any one of claims 1 to 5, or by connecting multiple solar cells prepared by the method of preparing solar cells as described in any one of claims 6 to 10; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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